Searched refs:VT1 (Results 1 - 13 of 13) sorted by relevance

/external/llvm/include/llvm/Support/
H A DPassNameParser.h89 static int ValLessThan(const void *VT1, const void *VT2) { argument
91 return std::strcmp(static_cast<const ValType *>(VT1)->Name,
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h357 SDVTList getVTList(EVT VT1, EVT VT2);
358 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
359 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
774 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
775 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
777 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
779 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
782 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
784 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
786 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h106 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
117 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
H A DMSP430ISelLowering.cpp996 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { argument
997 if (!VT1.isInteger() || !VT2.isInteger())
1000 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1008 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { argument
1010 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
/external/kernel-headers/original/asm-arm/
H A Dtermbits.h82 #define VT1 0040000 macro
/external/kernel-headers/original/asm-mips/
H A Dtermbits.h126 #define VT1 0040000 macro
/external/kernel-headers/original/asm-x86/
H A Dtermbits.h106 #define VT1 0040000 macro
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1552 SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { argument
1553 unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
1555 Type *Ty1 = VT1.getTypeForEVT(*getContext());
4707 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) { argument
4710 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
4714 Array[0] = VT1;
4721 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) { argument
4724 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
4729 Array[0] = VT1;
4737 SDVTList SelectionDAG::getVTList(EVT VT1, EV argument
4946 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) argument
4953 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2) argument
4959 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) argument
4966 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps) argument
4973 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1) argument
4981 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument
4989 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
4998 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
5164 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2) argument
5170 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1) argument
5178 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument
5186 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
5195 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) argument
5203 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument
5212 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
5221 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) argument
5229 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps) argument
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h83 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
H A DHexagonISelLowering.cpp1459 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { argument
1460 if (!VT1.isSimple() || !VT2.isSimple()) {
1463 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h601 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
612 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
621 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
623 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
H A DX86ISelLowering.cpp11742 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { argument
11743 if (!VT1.isInteger() || !VT2.isInteger())
11745 unsigned NumBits1 = VT1.getSizeInBits();
11757 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { argument
11759 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11762 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { argument
11764 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
/external/llvm/include/llvm/Target/
H A DTargetLowering.h579 EVT VT1, RegisterVT; local
581 (void)getVectorTypeBreakdown(Context, VT, VT1,
604 EVT VT1, VT2; local
606 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1670 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1686 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1711 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1713 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {

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