Searched refs:getOpcode (Results 1 - 25 of 383) sorted by relevance

1234567891011>>

/external/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h32 return Info->get(Inst.getOpcode()).isBranch();
36 return Info->get(Inst.getOpcode()).isConditionalBranch();
40 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
44 return Info->get(Inst.getOpcode()).isIndirectBranch();
48 return Info->get(Inst.getOpcode()).isCall();
52 return Info->get(Inst.getOpcode()).isReturn();
/external/dexmaker/src/dx/java/com/android/dx/dex/code/
H A DFixedSizeInsn.java53 return getOpcode().getFormat().codeSize();
59 getOpcode().getFormat().writeTo(out, this);
71 return getOpcode().getFormat().listingString(this, noteIndices);
/external/llvm/include/llvm/
H A DOperator.h41 /// getOpcode - Return the opcode for this Instruction or ConstantExpr.
43 unsigned getOpcode() const { function in class:llvm::Operator
45 return I->getOpcode();
46 return cast<ConstantExpr>(this)->getOpcode();
49 /// getOpcode - If V is an Instruction or ConstantExpr, return its
52 static unsigned getOpcode(const Value *V) { function in class:llvm::Operator
54 return I->getOpcode();
56 return CE->getOpcode();
108 return I->getOpcode() == Instruction::Add ||
109 I->getOpcode()
[all...]
H A DInstruction.h81 /// getOpcode() returns a member of one of the enums like Instruction::Add.
82 unsigned getOpcode() const { return getValueID() - InstructionVal; } function in class:llvm::Instruction
84 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); }
85 bool isTerminator() const { return isTerminator(getOpcode()); }
86 bool isBinaryOp() const { return isBinaryOp(getOpcode()); }
87 bool isShift() { return isShift(getOpcode()); }
88 bool isCast() const { return isCast(getOpcode()); }
108 return getOpcode() == Shl || getOpcode() == LShr;
113 return getOpcode()
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp113 if (II->getOpcode() == TargetOpcode::KILL)
163 if (MII->getOpcode() == Hexagon::CALLv3)
177 if (MII->getOpcode() == TargetOpcode::KILL ||
178 MII->getOpcode() == TargetOpcode::PHI ||
179 MII->getOpcode() == TargetOpcode::COPY)
186 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
187 MII->getOpcode() == Hexagon::TFR_condset_ii ||
188 MII->getOpcode() == Hexagon::TFR_condset_ri ||
189 MII->getOpcode() == Hexagon::TFR_condset_ir ||
190 MII->getOpcode()
[all...]
H A DHexagonRegisterInfo.cpp125 if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) {
127 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
167 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
174 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
183 if ( (MI.getOpcode() == Hexagon::LDriw) ||
184 (MI.getOpcode() == Hexagon::LDrid) ||
185 (MI.getOpcode() == Hexagon::LDrih) ||
186 (MI.getOpcode() == Hexagon::LDriuh) ||
187 (MI.getOpcode() == Hexagon::LDrib) ||
188 (MI.getOpcode()
[all...]
H A DHexagonSplitTFRCondSets.cpp85 switch(MI->getOpcode()) {
93 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
94 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
98 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) {
129 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) {
134 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) {
150 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) {
155 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) {
178 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) {
187 } else if (MI->getOpcode()
[all...]
H A DHexagonCFGOptimizer.cpp69 switch(MI->getOpcode()) {
106 int Opc = MI->getOpcode();
158 if ((MI->getOpcode() == Hexagon::JMP_c) ||
159 (MI->getOpcode() == Hexagon::JMP_cNot)) {
171 IsUnconditionalJump(LayoutSucc->front().getOpcode())) {
178 IsUnconditionalJump(JumpAroundTarget->back().getOpcode()) &&
/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
H A DMCInst.cpp43 OS << "<MCInst " << getOpcode();
54 OS << "<MCInst #" << getOpcode();
58 OS << ' ' << Printer->getOpcodeName(getOpcode());
/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DNormalSsaInsn.java128 public Rop getOpcode() { method in class:NormalSsaInsn
129 return insn.getOpcode();
143 if (insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) {
180 return insn.getOpcode().getOpcode() == RegOps.MOVE;
186 return insn.getOpcode().getOpcode() == RegOps.MOVE_EXCEPTION;
218 Rop opcode = getOpcode();
227 switch (opcode.getOpcode()) {
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp80 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
81 Addr.getOpcode() == ISD::TargetGlobalAddress)
84 if (Addr.getOpcode() == ISD::ADD) {
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
115 if (Addr.getOpcode() == ISD::FrameIndex) return false;
116 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
117 Addr.getOpcode() == ISD::TargetGlobalAddress)
120 if (Addr.getOpcode() == ISD::ADD) {
124 if (Addr.getOperand(0).getOpcode()
[all...]
H A DFPMover.cpp90 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
91 MI->getOpcode() == SP::FpNEGD) {
95 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) {
106 if (MI->getOpcode() == SP::FpMOVD)
108 else if (MI->getOpcode() == SP::FpNEGD)
110 else if (MI->getOpcode() == SP::FpABSD)
/external/dexmaker/src/dx/java/com/android/dx/rop/code/
H A DPlainInsn.java92 return new PlainInsn(getOpcode(), getPosition(),
115 Rop newRop = Rops.ropFor(getOpcode().getOpcode(), getResult(),
130 int opcode = getOpcode().getOpcode();
152 return new PlainInsn(getOpcode(), getPosition(),
H A DThrowingCstInsn.java84 return new ThrowingCstInsn(getOpcode(), getPosition(),
92 return new ThrowingCstInsn(getOpcode(), getPosition(),
103 return new ThrowingCstInsn(getOpcode(), getPosition(),
H A DThrowingInsn.java99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
/external/dexmaker/src/dx/java/com/android/dx/io/instructions/
H A DZeroRegisterDecodedInstruction.java41 getFormat(), getOpcode(), newIndex, getIndexType(),
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp101 unsigned Opc = N->getOpcode();
122 if (N.getOpcode() == ISD::FrameIndex) return false;
123 if (N.getOpcode() == ISD::TargetExternalSymbol ||
124 N.getOpcode() == ISD::TargetGlobalAddress)
128 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
153 if (N.getOpcode() == ISD::ADD || N.getOpcode()
[all...]
H A DMBlazeInstrInfo.cpp45 if (MI->getOpcode() == MBlaze::LWI) {
64 if (MI->getOpcode() == MBlaze::SWI) {
137 unsigned LastOpc = LastInst->getOpcode();
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
162 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) &&
163 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
173 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) &&
174 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
223 if (!MBlaze::isUncondBranchOpcode(I->getOpcode())
[all...]
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h140 inline unsigned getOpcode() const;
359 /// getOpcode - Return the SelectionDAG opcode value for this node. For
363 unsigned getOpcode() const { return (unsigned short)NodeType; } function in class:llvm::SDNode
774 inline unsigned SDValue::getOpcode() const {
775 return Node->getOpcode();
970 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
978 return N->getOpcode() == ISD::LOAD ||
979 N->getOpcode() == ISD::STORE ||
980 N->getOpcode() == ISD::PREFETCH ||
981 N->getOpcode()
[all...]
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp106 switch (I->getOpcode()) {
201 switch (I->getOpcode()) {
314 bool isLeftShift = I.getOpcode() == Instruction::Shl;
319 if (I.getOpcode() != Instruction::AShr &&
337 if (I.getOpcode() != Instruction::AShr)
346 if (BO->getOpcode() == Instruction::Mul && isLeftShift)
372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
386 if (I.getOpcode() == Instruction::Shl)
389 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift");
408 switch (Op0BO->getOpcode()) {
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp58 int Opcode = MI->getOpcode();
80 int Opcode = MI->getOpcode();
209 if (IsBRU(LastInst->getOpcode())) {
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
235 unsigned SecondLastOpc = SecondLastInst->getOpcode();
241 && IsBRU(LastInst->getOpcode())) {
253 if (IsBRU(SecondLastInst->getOpcode()) &&
254 IsBRU(LastInst->getOpcode())) {
263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
[all...]
H A DXCoreISelDAGToDAG.cpp99 if (Addr.getOpcode() == ISD::ADD) {
115 if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
120 if (Addr.getOpcode() == ISD::ADD) {
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
136 if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
141 if (Addr.getOpcode() == ISD::ADD) {
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
157 switch (N->getOpcode()) {
242 if (Chain->getOpcode() != ISD::TokenFactor)
265 if (Addr->getOpcode() !
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCBranchSelector.cpp106 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
143 if (I->getOpcode() == PPC::BCC) {
154 } else if (I->getOpcode() == PPC::BDNZ) {
156 } else if (I->getOpcode() == PPC::BDNZ8) {
158 } else if (I->getOpcode() == PPC::BDZ) {
160 } else if (I->getOpcode() == PPC::BDZ8) {
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp26 unsigned Opcode = MCID.getOpcode();
59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
60 (TII.canCauseFpMLxStall(MI->getOpcode()) ||

Completed in 834 milliseconds

1234567891011>>