/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 188 return isReg() ? 0 : TargetFlags; 191 assert(!isReg() && "Register operands can't have target flags"); 195 assert(!isReg() && "Register operands can't have target flags"); 221 /// isReg - Tests if this is a MO_Register operand. 222 bool isReg() const { return OpKind == MO_Register; } function in class:llvm::MachineOperand 258 assert(isReg() && "This is not a register operand!"); 263 assert(isReg() && "Wrong MachineOperand accessor"); 268 assert(isReg() && "Wrong MachineOperand accessor"); 273 assert(isReg() && "Wrong MachineOperand accessor"); 278 assert(isReg() [all...] |
H A D | LiveVariables.h | 223 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { 259 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 90 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 101 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 112 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 123 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 135 assert(MI.getOperand(OpNo+1).isReg()); 153 assert(MI.getOperand(OpNo+1).isReg()); 180 if (MO.isReg()) {
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/external/llvm/lib/CodeGen/ |
H A D | AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
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H A D | DeadMachineInstructionElim.cpp | 69 if (MO.isReg() && MO.isDef()) { 138 if (!MO.isReg() || !MO.isDef()) 167 if (MO.isReg() && MO.isDef()) { 186 if (MO.isReg() && MO.isUse()) {
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H A D | MachineInstr.cpp | 93 assert(isReg() && "Wrong MachineOperand accessor"); 114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 117 if (isReg() && isOnRegUseList()) 140 bool WasReg = isReg(); 627 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 647 if (Operands[i].isReg()) 656 if (Operands[i].isReg()) 666 bool isImpReg = Op.isReg() && Op.isImplicit(); 684 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 704 if (Operands[i].isReg()) [all...] |
H A D | ProcessImplicitDefs.cpp | 71 if (MO->isReg() && MO->isUse() && MO->readsReg()) 106 if (!MO->isReg())
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H A D | TargetInstrInfoImpl.cpp | 65 if (HasDef && !MI->getOperand(0).isReg()) 76 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && 135 if (!MI->getOperand(SrcOpIdx1).isReg() || 136 !MI->getOperand(SrcOpIdx2).isReg()) 170 if (MO.isReg()) { 385 if (!MI->getNumOperands() || !MI->getOperand(0).isReg()) 423 if (!MO.isReg()) continue;
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H A D | RegisterScavenging.cpp | 152 if (!MO.isReg()) 177 if (!MO.isReg()) 286 if (!MO.isReg() || MO.isUndef() || !MO.getReg()) 336 if (MO.isReg() && MO.getReg() != 0 &&
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H A D | ExpandPostRAPseudos.cpp | 89 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) 97 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && 99 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
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H A D | MachineInstrBundle.cpp | 54 if (MO.isReg() && MO.isInternalRead()) 124 if (!MO.isReg()) 257 if (!MO.isReg() || MO.getReg() != Reg)
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinterDwarf.cpp | 184 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { 192 } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { 193 assert(Dst.isReg() && "Machine move not supported yet."); 196 assert(!Dst.isReg() && "Machine move not supported yet.");
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 183 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 199 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 208 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 218 assert(MI.getOperand(OpNo+1).isReg()); 234 assert(MI.getOperand(OpNo+1).isReg()); 249 if (MO.isReg()) {
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H A D | PPCCTRLoops.cpp | 148 bool isReg() const { return Kind == CV_Register; } function in class:__anon8964::CountValue 153 assert(isReg() && "Wrong CountValue accessor"); 171 if (isReg()) { OS << PrintReg(getReg()); } 368 assert(InitialValue->isReg() && "Expecting register for init value"); 425 MI->getOperand(1).isReg() && // could be a frame index instead 442 if (MO.isReg() && MO.isDef() && 477 if (MO.isReg() && MO.isDef()) { 490 if (OPO.isReg() && OPO.isDef()) { 533 if (!MO.isReg() || !MO.isDef()) 633 if (TripCount->isReg()) { [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 56 bool isReg() const { return Kind == kRegister; } function in class:llvm::MCOperand 64 assert(isReg() && "This is not a register operand!"); 70 assert(isReg() && "This is not a register operand!");
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H A D | MachineLocation.h | 51 bool isReg() const { return IsRegister; } function in class:llvm::MachineLocation
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonNewValueJump.cpp | 133 if (II->getOperand(i).isReg() && 455 MI->getOperand(0).isReg() && 463 isSecondOpReg = MI->getOperand(2).isReg(); 497 if (MI->getOperand(0).isReg() && 556 if (MO.isReg() && MO.isUse()) { 563 if (localMO.isReg() && localMO.isUse() && 625 if (cmpInstr->getOperand(0).isReg() && 628 if (cmpInstr->getOperand(1).isReg() &&
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H A D | HexagonAsmPrinter.cpp | 145 if (!MI->getOperand(OpNo).isReg() || 147 !MI->getOperand(OpNo+1).isReg()) 174 if (Base.isReg())
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/external/llvm/lib/MC/ |
H A D | MCInst.cpp | 22 else if (isReg())
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/external/llvm/lib/Target/MBlaze/InstPrinter/ |
H A D | MBlazeInstPrinter.cpp | 38 if (Op.isReg()) {
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeDelaySlotFiller.cpp | 134 bool aop_is_reg = a->getOperand(aop).isReg(); 142 bool mop_is_reg = m->getOperand(mop).isReg(); 162 if (a->getOperand(aop).isReg()) { 166 if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit()) {
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/external/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 213 if (!MO.isReg()) 244 assert(Reg.isReg() && "JMPL first operand is not a register."); 251 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register."); 265 if (!MO.isReg())
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H A D | SparcAsmPrinter.cpp | 76 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) { 80 !MO.isReg() && !MO.isImm()) { 122 if (MI->getOperand(opNum+1).isReg() && 251 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
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/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 49 if (Op.isReg()) {
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 113 MI->getOperand(Op+2).isReg() && 123 MI->getOperand(Op+4).isReg() && 342 if (!MO.isReg()) return false;
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