Searched refs:r0 (Results 1 - 25 of 398) sorted by relevance

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/external/compiler-rt/lib/arm/
H A Dbswapsi2.S21 eor r1, r0, r0, ror #16
24 eor r0, r1, r0, ror #8
26 rev r0, r0
H A Dnegsf2vfp.S21 eor r0, r0, #-2147483648 // flip sign bit on float in r0
H A Dbswapdi2.S21 // r2 = rev(r0)
22 eor r2, r0, r0, ror #16
25 eor r2, r2, r0, ror #8
26 // r0 = rev(r1)
27 eor r0, r1, r1, ror #16
28 bic r0, r0, #0xff0000
29 mov r0, r0, ls
[all...]
H A Dswitch8.S35 cmp r0, ip // signed compare with index
36 ldrsbcc r0, [lr, r0] // get indexed byte out of table
37 ldrsbhs r0, [lr, ip] // if out of range, use last entry in table
38 add ip, lr, r0, lsl #1 // compute label = lr + element*2
H A Dswitchu8.S35 cmp r0, ip // compare with index
36 ldrbcc r0, [lr, r0] // get indexed byte out of table
37 ldrbhs r0, [lr, ip] // if out of range, use last entry in table
38 add ip, lr, r0, lsl #1 // compute label = lr + element*2
H A Dswitch16.S35 cmp r0, ip // compare with index
36 add r0, lr, r0, lsl #1 // compute address of element in table
37 ldrshcc r0, [r0, #1] // load 16-bit element if r0 is in range
39 ldrshhs r0, [ip, #1] // load 16-bit element if r0 out of range
40 add ip, lr, r0, lsl #1 // compute label = lr + element*2
H A Dswitch32.S35 cmp r0, ip // compare with index
36 add r0, lr, r0, lsl #2 // compute address of element in table
37 ldrcc r0, [r0, #3] // load 32-bit element if r0 is in range
39 ldrcs r0, [ip, #3] // load 32-bit element if r0 out of range
40 add ip, lr, r0 // compute label = lr + element
H A Dmodsi3.S28 mov r4, r0
30 eor r2, r0, r0, asr #31
32 sub r0, r2, r0, asr #31
37 eor r0, r0, r4, asr #31
38 sub r0, r0, r4, asr #31
H A Ddivmodsi4.S30 eor r4, r0, r1
31 mov r5, r0
34 eor ip, r0, r0, asr #31
36 sub r0, ip, r0, asr #31
42 eor r0, r0, r4, asr #31
44 sub r0, r0, r
[all...]
H A Dcomparesf2.S50 mov r2, r0, lsl #1
62 eorsne r12, r0, r1
65 // ignoring NaNs for now), this subtract will zero out r0. If they have the
68 subspl r0, r2, r3
71 // the negation of the sign of b in r0. Thus, if both are negative and
72 // a > b, this sets r0 to 0; if both are positive and a < b, this sets
73 // r0 to -1.
78 // negative, this places 0 in r0; if a is negative and b positive, -1 is
79 // placed in r0.
80 mvnlo r0, r
[all...]
H A Ddivsi3.S30 eor r4, r0, r1
32 eor r2, r0, r0, asr #31
34 sub r0, r2, r0, asr #31
39 eor r0, r0, r4, asr #31
40 sub r0, r0, r4, asr #31
H A Deqdf2vfp.S22 vmov d6, r0, r1 // load r0/r1 pair in double register
26 moveq r0, #1 // set result register to 1 if equal
27 movne r0, #0
H A Deqsf2vfp.S22 vmov s14, r0 // move from GPR 0 to float register
26 moveq r0, #1 // set result register to 1 if equal
27 movne r0, #0
H A Dgedf2vfp.S22 vmov d6, r0, r1 // load r0/r1 pair in double register
26 movge r0, #1 // set result register to 1 if greater than or equal
27 movlt r0, #0
H A Dgesf2vfp.S22 vmov s14, r0 // move from GPR 0 to float register
26 movge r0, #1 // set result register to 1 if greater than or equal
27 movlt r0, #0
H A Dgtdf2vfp.S22 vmov d6, r0, r1 // load r0/r1 pair in double register
26 movgt r0, #1 // set result register to 1 if equal
27 movle r0, #0
H A Dgtsf2vfp.S22 vmov s14, r0 // move from GPR 0 to float register
26 movgt r0, #1 // set result register to 1 if equal
27 movle r0, #0
H A Dledf2vfp.S22 vmov d6, r0, r1 // load r0/r1 pair in double register
26 movls r0, #1 // set result register to 1 if equal
27 movhi r0, #0
/external/webrtc/src/common_audio/signal_processing/
H A Dspl_sqrt_floor.s7 @ Input : r0 32 bit unsigned integer
8 @ Output: r0 = INT (SQRT (r0)), precision is 16 bits
21 cmp r0, r2, ror #2 * 0
22 subhs r0, r0, r2, ror #2 * 0
25 cmp r0, r2, ror #2 * 1
26 subhs r0, r0, r2, ror #2 * 1
29 cmp r0, r
[all...]
/external/llvm/test/MC/ARM/
H A Dmode-switch.s6 add.w r0, r0, r1
7 @ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00]
10 add r0, r0, r1
11 @ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0]
14 adds r0, r0, r
[all...]
H A Dthumb2-mclass.s12 mrs r0, apsr
13 mrs r0, iapsr
14 mrs r0, eapsr
15 mrs r0, xpsr
16 mrs r0, ipsr
17 mrs r0, epsr
18 mrs r0, iepsr
19 mrs r0, msp
20 mrs r0, psp
21 mrs r0, primas
[all...]
H A Darm_addrmode2.s4 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
6 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
7 @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
8 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
9 @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
10 @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
11 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
12 @ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
13 @ CHECK: strbt r1, [r0], r
[all...]
/external/skia/src/opts/
H A Dmemset32_neon.S14 /* r0 = buffer, r1 = value, r2 = times to write */
17 streq r1, [r0], #4
25 str r1, [r0], #4
44 vst1.64 {q0, q1}, [r0]!
45 vst1.64 {q0, q1}, [r0]!
46 vst1.64 {q0, q1}, [r0]!
47 vst1.64 {q0, q1}, [r0]!
48 vst1.64 {q0, q1}, [r0]!
49 vst1.64 {q0, q1}, [r0]!
50 vst1.64 {q0, q1}, [r0]!
[all...]
/external/valgrind/main/none/tests/arm/
H A Dv6media.c152 TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0);
153 TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
154 TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
155 TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
156 TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r
[all...]
H A Dv6intARM.c144 TESTINST2("mov r0, r1", 1, r0, r1, 0);
145 TESTINST2("cpy r0, r1", 1, r0, r1, 0);
146 TESTINST2("mov r0, #0", 0, r0, r1, 0);
147 TESTINST2("mov r0, #1", 0, r0, r1, 0);
149 TESTINST2("movs r0, r1", 1, r0, r
[all...]

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