Searched refs:ENDIAN_HANDLE_LONG (Results 1 - 15 of 15) sorted by relevance

/hardware/ti/wlan/wl1271/Test/
H A DTWD_Debug.c183 pCmd->addr = (TI_UINT32)ENDIAN_HANDLE_LONG (address);
184 pCmd->size = ENDIAN_HANDLE_LONG (len);
188 pCmd->addr = (TI_UINT32)ENDIAN_HANDLE_LONG (((address&0xFFFF) | REGISTERS_BASE));
193 pCmd->addr = (TI_UINT32)ENDIAN_HANDLE_LONG (((address&0xFFFF) | BB_REGISTER_ADDR_BASE));
285 pElem->ringStat.numOfTxProcs = ENDIAN_HANDLE_LONG(pElem->ringStat.numOfTxProcs);
286 pElem->ringStat.numOfPreparedDescs = ENDIAN_HANDLE_LONG(pElem->ringStat.numOfPreparedDescs);
287 pElem->ringStat.numOfTxXfr = ENDIAN_HANDLE_LONG(pElem->ringStat.numOfTxXfr);
288 pElem->ringStat.numOfTxDma = ENDIAN_HANDLE_LONG(pElem->ringStat.numOfTxDma);
289 pElem->ringStat.numOfTxCmplt = ENDIAN_HANDLE_LONG(pElem->ringStat.numOfTxCmplt);
290 pElem->ringStat.numOfRxProcs = ENDIAN_HANDLE_LONG(pEle
[all...]
/hardware/ti/wlan/wl1271/TWD/Ctrl/
H A DCmdBldCmdIE.c150 pCmd->rxFilter.ConfigOptions = ENDIAN_HANDLE_LONG (DB_WLAN(hCmdBld).RxConfigOption);
151 pCmd->rxFilter.FilterOptions = ENDIAN_HANDLE_LONG (DB_WLAN(hCmdBld).RxFilterOption);
167 pCmd->basicRateSet = ENDIAN_HANDLE_LONG(HwBasicRatesBitmap);
422 pCmd->AcSeqNum32[0] = ENDIAN_HANDLE_LONG(uSecuritySeqNumHigh);
709 pCmd->rateToTransmitNullData = ENDIAN_HANDLE_LONG(powerSaveParams->NullPktRateModulation);
779 AcxCmd_Disconnect.rxFilter.ConfigOptions = ENDIAN_HANDLE_LONG(uConfigOptions);
780 AcxCmd_Disconnect.rxFilter.FilterOptions = ENDIAN_HANDLE_LONG(uFilterOptions);
781 AcxCmd_Disconnect.disconnectReason = ENDIAN_HANDLE_LONG(uDisconReason);
819 pCmd->duration = ENDIAN_HANDLE_LONG(pMeasurementParams->duration);
820 pCmd->rxFilter.ConfigOptions = ENDIAN_HANDLE_LONG(pMeasurementParam
[all...]
H A DCmdBldCmd.c149 tnetScanParams.basicScanParameters.rxCfg.ConfigOptions = ENDIAN_HANDLE_LONG(RX_CONFIG_OPTION) ;
150 tnetScanParams.basicScanParameters.rxCfg.FilterOptions = ENDIAN_HANDLE_LONG( RX_FILTER_CFG_ );
155 tnetScanParams.basicScanParameters.rxCfg.ConfigOptions = ENDIAN_HANDLE_LONG(RX_CONFIG_OPTION | CFG_SSID_FILTER_EN | CFG_UNI_FILTER_EN) ;
162 tnetScanParams.basicScanParameters.txdRateSet = ENDIAN_HANDLE_LONG( tnetScanParams.basicScanParameters.txdRateSet );
182 ENDIAN_HANDLE_LONG( pScanVals->channelEntry[ i ].normalChannelEntry.minChannelDwellTime );
184 ENDIAN_HANDLE_LONG( pScanVals->channelEntry[ i ].normalChannelEntry.maxChannelDwellTime );
248 tnetSPSScanParams.scheduledGeneralParameters.rxCfg.ConfigOptions = ENDIAN_HANDLE_LONG(RX_CONFIG_OPTION);
249 tnetSPSScanParams.scheduledGeneralParameters.rxCfg.FilterOptions = ENDIAN_HANDLE_LONG( RX_FILTER_CFG_ );
250 tnetSPSScanParams.scheduledGeneralParameters.rxCfg.ConfigOptions = ENDIAN_HANDLE_LONG( tnetSPSScanParams.scheduledGeneralParameters.rxCfg.ConfigOptions );
253 tnetSPSScanParams.scheduledGeneralParameters.scanCmdTime_h = ENDIAN_HANDLE_LONG( INT64_HIGHE
[all...]
H A DCmdBldCfgIE.c80 pCfg->totalTxDescriptors = ENDIAN_HANDLE_LONG(NUM_TX_DESCRIPTORS);
175 pCfg->ConfigOptions = ENDIAN_HANDLE_LONG(apRxConfigOption);
176 pCfg->FilterOptions = ENDIAN_HANDLE_LONG(apRxFilterOption);
474 pCfg->coexPllStabilizationTime = ENDIAN_HANDLE_LONG(pFmCoexParams->uCoexPllStabilizationTime);
511 pSwap[i] = ENDIAN_HANDLE_LONG(pOrig[i]);
718 pCfg->Options = ENDIAN_HANDLE_LONG(options);
719 pCfg->dataflowOptions = ENDIAN_HANDLE_LONG(uDataFlowOptions);
946 pCfg->pdThreshold = ENDIAN_HANDLE_LONG(pdThreshold);
1177 pCfg->lowEventMask = ENDIAN_HANDLE_LONG(mask);
1178 pCfg->highEventMask = ENDIAN_HANDLE_LONG(
[all...]
H A DCmdBld.c285 pSwap[i] = ENDIAN_HANDLE_LONG(pSwap[i]);
/hardware/ti/wlan/wl1271/TWD/FW_Transfer/
H A DtxResult.c273 uTempCounters = ENDIAN_HANDLE_LONG(pFwStatus->counters);
370 uFwResultsCounter = ENDIAN_HANDLE_LONG(pTxResult->tResultsInfoReadTxn.tTxResultInfo.TxResultControl.TxResultFwCounter);
383 pTxResult->tHostCounterWriteTxn.uCounter = ENDIAN_HANDLE_LONG(uFwResultsCounter);
H A DRxXfer.c394 uTempCounters = ENDIAN_HANDLE_LONG (pFwStatus->counters);
414 pRxXfer->aRxPktsDesc[i] = ENDIAN_HANDLE_LONG (pFwStatus->rxPktsDesc[i]);
658 pRxXfer->aSlaveRegTxn[uIndex].uRegData = ENDIAN_HANDLE_LONG(uFirstMemBlkAddr);
659 pRxXfer->aSlaveRegTxn[uIndex].uRegAdata = ENDIAN_HANDLE_LONG(uFirstMemBlkAddr + 4);
670 pRxXfer->aCounterTxn[uIndex].uCounter = ENDIAN_HANDLE_LONG(pRxXfer->uDrvRxCntr);
H A DtxXfer.c349 pPktsCntrTxn->uPktsCntr = ENDIAN_HANDLE_LONG(pTxXfer->uPktsCntr);
H A DFwEvent.c513 ENDIAN_HANDLE_LONG (pFwEvent->tFwStatusTxn.tFwStatus.fwLocalTime);
/hardware/ti/wlan/wl1271/TWD/TwIf/
H A DTwIf.c495 pPartitionRegTxn[0].tData = ENDIAN_HANDLE_LONG(pTwIf->uMemAddr1);
496 pPartitionRegTxn[1].tData = ENDIAN_HANDLE_LONG(pTwIf->uMemSize1);
497 pPartitionRegTxn[2].tData = ENDIAN_HANDLE_LONG(pTwIf->uMemAddr2);
498 pPartitionRegTxn[3].tData = ENDIAN_HANDLE_LONG(pTwIf->uMemSize2);
499 pPartitionRegTxn[4].tData = ENDIAN_HANDLE_LONG(pTwIf->uMemAddr3);
500 pPartitionRegTxn[5].tData = ENDIAN_HANDLE_LONG(pTwIf->uMemSize3);
501 pPartitionRegTxn[6].tData = ENDIAN_HANDLE_LONG(pTwIf->uMemAddr4);
/hardware/ti/wlan/wl1271/utils/
H A Dtidef.h258 #define ENDIAN_HANDLE_LONG(x) BYTE_SWAP_LONG (x) macro
313 #define ENDIAN_HANDLE_LONG(x) (x) macro
/hardware/ti/wlan/wl1271/TWD/Data_Service/
H A DtxCtrlBlk.c282 ENDIAN_HANDLE_LONG(pTxCtrlBlk->aTxCtrlBlkTbl[entry].tTxDescriptor.startTime),
H A DtxHwQueue.c449 uFreeBlocks = ENDIAN_HANDLE_LONG(uFreeBlocks);
547 uTempFwCounters = (ENDIAN_HANDLE_LONG(pFwStatus->counters));
/hardware/ti/wlan/wl1271/stad/src/Data_link/
H A DtxCtrl.c141 pPktCtrlBlk->tTxDescriptor.startTime = ENDIAN_HANDLE_LONG (uPktStartTime);
1222 ENDIAN_HANDLE_LONG(pTxResultInfo->fwHandlingTime),
1224 ENDIAN_HANDLE_LONG(pTxResultInfo->mediumDelay));
1258 EHwBitRate eHwTxRate = ENDIAN_HANDLE_LONG((EHwBitRate)(pTxResultInfo->rate));
H A Drx.c1746 RxAttr.TimeStamp = ENDIAN_HANDLE_LONG(RxAttr.TimeStamp);

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