Searched refs:reg_imm (Results 1 - 11 of 11) sorted by relevance

/system/core/libpixelflinger/codeflinger/
H A Dload_store.cpp44 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
46 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
49 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 16));
84 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 8));
86 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 16));
91 ORR(AL, 0, s1, s1, reg_imm(s0, LSL, 8));
93 ORR(AL, 0, s.reg, s1, reg_imm(s0, LSL, 16));
125 MOV(AL, 0, d.reg, reg_imm(s, LSR, l)); // component = packed >> l;
141 MOV(AL, 0, d.reg, reg_imm(s, LSL, 32-h));
149 MOV(AL, 0, d.reg, reg_imm(
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H A Dtexturing.cpp102 MOV(AL, 0, end, reg_imm(parts.count.reg, LSR, 16));
105 BIC(AL, 0, c, c, reg_imm(c, ASR, 31));
166 reg_imm(parts.iterated.reg, LSR, 16));
224 reg_imm(fragment.reg, ASR, 31));
353 ADD(AL, 0, Rx, Rx, reg_imm(txPtr.reg, ASR, 16)); // x += (s>>16)
355 ADD(AL, 0, Ry, Ry, reg_imm(txPtr.reg, ASR, 16)); // y += (t>>16)
538 MOV(AL, 1, u, reg_imm(u, ASR, FRAC_BITS));
543 MOV(GE, 0, width, reg_imm(width, LSL, shift));
559 CMP(AL, width, reg_imm(u, ASR, FRAC_BITS));
560 MOV(LE, 0, u, reg_imm(widt
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H A Dblending.cpp55 BIC(AL, 0, factor.reg, factor.reg, reg_imm(factor.reg, ASR, 31));
138 MOV(AL, 0, temp.reg, reg_imm(temp.reg, LSR, temp.l));
148 MOV(AL, 0, fragment.reg, reg_imm(temp.reg, LSR, temp.l));
331 ADD(AL, 0, factor.reg, fb.reg, reg_imm(fb.reg, LSR, fb.s-1));
337 reg_imm(fragment.reg, LSR, fragment.s-1));
343 reg_imm(src_alpha.reg, LSR, src_alpha.s-1));
350 reg_imm(factor.reg, LSR, factor.s-1));
371 MOV(AL, 0, factor.reg, reg_imm(factor.reg, LSR, factor.s-8));
447 if (shift>0) RSB(AL, 0, diff.reg, fb.reg, reg_imm(fragment.reg, LSR, shift));
448 else if (shift<0) RSB(AL, 0, diff.reg, fb.reg, reg_imm(fragmen
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H A DGGLAssembler.cpp209 reg_imm(parts.count.reg, ROR, GGL_DITHER_ORDER_SHIFT));
213 reg_imm(parts.count.reg, ROR, 32 - GGL_DITHER_ORDER_SHIFT));
380 ADD(AL, 0, tx, tx, reg_imm(ty, LSL, GGL_DITHER_ORDER_SHIFT));
381 ORR(AL, 0, parts.count.reg, tx, reg_imm(parts.count.reg, LSL, 16));
385 MOV(AL, 0, parts.count.reg, reg_imm(parts.count.reg, LSL, 16));
433 ADD(AL, 0, Rs, Rs, reg_imm(parts.count.reg, LSR, 16));
434 ADD(AL, 0, zbase, zbase, reg_imm(Rs, LSL, 1));
449 ADD(AL, 0, parts.covPtr.reg, parts.covPtr.reg, reg_imm(Rx, LSL, 1));
556 MOV(AL, 0, fragment.reg, reg_imm(incoming.reg, LSR, incoming.l));
576 reg_imm(mAlphaSourc
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H A DARMAssembler.cpp510 uint32_t ARMAssembler::reg_imm(int Rm, int type, uint32_t shift) function in class:android::ARMAssembler
550 reg_imm(abs(Rm), type, shift);
555 return (1<<25) | (((uint32_t(Rm)>>31)^1)<<23) | reg_imm(abs(Rm), type, shift);
H A DARMAssemblerProxy.cpp93 uint32_t ARMAssemblerProxy::reg_imm(int Rm, int type, uint32_t shift) function in class:android::ARMAssemblerProxy
95 return mTarget->reg_imm(Rm, type, shift);
H A DARMAssembler.h71 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
H A DARMAssemblerProxy.h59 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
H A DARMAssemblerInterface.h81 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0;
H A DMIPSAssembler.h68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
H A DMIPSAssembler.cpp43 ** Refactored ARM address-mode static functions (imm(), reg_imm(), imm12_pre(), etc.)
234 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift) function in class:android::ArmToMipsAssembler
373 // this works with the imm(), reg_imm() methods above, which are directly

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