Searched refs:reg (Results 1 - 25 of 96) sorted by relevance

1234

/dalvik/libdex/
H A DDexDebugInfo.cpp120 static void emitLocalCbIfLive(void *cnxt, int reg, u4 endAddress, argument
123 if (localCb != NULL && localInReg[reg].live) {
124 localCb(cnxt, reg, localInReg[reg].startAddress, endAddress,
125 localInReg[reg].name,
126 localInReg[reg].descriptor,
127 localInReg[reg].signature == NULL
128 ? "" : localInReg[reg].signature );
182 int reg; local
190 reg
213 u2 reg; local
[all...]
H A DDexDebugInfo.h36 typedef void (*DexDebugNewLocalCb)(void *cnxt, u2 reg, u4 startAddress,
/dalvik/dexgen/src/com/android/dexgen/rop/code/
H A DRegisterSpec.java44 private final int reg; field in class:RegisterSpec
55 * @param reg {@code >= 0;} the register number
61 private static RegisterSpec intern(int reg, TypeBearer type, argument
63 theInterningItem.set(reg, type, local);
80 * @param reg {@code >= 0;} the register number
85 public static RegisterSpec make(int reg, TypeBearer type) { argument
86 return intern(reg, type, null);
94 * @param reg {@code >= 0;} the register number
100 public static RegisterSpec make(int reg, TypeBearer type, argument
106 return intern(reg, typ
121 makeLocalOptional( int reg, TypeBearer type, LocalItem local) argument
133 regString(int reg) argument
146 RegisterSpec(int reg, TypeBearer type, LocalItem local) argument
222 equals(int reg, TypeBearer type, LocalItem local) argument
273 hashCodeOf(int reg, TypeBearer type, LocalItem local) argument
596 private int reg; field in class:RegisterSpec.ForComparison
617 set(int reg, TypeBearer type, LocalItem local) argument
[all...]
H A DRegisterSpecSet.java33 * {@code null} or is an instance whose {@code reg}
163 * @param reg {@code >= 0;} the desired register number
167 public RegisterSpec get(int reg) { argument
169 return specs[reg];
172 throw new IllegalArgumentException("bogus reg");
201 for (int reg = 0; reg < length; reg++) {
202 RegisterSpec s = specs[reg];
226 for (int reg
[all...]
/dalvik/dx/src/com/android/dx/rop/code/
H A DRegisterSpec.java44 private final int reg; field in class:RegisterSpec
58 * @param reg {@code >= 0;} the register number
64 private static RegisterSpec intern(int reg, TypeBearer type, argument
67 theInterningItem.set(reg, type, local);
85 * @param reg {@code >= 0;} the register number
90 public static RegisterSpec make(int reg, TypeBearer type) { argument
91 return intern(reg, type, null);
99 * @param reg {@code >= 0;} the register number
105 public static RegisterSpec make(int reg, TypeBearer type, argument
111 return intern(reg, typ
126 makeLocalOptional( int reg, TypeBearer type, LocalItem local) argument
138 regString(int reg) argument
151 RegisterSpec(int reg, TypeBearer type, LocalItem local) argument
227 equals(int reg, TypeBearer type, LocalItem local) argument
278 hashCodeOf(int reg, TypeBearer type, LocalItem local) argument
603 private int reg; field in class:RegisterSpec.ForComparison
624 set(int reg, TypeBearer type, LocalItem local) argument
[all...]
H A DRegisterSpecSet.java32 * {@code null} or is an instance whose {@code reg}
162 * @param reg {@code >= 0;} the desired register number
166 public RegisterSpec get(int reg) { argument
168 return specs[reg];
171 throw new IllegalArgumentException("bogus reg");
200 for (int reg = 0; reg < length; reg++) {
201 RegisterSpec s = specs[reg];
225 for (int reg
[all...]
/dalvik/vm/compiler/codegen/x86/libenc/
H A Denc_base.h169 RegName reg;
317 Operand(RegName reg, OpndExt ext = OpndExt_None) : m_kind(getRegKind(reg)),
318 m_size(getRegSize(reg)),
319 m_ext(ext), m_reg(reg)
331 Operand(OpndSize sz, OpndKind kind, RegName reg, OpndExt ext = OpndExt_None) :
332 m_kind(kind), m_size(sz), m_ext(ext), m_reg(reg)
334 assert(m_size == getRegSize(reg));
335 assert(m_kind == getRegKind(reg));
477 RegName reg(voi
[all...]
H A Denc_wrapper.h183 int reg, bool isPhysical, LowOpndRegType type, char* stream);
185 int reg, bool isPhysical,
189 int reg, bool isPhysical, LowOpndRegType type, char* stream);
192 int reg, bool isPhysical, LowOpndRegType type, char* stream);
194 int reg, bool isPhysical,
199 int reg, bool isPhysical, LowOpndRegType type, char * stream);
202 int reg, bool isPhysical, LowOpndRegType type, char * stream);
204 int reg, bool isPhysical,
208 int reg, bool isPhysical,
211 int imm, int reg, boo
[all...]
/dalvik/vm/mterp/x86/
H A Dheader.S53 nick reg purpose
58 rINSTbh bh high byte of inst word, usually contains src/tgt reg names
111 #define SPILL(reg) movl reg##,reg##_SPILL(%ebp)
112 #define UNSPILL(reg) movl reg##_SPILL(%ebp),reg
113 #define SPILL_TMP1(reg) movl reg,TMP_SPILL
[all...]
/dalvik/vm/compiler/codegen/x86/
H A DNcgAot.h37 int reg, bool isPhysical);
40 int reg, bool isPhysical);
42 int reg, bool isPhysical);
H A DLower.h521 #define C_SCRATCH_3 scratchRegs[2] //scratch reg inside callee
563 int registerAlloc(int type, int reg, bool isPhysical, bool updateRef);
564 int registerAllocMove(int reg, int type, bool isPhysical, int srcReg);
565 int checkVirtualReg(int reg, LowOpndRegType type, int updateRef); //returns the physical register
566 int updateRefCount(int reg, LowOpndRegType type);
567 int updateRefCount2(int reg, int type, bool isPhysical);
570 int checkTempReg(int reg, int type, bool isPhysical, int vA);
571 bool checkTempReg2(int reg, int type, bool isPhysical, int physicalRegForVR);
574 int updateVirtualReg(int reg, LowOpndRegType type);
584 void updateGlue(int reg, boo
[all...]
H A DLowerHelper.cpp109 void set_reg_opnd(LowOpndReg* op_reg, int reg, bool isPhysical, LowOpndRegType type) { argument
113 op_reg->physicalReg = reg;
116 op_reg->logicalReg = reg;
290 //!update fields of LowOp and generate a x86 instruction that takes a single reg operand
294 int reg, LowOpndRegType type) {
295 stream = encoder_reg(m, size, reg, true, type, stream);
300 int reg, bool isPhysical, LowOpndRegType type) {
308 int regAll = registerAlloc(type, reg, isPhysical, true);
311 stream = encoder_reg(m, size, reg, isPhysical, type, stream);
316 int reg, boo
293 lower_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, LowOpndRegType type) argument
299 dump_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, LowOpndRegType type) argument
315 dump_reg_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, LowOpndRegType type) argument
320 lower_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, int reg2, LowOpndRegType type) argument
335 dump_reg_reg_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
349 dump_reg_reg_noalloc_dst(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
365 dump_reg_reg_noalloc_src(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
386 dump_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
419 lower_mem_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, MemoryAccessType mType, int mIndex, int reg, LowOpndRegType type, bool isMoves) argument
441 dump_mem_reg_noalloc(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
450 dump_mem_reg_noalloc_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
466 dump_mem_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
492 dump_moves_mem_reg(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
512 dump_movez_mem_reg(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
533 dump_movez_reg_reg(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
565 lower_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, int disp, int index_reg, int scale, int reg, LowOpndRegType type) argument
582 dump_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type) argument
610 lower_reg_mem_scale(Mnemonic m, OpndSize size, int reg, int base_reg, int disp, int index_reg, int scale, LowOpndRegType type) argument
621 dump_reg_mem_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type) argument
644 lower_reg_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, int disp, int base_reg, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
651 dump_reg_mem_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
660 dump_reg_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
680 lower_imm_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int imm, int reg, LowOpndRegType type, bool chaining) argument
686 dump_imm_reg_noalloc(Mnemonic m, OpndSize size, int imm, int reg, bool isPhysical, LowOpndRegType type) argument
693 dump_imm_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int imm, int reg, bool isPhysical, LowOpndRegType type, bool chaining) argument
745 lower_fp_mem(Mnemonic m, OpndSize size, int reg, int disp, int base_reg, MemoryAccessType mType, int mIndex) argument
751 dump_fp_mem(Mnemonic m, OpndSize size, int reg, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
766 lower_mem_fp(Mnemonic m, OpndSize size, int disp, int base_reg, MemoryAccessType mType, int mIndex, int reg) argument
772 dump_mem_fp(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg) argument
795 load_effective_addr(int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
804 load_effective_addr_scale(int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
872 compare_reg_mem(LowOp* op, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
880 compare_mem_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
889 compare_VR_reg_all(OpndSize size, int vA, int reg, bool isPhysical, Mnemonic m) argument
953 compare_VR_reg(OpndSize size, int vA, int reg, bool isPhysical) argument
959 compare_VR_ss_reg(int vA, int reg, bool isPhysical) argument
963 compare_VR_sd_reg(int vA, int reg, bool isPhysical) argument
1077 compare_imm_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1144 compare_ss_mem_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1161 compare_sd_mem_with_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1178 compare_fp_stack(bool pop, int reg, bool isDouble) argument
1199 test_imm_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1205 test_imm_mem(OpndSize size, int imm, int disp, int reg, bool isPhysical) argument
1211 alu_unary_reg(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical) argument
1244 alu_binary_imm_reg(OpndSize size, ALU_Opcode opc, int imm, int reg, bool isPhysical) argument
1255 alu_binary_mem_reg(OpndSize size, ALU_Opcode opc, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1266 alu_sd_binary_VR_reg(ALU_Opcode opc, int vA, int reg, bool isPhysical, bool isSD) argument
1319 alu_binary_VR_reg(OpndSize size, ALU_Opcode opc, int vA, int reg, bool isPhysical) argument
1381 alu_binary_reg_mem(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1401 alu_ss_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1409 alu_sd_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1417 push_reg_to_stack(OpndSize size, int reg, bool isPhysical) argument
1429 move_reg_to_mem(OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1438 move_reg_to_mem_noalloc(OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
1448 move_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1457 move_mem_to_reg_noalloc(OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical) argument
1467 move_ss_mem_to_reg_noalloc(int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical) argument
1475 move_ss_reg_to_mem_noalloc(int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
1483 movez_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1493 movez_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1500 movez_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1508 moves_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1520 moves_mem_to_reg(LowOp* op, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1529 move_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1538 move_reg_to_reg_noalloc(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1547 move_mem_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1554 move_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1564 move_reg_to_mem_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale) argument
1572 move_reg_to_mem_disp_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale) argument
1637 move_chain_to_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1644 move_imm_to_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1653 move_imm_to_reg_noalloc(OpndSize size, int imm, int reg, bool isPhysical) argument
1662 conditional_move_reg_to_reg(OpndSize size, ConditionCode cc, int reg1, bool isPhysical1, int reg, bool isPhysical) argument
1669 move_ss_mem_to_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1677 move_ss_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1684 move_sd_mem_to_reg(int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1691 move_sd_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1700 get_virtual_reg_all(u2 vB, OpndSize size, int reg, bool isPhysical, Mnemonic m) argument
1787 get_virtual_reg(u2 vB, OpndSize size, int reg, bool isPhysical) argument
1791 get_virtual_reg_noalloc(u2 vB, OpndSize size, int reg, bool isPhysical) argument
1801 set_virtual_reg_all(u2 vA, OpndSize size, int reg, bool isPhysical, Mnemonic m) argument
1860 set_virtual_reg(u2 vA, OpndSize size, int reg, bool isPhysical) argument
1864 set_virtual_reg_noalloc(u2 vA, OpndSize size, int reg, bool isPhysical) argument
1869 get_VR_ss(int vB, int reg, bool isPhysical) argument
1872 set_VR_ss(int vA, int reg, bool isPhysical) argument
1875 get_VR_sd(int vB, int reg, bool isPhysical) argument
1878 set_VR_sd(int vA, int reg, bool isPhysical) argument
1885 get_currentpc(int reg, bool isPhysical) argument
1892 simpleNullCheck(int reg, bool isPhysical, int vr) argument
1933 nullCheck(int reg, bool isPhysical, int exceptionNum, int vr) argument
2008 get_self_pointer(int reg, bool isPhysical) argument
2015 get_res_strings(int reg, bool isPhysical) argument
2043 get_res_classes(int reg, bool isPhysical) argument
2068 get_res_fields(int reg, bool isPhysical) argument
2093 get_res_methods(int reg, bool isPhysical) argument
2118 get_glue_method_class(int reg, bool isPhysical) argument
2127 get_glue_method(int reg, bool isPhysical) argument
2135 set_glue_method(int reg, bool isPhysical) argument
2144 get_glue_dvmdex(int reg, bool isPhysical) argument
2169 set_glue_dvmdex(int reg, bool isPhysical) argument
2177 get_suspendCount(int reg, bool isPhysical) argument
2186 get_return_value(OpndSize size, int reg, bool isPhysical) argument
2194 set_return_value(OpndSize size, int reg, bool isPhysical) argument
2210 get_exception(int reg, bool isPhysical) argument
2218 set_exception(int reg, bool isPhysical) argument
2238 savearea_from_fp(int reg, bool isPhysical) argument
[all...]
/dalvik/vm/compiler/codegen/
H A DRallocUtil.cpp62 regs[i].reg = regNums[i];
77 p[i].reg, p[i].inUse, p[i].pair, p[i].partner, p[i].live,
83 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg) argument
89 if (p[i].reg == reg) {
96 if (p[i].reg == reg) {
100 ALOGE("Tried to get info on a non-existant temp: r%d",reg);
110 (info1->partner == info2->reg) &&
111 (info2->partner == info1->reg));
124 dvmCompilerFlushReg(CompilationUnit *cUnit, int reg) argument
136 clobberRegBody(CompilationUnit *cUnit, RegisterInfo *p, int numTemps, int reg) argument
165 dvmCompilerClobber(CompilationUnit *cUnit, int reg) argument
342 dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg) argument
367 dvmCompilerIsLive(CompilationUnit *cUnit, int reg) argument
387 dvmCompilerIsTemp(CompilationUnit *cUnit, int reg) argument
412 dvmCompilerLockTemp(CompilationUnit *cUnit, int reg) argument
437 dvmCompilerResetDef(CompilationUnit *cUnit, int reg) argument
606 regClassMatches(int regClass, int reg) argument
617 dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg) argument
641 dvmCompilerMarkClean(CompilationUnit *cUnit, int reg) argument
647 dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg) argument
653 dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg) argument
[all...]
H A DRalloc.h82 extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
94 extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg);
96 extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg);
101 extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg);
103 extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg);
142 extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg);
144 extern void dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg);
153 extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg);
164 extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg);
188 extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg);
[all...]
/dalvik/vm/compiler/codegen/mips/
H A DRallocUtil.cpp64 regs[i].reg = regNums[i];
79 p[i].reg, p[i].inUse, p[i].pair, p[i].partner, p[i].live,
85 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg) argument
91 if (p[i].reg == reg) {
98 if (p[i].reg == reg) {
102 ALOGE("Tried to get info on a non-existant temp: r%d",reg);
112 (info1->partner == info2->reg) &&
113 (info2->partner == info1->reg));
126 flushReg(CompilationUnit *cUnit, int reg) argument
138 clobberRegBody(CompilationUnit *cUnit, RegisterInfo *p, int numTemps, int reg) argument
167 dvmCompilerClobber(CompilationUnit *cUnit, int reg) argument
343 dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg) argument
372 dvmCompilerIsLive(CompilationUnit *cUnit, int reg) argument
392 dvmCompilerIsTemp(CompilationUnit *cUnit, int reg) argument
417 dvmCompilerLockTemp(CompilationUnit *cUnit, int reg) argument
503 dvmCompilerResetDef(CompilationUnit *cUnit, int reg) argument
678 regClassMatches(int regClass, int reg) argument
689 dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg) argument
713 dvmCompilerMarkClean(CompilationUnit *cUnit, int reg) argument
719 dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg) argument
725 dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg) argument
1022 dvmCompilerFlushRegForV5TEVFP(CompilationUnit *cUnit, int reg) argument
[all...]
H A DRalloc.h86 extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
98 extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg);
100 extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg);
105 extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg);
107 extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg);
146 extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg);
148 extern void dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg);
157 extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg);
168 extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg);
192 extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg);
[all...]
/dalvik/dx/src/com/android/dx/ssa/
H A DSsaInsn.java108 * Returns whether or not the specified reg is the result reg.
110 * @param reg register to test
114 public boolean isResultReg(int reg) { argument
115 return result != null && result.getReg() == reg;
123 * @param reg new result register
125 public void changeResultReg(int reg) { argument
127 result = result.withReg(reg);
208 * @param reg the register in question
209 * @return true if the reg i
211 isRegASource(int reg) argument
[all...]
H A DPhiTypeResolver.java70 for (int reg = 0; reg < regCount; reg++) {
71 SsaInsn definsn = ssaMeth.getDefinitionForRegister(reg);
75 worklist.set(reg);
79 int reg;
80 while ( 0 <= (reg = worklist.nextSetBit(0))) {
81 worklist.clear(reg);
87 PhiInsn definsn = (PhiInsn)ssaMeth.getDefinitionForRegister(reg);
95 List<SsaInsn> useList = ssaMeth.getUseListForRegister(reg);
[all...]
/dalvik/dexgen/src/com/android/dexgen/dex/code/form/
H A DForm31c.java77 RegisterSpec reg;
81 reg = regs.get(0);
89 reg = regs.get(0);
90 if (reg.getReg() != regs.get(1).getReg()) {
100 if (!unsignedFitsInByte(reg.getReg())) {
H A DForm21c.java77 RegisterSpec reg;
81 reg = regs.get(0);
89 reg = regs.get(0);
90 if (reg.getReg() != regs.get(1).getReg()) {
100 if (!unsignedFitsInByte(reg.getReg())) {
/dalvik/dexgen/src/com/android/dexgen/dex/file/
H A DDebugInfoDecoder.java56 /** indexed by register, the last local variable live in a reg */
153 public int reg; field in class:DebugInfoDecoder.LocalEntry
164 public LocalEntry(int address, boolean isStart, int reg, int nameIndex, argument
168 this.reg = reg;
176 address, isStart ? "start" : "end", reg,
294 int reg = readUnsignedLeb128(bs);
298 address, true, reg, nameIdx, typeIdx, 0);
301 lastEntryForReg[reg] = le;
306 int reg
[all...]
/dalvik/dx/src/com/android/dx/dex/file/
H A DDebugInfoDecoder.java57 /** indexed by register, the last local variable live in a reg */
154 public int reg; field in class:DebugInfoDecoder.LocalEntry
165 public LocalEntry(int address, boolean isStart, int reg, int nameIndex, argument
169 this.reg = reg;
177 address, isStart ? "start" : "end", reg,
288 int reg = Leb128Utils.readUnsignedLeb128(bs);
292 address, true, reg, nameIdx, typeIdx, 0);
295 lastEntryForReg[reg] = le;
300 int reg
[all...]
/dalvik/dx/src/com/android/dx/ssa/back/
H A DRegisterAllocator.java78 * @param reg register
81 protected final int getCategoryForSsaReg(int reg) { argument
82 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
85 // an undefined reg
95 * @param reg {@code >= 0;} SSA register
99 protected final RegisterSpec getDefinitionSpecForSsaReg(int reg) { argument
100 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
109 * @param reg register in question
112 protected boolean isDefinitionMoveParam(int reg) { argument
113 SsaInsn defInsn = ssaMeth.getDefinitionForRegister(reg);
135 insertMoveBefore(SsaInsn insn, RegisterSpec reg) argument
[all...]
/dalvik/dx/src/com/android/dx/dex/code/form/
H A DForm21c.java79 RegisterSpec reg;
83 reg = regs.get(0);
91 reg = regs.get(0);
92 if (reg.getReg() != regs.get(1).getReg()) {
102 if (!unsignedFitsInByte(reg.getReg())) {
H A DForm31c.java79 RegisterSpec reg;
83 reg = regs.get(0);
91 reg = regs.get(0);
92 if (reg.getReg() != regs.get(1).getReg()) {
102 if (!unsignedFitsInByte(reg.getReg())) {

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