/external/qemu/ |
H A D | ppc-dis.c | 688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 689 #define RA NSI + 1 693 /* As above, but 0 in the RA field means zero, not r0. */ 694 #define RA0 RA + 1 697 /* The RA field in the DQ form lq instruction, which has special 702 /* The RA field in a D or X form instruction which is an updating 703 load, which means that the RA field may not be zero and may not 708 /* The RA field in an lmw instruction, which has special value 713 /* The RA field in a D or X form instruction which is an updating 714 store or an updating floating point load, which means that the RA 685 #define RA macro [all...] |
/external/qemu/tcg/ppc/ |
H A D | tcg-target.c | 397 #define RA(r) ((r)<<16) macro 407 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b)) 408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b)) 449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); 451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff)); 453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); 461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff)); 464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0)); 493 tcg_out32 (s, LWZ | RT (0) | RA (reg)); 494 tcg_out32 (s, MTSPR | RA ( [all...] |
/external/qemu/tcg/ppc64/ |
H A D | tcg-target.c | 394 #define RA(r) ((r)<<16) macro 405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b)) 406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b)) 447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb); 453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); 455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff)); 457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); 477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16); 478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16); 521 tcg_out32 (s, LD | RT (0) | RA (re [all...] |
/external/clang/test/CodeGenCXX/ |
H A D | devirtualize-virtual-function-calls-final.cpp | 165 struct RA { struct in namespace:Test9 170 struct RC final : public RA { 186 return static_cast<RA*>(x)->f();
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/external/llvm/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 533 unsigned RA = getRA(insn); local 546 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) 550 instr.addOperand(MCOperand::CreateReg(RA)); 554 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) 557 instr.addOperand(MCOperand::CreateReg(RA)); 562 if (RD == UNSUPPORTED || RA == UNSUPPORTED) 565 instr.addOperand(MCOperand::CreateReg(RA)); 579 if (RA == UNSUPPORTED) 582 instr.addOperand(MCOperand::CreateReg(RA)); 595 if (RD == UNSUPPORTED || RA [all...] |
/external/llvm/test/MC/MBlaze/ |
H A D | mblaze_pattern.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
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H A D | mblaze_shift.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
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H A D | mblaze_fpu.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
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H A D | mblaze_memory.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
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H A D | mblaze_typeb.s | 6 # TYPE B: OPCODE RD RA IMMEDIATE
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H A D | mblaze_special.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
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H A D | mblaze_typea.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
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/external/llvm/lib/Transforms/IPO/ |
H A D | DeadArgumentElimination.cpp | 145 void MarkValue(const RetOrArg &RA, Liveness L, 147 void MarkLive(const RetOrArg &RA); 149 void PropagateLiveness(const RetOrArg &RA); 571 /// MarkValue - This function marks the liveness of RA depending on L. If L is 573 /// such that RA will be marked live if any use in MaybeLiveUses gets marked 575 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument 578 case Live: MarkLive(RA); break; 585 Uses.insert(std::make_pair(*UI, RA)); 610 void DAE::MarkLive(const RetOrArg &RA) { argument 611 if (LiveFunctions.count(RA 623 PropagateLiveness(const RetOrArg &RA) argument [all...] |
/external/llvm/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 468 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex, 1391 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, 1393 if (RA == ATTR_MIXED && AllowMixed) 1395 else if (RA == ATTR_ALL_SET && !AllowMixed) 1513 bitAttr_t RA = ATTR_NONE; 1521 switch (RA) { 1528 RA = ATTR_ALL_SET; 1534 RA = ATTR_MIXED; 1543 reportRegion(RA, StartBit, BitIndex, AllowMixed); 1544 RA [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 126 // Reserve RA if in mips16 mode. 128 Reserved.set(Mips::RA);
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H A D | MipsLongBranch.cpp | 284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 295 .addReg(Mips::RA).addReg(Mips::AT); 296 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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H A D | MipsDelaySlotFiller.cpp | 243 // Add RA to RegDefs to prevent users of RA from going into delay slot. 245 RegDefs.insert(Mips::RA);
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 47 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local 50 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
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/external/llvm/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 503 const Argument *RA = cast<Argument>(RV); local 504 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo(); 538 const APInt &RA = RC->getValue()->getValue(); local 539 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth(); 542 return LA.ult(RA) ? -1 : 1; 547 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local 550 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop(); 559 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands(); 565 long X = compare(LA->getOperand(i), RA->getOperand(i)); 3842 const SCEV *RA [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 230 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument 241 RAReg = RA;
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/external/libffi/src/powerpc/ |
H A D | darwin.S | 200 .byte 0x41 ; CIE RA Column
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H A D | darwin_closure.S | 259 .byte 0x41 ; CIE RA Column
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H A D | linux64.S | 151 .byte 0x41 # CIE RA Column
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsBaseInfo.h | 203 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
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H A D | MipsMCTargetDesc.cpp | 77 InitMipsMCRegisterInfo(X, Mips::RA);
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