/external/llvm/lib/CodeGen/ |
H A D | LiveIntervalUnion.h | 120 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): argument 121 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), 136 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { argument 137 assert(VReg && LIU && "Invalid arguments"); 138 if (UserTag == UTag && VirtReg == VReg && 145 VirtReg = VReg; 163 bool isSeenInterference(LiveInterval *VReg) const;
|
H A D | LiveIntervalUnion.cpp | 151 LiveInterval *VReg = LiveUnionI.value(); local 152 if (VReg != RecentReg && !isSeenInterference(VReg)) { 153 RecentReg = VReg; 154 InterferingVRegs.push_back(VReg);
|
H A D | MachineFunction.cpp | 409 unsigned VReg = MRI.getLiveInVirtReg(PReg); local 410 if (VReg) { 411 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!"); 412 return VReg; 414 VReg = MRI.createVirtualRegister(RC); 415 MRI.addLiveIn(PReg, VReg); 416 return VReg;
|
H A D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local 38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); 40 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
|
H A D | MachineRegisterInfo.cpp | 250 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 252 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 254 if (I->second == VReg)
|
H A D | TailDuplication.cpp | 231 unsigned VReg = SSAUpdateVRs[i]; local 232 SSAUpdate.Initialize(VReg); 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); 240 SSAUpdate.AddAvailableValue(DefBB, VReg); 245 SSAUpdateVals.find(VReg); 253 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
|
H A D | RegAllocFast.cpp | 169 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 271 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); local 274 if (!VReg) { 276 VReg = MRI->createVirtualRegister(RC); 279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 280 return VReg; 302 unsigned VReg = getVR(Op, VRBaseMap); local 303 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 311 // shrink VReg's register class within reason. For example, if VReg == GR32 312 // and II requires a GR32_NOSP, just constrain VReg t [all...] |
H A D | InstrEmitter.h | 80 /// ConstrainForSubReg - Try to constrain VReg to a register class that 83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
|
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1RegisterInfo.cpp | 599 unsigned VReg = 0; 697 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); 702 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg, 705 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset); 709 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII, 712 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
|
H A D | ARMISelLowering.cpp | 2571 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); local 2572 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1905 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); local 1906 if (!VReg) 1907 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1909 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1924 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); local 1925 if (!VReg) 1926 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1928 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 2090 unsigned VReg; local 2092 VReg 2113 unsigned VReg; local 2140 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); local 2154 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local 2189 unsigned VReg; local 2212 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); local 2287 unsigned VReg; local [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local 212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 213 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local 324 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 325 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
|
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 457 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 459 unsigned getLiveInPhysReg(unsigned VReg) const;
|
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 638 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); local 649 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); 650 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); 833 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); local 844 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); 845 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); 1187 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); local 1188 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1189 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 1235 unsigned VReg local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 848 unsigned VReg = local 850 RegInfo.addLiveIn(VA.getLocReg(), VReg); 851 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 853 unsigned VReg = local 855 RegInfo.addLiveIn(VA.getLocReg(), VReg); 856 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1130 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local 1131 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1132 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 1180 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local 1181 RegInfo.addLiveIn(ArgRegs[i], VReg); 1182 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 338 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); local 339 RegInfo.addLiveIn(VA.getLocReg(), VReg); 340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 829 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); local 830 MF.getRegInfo().addLiveIn(PReg, VReg); 831 return VReg; 2959 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass); local 2962 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
|
/external/webkit/Source/JavaScriptCore/jit/ |
H A D | JIT.h | 536 void emitJumpSlowCaseIfNotJSCell(RegisterID, int VReg);
|
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 2048 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], local 2050 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2075 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], local 2077 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
|