TEMPLATE_CMPL_DOUBLE.S revision ba4fc8bfc1bccae048403bd1cea3b869dca61dd7 
1%default { "naninst":"mvn     r0, #0" }
2    /*
3     * For the JIT: incoming arguments are pointers to the arguments in r0/r1
4     *              result in r0
5     *
6     * Compare two floating-point values.  Puts 0, 1, or -1 into the
7     * destination register based on the results of the comparison.
8     *
9     * Provide a "naninst" instruction that puts 1 or -1 into r1 depending
10     * on what value we'd like to return when one of the operands is NaN.
11     *
12     * See OP_CMPL_FLOAT for an explanation.
13     *
14     * For: cmpl-double, cmpg-double
15     */
16    /* op vAA, vBB, vCC */
17    mov     r4, lr                      @ save return address
18    mov     r9, r0                      @ save copy of &arg1
19    mov     r10, r1                     @ save copy of &arg2
20    ldmia   r9, {r0-r1}                 @ r0/r1<- vBB/vBB+1
21    ldmia   r10, {r2-r3}                @ r2/r3<- vCC/vCC+1
22    LDR_PC_LR ".L__aeabi_cdcmple"       @ PIC way of "bl __aeabi_cdcmple"
23    bhi     .L${opcode}_gt_or_nan       @ C set and Z clear, disambiguate
24    mvncc   r0, #0                      @ (less than) r1<- -1
25    moveq   r0, #0                      @ (equal) r1<- 0, trumps less than
26    bx      r4
27
28    @ Test for NaN with a second comparison.  EABI forbids testing bit
29    @ patterns, and we can't represent 0x7fc00000 in immediate form, so
30    @ make the library call.
31.L${opcode}_gt_or_nan:
32    ldmia   r10, {r0-r1}                @ reverse order
33    ldmia   r9, {r2-r3}
34    LDR_PC_LR ".L__aeabi_cdcmple"       @ r0<- Z set if eq, C clear if <
35    movcc   r0, #1                      @ (greater than) r1<- 1
36    bxcc    r4
37    $naninst                            @ r1<- 1 or -1 for NaN
38    bx      r4
39
40