InterpAsm-armv5te-vfp.S revision 1df319e3674d993a07bc0ff1f56a5915410b5903
1a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 2a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * --> DO NOT EDIT <-- 5a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/header.S */ 8a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 10a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 11a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 13a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 14a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 15a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 17a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 18a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 21a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 22a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 23c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 24a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 25a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ARMv5 definitions and declarations. 26a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 27a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 28a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 29a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenARM EABI general notes: 30a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 31a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 32a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr4-r8 are available for general use 33a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr9 is given special treatment in some situations, but not for us 34a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr10 (sl) seems to be generally available 35a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr12 (ip) is scratch -- not preserved across method calls 37a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr13 (sp) should be managed carefully in case a signal arrives 38a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr14 (lr) must be preserved 39a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr15 (pc) can be tinkered with directly 40a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 41a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0 holds returns of <= 4 bytes 42a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 43a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 44a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 45a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 47a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 48a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 49a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 50a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden(i.e. the 5th arg). 51a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 52a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenVFP: single-precision results in s0, double-precision results in d0. 53a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 54a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 55a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 56a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 57a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 58a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 59a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMterp and ARM notes: 60a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 61a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenThe following registers have fixed assignments: 62a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 63a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden reg nick purpose 64a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r4 rPC interpreted program counter, used for fetching instructions 65a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 66a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r6 rGLUE MterpGlue pointer 671da12167d913efde56ec3b40491524b051679f2cAndy McFadden r7 rINST first 16-bit code unit of current instruction 681da12167d913efde56ec3b40491524b051679f2cAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 69a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 70a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMacros are provided for common operations. Each macro MUST emit only 71a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 72a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenunspecified registers or condition codes. 73a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 74a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 75a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* single-purpose registers, given names for clarity */ 76a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rPC r4 77a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rFP r5 78a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rGLUE r6 791da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rINST r7 801da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rIBASE r8 81a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 82a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* save/restore the PC and/or FP from the glue struct */ 83a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 84a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 85a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 86a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 87a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 88a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 89a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 90a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 91a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 92a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be done *before* something calls dvmThrowException. 93a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 94a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 97a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * It's okay to do this more than once. 98a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 99a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define EXPORT_PC() \ 100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Given a frame pointer, find the stack save area. 104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_INST() ldrh rINST, [rPC] 114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from the specified offset. Advances rPC 117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Because of the limited size of immediate constants on ARM, this is only 120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with this). 122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This must come AFTER anything that can throw an exception, or the 124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception catch may miss. (This also implies that it must come after 125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * EXPORT_PC().) 126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * here. 145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch a half-word code unit from an offset past the current PC. The 150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The "_S" variant works the same but treats the value as signed. 153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * byte of the halfword you want (lo/hi). 161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the instruction's opcode field into the specified register. 166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the prefetched instruction's opcode field into the specified register. 171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Get/set the 32-bit value from a Dalvik register. 184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 189ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 190d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 192ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert a virtual register index into an address. 195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add _reg, rFP, _vreg, lsl #2 198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is a #include, not a %include, because we want the C pre-processor 201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to expand the macros into assembler assignment statements. 202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#include "../common/asm-constants.h" 204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2057b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#if defined(WITH_JIT) 2067b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#include "../common/jit-config.h" 2077b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#endif 208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/platform.S */ 210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * CPU-version-specific defines 213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * one-way branch. 219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP. Does not modify LR. 221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC source 223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Jump to subroutine. 229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC_LR source 233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov lr, pc 234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDMFD_PC regs 243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {\regs,pc} 244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 246c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* 247c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Macro for data memory barrier; not meaningful pre-ARMv6K. 248c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 2490890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden.macro SMP_DMB 250c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.endm 251c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 2521df319e3674d993a07bc0ff1f56a5915410b5903Andy McFadden/* 2531df319e3674d993a07bc0ff1f56a5915410b5903Andy McFadden * Macro for data memory barrier; not meaningful pre-ARMv6K. 2541df319e3674d993a07bc0ff1f56a5915410b5903Andy McFadden */ 2551df319e3674d993a07bc0ff1f56a5915410b5903Andy McFadden.macro SMP_DMB_ST 2561df319e3674d993a07bc0ff1f56a5915410b5903Andy McFadden.endm 2571df319e3674d993a07bc0ff1f56a5915410b5903Andy McFadden 258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/entry.S */ 259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Interpreter entry point. 276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't have formal stack frames, so gdb scans upward in the code 280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to find the start of the function (a label with the %function type), 281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and then looks at the next few instructions to figure out what 282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * got pushed onto the stack. From this it figures out how to restore 283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the registers, including PC, for the previous stack frame. If gdb 284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sees a non-function label, it stops scanning, so either we need to 285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have nothing but assembler-local labels between the entry point and 286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the break, or we need to fake it out. 287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * When this is defined, we add some stuff to make gdb less confused. 289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define ASSIST_DEBUGGER 1 291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdRun 295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdRun, %function 296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This function returns a boolean "changeInterp" value. The return comes 302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * via a call to dvmMterpStdBail(). 303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdRun: 305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY1 \ 306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .save {r4-r10,fp,lr}; \ 307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY2 \ 309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .pad #4; \ 310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align 64 311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* save stack pointer, add magic word for debuggerd */ 317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up "named" registers, figure out entry point */ 320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rGLUE, r0 @ set rGLUE 32151ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee ldr r1, [r0, #offGlue_entryPoint] @ enum is 4 bytes in aapcs-EABI 322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryInstr @ usual case? 325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .Lnot_instr @ no, handle it 326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 327ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 328d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng.LentryInstr: 3297a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 330ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng /* Entry is always a possible trace start */ 331ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 332ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 3337a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r1, #0 @ prepare the value for the new state 3347a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r1, [r10, #offThread_inJitCodeCache] @ back to the interp land 3357a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 @ is profiling disabled? 3367a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#if !defined(WITH_SELF_VERIFICATION) 3377a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bne common_updateProfile @ profiling is enabled 3387a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#else 3397a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r2, [r10, #offThread_shadowSpace] @ to find out the jit exit state 3407a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq 1f @ profiling is disabled 3417a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 3427a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r3, #kSVSTraceSelect @ hot trace following? 3437a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng moveq r2,#kJitTSelectRequestHot @ ask for trace selection 3447a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq common_selectTrace @ go build the trace 3457a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r3, #kSVSNoProfile @ don't profile the next instruction? 3467a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq 1f @ intrepret the next instruction 3477a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b common_updateProfile @ collect profiles 3487a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#endif 3497a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng1: 350ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 351ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 352ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* start executing the instruction at rPC */ 354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 357ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_instr: 360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_returnFromMethod 362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_return: 364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown 366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 367ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 368ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lnot_throw: 369d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10,[rGLUE, #offGlue_jitResumeNPC] 370d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r2,[rGLUE, #offGlue_jitResumeDPC] 371ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 372ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lbad_arg 373ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp rPC,r2 374d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne .LentryInstr @ must have branched, don't resume 375d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#if defined(WITH_SELF_VERIFICATION) 376d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ glue->entryPoint will be set in dvmSelfVerificationSaveState 377d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunStart @ re-enter the translation after the 378d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ single-stepped instruction 379d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @noreturn 380d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#endif 381ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1, #kInterpEntryInstr 38251ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee str r1, [rGLUE, #offGlue_entryPoint] 383d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bx r10 @ re-enter the translation 384ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 385ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lbad_arg: 387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strBadEntryPoint 388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r1 holds value of entryPoint 389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAbort 391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdBail 395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdBail, %function 396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Restore the stack pointer and PC from the save point established on entry. 399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * LR to PC. 405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 bool changeInterp 409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdBail: 411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ return the changeInterp value 413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 @ un-align 64 414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references. 419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrBadEntryPoint: 421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrBadEntryPoint 422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionStart 425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmInstructionStart, %function 426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionStart = .L_OP_NOP 427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOP: /* 0x00 */ 432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOP.S */ 433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_inst, %function 440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_inst: 441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE: /* 0x01 */ 450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_16: /* 0x03 */ 479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE.S */ 494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide vA, vB */ 495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/from16 vAA, vBBBB */ 512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- BBBB 514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/16 vAAAA, vBBBB */ 528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- BBBB 530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- AAAA 531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 534445194bc141dc67e2f678aa1bbd5e59ca66254e5Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-result-wide vAA */ 606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-exception vAA */ 635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ r1<- 0 639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN: /* 0x0f */ 654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 64-bit value. Copies the return value into the "glue" 673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* return-wide vAA */ 676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_4: /* 0x12 */ 704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_4.S */ 705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/4 vA, #+B */ 706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_16: /* 0x13 */ 718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_16.S */ 719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/16 vAA, #+BBBB */ 720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST: /* 0x14 */ 730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST.S */ 731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const vAA, #+BBBBbbbb */ 732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/high16 vAA, #+BBBB0000 */ 746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/16 vAA, #+BBBB */ 759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #0 @ r0<- 00000000 810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING: /* 0x1a */ 820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING.S */ 821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBB */ 822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_resolve 829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBBBBBB */ 839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/class vAA, Class@BBBB */ 858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_CLASS_resolve 865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Synchronize on an object. 876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-enter vAA */ 878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null object, throw an exception 884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLockObject @ call(self, obj) 886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ exception raised, bail out 891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlock an object. 901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exceptions that occur when unlocking a monitor need to appear as 903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if they happened at the following instruction. See the Dalvik 904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction spec. 905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-exit vAA */ 907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ before fetch: export the PC 909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 9116bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq 1f @ yes 912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 9166bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq common_exceptionThrown @ yes, exception is pending 917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9196bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee1: 9206bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee FETCH_ADVANCE_INST(1) @ advance before throw 9216bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee b common_errNullObject 922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if a cast from one class to another is allowed. 929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* check-cast vAA, class@BBBB */ 931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r3) @ r9<- object 934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ is object null? 936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolved: 943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_okay: 946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if an object reference is an instance of a class. 956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Most common situation is a non-null object, being compared against 958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an already-resolved class. 959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* instance-of vA, vB, class@CCCC */ 961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- CCCC 969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ARRAY_LENGTH.S */ 983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return the length of an array. 985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yup, fail 992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ vB<- length 996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 1001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 1002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new instance of a class. 1004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-instance vAA, class@BBBB */ 1006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocObject @ r0<- new object 1020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Allocate an array of objects, specified with the array class 1028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and a count. 1029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The verifier guarantees that this is an array class, so we don't 1031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * check for it here. 1032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-array vA, vB, class@CCCC */ 1034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 1035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- CCCC 1036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ check length 1040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_errNegativeArraySize @ negative length, bail 1042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for resolve, alloc 1044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC(); 1115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ 0 means an exception is thrown 1117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ has exception 1118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW: /* 0x27 */ 1125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW.S */ 1126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception object in the current thread. 1128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* throw vAA */ 1130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 11338ba2708ea118381f2df5ca55b9bad2ae4c050504Andy McFadden EXPORT_PC() @ exception handler can throw 1134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 1135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, throw an NPE instead 1136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ bypass dvmSetException, just store it 1137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 1139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO: /* 0x28 */ 1143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO.S */ 1144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 8-bit offset. 1146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto +AA */ 1151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1155ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1156ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1158ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1159ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1162ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1163ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1164ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1165ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1166ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_16: /* 0x29 */ 1171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_16.S */ 1172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 16-bit offset. 1174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/16 +AAAA */ 1179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1182ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1183ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1184ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1185ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1186ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1189ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1193ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_32: /* 0x2a */ 1198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_32.S */ 1199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 32-bit offset. 1201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction doesn't affect the V flag, so we need to clear it 1208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * explicitly. 1209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/32 +AAAAAAAA */ 1211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, ip @ (clear V flag during stall) 1214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1217ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1218ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1220ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1221ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1224ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1225ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1226ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1227ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1228ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1254ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1255ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1256ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1258ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1259ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1260ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1261ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1265ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1292ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1293ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1295ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1296ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1299ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1300ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1301ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1302ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1303ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1309968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13288fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13318fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13338fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13428fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1348968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13678fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13708fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13728fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13818fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1387968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14068fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14098fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14118fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14208fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1426968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14458fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14488fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14508fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14598fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * register based on the results of the comparison. 1469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We load the full values with LDM, but in practice many values could 1471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be resolved by only looking at the high word. This could be made 1472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If we just wanted to set condition flags, we could do this: 1475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subs ip, r0, r2 1476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sbcs ip, r1, r3 1477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subeqs ip, r0, r2 1478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * us a constant 5-cycle path plus a branch at the end to the 1482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction epilogue code. The multi-compare approach below needs 1483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in the worst case (the 64-bit values are equal). 1485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* cmp-long vAA, vBB, vCC */ 1487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 1488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 1491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt .LOP_CMP_LONG_greater 1498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CMP_LONG_less 1501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQ: /* 0x32 */ 1506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQ.S */ 1507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1527ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1528ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1529ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1530ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1531ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1532ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1533ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1536ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NE: /* 0x33 */ 1542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NE.S */ 1543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1564ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1565ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1566ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1567ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1568ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1572ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LT: /* 0x34 */ 1578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LT.S */ 1579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1599ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1600ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1601ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1602ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1603ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1604ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1605ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1608ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GE: /* 0x35 */ 1614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GE.S */ 1615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1635ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1636ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1637ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1638ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1639ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1640ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1641ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1644ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GT: /* 0x36 */ 1650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GT.S */ 1651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1671ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1672ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1673ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1674ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1675ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1676ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1677ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1680ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LE: /* 0x37 */ 1686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LE.S */ 1687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1707ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1708ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1709ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1710ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1711ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1712ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1713ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1716ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1740ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1741ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1742ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1743ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1744ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1745ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1748ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1749ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1750ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1751ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1752ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1776ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1777ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1778ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1779ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1780ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1781ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1784ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1785ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1786ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1787ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1788ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1812ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1813ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1814ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1815ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1816ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1817ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1820ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1821ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1822ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1823ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1824ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1848ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1849ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1850ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1851ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1852ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1853ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1854ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1855ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1856ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1857ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1860ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1884ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1885ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1886ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1887ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1888ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1889ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1890ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1891ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1892ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1893ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1896ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1920ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1921ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1922ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1923ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1924ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1925ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1928ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1929ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1930ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1931ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1932ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET: /* 0x44 */ 1986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 1987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 1989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 1992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 1997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 1999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aget-wide vAA, vBB, vCC */ 2023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT: /* 0x4b */ 2203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aput-wide vAA, vBB, vCC */ 2240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null array object? 2276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r9) @ r9<- vAA 2277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r3 @ compare unsigned index, length 2281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET: /* 0x52 */ 2416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish @ no, already resolved 2431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish 2437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 2443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Wide 32-bit instance field get. 2445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide vA, vB, field@CCCC */ 2447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish 2461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish 2488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish 2517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish 2546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish 2575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish 2604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT: /* 0x59 */ 2610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2614919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ no, already resolved 2625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ yes, finish up 2631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 2637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide vA, vB, field@CCCC */ 2638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2659919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit instance field put. 2660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2661919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput-object, iput-object-volatile 2662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2689919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2718919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2747919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2776919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET: /* 0x60 */ 2799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_finish: @ field ptr in r0 2813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28140890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SGET handler. 2827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sget-wide vAA, field@BBBB */ 2829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_finish: 2836861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2837861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 2838861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 28396e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2840861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 2841861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2842861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 2843861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2845861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28680890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28950890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29220890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29490890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29760890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT: /* 0x67 */ 2987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 2988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 2990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2991919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 3000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_finish: @ field ptr in r0 3001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 30050890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SPUT handler. 3015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sput-wide vAA, field@BBBB */ 3017861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 3018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3019861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 3020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3021861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 3022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3023861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 3024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3025861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 3026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3027861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 3028861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 3029861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 3030861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 30316e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 3032861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 3033861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 3034861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 3035861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 3036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3042919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit SPUT handler for objects 3043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3044919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput-object, sput-object-volatile 3045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3052919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_finish @ no, continue 3053919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 3054919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee EXPORT_PC() @ resolve() could throw, so export now 3055919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 3056919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3057919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ success? 3058919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_finish @ yes, finish 3059919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee b common_exceptionThrown @ no, handle exception 3060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3070919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 30840890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3097919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31110890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3124919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31380890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3151919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31650890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_finish: 3258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue on 3260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ yes, continue on 3280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue 3286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3314de75089fb7216d19e9c22cce4dc62a49513477d3Carl Shapiro b common_invokeMethodNoRange @ jump to common handler 3315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue on 3419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ yes, continue on 3441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue 3447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3477de75089fb7216d19e9c22cce4dc62a49513477d3Carl Shapiro b common_invokeMethodRange @ jump to common handler 3478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_INT: /* 0x7b */ 3499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_INT.S */ 3500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_INT: /* 0x7c */ 3526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_INT.S */ 3527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_LONG.S */ 3554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_LONG.S */ 3582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ optional op; may set condition codes 3599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_FLOAT.S */ 3610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_DOUBLE.S */ 3637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_LONG.S */ 3665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3691968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3692968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 370138214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitos s1, s0 @ s1<- op 3707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3716968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3717968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 372638214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitod d0, s0 @ d0<- op 3732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 3744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 3745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 3746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 3751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 3754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopNarrower.S */ 3761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 32-bit quantity in r0. 3765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: long-to-float, double-to-int, double-to-float 3767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (This would work for long-to-int, but that instruction is actually 3769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an exact match for OP_MOVE.) 3770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 3782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3817968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3818968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 382738214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizs s1, s0 @ s1<- op 3833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3871968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3872968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 388138214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtds d0, s0 @ d0<- op 3887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3896968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3897968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 390638214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizd s0, d0 @ s0<- op 3912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3951968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3952968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 396138214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtsd s0, d0 @ s0<- op 3967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_BYTE.S */ 3977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #24 @ optional op; may set condition codes 3992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 3994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 4003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_CHAR.S */ 4004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 4021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_SHORT.S */ 4031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT: /* 0x90 */ 4057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT.S */ 4058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT: /* 0x91 */ 4098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT.S */ 4099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT: /* 0x92 */ 4139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT.S */ 4140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT: /* 0x93 */ 4181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT.S */ 4182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT: /* 0x94 */ 4222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT.S */ 4223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 4257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT: /* 0x95 */ 4264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT.S */ 4265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT: /* 0x96 */ 4305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT.S */ 4306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT: /* 0x97 */ 4346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT.S */ 4347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT: /* 0x98 */ 4387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT.S */ 4388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT: /* 0x99 */ 4428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT.S */ 4429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT: /* 0x9a */ 4469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT.S */ 4470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply. 4601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WX 4604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * x YZ 4605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * -------- 4606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ZW ZX 4607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * YW YX 4608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The low word of the result holds ZX, the high word holds 4610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * it doesn't fit in the low 64 bits. 4612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most ARM math operations, multiply instructions have 4614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * restrictions on using the same register more than once (Rd and Rm 4615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * cannot be the same). 4616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long vAA, vBB, vCC */ 4618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 4626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_MUL_LONG_finish 4633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG: /* 0x9f */ 4681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG.S */ 4682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG.S */ 4727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 4760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG.S */ 4771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long vAA, vBB, vCC */ 4866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_finish 4883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long vAA, vBB, vCC */ 4895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_finish 4912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long vAA, vBB, vCC */ 4924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_finish 4941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4945968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4946968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 4947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 4953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 4955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 495938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 496138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 4962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 4963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 4966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 4969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 4975968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 4976968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 4977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 4983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 4985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 498938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 499138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 4992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 4993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 4996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 4999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 5005968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5006968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 501938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 502138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 5026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5035968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5036968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 504938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 505138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 5056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 5068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 5071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 5078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 5082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 5089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 5090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 5098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 5102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5107968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5108968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 512138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 512338214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ s2<- op 5128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5137968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5138968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 515138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 515338214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ s2<- op 5158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5167968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5168968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 518138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 518338214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ s2<- op 5188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5197968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5198968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 521138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 521338214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ s2<- op 5218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 5230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 5242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 5263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 5267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_2ADDR.S */ 5430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 5462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_2ADDR.S */ 5470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_2ADDR.S */ 5509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See OP_MUL_LONG for an explanation. 5790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * again we stuff it into rINST. 5793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long/2addr vA, vB */ 5795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 5803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 5929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG_2ADDR.S */ 5940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 5970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 5971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 5981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 6022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long/2addr vA, vB */ 6027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_2ADDR_finish 6043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long/2addr vA, vB */ 6053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_2ADDR_finish 6069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long/2addr vA, vB */ 6079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_2ADDR_finish 6095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6099968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6100968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 611138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 611338214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 6119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6127968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6128968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 613938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 614138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 6147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6155968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6156968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 616738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 616938214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 6175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6183968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6184968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 619538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 619738214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 6203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 6214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 6233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 6242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6251968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6252968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 626438214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 626638214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ d2<- op 6272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6280968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6281968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 629338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 629538214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ d2<- op 6301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6309968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6310968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 632238214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 632438214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ d2<- op 6330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6338968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6339968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 635138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 635338214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ d2<- op 6359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 6400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT16.S */ 6410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT.S */ 6446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT16.S */ 6483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT16.S */ 6520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT16.S */ 6556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT16.S */ 6593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT16.S */ 6629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT16.S */ 6665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 6930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 6931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 6968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 6969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7119c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IGET_VOLATILE: /* 0xe3 */ 7120c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET_VOLATILE.S */ 7121c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET.S */ 7122c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7123c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field get. 7124c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7125c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7126c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7127c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7128c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7129c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7130c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7131c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7132c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7133c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7134c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7135c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_VOLATILE_finish @ no, already resolved 7136c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7137c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7138c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7139c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7140c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 7141c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_VOLATILE_finish 7142c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7147c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7148c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT_VOLATILE.S */ 7149c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT.S */ 7150c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7151c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field put. 7152c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7153919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7154c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7155c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7156c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7157c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7158c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7159c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7160c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7161c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7162c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7163c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 7164c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7165c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7166c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7167c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7168c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 7169c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7170c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7175c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SGET_VOLATILE: /* 0xe5 */ 7176c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET_VOLATILE.S */ 7177c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET.S */ 7178c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7179c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SGET handler. 7180c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7181c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7182c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7183c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7184c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7185c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7186c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7187c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7188c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7189c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7190c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7191c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 71920890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 7193c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7194c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7195c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 7196c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7197c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7202c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7203c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT_VOLATILE.S */ 7204c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT.S */ 7205c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7206c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SPUT handler. 7207c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7208919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7209c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7210c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7211c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7212c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7213c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7214c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7215c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7216c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7217c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7218c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7219c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7220c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 7221c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 72220890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 7223c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 7224c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7229c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7230c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7231c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET.S */ 7232c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7233c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field get. 7234c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7235c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7236c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7237c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7238c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7239c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7240c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7241c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7242c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7243c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7244c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7245c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 7246c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7247c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7248c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7249c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7250c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 7251c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_OBJECT_VOLATILE_finish 7252c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 72575387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 72585387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 72595387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 72605387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Wide 32-bit instance field get. 72625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iget-wide vA, vB, field@CCCC */ 72645387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72655387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72665387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72675387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72685387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72695387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72705387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72715387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 72725387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72735387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72745387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72755387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72765387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 72775387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish 72785387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 72835387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 72845387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 72855387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 72865387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iput-wide vA, vB, field@CCCC */ 72875387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72885387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72895387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72905387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72915387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72925387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72935387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72945387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72955387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72965387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72975387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72985387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72995387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 73005387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 73015387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 73065387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 73075387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 73085387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 73095387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 73105387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SGET handler. 73115387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 73125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sget-wide vAA, field@BBBB */ 73135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 73145387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 73155387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 73165387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 73175387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 73185387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 73195387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_finish: 7320861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7321861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7322861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 73236e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7324861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7325861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7326861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7327861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 73285387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7329861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 73305387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 73315387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 73365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 73375387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 73385387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 73395387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 73405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SPUT handler. 73415387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 73425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sput-wide vAA, field@BBBB */ 7343861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 73445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7345861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 73465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7347861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 73485387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7349861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 73505387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7351861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 73525387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7353861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7354861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 7355861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7356861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 73576e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7358861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7359861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7360861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7361861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 7362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 736696516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 736796516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a throw-verification-error instruction. This throws an 7378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception for an error discovered during verification. The 7379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op AA, ref@BBBB */ 7382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 7384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ export the PC 7385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowVerificationError @ always throws 7387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ handle exception 7388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Execute a "native inline" instruction. 7395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7396b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7397b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7399b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7400b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7401b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ can throw 7407b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 7409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [sp] @ push &glue->retval 7410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ pop stack 7412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ test boolean result of inline 7413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7420b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7421b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7422b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7423b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7424b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7425b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7426b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7427b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7428b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7429b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7430b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7431b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7432b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7433b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7434b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7435b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7436b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7437b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7438b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7439b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7440b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7441b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7442b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7443b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7444b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7445b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7446b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7461291758c5c4902900c6f86794ba8ab9cad9b26197Andy McFadden.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7462291758c5c4902900c6f86794ba8ab9cad9b26197Andy McFadden/* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 74631df319e3674d993a07bc0ff1f56a5915410b5903Andy McFadden SMP_DMB_ST 7464291758c5c4902900c6f86794ba8ab9cad9b26197Andy McFadden b common_returnFromMethod 7465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7492b48a4d53bc3349b5c99f8b87a396e7374e2d335cDave Butcher FETCH(ip, 1) @ ip<- field byte offset 7493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7496b48a4d53bc3349b5c99f8b87a396e7374e2d335cDave Butcher ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7529919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee /* For: iput-quick */ 7530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A(+) 7550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 7551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 7552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ check object for null 7555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- field byte offset 7558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7567919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee /* For: iput-object-quick */ 7568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7577919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 7578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7580919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 7581919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card on non-null store 7582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7695c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7696c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7697919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee/* File: armv5te/OP_IPUT_OBJECT.S */ 7698c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7699919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit instance field put. 7700c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7701919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput-object, iput-object-volatile 7702c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7703c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7704c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7705c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7706c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7707c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7708c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7709c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7710c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7711c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 7712c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7713c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7714c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7715c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7716c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 7717c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7718c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7723c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7724c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7725c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET.S */ 7726c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7727c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SGET handler. 7728c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7729c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7730c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7731c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7732c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7733c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7734c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7735c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7736c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7737c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7738c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7739c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 77400890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 7741c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7742c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7743c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 7744c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7745c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7750c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7751c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7752919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee/* File: armv5te/OP_SPUT_OBJECT.S */ 7753c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7754919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit SPUT handler for objects 7755c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7756919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput-object, sput-object-volatile 7757c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7758c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7759c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7760c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7761c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7762c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7763c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7764919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7765919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7766919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee EXPORT_PC() @ resolve() could throw, so export now 7767919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7768919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7769919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ success? 7770919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7771919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee b common_exceptionThrown @ no, handle exception 7772919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee 7773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionEnd 7787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionEnd: 7788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 7790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Sister implementations 7792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterStart 7795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmSisterStart, %function 7796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 7797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 4 7798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterStart: 7799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING */ 7801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (String ref) 7805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_resolve: 7808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBBBBBB (String ref) 7824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_CLASS */ 7839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the Class has not yet been resolved. 7842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (Class ref) 7843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_CLASS_resolve: 7846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- Class reference 7851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CHECK_CAST */ 7859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_fullcheck: 7867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ class of the object that failed to be cast. 7873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ about to throw 7874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .LstrClassCastExceptionPtr 7876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowExceptionWithClassMessage 7878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds BBBB 7884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolve: 7887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- BBBB 7890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastExceptionPtr: 7900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrClassCastException 7901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INSTANCE_OF */ 7903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_fullcheck: 7911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_INSTANCE_OF_store 7913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds boolean result 7916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_store: 7919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test succeeded, save and bail. 7926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_trivial: 7929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ indicate success 7930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r3 holds BBBB 7940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolve: 7943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r3 @ r1<- BBBB 7946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 7953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_INSTANCE */ 7958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 32 @ minimize cache lines 7960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 7967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Class initialization required. 7971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class object 7973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_needinit: 7975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0 @ save r0 7976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInitClass @ initialize class 7977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ check boolean result 7978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ restore r0 7979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ failed, deal with init exception 7981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds BBBB 7986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolve: 7988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 7995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationErrorPtr: 7997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInstantiationError 7998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_ARRAY */ 8000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolve class. (This is an uncommon case.) 8004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 8006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds class ref CCCC 8007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_resolve: 8009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ r9<- length (save) 8011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- CCCC 8012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 8013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 8015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ r1<- length (restore) 8017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 8018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_NEW_ARRAY_finish 8019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Finish allocation. 8022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class 8024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 8025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_finish: 8027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 8028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 8029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 8030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 8032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ vA<- r0 8036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 8039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 8043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 8044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_continue: 8046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8048919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 8049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 8050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 8051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8054919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp rINST, #'I' @ array of ints? 8055919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'L' @ array of objects? 8056919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'[' @ array of arrays? 8057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 8058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 8059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 8061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8064919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8065919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str rINST, [rGLUE, #offGlue_retval+4] @ retval.h <- type 8066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 8068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 8070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 8072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 8074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 8082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 8083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 8084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 8085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 8086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 8087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 8097919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [rGLUE, #offGlue_retval] @ r0<- object 8098919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r1, [rGLUE, #offGlue_retval+4] @ r1<- type 8099919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8100919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8101919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #'I' @ Is int array? 8102919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card if not 8103919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ execute it 8104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 8107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 8108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 8110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 8111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 8113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 8114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) @ define in one or the other, not both 8116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 8117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 8118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 8123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 8127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 8128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 8130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8132919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 8133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 8135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8138919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp rINST, #'I' @ array of ints? 8139919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'L' @ array of objects? 8140919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'[' @ array of arrays? 8141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 8142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 8143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 8145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8148919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8149919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str rINST, [rGLUE, #offGlue_retval+4] @ retval.h <- type 8150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 8152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 8154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 8156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 8166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 8167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 8168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 8169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 8170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 8171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 8181919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [rGLUE, #offGlue_retval] @ r0<- object 8182919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r1, [rGLUE, #offGlue_retval+4] @ r1<- type 8183919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8184919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8185919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #'I' @ Is int array? 8186919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card if not 8187919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ execute it 8188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 8191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 8192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 8195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 8197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 8198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) @ define in one or the other, not both 8200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 8201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 8202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_FLOAT */ 8207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_FLOAT_finish: 8208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_FLOAT */ 8212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_FLOAT_finish: 8213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_DOUBLE */ 8217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_DOUBLE_finish: 8218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_DOUBLE */ 8222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_DOUBLE_finish: 8223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMP_LONG */ 8227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_less: 8229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, #0 @ r1<- -1 8230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ instead, we just replicate the tail end. 8232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_greater: 8238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ r1<- 1 8239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to _finish 8240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_finish: 8242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_AGET_WIDE */ 8248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_AGET_WIDE_finish: 8250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_WIDE */ 8258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_WIDE_finish: 8260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_OBJECT */ 8267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = vBB (arrayObj) 8270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = vAA (obj) 8271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = offset into array (vBB + vCC * width) 8272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_finish: 8274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ storing null reference? 8275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ okay? 8280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errArrayStore @ no 8281919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8282919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ get biased CT base 8283919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r10, #offArrayObject_contents @ r0<- pointer to slot 8284919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 8285919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r9, [r10] @ vBB[vCC]<- vAA 8286919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strb r2, [r2, r10, lsr #GC_CARD_SHIFT] @ mark card 8287919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 8288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_skip_check: 8289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET */ 8295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_finish: 8302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83070890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_WIDE */ 8316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_WIDE_finish: 8323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8326c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 0 8327861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r9, r3 @ r0<- address of field 83286e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 8329861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 8330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8331861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 8332861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8334861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden and r2, r2, #15 @ r2<- A 8335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_OBJECT */ 8341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_OBJECT_finish: 8348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83530890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BOOLEAN */ 8362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BOOLEAN_finish: 8369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83740890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BYTE */ 8383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BYTE_finish: 8390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83950890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_CHAR */ 8404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_CHAR_finish: 8411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 84160890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_SHORT */ 8425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_SHORT_finish: 8432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 84370890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT */ 8446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_finish: 8453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 84620890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_WIDE */ 8467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_WIDE_finish: 8474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8482861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 8483c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 0 8484861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r9, r3 @ r2<- target address 84856e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 8486861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 8487861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 8488861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 8489861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 8490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_OBJECT */ 8492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_OBJECT_finish: 8499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8505919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8508919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r9, r3 @ r9<- direct ptr to target location 8509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85100890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8511919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [r9] @ obj.field (8/16/32 bits)<- r0 8512919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ stored a null reference? 8513919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 8514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BOOLEAN_finish: 8524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85330890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BYTE */ 8538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BYTE_finish: 8545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85540890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_CHAR */ 8559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_CHAR_finish: 8566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85750890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_SHORT */ 8580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_SHORT_finish: 8587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85960890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET */ 8601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_resolve: 8607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_finish @ yes, finish 8613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_WIDE */ 8616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8620861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8621861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 8622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_resolve: 8624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_OBJECT */ 8633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_resolve: 8639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BOOLEAN */ 8648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_resolve: 8654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BYTE */ 8663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_resolve: 8669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_CHAR */ 8678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_resolve: 8684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_SHORT */ 8693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_resolve: 8699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT */ 8708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_resolve: 8714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_finish @ yes, finish 8720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_WIDE */ 8723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: &fp[AA] 8728861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8729861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 8730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_resolve: 8732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8737861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 8738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_OBJECT */ 8742919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee.LOP_SPUT_OBJECT_finish: @ field ptr in r0 8743919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee mov r2, rINST, lsr #8 @ r2<- AA 8744919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8745919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_VREG(r1, r2) @ r1<- fp[AA] 8746919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8747919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 8748919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r0, #offStaticField_value @ r0<- pointer to store target 8749919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee @ no-op @ releasing store 8750919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r1, [r0] @ field<- vAA 8751919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #0 @ stored a null object? 8752919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ mark card if not 8753919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 8754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_resolve: 8762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BYTE */ 8771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_resolve: 8777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_CHAR */ 8786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_resolve: 8792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_SHORT */ 8801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_resolve: 8807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_continue: 8823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER */ 8833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_continue: 8840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_resolve: 8851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_nsm: 8863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT */ 8867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_resolve: 8874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the float in r0 to a long in r0/r1. 8954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenf2l_doconv: 8960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, lr} 8961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0x5f000000 @ (float)maxlong 8962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r4, r0 8963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0xdf000000 @ (float)minlong 8971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (80000000) 8974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r4 8979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpeq @ is arg == self? 8980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmeqfd sp!, {r4, pc} 8983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_f2lz @ convert float to long 8986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, pc} 8987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddend2l_doconv: 8997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, r5, lr} @ save regs 89985162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 89995162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 90005162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 9001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align for EABI 90025162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 9003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r5, r1 @ and r1 9004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 9005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 9006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 9007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 9008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 9009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 9011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 90125162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 90135162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 90145162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 9015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmple @ is arg <= minlong? 9016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 9017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (8000000000000000) 9018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 9019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 9020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 9022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 9023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r4 @ compare against self 9024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r5 9025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpeq @ is arg == self? 9026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 9027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 9028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f 9029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 9031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 9032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_d2lz @ convert double to long 9033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 9035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 9036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, r5, pc} 9037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_MUL_LONG */ 9039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_MUL_LONG_finish: 9041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 9043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG */ 9046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_finish: 9048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 9049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG */ 9054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_finish: 9056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 9057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG */ 9062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_finish: 9064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 9065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 9070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_2ADDR_finish: 9072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 9077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_2ADDR_finish: 9079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 9084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_2ADDR_finish: 9086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9090c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IGET_VOLATILE */ 9091c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9092c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9093c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9094c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9095c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9096c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9097c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IGET_VOLATILE_finish: 9098c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9099c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9100c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9101c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9102c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 91030890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 9104c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 9105c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9106c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r2, r2, #15 @ r2<- A 9107c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9108c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 9109c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9110c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9111c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IPUT_VOLATILE */ 9112c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9113c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9114c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9115c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9116c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9117c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9118c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IPUT_VOLATILE_finish: 9119c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9120c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 9121c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9122c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r1, r1, #15 @ r1<- A 9123c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9124c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 9125c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9126c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9127c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 91280890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 9129c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 9130c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9131c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9132c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SGET_VOLATILE */ 9133c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9134c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9135c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9136c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9137c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9138c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_VOLATILE_resolve: 9139c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9140c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9141c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9142c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9143c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9144c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SGET_VOLATILE_finish @ yes, finish 9145c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9146c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9147c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SPUT_VOLATILE */ 9148c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9149c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9150c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9151c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9152c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9153c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SPUT_VOLATILE_resolve: 9154c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9155c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9156c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9157c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9158c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9159c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SPUT_VOLATILE_finish @ yes, finish 9160c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9161c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9162c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IGET_OBJECT_VOLATILE */ 9163c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9164c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9165c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9166c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9167c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9168c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9169c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IGET_OBJECT_VOLATILE_finish: 9170c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9171c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9172c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9173c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9174c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 91750890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 9176c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 9177c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9178c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r2, r2, #15 @ r2<- A 9179c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9180c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 9181c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9182c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 91835387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IGET_WIDE_VOLATILE */ 91845387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91855387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 91865387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 91875387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 91885387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 91895387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 91905387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IGET_WIDE_VOLATILE_finish: 91915387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 91925387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 91935387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 9194c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 1 9195861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r9, r3 @ r0<- address of field 91966e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 9197861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 91985387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 9199861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9200861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 92015387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9202861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden and r2, r2, #15 @ r2<- A 92035387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 92045387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 92055387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 92065387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 92075387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92085387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IPUT_WIDE_VOLATILE */ 92095387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92105387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 92115387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 92125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 92135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 92145387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 92155387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IPUT_WIDE_VOLATILE_finish: 92165387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 92175387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 92185387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden and r2, r2, #15 @ r2<- A 92195387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 92205387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 92215387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 92225387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 92235387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 9224861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 9225c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 1 9226861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r9, r3 @ r2<- target address 92276e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 9228861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 9229861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 9230861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9231861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 92325387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92335387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SGET_WIDE_VOLATILE */ 92345387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92355387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 92365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 92375387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 9238861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9239861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 92405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 92415387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_resolve: 92425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 92435387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 92445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 92455387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 92465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 92475387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 92485387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 92495387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92505387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SPUT_WIDE_VOLATILE */ 92515387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92525387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 92535387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 92545387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 92555387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9: &fp[AA] 9256861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9257861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 92585387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 92595387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SPUT_WIDE_VOLATILE_resolve: 92605387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 92615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 92625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 92635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 92645387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 9265861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 92665387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 92675387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 92685387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 9269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_EXECUTE_INLINE */ 9270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Extract args, call function. 9273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = #of args (0-4) 9274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = call index 9275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Other ideas: 9278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Use a jump table from the main piece to jump directly into the 9279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 9280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Have five separate pieces that do the loading, so we can work the 9281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interleave a little better. Increases code size. 9282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_continue: 9284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r9, 2) @ r9<- FEDC 9286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r9, #0xf000 @ isolate F 9289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 9290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r9, #0x0f00 @ isolate E 9291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 9292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r9, #0x00f0 @ isolate D 9293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 9294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r9, #0x000f @ isolate C 9295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 9296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: 9297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 9298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (not reached) 9300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_table: 9302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word gDvmInlineOpsTable 9303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9304b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 9305b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9306b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 9307b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 9308b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 9309b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 9310b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9311b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 9312b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 9313b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9314b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 9315b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9316b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9317b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 9318b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 9319b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 9320b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 9321b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 9322b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 9323b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 9324b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 9325b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 9326b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 9327b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9328b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 9329b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9330b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 9331b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 9332b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9333c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IPUT_OBJECT_VOLATILE */ 9334c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9335c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9336c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9337c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9338c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9339c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9340c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IPUT_OBJECT_VOLATILE_finish: 9341c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9342c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 9343c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9344c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r1, r1, #15 @ r1<- A 9345c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9346c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 9347919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 9348c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9349c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9350919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r9, r3 @ r9<- direct ptr to target location 9351c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 93520890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 9353919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [r9] @ obj.field (8/16/32 bits)<- r0 9354919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ stored a null reference? 9355919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 9356c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9357c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9358c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SGET_OBJECT_VOLATILE */ 9359c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9360c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9361c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9362c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9363c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9364c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_OBJECT_VOLATILE_resolve: 9365c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9366c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9367c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9368c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9369c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9370c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 9371c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9372c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9373c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SPUT_OBJECT_VOLATILE */ 9374919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 9375919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee mov r2, rINST, lsr #8 @ r2<- AA 9376919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9377919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_VREG(r1, r2) @ r1<- fp[AA] 9378919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 9379919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 9380919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r0, #offStaticField_value @ r0<- pointer to store target 9381919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee SMP_DMB @ releasing store 9382919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r1, [r0] @ field<- vAA 9383919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #0 @ stored a null object? 9384919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ mark card if not 9385919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 9386c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 9388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterEnd 9389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterEnd: 9390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/footer.S */ 9392ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common subroutines and data 9396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9399ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9400ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 9402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 9403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9404ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 940597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 940697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 940797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 9408d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 940997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 9410d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9411d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9412d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 941397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 941497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 941597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 9416d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9417d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 941897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 9419d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 942097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 94217a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng .global dvmJitToInterpNoChainNoProfile 94227a2697d327936e20ef5484f7819e2e4bf91c891fBen ChengdvmJitToInterpNoChainNoProfile: 94237a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94247a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r0,rPC @ pass our target PC 94257a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r2,#kSVSNoProfile @ r2<- interpreter entry point 94267a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 94277a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r3, [r10, #offThread_inJitCodeCache] @ back to the interp land 94287a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b jitSVShadowRunEnd @ doesn't return 94297a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 943040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 943140094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 9432d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 943340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC @ pass our target PC 94347a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 94357a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9436d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9437d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 943840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng 943940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 944040094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 9441d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94429a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 944397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 94447a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9445d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9446d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 944797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 944840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpBackwardBranch 944940094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpBackwardBranch: 9450d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94519a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 945297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 94537a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9454d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9455d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 945697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 945797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 945897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 9459d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94609a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 946197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 94627a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9463d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9464d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 946597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 946697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 946797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 9468d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 946997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 947097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 94717a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9472d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9473d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 947497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9475ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9476ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter when the compiler is 9477ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * having issues translating/executing a Dalvik instruction. We have to skip 9478ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the code cache lookup otherwise it is possible to indefinitely bouce 9479ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * between the interpreter and the code cache if the instruction that fails 9480ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * to be compiled happens to be at a trace start. 9481ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9482ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpPunt 9483ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpPunt: 94847a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9485ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r0 9486978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9487ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,lr 9488ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpPunt; 9489ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9490ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 94917a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r0, #0 94927a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9493ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9494ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9495ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9496ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9497ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9498ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9499ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return to the interpreter to handle a single instruction. 9500ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * On entry: 9501ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r0 <= PC 9502ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r1 <= PC of resume instruction 9503ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * lr <= resume point in translation 9504ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9505ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpSingleStep 9506ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpSingleStep: 9507d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9508d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 9509ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#kInterpEntryInstr 9510ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ enum is 4 byte in aapcs-EABI 9511ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_entryPoint] 9512ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC,r0 9513ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 95147a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng 9515ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9516ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitSingleStep @ Ask for single step and then revert 9517ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9518ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp to bail to debug interp 9519ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9520ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 952140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 952240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * Return from the translation cache and immediately request 952340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * a translation for the exit target. Commonly used for callees. 952440094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 952540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 952640094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 9527978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 952840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmBumpNoChain 952940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng#endif 953040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 953140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC 953240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 953340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 953440094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r1, rPC @ arg1 of translation may need this 953540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 95367a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 @ !0 means translation exists 953740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bxne r0 @ continue native execution if so 95387a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b 2f @ branch over to use the interpreter 9539ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9540ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9541ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache and immediately request 9542ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a translation for the exit target. Commonly used following 9543ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * invokes. 9544ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 954540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 954640094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 95479a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 95487a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 95499a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9550bd0472480c6e876198fe19c4ffa22350c0ce57daBill Buzbee add rINST, #-4 @ .. which is 9 bytes back 9551ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 95527a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 95537a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9554ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9555ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng beq 2f 9556ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9557ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 95589a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 95599a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 956046cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 956146cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 956246cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9564ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* No translation, so request one if profiling isn't disabled*/ 9565ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng2: 95661da12167d913efde56ec3b40491524b051679f2cAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9567ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9568ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0, #0 957040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng movne r2,#kJitTSelectRequestHot @ ask for trace selection 9571ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_selectTrace 9572ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9573ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9574ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9575ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9576ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter. 9577ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * The return was done with a BLX from thumb mode, and 9578ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the following 32-bit word contains the target rPC value. 9579ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Note that lr (r14) will have its low-order bit set to denote 9580ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * its thumb-mode origin. 9581ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 9582ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * We'll need to stash our lr origin away, recover the new 9583ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * target and then check to see if there is a translation available 9584ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * for our new target. If so, we do a translation chain and 9585ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * go back to native execution. Otherwise, it's back to the 9586ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * interpreter (after treating this entry as a potential 9587ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace start). 9588ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9589ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNormal 9590ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNormal: 95919a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 95927a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 95939a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9594bd0472480c6e876198fe19c4ffa22350c0ce57daBill Buzbee add rINST,#-4 @ .. which is 9 bytes back 9595978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9596ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNormal 9597ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9598ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9599ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 96007a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9601ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 960246cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee beq toInterpreter @ go if not, otherwise do chain 9603ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9604ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 96059a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 96069a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 960746cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 960846cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 960946cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9610ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9611ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9612ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter to do method invocation. 9613ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Check if translation exists for the callee, but don't chain to it. 9614ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 96157a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng .global dvmJitToInterpNoChainNoProfile 96167a2697d327936e20ef5484f7819e2e4bf91c891fBen ChengdvmJitToInterpNoChainNoProfile: 96177a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#if defined(WITH_JIT_TUNING) 96187a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bl dvmBumpNoChain 96197a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#endif 96207a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 96217a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r0,rPC 96227a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bl dvmJitGetCodeAddr @ Is there a translation? 96237a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 96247a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r1, rPC @ arg1 of translation may need this 96257a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 96267a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 96277a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bxne r0 @ continue native execution if so 96287a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng EXPORT_PC() 96297a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng adrl rIBASE, dvmAsmInstructionStart 96307a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng FETCH_INST() 96317a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 96327a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng GOTO_OPCODE(ip) @ jump to next instruction 96337a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 96347a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng/* 96357a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng * Return from the translation cache to the interpreter to do method invocation. 96367a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng * Check if translation exists for the callee, but don't chain to it. 96377a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng */ 9638ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNoChain 9639ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNoChain: 9640978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9641ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNoChain 9642ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 96437a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9644ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9645ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 96467a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 96479a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 96489a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9649ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9650ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ continue native execution if so 965197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9652ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9653ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9654ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * No translation, restore interpreter regs and start interpreting. 9655ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * rGLUE & rFP were preserved in the translated code, and rPC has 9656ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * already been restored by the time we get here. We'll need to set 9657ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * up rIBASE & rINST, and load the address of the JitTable into r0. 9658ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 965946cd5b63c29d3284a9ff3e0d0711fb136f409313Bill BuzbeetoInterpreter: 9660ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9661ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9662ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9663ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9664ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ NOTE: intended fallthrough 96657a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 9666ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9667ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Common code to update potential trace start counter, and initiate 9668ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a trace-build if appropriate. On entry, rPC should point to the 9669ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * next instruction to execute, and rINST should be already loaded with 9670ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the next opcode word, and r0 holds a pointer to the jit profile 9671ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * table (pJitProfTable). 9672ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9673ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_testUpdateProfile: 9674ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9675ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9676ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9677ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9678ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_updateProfile: 9679ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 96807b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 96817b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 9682ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9683ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng subs r1,r1,#1 @ decrement counter 96847b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 9685ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9686ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9687ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9688ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Here, we switch to the debug interpreter to request 9689ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace selection. First, though, check to see if there 9690ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * is already a native translation in place (and, if so, 9691ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * jump to it now). 9692ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9693d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 96947a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 96957b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 9696ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9697ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9698ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 96997a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 97007a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, rPC @ arg1 of translation may need this 97017a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 9702ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 970397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9704ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ jump to the translation 970540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r2,#kJitTSelectRequest @ ask for trace selection 970640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng @ fall-through to common_selectTrace 970797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 970840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng moveq r2,#kJitTSelectRequest @ ask for trace selection 97099a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 97109a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 97119a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 97129a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 97139a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 97149a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 9715d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r10, r0 @ save target 97169a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 9717d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng cmp r0, r10 @ special case? 9718d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne jitSVShadowRunStart @ set up self verification shadow space 97199a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 97209a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 97219a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 972297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 97239a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 972440094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 972540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * On entry: 972640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 972740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 9728ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_selectTrace: 9729ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 97309c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 97319c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9732ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp 9733ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9734ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 973597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 973697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 973797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 973897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 9739d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * On entry: 9740d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * rPC, rFP, rGLUE: the values that they should contain 9741d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * r10: the address of the target translation. 974297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9743d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunStart: 974497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 974597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 974697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 97479a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 974897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9749ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9750ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9751ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 975297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 975397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 975497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 975597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 975697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9757d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunEnd: 975897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 975997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9760ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9761ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9762ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9763ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 976497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 976597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 976697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 976797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 976830f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 976930f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 977097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 977197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 977297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 977397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 977497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 977597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 977697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 977797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 977897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 977997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 978097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9781ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9782ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code when a backward branch is taken. 9785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9786c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * TODO: we could avoid a branch by just setting r0 and falling through 9787c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * into the common_periodicChecks code, and having a test on r0 at the 9788c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * end determine if we should return to the caller or update & branch to 9789c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * the next instr. 9790c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is PC adjustment *in bytes* 9793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_backwardBranch: 9795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryInstr 9796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9797ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9798ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9799ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9800ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9801ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9802ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9803ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9804ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9808ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9813c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * activity has begun. If so, we suspend the thread or side-exit to 9814c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * the debug interpreter as appropriate. 9815c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9816c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * The common case is no activity on any of these, so we want to figure 9817c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * that out quickly. If something is up, we can then sort out what. 9818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9819c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * We want to be fast if the VM was built without debugger or profiler 9820c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * support, but we also need to recognize that the system is usually 9821c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * shipped with both of these enabled. 9822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: reduce this so we're just checking a single location. 9824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9826c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 9827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is trampoline PC adjustment *in bytes* 9828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_periodicChecks: 9830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9835c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr ip, [r3] @ ip<- suspendCount (int) 9836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9837c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp r1, #0 @ debugger enabled? 9838c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldrneb r1, [r1] @ yes, r1<- debuggerActive (boolean) 9839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 98405cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng orrnes ip, ip, r1 @ ip<- suspendCount | debuggerActive 98415cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng /* 98425cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng * Don't switch the interpreter in the libdvm_traceview build even if the 98435cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng * profiler is active. 98445cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng * The code here is opted for less intrusion instead of performance. 98455cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng * That is, *pActiveProfilers is still loaded into r2 even though it is not 98465cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng * used when WITH_INLINE_PROFILING is defined. 98475cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng */ 98485cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#if !defined(WITH_INLINE_PROFILING) 9849c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrs ip, ip, r2 @ ip<- suspend|debugger|profiler; set Z 98505cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#endif 98515cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng 9852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9853c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bxeq lr @ all zero, return 9854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9855c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden /* 9856c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * One or more interesting events have happened. Figure out what. 9857c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9858c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * If debugging or profiling are compiled in, we need to disambiguate. 9859c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9860c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * r0 still holds the reentry type. 9861c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden */ 9862c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr ip, [r3] @ ip<- suspendCount (int) 9863c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp ip, #0 @ want suspend? 9864c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden beq 1f @ no, must be debugger/profiler 9865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9866c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden stmfd sp!, {r0, lr} @ preserve r0 and lr 9867964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9868964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee /* 9869964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * Refresh the Jit's cached copy of profile table pointer. This pointer 9870964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * doubles as the Jit's on/off switch. 9871964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee */ 9872d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 9873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9874d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [r3] @ r3 <- pJitProfTable 9875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC 9876964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh Jit's on/off switch 9877964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#else 9878964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9879964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee EXPORT_PC() @ need for precise GC 9880964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9881c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bl dvmCheckSuspendPending @ do full check, suspend if necessary 9882c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldmfd sp!, {r0, lr} @ restore r0 and lr 9883c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9884c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden /* 9885c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * Reload the debugger/profiler enable flags. We're checking to see 9886c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * if either of these got set while we were suspended. 9887c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 98885cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng * If WITH_INLINE_PROFILING is configured, don't check whether the profiler 98895cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng * is enabled or not as the profiling will be done inline. 9890c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden */ 9891c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9892c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp r1, #0 @ debugger enabled? 9893c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldrneb r1, [r1] @ yes, r1<- debuggerActive (boolean) 98945cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng 98955cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#if !defined(WITH_INLINE_PROFILING) 9896c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9897c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9898c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrs r1, r1, r2 98995cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#else 99005cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng cmp r1, #0 @ only consult the debuggerActive flag 99015cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#endif 99025cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng 9903c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden beq 2f 9904c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9905c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden1: @ debugger/profiler enabled, bail out; glue->entryPoint was set above 9906c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden str r0, [rGLUE, #offGlue_entryPoint] @ store r0, need for debug/prof 9907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, rPC, r9 @ update rPC 9908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ "want switch" = true 9909c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden b common_gotoBail @ side exit 9910c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9911c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden2: 9912c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bx lr @ nothing to do, return 9913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * State registers will be saved to the "glue" area before bailing. 9919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * other interpreter or just bail all the way out 9923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_gotoBail: 9925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ r0<- glue ptr 9927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r1, r1, #1 @ using (boolean+1) 9930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl _longjmp @ does not return 9932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_abort 9933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation with range. 9937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodRange: 9942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewRange: 9943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- CCCC 9948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r2, r2, #1 @ count-- 9956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r10], #4 @ *outs++ = val 9957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1b @ ...while count != 0 9958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LinvokeArgsDone 9960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation without range. 9963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodNoRange: 9968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewNoRange: 9969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone 9976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNonRange: 9979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vA 9986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r1, #0xf000 @ isolate G 9987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vG 9990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r1, #0x0f00 @ isolate F 9991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vF 9994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r1, #0x00f0 @ isolate E 9995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vE 9998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r1, #0x000f @ isolate D 9999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 10000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 10001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vD 10002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: @ fall through to .LinvokeArgsDone 10003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 10005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 10006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 10007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ find space for the new stack frame, check for overflow 10008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 10009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 10010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 10011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@ bl common_dumpRegs 10012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 10013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 10014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, r9 @ bottom < interpStackEnd? 10015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 100167a44e4ee0782d24b4c6090be1f0a3c66f971f2c1Andy McFadden blo .LstackOverflow @ yes, this frame will overflow stack 10017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ set up newSaveArea 10019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef EASY_GDB 10020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 10021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [r10, #offStackSaveArea_prevSave] 10022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 10024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 10025ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 10026ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r9, #0 10027ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r9, [r10, #offStackSaveArea_returnAddr] 10028ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 100295cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#if defined(WITH_INLINE_PROFILING) 100305cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng stmfd sp!, {r0-r3} @ preserve r0-r3 100315cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng mov r1, r6 100325cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng @ r0=methodToCall, r1=rGlue 100335cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng bl dvmFastMethodTraceEnter 100345cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng ldmfd sp!, {r0-r3} @ restore r0-r3 100355cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#endif 10036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r10, #offStackSaveArea_method] 10037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden tst r3, #ACC_NATIVE 10038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LinvokeNative 10039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 10042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 10043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP 10044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 10046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 10047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 10048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 10049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 10050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 10051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 10052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 10053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 10056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 10057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r2 @ publish new rPC 10058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 10059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Update "glue" values for the new method 10061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 10062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 10063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 10064ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 10065ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 10066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r1 @ fp = newFp 10067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 10068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rINST, r9 @ publish new rINST 10069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 10070ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 10071ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 10072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10073ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 10074ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rFP, r1 @ fp = newFp 10075ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 10076ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rINST, r9 @ publish new rINST 10077ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 10078ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 10079ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 10080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNative: 10082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Prep for the native call 10083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 10084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 10085d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 10086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 10087d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 10088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r3 @ r9<- glue->self (preserve) 10089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ r2<- methodToCall 10091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ r0<- newFp (points to args) 10092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 10093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 10095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 10096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .Lskip 10097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_mterp, %function 10098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_mterp: 10099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 10100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 10101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 10102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lskip: 10103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101055cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#if defined(WITH_INLINE_PROFILING) 101065cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng @ r2=JNIMethod, r6=rGLUE 101075cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng stmfd sp!, {r2,r6} 101085cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#endif 101095cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng 10110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @mov lr, pc @ set return addr 10111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 10112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 10113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101145cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#if defined(WITH_INLINE_PROFILING) 101155cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng @ r0=JNIMethod, r1=rGLUE 101165cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng ldmfd sp!, {r0-r1} 101175cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng bl dvmFastNativeMethodTraceExit 101185cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#endif 101195cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng 10120964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10121964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ Refresh Jit's on/off status 10122964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10123964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee 10124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ native return; r9=self, r10=newSaveArea 10125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ equivalent to dvmPopJniLocals 10126d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 10127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 10128964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10129964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 10130964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 10132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null? 10133d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 10134964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10135964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh cached on/off switch 10136964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ no, handle exception 10138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101436ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 101446ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 10145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 10146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmHandleStackOverflow 10147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 10149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 10150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation, calling through "glue code". 10155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: now that we have range and non-range invoke handlers, this 10157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * needs to be split into two. Maybe just create entry points 10158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that set r9 and jump here? 10159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 10161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 10162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 10163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeOld: 10166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #8 @ space for args + pad 10167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 10168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ A2<- methodToCall 10169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ A0<- glue 10170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 10171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ A1<- methodCallRange 10172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ A3<- AA 10173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #0] @ A4<- ip 10174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 10175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ remove arg area 10176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall @ continue to next instruction 10177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for handling a return instruction. 10183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 10185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_returnFromMethod: 10187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnNew: 10188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryReturn 10189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 10190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 10191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101925cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#if defined(WITH_INLINE_PROFILING) 101935cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng stmfd sp!, {r0-r3} @ preserve r0-r3 101945cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng mov r0, r6 101955cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng @ r0=rGlue 101965cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng bl dvmFastJavaMethodTraceExit 101975cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng ldmfd sp!, {r0-r3} @ restore r0-r3 101985cc61d70ec727aa22f58463bf7940cc717cf3eb1Ben Cheng#endif 10199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 10200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 10201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 10202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 10203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r2<- method we're returning to 10204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 10205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is this a break frame? 10206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 10207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 10208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_gotoBail @ break frame, bail out completely 10209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 10211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 10212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 10213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 10214ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 102157a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 10216ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r9 @ publish new rPC 10217ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_methodClassDex] 102187a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r10, [r3, #offThread_inJitCodeCache] @ may return to JIT'ed land 102197a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng cmp r10, #0 @ caller is compiled code 102207a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng blxne r10 10221ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 10222ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 10223ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 10224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r9 @ publish new rPC 10226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 10227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10228ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 10229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return handling, calls through "glue code". 10232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnOld: 10235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 10236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 10237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_returnFromMethod 10238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 10239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Somebody has thrown an exception. Handle it. 10244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If the exception processing code returns to us (instead of falling 10246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out of the interpreter), continue with whatever the next instruction 10247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * now happens to be. 10248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 10250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10251ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmMterpCommonExceptionThrown 10252ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmMterpCommonExceptionThrown: 10253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_exceptionThrown: 10254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionNew: 10255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryThrow 10256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 10257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 10258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 10260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 10261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 10262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 10263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 10264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- NULL 10265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 10266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up args and a local for "&fp" */ 10268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 10269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [sp, #-4]! @ *--sp = fp 10270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov ip, sp @ ip<- &fp 10271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- false 10272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #-4]! @ *--sp = &fp 10273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 10274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 10275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 10276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r9 @ r2<- exception 10277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 10278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 10279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 10281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 10282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 10284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 10285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 10286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ no, skip ahead 10287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r0 @ save relPc result in rFP 10288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 102894fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden mov r1, r9 @ r1<- exception 10290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCleanupStackOverflow @ call(self) 10291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP @ restore result 10292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 10293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 10295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 10296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is catchRelPc < 0? 10297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ restore stack 10298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi .LnotCaughtLocally 10299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* adjust locals to match self->curFrame and updated PC */ 10301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 10302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 10303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 10304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 10305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 10306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 10307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 10308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 10309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* release the tracked alloc on the exception */ 10311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 10312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 10313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* restore the exception if the handler wants it */ 10316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 10317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 10319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 10320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 10323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix stack overflow if necessary */ 10324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 10325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 10326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, r10 @ if yes: r0<- self 103274fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden movne r1, r9 @ if yes: r1<- exception 10328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 10329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ may want to show "not caught locally" debug messages here 10331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if DVM_SHOW_EXCEPTION >= 2 10332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call __android_log_print(prio, tag, format, ...) */ 10333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* "Exception %s from %s:%d not caught locally" */ 10334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 10335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 10336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_insns] 10337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 10338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden asr r1, r1, #1 10339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLineNumFromPC 10340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 10341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmGetMethodSourceFile(method) 10342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 10343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmGetMethodSourceFile 10344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 10345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ exception->clazz->descriptor 10346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] 10347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_descriptor] 10348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ 10349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, strExceptionNotCaughtLocally 10350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strLogTag 10351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #3 @ LOG_DEBUG 10352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __android_log_print 10353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offThread_exception] @ restore exception 10355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 10356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 10357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 10359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail @ bail out 10360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exception handling, calls through "glue code". 10364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionOld: 10367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 10368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 10369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_exceptionThrown 10370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 10371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * After returning from a "glued" function, pull out the updated 10376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * values and start executing at the next instruction. 10377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_resumeAfterGlueCall: 10379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 10380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 10381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array index. 10386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayIndex: 10388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayIndexException 10390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array value. 10396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayStore: 10398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayStoreException 10400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Integer divide or mod by zero. 10406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errDivideByZero: 10408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArithmeticException 10410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strDivideByZero 10411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Attempt to allocate an array with a negative size. 10416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNegativeArraySize: 10418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNegativeArraySizeException 10420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invocation of a non-existent method. 10426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNoSuchMethod: 10428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNoSuchMethodError 10430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We encountered a null object when we weren't expecting one. We 10436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * export the PC, throw a NullPointerException, and goto the exception 10437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * processing code. 10438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNullObject: 10440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNullPointerException 10442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For debugging, cause an immediate fault. The source address will 10448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be in lr (use a bl instruction to jump here). 10449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_abort: 10451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, .LdeadFood 10452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LdeadFood: 10453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word 0xdeadf00d 10454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out a "we were here", preserving all registers. (The attempt 10457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to save ip won't work, but we need to save an even number of 10458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * registers for EABI 64-bit stack alignment.) 10459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .macro SQUEAK num 10461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_squeak\num: 10462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 10464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #\num 10465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endm 10469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 0 10471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 1 10472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 2 10473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 3 10474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 4 10475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 5 10476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out the number in r0, preserving registers. 10479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNum: 10481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 10484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print a newline, preserving registers. 10490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNewline: 10492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNewline 10494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 10500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printHex: 10502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintHex 10505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 10511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printLong: 10513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r1 10515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 10516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintLong 10517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 10523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printMethod: 10525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpPrintMethod 10527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Call a C helper function that dumps regs and possibly some 10532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * additional info. Requires the C function to be compiled in. 10533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_dumpRegs: 10536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpDumpArmRegs 10538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10542d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#if 0 10543d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden/* 10544d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Experiment on VFP mode. 10545d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10546d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 10547d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10548d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 10549d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden */ 10550d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddensetFPSCR: 10551d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r0, r0, r1 @ make sure no stray bits are set 10552d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmrx r2, fpscr @ get VFP reg 10553d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mvn r1, r1 @ bit-invert mask 10554d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r2, r2, r1 @ clear masked bits 10555d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden orr r2, r2, r0 @ set specified bits 10556d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmxr fpscr, r2 @ set VFP reg 10557d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, r2 @ return new value 10558d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bx lr 10559d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10560d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .align 2 10561d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .global dvmConfigureFP 10562d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .type dvmConfigureFP, %function 10563d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddendvmConfigureFP: 10564d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden stmfd sp!, {ip, lr} 10565d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x03000000 sets DN/FZ */ 10566d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x00009f00 clears the six exception enable flags */ 10567d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl common_squeak0 10568d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10569d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10570d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl setFPSCR 10571d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden ldmfd sp!, {ip, pc} 10572d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#endif 10573d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references, must be close to the code that uses them. 10577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 10579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArithmeticException: 10580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArithmeticException 10581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayIndexException: 10582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayIndexException 10583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayStoreException: 10584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayStoreException 10585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrDivideByZero: 10586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrDivideByZero 10587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNegativeArraySizeException: 10588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNegativeArraySizeException 10589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNoSuchMethodError: 10590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNoSuchMethodError 10591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNullPointerException: 10592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNullPointerException 10593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrLogTag: 10595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrLogTag 10596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrExceptionNotCaughtLocally: 10597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrExceptionNotCaughtLocally 10598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNewline: 10600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNewline 10601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrSqueak: 10602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrSqueak 10603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintHex: 10604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintHex 10605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintLong: 10606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintLong 10607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Zero-terminated ASCII string data. 10610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with the address, or use an ADR pseudo-op to get the address 10613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * PC-relative addressing mode and hence has a limited range, which 10615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * makes it not work well with mergeable string sections. 10616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrBadEntryPoint: 10620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Bad entry point %d\n" 10621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArithmeticException: 10622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArithmeticException;" 10623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayIndexException: 10624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayStoreException: 10626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastException: 10628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ClassCastException;" 10629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrDivideByZero: 10630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "divide by zero" 10631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrFilledNewArrayNotImpl: 10632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInternalError: 10634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InternalError;" 10635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationError: 10636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InstantiationError;" 10637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNegativeArraySizeException: 10638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNoSuchMethodError: 10640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNullPointerException: 10642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NullPointerException;" 10643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrLogTag: 10645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "mterp" 10646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrExceptionNotCaughtLocally: 10647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNewline: 10650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "\n" 10651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrSqueak: 10652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%d>" 10653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintHex: 10654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<0x%x>" 10655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintLong: 10656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%lld>" 10657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10658