InterpAsm-armv5te-vfp.S revision 4fbba1f95b3e27bdc5f5572bb0420b5f928aa54e
1a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 2a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * --> DO NOT EDIT <-- 5a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/header.S */ 8a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 10a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 11a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 13a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 14a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 15a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 17a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 18a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 21a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 22a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 23a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 24a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ARMv5 definitions and declarations. 25a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 26a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 27a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 28a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenARM EABI general notes: 29a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 30a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 31a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr4-r8 are available for general use 32a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr9 is given special treatment in some situations, but not for us 33a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr10 (sl) seems to be generally available 34a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 35a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr12 (ip) is scratch -- not preserved across method calls 36a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr13 (sp) should be managed carefully in case a signal arrives 37a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr14 (lr) must be preserved 38a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr15 (pc) can be tinkered with directly 39a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 40a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0 holds returns of <= 4 bytes 41a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 42a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 43a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 44a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 45a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 46a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 47a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 48a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 49a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden(i.e. the 5th arg). 50a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 51a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenVFP: single-precision results in s0, double-precision results in d0. 52a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 53a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 54a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 55a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 56a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 57a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 58a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMterp and ARM notes: 59a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 60a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenThe following registers have fixed assignments: 61a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 62a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden reg nick purpose 63a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r4 rPC interpreted program counter, used for fetching instructions 64a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 65a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r6 rGLUE MterpGlue pointer 661da12167d913efde56ec3b40491524b051679f2cAndy McFadden r7 rINST first 16-bit code unit of current instruction 671da12167d913efde56ec3b40491524b051679f2cAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 68a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 69a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMacros are provided for common operations. Each macro MUST emit only 70a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 71a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenunspecified registers or condition codes. 72a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 73a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 74a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* single-purpose registers, given names for clarity */ 75a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rPC r4 76a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rFP r5 77a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rGLUE r6 781da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rINST r7 791da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rIBASE r8 80a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 81a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* save/restore the PC and/or FP from the glue struct */ 82a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 83a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 84a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 85a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 86a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 87a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 88a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 89a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 90a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 91a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be done *before* something calls dvmThrowException. 92a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 93a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 94a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 95a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 96a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * It's okay to do this more than once. 97a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 98a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define EXPORT_PC() \ 99a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Given a frame pointer, find the stack save area. 103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_INST() ldrh rINST, [rPC] 113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from the specified offset. Advances rPC 116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Because of the limited size of immediate constants on ARM, this is only 119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with this). 121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This must come AFTER anything that can throw an exception, or the 123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception catch may miss. (This also implies that it must come after 124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * EXPORT_PC().) 125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * here. 144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch a half-word code unit from an offset past the current PC. The 149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The "_S" variant works the same but treats the value as signed. 152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * byte of the halfword you want (lo/hi). 160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the instruction's opcode field into the specified register. 165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the prefetched instruction's opcode field into the specified register. 170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Get/set the 32-bit value from a Dalvik register. 183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 189d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 190ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert a virtual register index into an address. 194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add _reg, rFP, _vreg, lsl #2 197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is a #include, not a %include, because we want the C pre-processor 200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to expand the macros into assembler assignment statements. 201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#include "../common/asm-constants.h" 203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/platform.S */ 206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * CPU-version-specific defines 209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * one-way branch. 215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP. Does not modify LR. 217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC source 219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Jump to subroutine. 225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC_LR source 229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov lr, pc 230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDMFD_PC regs 239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {\regs,pc} 240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/entry.S */ 244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Interpreter entry point. 261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't have formal stack frames, so gdb scans upward in the code 265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to find the start of the function (a label with the %function type), 266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and then looks at the next few instructions to figure out what 267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * got pushed onto the stack. From this it figures out how to restore 268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the registers, including PC, for the previous stack frame. If gdb 269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sees a non-function label, it stops scanning, so either we need to 270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have nothing but assembler-local labels between the entry point and 271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the break, or we need to fake it out. 272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * When this is defined, we add some stuff to make gdb less confused. 274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define ASSIST_DEBUGGER 1 276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdRun 280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdRun, %function 281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This function returns a boolean "changeInterp" value. The return comes 287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * via a call to dvmMterpStdBail(). 288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdRun: 290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY1 \ 291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .save {r4-r10,fp,lr}; \ 292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY2 \ 294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .pad #4; \ 295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align 64 296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* save stack pointer, add magic word for debuggerd */ 302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up "named" registers, figure out entry point */ 305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rGLUE, r0 @ set rGLUE 306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offGlue_entryPoint] @ InterpEntry enum is char 307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryInstr @ usual case? 310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .Lnot_instr @ no, handle it 311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 312ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 313ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lno_singleStep: 3147a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 315ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng /* Entry is always a possible trace start */ 316ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 317ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 3187a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, #0 @ prepare the value for the new state 3197a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r1, [r10, #offThread_inJitCodeCache] @ back to the interp land 320ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 321ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 322ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 323ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 324ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* start executing the instruction at rPC */ 326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 329ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_instr: 332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_returnFromMethod 334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_return: 336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown 338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 339ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 340ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lnot_throw: 341ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr r0,[rGLUE, #offGlue_jitResume] 342ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr r2,[rGLUE, #offGlue_jitResumePC] 343ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 344ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lbad_arg 345ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp rPC,r2 346ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lno_singleStep @ must have branched, don't resume 347ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1, #kInterpEntryInstr 348ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng strb r1, [rGLUE, #offGlue_entryPoint] 349ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr rINST, .LdvmCompilerTemplate 350ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bx r0 @ re-enter the translation 351ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.LdvmCompilerTemplate: 352ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .word dvmCompilerTemplateStart 353ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 354ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lbad_arg: 356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strBadEntryPoint 357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r1 holds value of entryPoint 358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAbort 360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdBail 364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdBail, %function 365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Restore the stack pointer and PC from the save point established on entry. 368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * LR to PC. 374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 bool changeInterp 378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdBail: 380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ return the changeInterp value 382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 @ un-align 64 383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references. 388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrBadEntryPoint: 390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrBadEntryPoint 391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionStart 395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmInstructionStart, %function 396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionStart = .L_OP_NOP 397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOP: /* 0x00 */ 402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOP.S */ 403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_inst, %function 410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_inst: 411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE: /* 0x01 */ 421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_16: /* 0x03 */ 452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE.S */ 468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide vA, vB */ 469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/from16 vAA, vBBBB */ 487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- BBBB 489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/16 vAAAA, vBBBB */ 504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- BBBB 506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- AAAA 507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 510445194bc141dc67e2f678aa1bbd5e59ca66254e5Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-result-wide vAA */ 587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-exception vAA */ 618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ r1<- 0 622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN: /* 0x0f */ 639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 64-bit value. Copies the return value into the "glue" 659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* return-wide vAA */ 662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_4: /* 0x12 */ 692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_4.S */ 693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/4 vA, #+B */ 694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_16: /* 0x13 */ 707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_16.S */ 708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/16 vAA, #+BBBB */ 709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST: /* 0x14 */ 720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST.S */ 721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const vAA, #+BBBBbbbb */ 722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/high16 vAA, #+BBBB0000 */ 737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/16 vAA, #+BBBB */ 751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #0 @ r0<- 00000000 805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING: /* 0x1a */ 816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING.S */ 817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBB */ 818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_resolve 825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBBBBBB */ 835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/class vAA, Class@BBBB */ 854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_CLASS_resolve 861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Synchronize on an object. 872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-enter vAA */ 874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null object, throw an exception 880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLockObject @ call(self, obj) 882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ exception raised, bail out 887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlock an object. 898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exceptions that occur when unlocking a monitor need to appear as 900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if they happened at the following instruction. See the Dalvik 901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction spec. 902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-exit vAA */ 904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ before fetch: export the PC 906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes 909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, exception is pending 913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if a cast from one class to another is allowed. 924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* check-cast vAA, class@BBBB */ 926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r3) @ r9<- object 929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ is object null? 931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolved: 938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_okay: 941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if an object reference is an instance of a class. 951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Most common situation is a non-null object, being compared against 953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an already-resolved class. 954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* instance-of vA, vB, class@CCCC */ 956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- CCCC 964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ARRAY_LENGTH.S */ 978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return the length of an array. 980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yup, fail 987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ vB<- length 991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new instance of a class. 1000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-instance vAA, class@BBBB */ 1002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocObject @ r0<- new object 1016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Allocate an array of objects, specified with the array class 1024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and a count. 1025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The verifier guarantees that this is an array class, so we don't 1027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * check for it here. 1028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-array vA, vB, class@CCCC */ 1030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 1031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- CCCC 1032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ check length 1036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_errNegativeArraySize @ negative length, bail 1038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for resolve, alloc 1040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC(); 1111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ 0 means an exception is thrown 1113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ has exception 1114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW: /* 0x27 */ 1121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW.S */ 1122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception object in the current thread. 1124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* throw vAA */ 1126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 1129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 1130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, throw an NPE instead 1131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ bypass dvmSetException, just store it 1132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 1134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO: /* 0x28 */ 1139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO.S */ 1140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 8-bit offset. 1142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto +AA */ 1147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1151ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1152ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1154ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1155ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1158ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1159ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1160ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1161ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1162ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_16: /* 0x29 */ 1167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_16.S */ 1168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 16-bit offset. 1170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/16 +AAAA */ 1175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1181ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1182ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1183ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1184ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1185ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1189ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_32: /* 0x2a */ 1195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_32.S */ 1196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 32-bit offset. 1198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction doesn't affect the V flag, so we need to clear it 1205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * explicitly. 1206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/32 +AAAAAAAA */ 1208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, ip @ (clear V flag during stall) 1211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1214ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1215ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1217ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1218ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1221ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1222ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1223ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1224ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1225ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1251ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1252ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1253ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1254ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1255ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1256ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1257ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1258ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1262ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1290ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1291ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1293ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1294ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1297ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1298ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1299ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1300ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1301ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1308968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13278fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13308fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13328fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13418fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1347968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13668fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13698fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13718fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13808fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1386968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14058fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14088fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14108fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14198fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1425968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14448fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14478fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14498fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14588fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * register based on the results of the comparison. 1468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We load the full values with LDM, but in practice many values could 1470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be resolved by only looking at the high word. This could be made 1471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If we just wanted to set condition flags, we could do this: 1474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subs ip, r0, r2 1475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sbcs ip, r1, r3 1476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subeqs ip, r0, r2 1477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * us a constant 5-cycle path plus a branch at the end to the 1481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction epilogue code. The multi-compare approach below needs 1482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in the worst case (the 64-bit values are equal). 1484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* cmp-long vAA, vBB, vCC */ 1486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 1487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 1490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt .LOP_CMP_LONG_greater 1497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CMP_LONG_less 1500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQ: /* 0x32 */ 1505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQ.S */ 1506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1526ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1527ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1528ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1529ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1530ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1531ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1532ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1535ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NE: /* 0x33 */ 1542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NE.S */ 1543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1564ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1565ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1566ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1567ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1568ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1572ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LT: /* 0x34 */ 1579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LT.S */ 1580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1600ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1601ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1602ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1603ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1604ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1605ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1606ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1609ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GE: /* 0x35 */ 1616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GE.S */ 1617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1637ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1638ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1639ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1640ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1641ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1642ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1643ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1646ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GT: /* 0x36 */ 1653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GT.S */ 1654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1674ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1675ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1676ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1677ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1678ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1679ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1680ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1683ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LE: /* 0x37 */ 1690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LE.S */ 1691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1711ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1712ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1713ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1714ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1715ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1716ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1717ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1720ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1745ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1746ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1747ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1748ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1749ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1750ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1753ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1754ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1755ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1756ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1757ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1782ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1783ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1784ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1785ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1786ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1787ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1790ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1791ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1792ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1793ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1794ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1819ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1820ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1821ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1822ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1823ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1824ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1827ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1828ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1829ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1830ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1831ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1856ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1857ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1858ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1859ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1860ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1861ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1862ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1863ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1864ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1865ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1868ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1893ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1894ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1895ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1896ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1897ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1898ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1899ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1900ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1901ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1902ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1905ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1930ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1931ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1932ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1933ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1934ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1935ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1938ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1939ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1940ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1941ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1942ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET: /* 0x44 */ 2003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aget-wide vAA, vBB, vCC */ 2041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT: /* 0x4b */ 2226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aput-wide vAA, vBB, vCC */ 2264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null array object? 2300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r9) @ r9<- vAA 2301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r3 @ compare unsigned index, length 2305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET: /* 0x52 */ 2444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish @ no, already resolved 2459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish 2465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 2471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Wide 32-bit instance field get. 2473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide vA, vB, field@CCCC */ 2475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish 2489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish 2516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish 2545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish 2574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish 2603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish 2632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT: /* 0x59 */ 2638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ no, already resolved 2653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ yes, finish up 2659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 2665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide vA, vB, field@CCCC */ 2666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET: /* 0x60 */ 2829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_finish: @ field ptr in r0 2843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SGET handler. 2856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sget-wide vAA, field@BBBB */ 2858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_finish: 2865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 2866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offStaticField_value] @ r2/r3<- field value (aligned) 2867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[AA] 2868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r1, {r2-r3} @ vAA/vAA+1<- r2/r3 2870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT: /* 0x67 */ 3006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 3019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_finish: @ field ptr in r0 3020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SPUT handler. 3033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sput-wide vAA, field@BBBB */ 3035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r0, AA in r9 3044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 3046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offStaticField_value] @ field<- vAA/vAA+1 3048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve 3067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_OBJECT_finish: @ field ptr in r0 3068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_finish: 3268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue on 3270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ yes, continue on 3290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue 3296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_invokeMethodNoRange @ jump to common handler 3326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue on 3432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ yes, continue on 3454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue 3460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_invokeMethodRange @ jump to common handler 3492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_INT: /* 0x7b */ 3516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_INT.S */ 3517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_INT: /* 0x7c */ 3543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_INT.S */ 3544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_LONG.S */ 3571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_LONG.S */ 3600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ optional op; may set condition codes 3617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_FLOAT.S */ 3629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_DOUBLE.S */ 3656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_LONG.S */ 3685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3711968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3712968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 372138214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitos s1, s0 @ s1<- op 3727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3736968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3737968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 374638214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitod d0, s0 @ d0<- op 3752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 3764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 3765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 3766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 3771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 3774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopNarrower.S */ 3782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 32-bit quantity in r0. 3786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: long-to-float, double-to-int, double-to-float 3788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (This would work for long-to-int, but that instruction is actually 3790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an exact match for OP_MOVE.) 3791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 3803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3839968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3840968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 384938214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizs s1, s0 @ s1<- op 3855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3893968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3894968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 390338214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtds d0, s0 @ d0<- op 3909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3918968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3919968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 392838214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizd s0, d0 @ s0<- op 3934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3974968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3975968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 398438214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtsd s0, d0 @ s0<- op 3990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_BYTE.S */ 4000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #24 @ optional op; may set condition codes 4015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 4017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 4026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_CHAR.S */ 4027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 4044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_SHORT.S */ 4054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT: /* 0x90 */ 4080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT.S */ 4081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT: /* 0x91 */ 4122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT.S */ 4123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT: /* 0x92 */ 4164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT.S */ 4165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT: /* 0x93 */ 4207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT.S */ 4208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT: /* 0x94 */ 4249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT.S */ 4250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 4284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT: /* 0x95 */ 4292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT.S */ 4293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT: /* 0x96 */ 4334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT.S */ 4335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT: /* 0x97 */ 4376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT.S */ 4377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT: /* 0x98 */ 4418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT.S */ 4419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT: /* 0x99 */ 4460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT.S */ 4461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT: /* 0x9a */ 4502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT.S */ 4503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply. 4637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WX 4640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * x YZ 4641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * -------- 4642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ZW ZX 4643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * YW YX 4644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The low word of the result holds ZX, the high word holds 4646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * it doesn't fit in the low 64 bits. 4648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most ARM math operations, multiply instructions have 4650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * restrictions on using the same register more than once (Rd and Rm 4651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * cannot be the same). 4652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long vAA, vBB, vCC */ 4654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 4662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_MUL_LONG_finish 4669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG: /* 0x9f */ 4718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG.S */ 4719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG.S */ 4765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 4798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG.S */ 4810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long vAA, vBB, vCC */ 4907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_finish 4924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long vAA, vBB, vCC */ 4936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_finish 4953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long vAA, vBB, vCC */ 4965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_finish 4982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4986968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4987968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 4988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 4994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 4996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 500038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 500238214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 5007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 5016968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 5017968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 503038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 503238214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 5037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 5046968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5047968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 506038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 506238214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 5067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5076968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5077968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 509038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 509238214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 5097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 5109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 5112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 5119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 5123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 5130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 5131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 5139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 5143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5149968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5150968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 516338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 516538214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ s2<- op 5170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5179968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5180968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 519338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 519538214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ s2<- op 5200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5209968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5210968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 522338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 522538214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ s2<- op 5230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5239968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5240968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 525338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 525538214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ s2<- op 5260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 5272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 5284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 5305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 5309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_2ADDR.S */ 5477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 5509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_2ADDR.S */ 5518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_2ADDR.S */ 5558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See OP_MUL_LONG for an explanation. 5846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * again we stuff it into rINST. 5849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long/2addr vA, vB */ 5851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 5859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 5988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG_2ADDR.S */ 6000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 6030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 6031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 6041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 6042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 6084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long/2addr vA, vB */ 6089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_2ADDR_finish 6105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long/2addr vA, vB */ 6115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_2ADDR_finish 6131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long/2addr vA, vB */ 6141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_2ADDR_finish 6157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6161968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6162968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 617338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 617538214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 6181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6189968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6190968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 620138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 620338214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 6209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6217968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6218968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 622938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 623138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 6237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6245968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6246968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 625738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 625938214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 6265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 6276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 6295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 6304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6314968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6315968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 632738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 632938214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ d2<- op 6335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6343968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6344968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 635638214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 635838214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ d2<- op 6364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6372968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6373968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 638538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 638738214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ d2<- op 6393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6401968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6402968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 641438214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 641638214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ d2<- op 6422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 6463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT16.S */ 6474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT.S */ 6511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT16.S */ 6549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT16.S */ 6587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT16.S */ 6624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT16.S */ 6662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT16.S */ 6699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT16.S */ 6736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 7008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 7009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 7036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 7037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 7047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 7048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 7075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 7076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E3: /* 0xe3 */ 7203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E3.S */ 7204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E4: /* 0xe4 */ 7212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E4.S */ 7213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E5: /* 0xe5 */ 7221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E5.S */ 7222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E6: /* 0xe6 */ 7230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E6.S */ 7231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E7: /* 0xe7 */ 7239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E7.S */ 7240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E8: /* 0xe8 */ 7248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E8.S */ 7249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E9: /* 0xe9 */ 7257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E9.S */ 7258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_EA: /* 0xea */ 7266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_EA.S */ 7267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_EB: /* 0xeb */ 7275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_EB.S */ 7276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 728396516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 728496516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a throw-verification-error instruction. This throws an 7296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception for an error discovered during verification. The 7297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op AA, ref@BBBB */ 7300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 7302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ export the PC 7303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowVerificationError @ always throws 7305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ handle exception 7306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Execute a "native inline" instruction. 7314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7315b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7316b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7318b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7319b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7320b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ can throw 7326b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 7328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [sp] @ push &glue->retval 7329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ pop stack 7331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ test boolean result of inline 7332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7339b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7340b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7341b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7342b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7343b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7344b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7345b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7346b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7347b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7348b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7349b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7350b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7351b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7352b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7353b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7354b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7355b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7356b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7357b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7358b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7359b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7360b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7361b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7362b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7363b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7364b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7365b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) 7419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iput-quick, iput-object-quick */ 7454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A(+) 7475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 7476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 7477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ check object for null 7480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- field byte offset 7483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iput-quick, iput-object-quick */ 7495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FC: /* 0xfc */ 7624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FC.S */ 7625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FD: /* 0xfd */ 7633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FD.S */ 7634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FE: /* 0xfe */ 7642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FE.S */ 7643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionEnd 7661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionEnd: 7662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 7664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Sister implementations 7666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterStart 7669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmSisterStart, %function 7670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 7671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 4 7672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterStart: 7673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING */ 7675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (String ref) 7679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_resolve: 7682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBBBBBB (String ref) 7699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_CLASS */ 7715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the Class has not yet been resolved. 7718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (Class ref) 7719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_CLASS_resolve: 7722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- Class reference 7727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CHECK_CAST */ 7736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_fullcheck: 7744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ class of the object that failed to be cast. 7750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ about to throw 7751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .LstrClassCastExceptionPtr 7753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowExceptionWithClassMessage 7755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds BBBB 7761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolve: 7764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- BBBB 7767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastExceptionPtr: 7777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrClassCastException 7778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INSTANCE_OF */ 7781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_fullcheck: 7789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_INSTANCE_OF_store 7791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds boolean result 7794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_store: 7797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test succeeded, save and bail. 7804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_trivial: 7807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ indicate success 7808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r3 holds BBBB 7818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolve: 7821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r3 @ r1<- BBBB 7824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 7831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_INSTANCE */ 7837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 32 @ minimize cache lines 7839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 7846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Class initialization required. 7850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class object 7852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_needinit: 7854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0 @ save r0 7855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInitClass @ initialize class 7856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ check boolean result 7857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ restore r0 7858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ failed, deal with init exception 7860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds BBBB 7865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolve: 7867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 7874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationErrorPtr: 7876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInstantiationError 7877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_ARRAY */ 7880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolve class. (This is an uncommon case.) 7884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 7886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds class ref CCCC 7887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_resolve: 7889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ r9<- length (save) 7891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- CCCC 7892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 7895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ r1<- length (restore) 7897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_NEW_ARRAY_finish 7899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Finish allocation. 7902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class 7904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 7905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_finish: 7907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 7908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 7909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 7911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 7914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ vA<- r0 7916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 7920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 7923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 7924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 7925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_continue: 7927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 7932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 7933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #'I' @ array of ints? 7936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'L' @ array of objects? 7937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'[' @ array of arrays? 7938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 7939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 7940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 7942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 7948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 7950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 7952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 7957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 7958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 7959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 7960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 7961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 7962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 7963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 7964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 7965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 7966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 7967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 7968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 7969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 7970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 7971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 7972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 7973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 7974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 7977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 7982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 7983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 7985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 7986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 7987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 7988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) @ define in one or the other, not both 7991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 7992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 7993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 7994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 7995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 7999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 8003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 8004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 8006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 8009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 8011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #'I' @ array of ints? 8015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'L' @ array of objects? 8016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'[' @ array of arrays? 8017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 8018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 8019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 8021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 8027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 8029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 8031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 8041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 8042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 8043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 8044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 8045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 8046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 8056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 8058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 8061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 8062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 8065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 8067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 8068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) @ define in one or the other, not both 8070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 8071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 8072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_FLOAT */ 8078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_FLOAT_finish: 8079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_FLOAT */ 8084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_FLOAT_finish: 8085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_DOUBLE */ 8090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_DOUBLE_finish: 8091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_DOUBLE */ 8096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_DOUBLE_finish: 8097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMP_LONG */ 8102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_less: 8104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, #0 @ r1<- -1 8105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ instead, we just replicate the tail end. 8107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_greater: 8113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ r1<- 1 8114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to _finish 8115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_finish: 8117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_AGET_WIDE */ 8124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_AGET_WIDE_finish: 8126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_WIDE */ 8135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_WIDE_finish: 8137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_OBJECT */ 8145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = vBB (arrayObj) 8148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = vAA (obj) 8149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = offset into array (vBB + vCC * width) 8150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_finish: 8152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ storing null reference? 8153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ okay? 8158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errArrayStore @ no 8159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_skip_check: 8160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET */ 8167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_finish: 8174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_WIDE */ 8188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_WIDE_finish: 8195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_OBJECT */ 8209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_OBJECT_finish: 8216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BOOLEAN */ 8230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BOOLEAN_finish: 8237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BYTE */ 8251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BYTE_finish: 8258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_CHAR */ 8272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_CHAR_finish: 8279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_SHORT */ 8293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_SHORT_finish: 8300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT */ 8314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_finish: 8321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_WIDE */ 8335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_WIDE_finish: 8342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 8352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_OBJECT */ 8356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_OBJECT_finish: 8363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BOOLEAN_finish: 8384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BYTE */ 8398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BYTE_finish: 8405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_CHAR */ 8419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_CHAR_finish: 8426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_SHORT */ 8440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_SHORT_finish: 8447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET */ 8461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_resolve: 8467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_finish @ yes, finish 8473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_WIDE */ 8477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_resolve: 8483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_OBJECT */ 8493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_resolve: 8499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BOOLEAN */ 8509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_resolve: 8515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BYTE */ 8525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_resolve: 8531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_CHAR */ 8541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_resolve: 8547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_SHORT */ 8557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_resolve: 8563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT */ 8573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_resolve: 8579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_finish @ yes, finish 8585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_WIDE */ 8589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: &fp[AA] 8594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_resolve: 8596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_OBJECT */ 8606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_OBJECT_resolve: 8612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_OBJECT_finish @ yes, finish 8618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_resolve: 8628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BYTE */ 8638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_resolve: 8644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_CHAR */ 8654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_resolve: 8660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_SHORT */ 8670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_resolve: 8676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_continue: 8693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER */ 8704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_continue: 8711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_resolve: 8722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_nsm: 8734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT */ 8739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_resolve: 8746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the float in r0 to a long in r0/r1. 8830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenf2l_doconv: 8836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, lr} 8837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0x5f000000 @ (float)maxlong 8838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r4, r0 8839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0xdf000000 @ (float)minlong 8847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (80000000) 8850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r4 8855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpeq @ is arg == self? 8856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmeqfd sp!, {r4, pc} 8859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_f2lz @ convert float to long 8862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, pc} 8863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddend2l_doconv: 8874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, r5, lr} @ save regs 88755162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 88765162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 88775162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align for EABI 88795162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r5, r1 @ and r1 8881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 8882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 8884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 8886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 88895162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 88905162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 88915162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 8892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmple @ is arg <= minlong? 8893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (8000000000000000) 8895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 8897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 8900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r4 @ compare against self 8901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r5 8902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpeq @ is arg == self? 8903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f 8906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 8909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_d2lz @ convert double to long 8910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 8912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 8913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, r5, pc} 8914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_MUL_LONG */ 8917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_MUL_LONG_finish: 8919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 8921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG */ 8925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_finish: 8927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 8928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG */ 8934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_finish: 8936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 8937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG */ 8943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_finish: 8945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 8946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 8952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_2ADDR_finish: 8954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 8960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_2ADDR_finish: 8962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 8968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_2ADDR_finish: 8970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_EXECUTE_INLINE */ 8976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Extract args, call function. 8979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = #of args (0-4) 8980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = call index 8981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 8982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Other ideas: 8984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Use a jump table from the main piece to jump directly into the 8985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 8986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Have five separate pieces that do the loading, so we can work the 8987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interleave a little better. Increases code size. 8988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_continue: 8990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 8991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r9, 2) @ r9<- FEDC 8992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 8993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 8994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r9, #0xf000 @ isolate F 8995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 8996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r9, #0x0f00 @ isolate E 8997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 8998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r9, #0x00f0 @ isolate D 8999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 9000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r9, #0x000f @ isolate C 9001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 9002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: 9003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 9004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (not reached) 9006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_table: 9008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word gDvmInlineOpsTable 9009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9011b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 9012b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9013b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 9014b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 9015b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 9016b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 9017b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9018b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 9019b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 9020b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9021b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 9022b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9023b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9024b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 9025b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 9026b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 9027b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 9028b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 9029b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 9030b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 9031b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 9032b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 9033b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 9034b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9035b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 9036b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9037b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 9038b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 9039b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9040b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 9042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterEnd 9043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterEnd: 9044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/footer.S */ 9046ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common subroutines and data 9050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9053ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9054ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 9056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 9057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9058ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 905997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 906097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 906197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 906297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 906397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 906497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 906597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 906697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 906797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 906897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 906997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 907097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToTraceSelect 907197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToTraceSelect: 90729a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 907397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 907497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 907597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 907697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToBackwardBranch 907797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToBackwardBranch: 90789a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 907997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 908097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 908197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 908297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 908397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 90849a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 908597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 908697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 908797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 908897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 908997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 909097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 909197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 909297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 909397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9094ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9095ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter when the compiler is 9096ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * having issues translating/executing a Dalvik instruction. We have to skip 9097ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the code cache lookup otherwise it is possible to indefinitely bouce 9098ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * between the interpreter and the code cache if the instruction that fails 9099ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * to be compiled happens to be at a trace start. 9100ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9101ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpPunt 9102ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpPunt: 91037a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9104ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r0 9105ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9106ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,lr 9107ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpPunt; 9108ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9109ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 91107a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r0, #0 91117a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9112ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9113ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9114ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9115ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9116ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9117ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9118ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return to the interpreter to handle a single instruction. 9119ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * On entry: 9120ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r0 <= PC 9121ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r1 <= PC of resume instruction 9122ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * lr <= resume point in translation 9123ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9124ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpSingleStep 9125ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpSingleStep: 9126ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str lr,[rGLUE,#offGlue_jitResume] 9127ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1,[rGLUE,#offGlue_jitResumePC] 9128ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#kInterpEntryInstr 9129ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ enum is 4 byte in aapcs-EABI 9130ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_entryPoint] 9131ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC,r0 9132ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 91337a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng 9134ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9135ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitSingleStep @ Ask for single step and then revert 9136ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9137ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp to bail to debug interp 9138ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9139ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9140ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9141ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9142ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache and immediately request 9143ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a translation for the exit target. Commonly used following 9144ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * invokes. 9145ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9146ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToTraceSelect 9147ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToTraceSelect: 91489a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 91497a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 91509a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9151ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 91527a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 91537a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9154ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9155ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng beq 2f 9156ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9157ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 91589a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 91599a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 916046cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 916146cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 916246cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9163ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9164ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* No translation, so request one if profiling isn't disabled*/ 9165ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng2: 91661da12167d913efde56ec3b40491524b051679f2cAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9167ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9168ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9169ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0, #0 9170ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_selectTrace 9171ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9172ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9173ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9174ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9175ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter. 9176ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * The return was done with a BLX from thumb mode, and 9177ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the following 32-bit word contains the target rPC value. 9178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Note that lr (r14) will have its low-order bit set to denote 9179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * its thumb-mode origin. 9180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 9181ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * We'll need to stash our lr origin away, recover the new 9182ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * target and then check to see if there is a translation available 9183ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * for our new target. If so, we do a translation chain and 9184ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * go back to native execution. Otherwise, it's back to the 9185ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * interpreter (after treating this entry as a potential 9186ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace start). 9187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNormal 9189ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNormal: 91909a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 91917a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 91929a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9193ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9194ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNormal 9195ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9196ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9197ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 91987a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9199ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 920046cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee beq toInterpreter @ go if not, otherwise do chain 9201ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9202ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 92039a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 92049a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 920546cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 920646cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 920746cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9208ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9209ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9210ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter to do method invocation. 9211ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Check if translation exists for the callee, but don't chain to it. 9212ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9213ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNoChain 9214ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNoChain: 9215ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9216ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNoChain 9217ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 92187a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9219ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9220ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 92217a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 92229a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 92239a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9224ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9225ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ continue native execution if so 922697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9227ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9228ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9229ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * No translation, restore interpreter regs and start interpreting. 9230ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * rGLUE & rFP were preserved in the translated code, and rPC has 9231ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * already been restored by the time we get here. We'll need to set 9232ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * up rIBASE & rINST, and load the address of the JitTable into r0. 9233ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 923446cd5b63c29d3284a9ff3e0d0711fb136f409313Bill BuzbeetoInterpreter: 9235ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9236ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9237ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9238ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9239ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ NOTE: intended fallthrough 9240ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9241ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Common code to update potential trace start counter, and initiate 9242ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a trace-build if appropriate. On entry, rPC should point to the 9243ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * next instruction to execute, and rINST should be already loaded with 9244ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the next opcode word, and r0 holds a pointer to the jit profile 9245ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * table (pJitProfTable). 9246ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9247ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_testUpdateProfile: 9248ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9249ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9250ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9251ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9252ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_updateProfile: 9253ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 92549797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee lsl r3,r3,#21 @ shift out excess 2047 92559797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee ldrb r1,[r0,r3,lsr #21] @ get counter 9256ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9257ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng subs r1,r1,#1 @ decrement counter 92589797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee strb r1,[r0,r3,lsr #21] @ and store it 9259ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9260ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9261ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9262ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Here, we switch to the debug interpreter to request 9263ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace selection. First, though, check to see if there 9264ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * is already a native translation in place (and, if so, 9265ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * jump to it now). 9266ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9267d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 92687a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 92699797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee strb r1,[r0,r3,lsr #21] @ reset counter 9270ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9271ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9272ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 92737a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 92747a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, rPC @ arg1 of translation may need this 92757a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 9276ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 927797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9278ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ jump to the translation 927997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 92809a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 92819a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 92829a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 92839a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 92849a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 92859a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 92869a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r10, r0 @ save target 92879a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 92889a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee cmp r0, r10 @ special case? 92899a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bne dvmJitSelfVerificationStart @ set up self verification 92909a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 92919a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 92929a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 929397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 92949a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 9295ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_selectTrace: 9296ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitTSelectRequest @ ask for trace selection 9297ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 92989c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 92999c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9300ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp 9301ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9302ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 930397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 930497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 930597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 930697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 93079a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * On entry, r10 contains the address of the target translation. 930897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 930997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationStart: 931097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 931197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 931297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 93139a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 931497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9315ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9316ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9317ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 931897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 931997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 932097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 932197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 932297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 932397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationEnd: 93246999d84e2c55dc4a46a6c311b55bd5811336d9c4Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93256999d84e2c55dc4a46a6c311b55bd5811336d9c4Ben Cheng mov r1, #0 93266999d84e2c55dc4a46a6c311b55bd5811336d9c4Ben Cheng str r1, [r10, #offThread_inJitCodeCache] @ Back to the interp land 932797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 932897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9329ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9330ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9331ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9332ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 933397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 933497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 933597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 933697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 933730f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 933830f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 933997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 934097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 934197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 934297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 934397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 934497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 934597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 934697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 934797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 934897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 934997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9350ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9351ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code when a backward branch is taken. 9354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is PC adjustment *in bytes* 9357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_backwardBranch: 9359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryInstr 9360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9361ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9362ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9363ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9364ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9365ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9366ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9367ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9368ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9372ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * activity has begun. 9378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: if JDWP isn't running, zero out pDebuggerActive pointer so we don't 9380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have to do the second ldr. 9381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: reduce this so we're just checking a single location. 9383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is reentry type, e.g. kInterpEntryInstr 9386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is trampoline PC adjustment *in bytes* 9387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_periodicChecks: 9389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 93919c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng @ speculatively store r0 before it is clobbered by dvmCheckSuspendPending 93929c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r0, [rGLUE, #offGlue_entryPoint] 93939c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng 9394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) 9395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_PROFILER) 9398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3] @ r3<- suspendCount (int) 9402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) 9404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r1] @ r1<- debuggerActive (boolean) 9405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined (WITH_PROFILER) 9407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ suspend pending? 9411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 2f @ yes, do full suspension check 9412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# if defined(WITH_DEBUGGER) && defined(WITH_PROFILER) 9415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r1, r1, r2 @ r1<- r1 | r2 9416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ debugger attached or profiler started? 9417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# elif defined(WITH_DEBUGGER) 9418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ debugger attached? 9419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# elif defined(WITH_PROFILER) 9420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ profiler started? 9421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# endif 9422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 3f @ debugger/profiler, switch interp 9423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr @ nothing to do, return 9426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: @ check suspend 9428964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9429964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee /* 9430964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * Refresh the Jit's cached copy of profile table pointer. This pointer 9431964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * doubles as the Jit's on/off switch. 9432964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee */ 9433964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ r10<-&gDvmJit.pJitProfTable 9434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9435964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r10 <- pJitProfTable 9436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC 9437964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh Jit's on/off switch 9438964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#else 9439964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9440964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee EXPORT_PC() @ need for precise GC 9441964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmCheckSuspendPending @ suspend if necessary, then return 9443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: @ debugger/profiler enabled, bail out 9445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, rPC, r9 @ update rPC 9446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ "want switch" = true 9447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail 9448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * State registers will be saved to the "glue" area before bailing. 9454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * other interpreter or just bail all the way out 9458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_gotoBail: 9460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ r0<- glue ptr 9462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r1, r1, #1 @ using (boolean+1) 9465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl _longjmp @ does not return 9467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_abort 9468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation with range. 9472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodRange: 9477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewRange: 9478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- CCCC 9483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r2, r2, #1 @ count-- 9491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r10], #4 @ *outs++ = val 9492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1b @ ...while count != 0 9493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LinvokeArgsDone 9495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation without range. 9498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodNoRange: 9503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewNoRange: 9504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone 9511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNonRange: 9514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vA 9521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r1, #0xf000 @ isolate G 9522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vG 9525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r1, #0x0f00 @ isolate F 9526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vF 9529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r1, #0x00f0 @ isolate E 9530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vE 9533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r1, #0x000f @ isolate D 9534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 9535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vD 9537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: @ fall through to .LinvokeArgsDone 9538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 9540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 9541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 9542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ find space for the new stack frame, check for overflow 9543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 9544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 9545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 9546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@ bl common_dumpRegs 9547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 9548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 9549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, r9 @ bottom < interpStackEnd? 9550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 9551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LstackOverflow @ yes, this frame will overflow stack 9552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ set up newSaveArea 9554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef EASY_GDB 9555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 9556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [r10, #offStackSaveArea_prevSave] 9557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 9559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 9560ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9561ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r9, #0 9562ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r9, [r10, #offStackSaveArea_returnAddr] 9563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r10, #offStackSaveArea_method] 9565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden tst r3, #ACC_NATIVE 9566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LinvokeNative 9567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 9570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 9571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP 9572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 9574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 9575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 9576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 9577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 9578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 9579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 9580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 9581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 9584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 9585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r2 @ publish new rPC 9586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 9587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Update "glue" values for the new method 9589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 9590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 9591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 9592ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9593ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r1 @ fp = newFp 9595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rINST, r9 @ publish new rINST 9597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9598ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9599ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9601ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9602ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rFP, r1 @ fp = newFp 9603ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9604ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rINST, r9 @ publish new rINST 9605ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9606ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 9607ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNative: 9610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Prep for the native call 9611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 9612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9613d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 9614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 9615d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 9616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r3 @ r9<- glue->self (preserve) 9617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ r2<- methodToCall 9619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ r0<- newFp (points to args) 9620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 9621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 9623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 9624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .Lskip 9625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_mterp, %function 9626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_mterp: 9627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 9628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 9629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 9630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lskip: 9631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @mov lr, pc @ set return addr 9634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 9635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 9636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9637964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9638964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ Refresh Jit's on/off status 9639964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9640964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee 9641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ native return; r9=self, r10=newSaveArea 9642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ equivalent to dvmPopJniLocals 9643d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 9644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 9645964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9646964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 9647964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 9649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null? 9650d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 9651964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9652964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh cached on/off switch 9653964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ no, handle exception 9655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 9657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 96606ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 96616ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 9662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 9663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmHandleStackOverflow 9664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 9666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 9667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation, calling through "glue code". 9672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: now that we have range and non-range invoke handlers, this 9674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * needs to be split into two. Maybe just create entry points 9675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that set r9 and jump here? 9676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 9680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeOld: 9683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #8 @ space for args + pad 9684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 9685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ A2<- methodToCall 9686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ A0<- glue 9687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ A1<- methodCallRange 9689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ A3<- AA 9690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #0] @ A4<- ip 9691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 9692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ remove arg area 9693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall @ continue to next instruction 9694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for handling a return instruction. 9700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 9702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_returnFromMethod: 9704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnNew: 9705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryReturn 9706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 9707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 9710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 9711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 9712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 9713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r2<- method we're returning to 9714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is this a break frame? 9716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 9717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 9718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_gotoBail @ break frame, bail out completely 9719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 9721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 9722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 9723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 9724ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 97257a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 9726ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9727ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r9 @ publish new rPC 9728ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_methodClassDex] 97297a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r10, [r3, #offThread_inJitCodeCache] @ may return to JIT'ed land 97307a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng cmp r10, #0 @ caller is compiled code 97317a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng blxne r10 9732ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 9733ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9734ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9735ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 9736ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r9 @ publish new rPC 9739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 9740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9741ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return handling, calls through "glue code". 9745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnOld: 9748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 9750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_returnFromMethod 9751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 9752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Somebody has thrown an exception. Handle it. 9757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If the exception processing code returns to us (instead of falling 9759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out of the interpreter), continue with whatever the next instruction 9760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * now happens to be. 9761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 9763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9764ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmMterpCommonExceptionThrown 9765ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmMterpCommonExceptionThrown: 9766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_exceptionThrown: 9767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionNew: 9768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryThrow 9769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 9770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9772ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9773ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitTSelectAbort @ abandon trace selection in progress 9774ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9775ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9776ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 9778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 9779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 9782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- NULL 9783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 9784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up args and a local for "&fp" */ 9786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 9787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [sp, #-4]! @ *--sp = fp 9788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov ip, sp @ ip<- &fp 9789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- false 9790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #-4]! @ *--sp = &fp 9791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 9792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 9793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 9794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r9 @ r2<- exception 9795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 9796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 9797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 9799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 9800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 9802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 9804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ no, skip ahead 9805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r0 @ save relPc result in rFP 9806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 98074fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden mov r1, r9 @ r1<- exception 9808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCleanupStackOverflow @ call(self) 9809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP @ restore result 9810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 9811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 9813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 9814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is catchRelPc < 0? 9815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ restore stack 9816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi .LnotCaughtLocally 9817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* adjust locals to match self->curFrame and updated PC */ 9819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 9820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 9821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 9822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 9823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 9824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 9825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 9826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 9827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* release the tracked alloc on the exception */ 9829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* restore the exception if the handler wants it */ 9834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 9835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 9837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 9838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 9841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix stack overflow if necessary */ 9842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 9844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, r10 @ if yes: r0<- self 98454fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden movne r1, r9 @ if yes: r1<- exception 9846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 9847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ may want to show "not caught locally" debug messages here 9849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if DVM_SHOW_EXCEPTION >= 2 9850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call __android_log_print(prio, tag, format, ...) */ 9851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* "Exception %s from %s:%d not caught locally" */ 9852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 9853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 9854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_insns] 9855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 9856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden asr r1, r1, #1 9857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLineNumFromPC 9858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 9859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmGetMethodSourceFile(method) 9860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 9861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmGetMethodSourceFile 9862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 9863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ exception->clazz->descriptor 9864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] 9865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_descriptor] 9866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ 9867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, strExceptionNotCaughtLocally 9868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strLogTag 9869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #3 @ LOG_DEBUG 9870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __android_log_print 9871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offThread_exception] @ restore exception 9873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 9877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail @ bail out 9878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exception handling, calls through "glue code". 9882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionOld: 9885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 9887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_exceptionThrown 9888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 9889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * After returning from a "glued" function, pull out the updated 9894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * values and start executing at the next instruction. 9895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_resumeAfterGlueCall: 9897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 9898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 9899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array index. 9904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayIndex: 9906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayIndexException 9908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array value. 9914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayStore: 9916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayStoreException 9918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Integer divide or mod by zero. 9924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errDivideByZero: 9926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArithmeticException 9928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strDivideByZero 9929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Attempt to allocate an array with a negative size. 9934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNegativeArraySize: 9936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNegativeArraySizeException 9938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invocation of a non-existent method. 9944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNoSuchMethod: 9946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNoSuchMethodError 9948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We encountered a null object when we weren't expecting one. We 9954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * export the PC, throw a NullPointerException, and goto the exception 9955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * processing code. 9956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNullObject: 9958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNullPointerException 9960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For debugging, cause an immediate fault. The source address will 9966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be in lr (use a bl instruction to jump here). 9967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_abort: 9969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, .LdeadFood 9970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LdeadFood: 9971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word 0xdeadf00d 9972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out a "we were here", preserving all registers. (The attempt 9975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to save ip won't work, but we need to save an even number of 9976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * registers for EABI 64-bit stack alignment.) 9977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .macro SQUEAK num 9979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_squeak\num: 9980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 9982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #\num 9983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 9984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 9986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endm 9987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 0 9989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 1 9990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 2 9991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 3 9992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 4 9993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 5 9994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out the number in r0, preserving registers. 9997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNum: 9999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 10002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print a newline, preserving registers. 10008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNewline: 10010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNewline 10012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 10018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printHex: 10020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintHex 10023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 10029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printLong: 10031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r1 10033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 10034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintLong 10035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 10041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printMethod: 10043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpPrintMethod 10045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Call a C helper function that dumps regs and possibly some 10050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * additional info. Requires the C function to be compiled in. 10051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_dumpRegs: 10054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpDumpArmRegs 10056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10060d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#if 0 10061d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden/* 10062d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Experiment on VFP mode. 10063d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10064d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 10065d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10066d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 10067d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden */ 10068d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddensetFPSCR: 10069d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r0, r0, r1 @ make sure no stray bits are set 10070d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmrx r2, fpscr @ get VFP reg 10071d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mvn r1, r1 @ bit-invert mask 10072d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r2, r2, r1 @ clear masked bits 10073d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden orr r2, r2, r0 @ set specified bits 10074d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmxr fpscr, r2 @ set VFP reg 10075d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, r2 @ return new value 10076d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bx lr 10077d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10078d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .align 2 10079d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .global dvmConfigureFP 10080d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .type dvmConfigureFP, %function 10081d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddendvmConfigureFP: 10082d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden stmfd sp!, {ip, lr} 10083d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x03000000 sets DN/FZ */ 10084d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x00009f00 clears the six exception enable flags */ 10085d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl common_squeak0 10086d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10087d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10088d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl setFPSCR 10089d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden ldmfd sp!, {ip, pc} 10090d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#endif 10091d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references, must be close to the code that uses them. 10095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 10097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArithmeticException: 10098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArithmeticException 10099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayIndexException: 10100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayIndexException 10101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayStoreException: 10102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayStoreException 10103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrDivideByZero: 10104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrDivideByZero 10105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNegativeArraySizeException: 10106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNegativeArraySizeException 10107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNoSuchMethodError: 10108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNoSuchMethodError 10109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNullPointerException: 10110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNullPointerException 10111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrLogTag: 10113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrLogTag 10114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrExceptionNotCaughtLocally: 10115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrExceptionNotCaughtLocally 10116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNewline: 10118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNewline 10119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrSqueak: 10120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrSqueak 10121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintHex: 10122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintHex 10123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintLong: 10124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintLong 10125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Zero-terminated ASCII string data. 10128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with the address, or use an ADR pseudo-op to get the address 10131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * PC-relative addressing mode and hence has a limited range, which 10133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * makes it not work well with mergeable string sections. 10134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrBadEntryPoint: 10138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Bad entry point %d\n" 10139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArithmeticException: 10140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArithmeticException;" 10141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayIndexException: 10142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayStoreException: 10144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastException: 10146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ClassCastException;" 10147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrDivideByZero: 10148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "divide by zero" 10149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrFilledNewArrayNotImpl: 10150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInternalError: 10152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InternalError;" 10153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationError: 10154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InstantiationError;" 10155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNegativeArraySizeException: 10156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNoSuchMethodError: 10158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNullPointerException: 10160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NullPointerException;" 10161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrLogTag: 10163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "mterp" 10164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrExceptionNotCaughtLocally: 10165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNewline: 10168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "\n" 10169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrSqueak: 10170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%d>" 10171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintHex: 10172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<0x%x>" 10173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintLong: 10174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%lld>" 10175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10177