InterpAsm-armv5te-vfp.S revision 6bbdd6b005ec5cb567ec9576190a7cd784248c5c
1a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 2a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * --> DO NOT EDIT <-- 5a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/header.S */ 8a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 10a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 11a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 13a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 14a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 15a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 17a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 18a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 21a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 22a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 23a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 24a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ARMv5 definitions and declarations. 25a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 26a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 27a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 28a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenARM EABI general notes: 29a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 30a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 31a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr4-r8 are available for general use 32a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr9 is given special treatment in some situations, but not for us 33a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr10 (sl) seems to be generally available 34a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 35a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr12 (ip) is scratch -- not preserved across method calls 36a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr13 (sp) should be managed carefully in case a signal arrives 37a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr14 (lr) must be preserved 38a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr15 (pc) can be tinkered with directly 39a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 40a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0 holds returns of <= 4 bytes 41a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 42a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 43a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 44a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 45a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 46a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 47a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 48a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 49a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden(i.e. the 5th arg). 50a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 51a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenVFP: single-precision results in s0, double-precision results in d0. 52a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 53a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 54a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 55a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 56a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 57a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 58a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMterp and ARM notes: 59a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 60a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenThe following registers have fixed assignments: 61a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 62a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden reg nick purpose 63a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r4 rPC interpreted program counter, used for fetching instructions 64a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 65a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r6 rGLUE MterpGlue pointer 661da12167d913efde56ec3b40491524b051679f2cAndy McFadden r7 rINST first 16-bit code unit of current instruction 671da12167d913efde56ec3b40491524b051679f2cAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 68a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 69a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMacros are provided for common operations. Each macro MUST emit only 70a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 71a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenunspecified registers or condition codes. 72a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 73a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 74a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* single-purpose registers, given names for clarity */ 75a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rPC r4 76a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rFP r5 77a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rGLUE r6 781da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rINST r7 791da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rIBASE r8 80a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 81a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* save/restore the PC and/or FP from the glue struct */ 82a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 83a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 84a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 85a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 86a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 87a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 88a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 89a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 90a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 91a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be done *before* something calls dvmThrowException. 92a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 93a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 94a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 95a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 96a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * It's okay to do this more than once. 97a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 98a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define EXPORT_PC() \ 99a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Given a frame pointer, find the stack save area. 103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_INST() ldrh rINST, [rPC] 113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from the specified offset. Advances rPC 116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Because of the limited size of immediate constants on ARM, this is only 119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with this). 121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This must come AFTER anything that can throw an exception, or the 123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception catch may miss. (This also implies that it must come after 124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * EXPORT_PC().) 125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * here. 144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch a half-word code unit from an offset past the current PC. The 149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The "_S" variant works the same but treats the value as signed. 152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * byte of the halfword you want (lo/hi). 160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the instruction's opcode field into the specified register. 165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the prefetched instruction's opcode field into the specified register. 170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Get/set the 32-bit value from a Dalvik register. 183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 189d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 190ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert a virtual register index into an address. 194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add _reg, rFP, _vreg, lsl #2 197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is a #include, not a %include, because we want the C pre-processor 200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to expand the macros into assembler assignment statements. 201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#include "../common/asm-constants.h" 203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2047b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#if defined(WITH_JIT) 2057b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#include "../common/jit-config.h" 2067b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#endif 207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/platform.S */ 209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * CPU-version-specific defines 212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * one-way branch. 218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP. Does not modify LR. 220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC source 222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Jump to subroutine. 228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC_LR source 232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov lr, pc 233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDMFD_PC regs 242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {\regs,pc} 243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/entry.S */ 247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Interpreter entry point. 264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't have formal stack frames, so gdb scans upward in the code 268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to find the start of the function (a label with the %function type), 269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and then looks at the next few instructions to figure out what 270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * got pushed onto the stack. From this it figures out how to restore 271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the registers, including PC, for the previous stack frame. If gdb 272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sees a non-function label, it stops scanning, so either we need to 273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have nothing but assembler-local labels between the entry point and 274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the break, or we need to fake it out. 275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * When this is defined, we add some stuff to make gdb less confused. 277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define ASSIST_DEBUGGER 1 279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdRun 283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdRun, %function 284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This function returns a boolean "changeInterp" value. The return comes 290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * via a call to dvmMterpStdBail(). 291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdRun: 293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY1 \ 294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .save {r4-r10,fp,lr}; \ 295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY2 \ 297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .pad #4; \ 298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align 64 299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* save stack pointer, add magic word for debuggerd */ 305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up "named" registers, figure out entry point */ 308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rGLUE, r0 @ set rGLUE 309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offGlue_entryPoint] @ InterpEntry enum is char 310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryInstr @ usual case? 313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .Lnot_instr @ no, handle it 314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 315ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 316ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lno_singleStep: 3177a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 318ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng /* Entry is always a possible trace start */ 319ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 320ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 3217a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, #0 @ prepare the value for the new state 3227a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r1, [r10, #offThread_inJitCodeCache] @ back to the interp land 323ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 324ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 325ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 326ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 327ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* start executing the instruction at rPC */ 329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 332ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_instr: 335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_returnFromMethod 337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_return: 339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown 341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 342ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 343ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lnot_throw: 344ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr r0,[rGLUE, #offGlue_jitResume] 345ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr r2,[rGLUE, #offGlue_jitResumePC] 346ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 347ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lbad_arg 348ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp rPC,r2 349ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lno_singleStep @ must have branched, don't resume 350ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1, #kInterpEntryInstr 351ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng strb r1, [rGLUE, #offGlue_entryPoint] 352ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr rINST, .LdvmCompilerTemplate 353ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bx r0 @ re-enter the translation 354ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.LdvmCompilerTemplate: 355ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .word dvmCompilerTemplateStart 356ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 357ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lbad_arg: 359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strBadEntryPoint 360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r1 holds value of entryPoint 361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAbort 363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdBail 367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdBail, %function 368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Restore the stack pointer and PC from the save point established on entry. 371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * LR to PC. 377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 bool changeInterp 381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdBail: 383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ return the changeInterp value 385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 @ un-align 64 386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references. 391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrBadEntryPoint: 393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrBadEntryPoint 394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionStart 398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmInstructionStart, %function 399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionStart = .L_OP_NOP 400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOP: /* 0x00 */ 405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOP.S */ 406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_inst, %function 413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_inst: 414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE: /* 0x01 */ 424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_16: /* 0x03 */ 455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE.S */ 471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide vA, vB */ 472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/from16 vAA, vBBBB */ 490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- BBBB 492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/16 vAAAA, vBBBB */ 507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- BBBB 509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- AAAA 510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 513445194bc141dc67e2f678aa1bbd5e59ca66254e5Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-result-wide vAA */ 590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-exception vAA */ 621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ r1<- 0 625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN: /* 0x0f */ 642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 64-bit value. Copies the return value into the "glue" 662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* return-wide vAA */ 665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_4: /* 0x12 */ 695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_4.S */ 696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/4 vA, #+B */ 697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_16: /* 0x13 */ 710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_16.S */ 711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/16 vAA, #+BBBB */ 712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST: /* 0x14 */ 723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST.S */ 724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const vAA, #+BBBBbbbb */ 725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/high16 vAA, #+BBBB0000 */ 740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/16 vAA, #+BBBB */ 754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #0 @ r0<- 00000000 808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING: /* 0x1a */ 819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING.S */ 820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBB */ 821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_resolve 828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBBBBBB */ 838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/class vAA, Class@BBBB */ 857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_CLASS_resolve 864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Synchronize on an object. 875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-enter vAA */ 877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null object, throw an exception 883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLockObject @ call(self, obj) 885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ exception raised, bail out 890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlock an object. 901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exceptions that occur when unlocking a monitor need to appear as 903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if they happened at the following instruction. See the Dalvik 904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction spec. 905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-exit vAA */ 907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ before fetch: export the PC 909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 9116bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq 1f @ yes 912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 9166bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq common_exceptionThrown @ yes, exception is pending 917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9196bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee1: 9206bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee FETCH_ADVANCE_INST(1) @ advance before throw 9216bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee b common_errNullObject 922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if a cast from one class to another is allowed. 930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* check-cast vAA, class@BBBB */ 932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r3) @ r9<- object 935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ is object null? 937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolved: 944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_okay: 947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if an object reference is an instance of a class. 957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Most common situation is a non-null object, being compared against 959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an already-resolved class. 960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* instance-of vA, vB, class@CCCC */ 962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- CCCC 970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ARRAY_LENGTH.S */ 984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return the length of an array. 986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yup, fail 993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ vB<- length 997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 1003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 1004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new instance of a class. 1006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-instance vAA, class@BBBB */ 1008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocObject @ r0<- new object 1022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Allocate an array of objects, specified with the array class 1030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and a count. 1031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The verifier guarantees that this is an array class, so we don't 1033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * check for it here. 1034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-array vA, vB, class@CCCC */ 1036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 1037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- CCCC 1038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ check length 1042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_errNegativeArraySize @ negative length, bail 1044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for resolve, alloc 1046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC(); 1117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ 0 means an exception is thrown 1119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ has exception 1120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW: /* 0x27 */ 1127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW.S */ 1128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception object in the current thread. 1130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* throw vAA */ 1132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 1135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 1136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, throw an NPE instead 1137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ bypass dvmSetException, just store it 1138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 1140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO: /* 0x28 */ 1145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO.S */ 1146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 8-bit offset. 1148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto +AA */ 1153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1157ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1158ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1160ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1161ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1164ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1165ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1166ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1167ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1168ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_16: /* 0x29 */ 1173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_16.S */ 1174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 16-bit offset. 1176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/16 +AAAA */ 1181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1184ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1185ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1186ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1189ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1190ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1195ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_32: /* 0x2a */ 1201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_32.S */ 1202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 32-bit offset. 1204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction doesn't affect the V flag, so we need to clear it 1211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * explicitly. 1212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/32 +AAAAAAAA */ 1214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, ip @ (clear V flag during stall) 1217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1220ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1221ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1223ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1224ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1227ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1228ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1229ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1230ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1231ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1257ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1258ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1259ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1260ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1261ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1262ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1263ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1264ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1268ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1296ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1297ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1299ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1300ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1303ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1304ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1305ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1306ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1307ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1314968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13338fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13368fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13388fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13478fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1353968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13728fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13758fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13778fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13868fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1392968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14118fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14148fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14168fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14258fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1431968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14508fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14538fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14558fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14648fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * register based on the results of the comparison. 1474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We load the full values with LDM, but in practice many values could 1476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be resolved by only looking at the high word. This could be made 1477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If we just wanted to set condition flags, we could do this: 1480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subs ip, r0, r2 1481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sbcs ip, r1, r3 1482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subeqs ip, r0, r2 1483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * us a constant 5-cycle path plus a branch at the end to the 1487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction epilogue code. The multi-compare approach below needs 1488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in the worst case (the 64-bit values are equal). 1490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* cmp-long vAA, vBB, vCC */ 1492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 1493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 1496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt .LOP_CMP_LONG_greater 1503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CMP_LONG_less 1506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQ: /* 0x32 */ 1511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQ.S */ 1512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1532ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1533ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1534ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1535ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1536ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1537ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1538ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1541ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NE: /* 0x33 */ 1548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NE.S */ 1549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1570ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1571ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1572ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1573ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1574ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1575ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1578ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LT: /* 0x34 */ 1585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LT.S */ 1586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1606ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1607ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1608ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1609ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1610ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1611ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1612ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1615ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GE: /* 0x35 */ 1622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GE.S */ 1623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1643ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1644ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1645ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1646ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1647ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1648ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1649ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1652ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GT: /* 0x36 */ 1659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GT.S */ 1660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1680ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1681ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1682ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1683ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1684ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1685ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1686ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1689ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LE: /* 0x37 */ 1696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LE.S */ 1697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1717ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1718ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1719ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1720ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1721ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1722ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1723ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1726ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1751ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1752ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1753ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1754ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1755ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1756ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1759ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1760ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1761ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1762ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1763ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1788ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1789ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1790ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1791ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1792ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1793ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1796ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1797ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1798ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1799ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1800ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1825ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1826ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1827ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1828ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1829ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1830ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1833ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1834ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1835ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1836ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1837ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1862ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1863ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1864ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1865ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1866ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1867ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1868ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1869ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1870ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1871ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1874ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1899ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1900ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1901ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1902ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1903ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1904ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1905ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1906ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1907ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1908ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1911ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1936ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1937ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1938ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1939ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1940ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1941ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1944ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1945ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1946ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1947ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1948ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_43: /* 0x43 */ 2000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_43.S */ 2001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 2002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 2003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET: /* 0x44 */ 2009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aget-wide vAA, vBB, vCC */ 2047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT: /* 0x4b */ 2232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aput-wide vAA, vBB, vCC */ 2270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null array object? 2306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r9) @ r9<- vAA 2307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r3 @ compare unsigned index, length 2311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET: /* 0x52 */ 2450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish @ no, already resolved 2465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish 2471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 2477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Wide 32-bit instance field get. 2479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide vA, vB, field@CCCC */ 2481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish 2495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish 2522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish 2551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish 2580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish 2609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish 2638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT: /* 0x59 */ 2644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ no, already resolved 2659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ yes, finish up 2665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 2671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide vA, vB, field@CCCC */ 2672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET: /* 0x60 */ 2835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_finish: @ field ptr in r0 2849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SGET handler. 2862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sget-wide vAA, field@BBBB */ 2864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_finish: 2871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 2872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offStaticField_value] @ r2/r3<- field value (aligned) 2873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[AA] 2874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r1, {r2-r3} @ vAA/vAA+1<- r2/r3 2876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 3000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 3001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 3002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 3005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT: /* 0x67 */ 3012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 3025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_finish: @ field ptr in r0 3026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SPUT handler. 3039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sput-wide vAA, field@BBBB */ 3041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r0, AA in r9 3050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 3052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offStaticField_value] @ field<- vAA/vAA+1 3054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve 3073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_OBJECT_finish: @ field ptr in r0 3074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_finish: 3274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue on 3276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ yes, continue on 3296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue 3302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_invokeMethodNoRange @ jump to common handler 3332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue on 3438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ yes, continue on 3460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue 3466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_invokeMethodRange @ jump to common handler 3498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_INT: /* 0x7b */ 3522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_INT.S */ 3523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_INT: /* 0x7c */ 3549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_INT.S */ 3550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_LONG.S */ 3577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_LONG.S */ 3606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ optional op; may set condition codes 3623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_FLOAT.S */ 3635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_DOUBLE.S */ 3662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_LONG.S */ 3691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3717968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3718968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 372738214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitos s1, s0 @ s1<- op 3733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3742968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3743968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 375238214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitod d0, s0 @ d0<- op 3758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 3770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 3771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 3772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 3777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 3780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopNarrower.S */ 3788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 32-bit quantity in r0. 3792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: long-to-float, double-to-int, double-to-float 3794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (This would work for long-to-int, but that instruction is actually 3796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an exact match for OP_MOVE.) 3797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 3809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3845968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3846968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 385538214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizs s1, s0 @ s1<- op 3861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3899968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3900968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 390938214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtds d0, s0 @ d0<- op 3915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3924968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3925968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 393438214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizd s0, d0 @ s0<- op 3940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3980968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3981968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 399038214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtsd s0, d0 @ s0<- op 3996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 4005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_BYTE.S */ 4006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #24 @ optional op; may set condition codes 4021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 4023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 4032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_CHAR.S */ 4033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 4050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_SHORT.S */ 4060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT: /* 0x90 */ 4086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT.S */ 4087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT: /* 0x91 */ 4128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT.S */ 4129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT: /* 0x92 */ 4170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT.S */ 4171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT: /* 0x93 */ 4213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT.S */ 4214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT: /* 0x94 */ 4255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT.S */ 4256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 4290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT: /* 0x95 */ 4298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT.S */ 4299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT: /* 0x96 */ 4340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT.S */ 4341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT: /* 0x97 */ 4382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT.S */ 4383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT: /* 0x98 */ 4424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT.S */ 4425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT: /* 0x99 */ 4466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT.S */ 4467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT: /* 0x9a */ 4508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT.S */ 4509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply. 4643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WX 4646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * x YZ 4647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * -------- 4648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ZW ZX 4649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * YW YX 4650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The low word of the result holds ZX, the high word holds 4652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * it doesn't fit in the low 64 bits. 4654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most ARM math operations, multiply instructions have 4656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * restrictions on using the same register more than once (Rd and Rm 4657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * cannot be the same). 4658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long vAA, vBB, vCC */ 4660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 4668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_MUL_LONG_finish 4675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG: /* 0x9f */ 4724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG.S */ 4725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG.S */ 4771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 4804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG.S */ 4816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long vAA, vBB, vCC */ 4913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_finish 4930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long vAA, vBB, vCC */ 4942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_finish 4959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long vAA, vBB, vCC */ 4971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_finish 4988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4992968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4993968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 4994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 500638214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 500838214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 5013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 5022968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 5023968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 503638214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 503838214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 5043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 5052968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5053968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 506638214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 506838214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 5073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5082968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5083968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 509638214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 509838214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 5103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 5115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 5118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 5125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 5129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 5136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 5137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 5145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 5149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5155968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5156968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 516938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 517138214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ s2<- op 5176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5185968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5186968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 519938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 520138214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ s2<- op 5206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5215968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5216968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 522938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 523138214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ s2<- op 5236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5245968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5246968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 525938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 526138214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ s2<- op 5266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 5278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 5290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 5311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 5315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_2ADDR.S */ 5483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 5515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_2ADDR.S */ 5524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_2ADDR.S */ 5564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See OP_MUL_LONG for an explanation. 5852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * again we stuff it into rINST. 5855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long/2addr vA, vB */ 5857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 5865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 5994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 6005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG_2ADDR.S */ 6006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 6036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 6037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 6047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 6048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 6090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long/2addr vA, vB */ 6095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_2ADDR_finish 6111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long/2addr vA, vB */ 6121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_2ADDR_finish 6137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long/2addr vA, vB */ 6147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_2ADDR_finish 6163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6167968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6168968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 617938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 618138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 6187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6195968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6196968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 620738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 620938214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 6215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6223968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6224968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 623538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 623738214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 6243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6251968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6252968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 626338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 626538214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 6271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 6282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 6301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 6310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6320968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6321968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 633338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 633538214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ d2<- op 6341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6349968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6350968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 636238214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 636438214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ d2<- op 6370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6378968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6379968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 639138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 639338214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ d2<- op 6399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6407968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6408968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 642038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 642238214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ d2<- op 6428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 6469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT16.S */ 6480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT.S */ 6517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT16.S */ 6555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT16.S */ 6593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT16.S */ 6630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT16.S */ 6668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT16.S */ 6705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT16.S */ 6742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 7003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 7004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 7014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 7015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 7042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 7043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 7053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 7054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 7081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 7082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E3: /* 0xe3 */ 7209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E3.S */ 7210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E4: /* 0xe4 */ 7218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E4.S */ 7219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E5: /* 0xe5 */ 7227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E5.S */ 7228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E6: /* 0xe6 */ 7236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E6.S */ 7237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E7: /* 0xe7 */ 7245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E7.S */ 7246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E8: /* 0xe8 */ 7254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E8.S */ 7255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E9: /* 0xe9 */ 7263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E9.S */ 7264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_EA: /* 0xea */ 7272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_EA.S */ 7273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_EB: /* 0xeb */ 7281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_EB.S */ 7282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 728996516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 729096516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a throw-verification-error instruction. This throws an 7302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception for an error discovered during verification. The 7303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op AA, ref@BBBB */ 7306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 7308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ export the PC 7309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowVerificationError @ always throws 7311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ handle exception 7312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Execute a "native inline" instruction. 7320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7321b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7322b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7324b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7325b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7326b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ can throw 7332b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 7334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [sp] @ push &glue->retval 7335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ pop stack 7337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ test boolean result of inline 7338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7345b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7346b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7347b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7348b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7349b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7350b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7351b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7352b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7353b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7354b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7355b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7356b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7357b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7358b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7359b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7360b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7361b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7362b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7363b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7364b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7365b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7366b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7367b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7368b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7369b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7370b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7371b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) 7425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iput-quick, iput-object-quick */ 7460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A(+) 7481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 7482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 7483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ check object for null 7486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- field byte offset 7489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iput-quick, iput-object-quick */ 7501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FC: /* 0xfc */ 7630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FC.S */ 7631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FD: /* 0xfd */ 7639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FD.S */ 7640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FE: /* 0xfe */ 7648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FE.S */ 7649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionEnd 7667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionEnd: 7668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 7670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Sister implementations 7672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterStart 7675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmSisterStart, %function 7676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 7677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 4 7678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterStart: 7679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING */ 7681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (String ref) 7685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_resolve: 7688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBBBBBB (String ref) 7705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_CLASS */ 7721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the Class has not yet been resolved. 7724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (Class ref) 7725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_CLASS_resolve: 7728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- Class reference 7733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CHECK_CAST */ 7742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_fullcheck: 7750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ class of the object that failed to be cast. 7756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ about to throw 7757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .LstrClassCastExceptionPtr 7759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowExceptionWithClassMessage 7761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds BBBB 7767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolve: 7770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- BBBB 7773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastExceptionPtr: 7783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrClassCastException 7784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INSTANCE_OF */ 7787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_fullcheck: 7795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_INSTANCE_OF_store 7797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds boolean result 7800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_store: 7803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test succeeded, save and bail. 7810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_trivial: 7813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ indicate success 7814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r3 holds BBBB 7824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolve: 7827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r3 @ r1<- BBBB 7830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 7837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_INSTANCE */ 7843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 32 @ minimize cache lines 7845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 7852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Class initialization required. 7856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class object 7858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_needinit: 7860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0 @ save r0 7861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInitClass @ initialize class 7862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ check boolean result 7863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ restore r0 7864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ failed, deal with init exception 7866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds BBBB 7871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolve: 7873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 7880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationErrorPtr: 7882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInstantiationError 7883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_ARRAY */ 7886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolve class. (This is an uncommon case.) 7890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 7892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds class ref CCCC 7893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_resolve: 7895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ r9<- length (save) 7897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- CCCC 7898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 7901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ r1<- length (restore) 7903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_NEW_ARRAY_finish 7905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Finish allocation. 7908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class 7910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 7911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_finish: 7913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 7914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 7915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 7917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 7920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ vA<- r0 7922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 7926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 7929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 7930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 7931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_continue: 7933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 7938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 7939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #'I' @ array of ints? 7942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'L' @ array of objects? 7943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'[' @ array of arrays? 7944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 7945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 7946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 7948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 7954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 7956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 7958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 7963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 7964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 7965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 7966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 7967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 7968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 7969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 7970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 7971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 7972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 7973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 7974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 7975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 7976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 7977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 7978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 7979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 7980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 7983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 7988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 7989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 7991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 7992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 7993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 7994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) @ define in one or the other, not both 7997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 7998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 7999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 8005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 8009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 8010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 8012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 8015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 8017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #'I' @ array of ints? 8021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'L' @ array of objects? 8022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'[' @ array of arrays? 8023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 8024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 8025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 8027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 8033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 8035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 8037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 8047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 8048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 8049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 8050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 8051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 8052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 8062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 8064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 8067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 8068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 8071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 8073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 8074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) @ define in one or the other, not both 8076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 8077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 8078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_FLOAT */ 8084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_FLOAT_finish: 8085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_FLOAT */ 8090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_FLOAT_finish: 8091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_DOUBLE */ 8096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_DOUBLE_finish: 8097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_DOUBLE */ 8102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_DOUBLE_finish: 8103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMP_LONG */ 8108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_less: 8110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, #0 @ r1<- -1 8111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ instead, we just replicate the tail end. 8113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_greater: 8119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ r1<- 1 8120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to _finish 8121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_finish: 8123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_AGET_WIDE */ 8130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_AGET_WIDE_finish: 8132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_WIDE */ 8141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_WIDE_finish: 8143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_OBJECT */ 8151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = vBB (arrayObj) 8154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = vAA (obj) 8155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = offset into array (vBB + vCC * width) 8156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_finish: 8158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ storing null reference? 8159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ okay? 8164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errArrayStore @ no 8165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_skip_check: 8166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET */ 8173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_finish: 8180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_WIDE */ 8194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_WIDE_finish: 8201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_OBJECT */ 8215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_OBJECT_finish: 8222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BOOLEAN */ 8236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BOOLEAN_finish: 8243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BYTE */ 8257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BYTE_finish: 8264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_CHAR */ 8278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_CHAR_finish: 8285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_SHORT */ 8299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_SHORT_finish: 8306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT */ 8320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_finish: 8327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_WIDE */ 8341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_WIDE_finish: 8348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 8358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_OBJECT */ 8362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_OBJECT_finish: 8369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BOOLEAN_finish: 8390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BYTE */ 8404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BYTE_finish: 8411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_CHAR */ 8425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_CHAR_finish: 8432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_SHORT */ 8446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_SHORT_finish: 8453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET */ 8467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_resolve: 8473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_finish @ yes, finish 8479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_WIDE */ 8483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_resolve: 8489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_OBJECT */ 8499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_resolve: 8505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BOOLEAN */ 8515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_resolve: 8521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BYTE */ 8531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_resolve: 8537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_CHAR */ 8547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_resolve: 8553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_SHORT */ 8563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_resolve: 8569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT */ 8579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_resolve: 8585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_finish @ yes, finish 8591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_WIDE */ 8595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: &fp[AA] 8600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_resolve: 8602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_OBJECT */ 8612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_OBJECT_resolve: 8618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_OBJECT_finish @ yes, finish 8624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_resolve: 8634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BYTE */ 8644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_resolve: 8650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_CHAR */ 8660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_resolve: 8666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_SHORT */ 8676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_resolve: 8682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_continue: 8699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER */ 8710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_continue: 8717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_resolve: 8728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_nsm: 8740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT */ 8745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_resolve: 8752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the float in r0 to a long in r0/r1. 8836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenf2l_doconv: 8842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, lr} 8843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0x5f000000 @ (float)maxlong 8844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r4, r0 8845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0xdf000000 @ (float)minlong 8853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (80000000) 8856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r4 8861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpeq @ is arg == self? 8862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmeqfd sp!, {r4, pc} 8865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_f2lz @ convert float to long 8868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, pc} 8869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddend2l_doconv: 8880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, r5, lr} @ save regs 88815162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 88825162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 88835162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align for EABI 88855162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r5, r1 @ and r1 8887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 8888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 8890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 8892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 88955162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 88965162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 88975162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 8898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmple @ is arg <= minlong? 8899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (8000000000000000) 8901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 8903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 8906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r4 @ compare against self 8907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r5 8908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpeq @ is arg == self? 8909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f 8912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 8915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_d2lz @ convert double to long 8916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 8918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 8919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, r5, pc} 8920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_MUL_LONG */ 8923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_MUL_LONG_finish: 8925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 8927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG */ 8931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_finish: 8933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 8934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG */ 8940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_finish: 8942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 8943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG */ 8949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_finish: 8951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 8952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 8958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_2ADDR_finish: 8960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 8966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_2ADDR_finish: 8968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 8974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_2ADDR_finish: 8976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_EXECUTE_INLINE */ 8982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Extract args, call function. 8985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = #of args (0-4) 8986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = call index 8987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 8988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Other ideas: 8990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Use a jump table from the main piece to jump directly into the 8991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 8992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Have five separate pieces that do the loading, so we can work the 8993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interleave a little better. Increases code size. 8994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_continue: 8996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 8997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r9, 2) @ r9<- FEDC 8998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 8999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r9, #0xf000 @ isolate F 9001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 9002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r9, #0x0f00 @ isolate E 9003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 9004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r9, #0x00f0 @ isolate D 9005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 9006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r9, #0x000f @ isolate C 9007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 9008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: 9009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 9010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (not reached) 9012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_table: 9014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word gDvmInlineOpsTable 9015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9017b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 9018b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9019b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 9020b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 9021b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 9022b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 9023b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9024b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 9025b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 9026b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9027b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 9028b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9029b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9030b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 9031b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 9032b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 9033b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 9034b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 9035b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 9036b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 9037b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 9038b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 9039b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 9040b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9041b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 9042b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9043b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 9044b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 9045b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9046b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 9048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterEnd 9049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterEnd: 9050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/footer.S */ 9052ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common subroutines and data 9056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9059ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9060ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 9062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 9063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9064ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 906597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 906697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 906797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 906897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 906997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 907097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 907197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 907297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 907397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 907497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 907597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 907697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToTraceSelect 907797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToTraceSelect: 90789a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 907997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 908097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 908197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 908297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToBackwardBranch 908397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToBackwardBranch: 90849a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 908597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 908697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 908797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 908897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 908997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 90909a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 909197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 909297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 909397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 909497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 909597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 909697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 909797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 909897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 909997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9100ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9101ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter when the compiler is 9102ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * having issues translating/executing a Dalvik instruction. We have to skip 9103ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the code cache lookup otherwise it is possible to indefinitely bouce 9104ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * between the interpreter and the code cache if the instruction that fails 9105ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * to be compiled happens to be at a trace start. 9106ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9107ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpPunt 9108ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpPunt: 91097a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9110ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r0 9111ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9112ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,lr 9113ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpPunt; 9114ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9115ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 91167a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r0, #0 91177a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9118ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9119ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9120ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9121ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9122ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9123ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9124ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return to the interpreter to handle a single instruction. 9125ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * On entry: 9126ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r0 <= PC 9127ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r1 <= PC of resume instruction 9128ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * lr <= resume point in translation 9129ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9130ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpSingleStep 9131ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpSingleStep: 9132ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str lr,[rGLUE,#offGlue_jitResume] 9133ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1,[rGLUE,#offGlue_jitResumePC] 9134ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#kInterpEntryInstr 9135ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ enum is 4 byte in aapcs-EABI 9136ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_entryPoint] 9137ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC,r0 9138ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 91397a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng 9140ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9141ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitSingleStep @ Ask for single step and then revert 9142ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9143ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp to bail to debug interp 9144ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9145ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9146ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9147ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9148ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache and immediately request 9149ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a translation for the exit target. Commonly used following 9150ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * invokes. 9151ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9152ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToTraceSelect 9153ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToTraceSelect: 91549a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 91557a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 91569a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9157ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 91587a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 91597a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9160ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9161ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng beq 2f 9162ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9163ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 91649a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 91659a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 916646cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 916746cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 916846cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9169ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9170ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* No translation, so request one if profiling isn't disabled*/ 9171ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng2: 91721da12167d913efde56ec3b40491524b051679f2cAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9173ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9174ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9175ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0, #0 9176ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_selectTrace 9177ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9181ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter. 9182ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * The return was done with a BLX from thumb mode, and 9183ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the following 32-bit word contains the target rPC value. 9184ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Note that lr (r14) will have its low-order bit set to denote 9185ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * its thumb-mode origin. 9186ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 9187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * We'll need to stash our lr origin away, recover the new 9188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * target and then check to see if there is a translation available 9189ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * for our new target. If so, we do a translation chain and 9190ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * go back to native execution. Otherwise, it's back to the 9191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * interpreter (after treating this entry as a potential 9192ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace start). 9193ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9194ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNormal 9195ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNormal: 91969a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 91977a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 91989a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9199ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9200ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNormal 9201ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9202ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9203ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 92047a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9205ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 920646cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee beq toInterpreter @ go if not, otherwise do chain 9207ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9208ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 92099a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 92109a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 921146cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 921246cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 921346cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9214ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9215ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9216ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter to do method invocation. 9217ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Check if translation exists for the callee, but don't chain to it. 9218ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9219ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNoChain 9220ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNoChain: 9221ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9222ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNoChain 9223ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 92247a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9225ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9226ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 92277a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 92289a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 92299a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9230ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9231ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ continue native execution if so 923297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9233ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9234ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9235ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * No translation, restore interpreter regs and start interpreting. 9236ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * rGLUE & rFP were preserved in the translated code, and rPC has 9237ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * already been restored by the time we get here. We'll need to set 9238ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * up rIBASE & rINST, and load the address of the JitTable into r0. 9239ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 924046cd5b63c29d3284a9ff3e0d0711fb136f409313Bill BuzbeetoInterpreter: 9241ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9242ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9243ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9244ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9245ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ NOTE: intended fallthrough 9246ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9247ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Common code to update potential trace start counter, and initiate 9248ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a trace-build if appropriate. On entry, rPC should point to the 9249ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * next instruction to execute, and rINST should be already loaded with 9250ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the next opcode word, and r0 holds a pointer to the jit profile 9251ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * table (pJitProfTable). 9252ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9253ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_testUpdateProfile: 9254ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9255ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9256ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9257ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9258ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_updateProfile: 9259ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 92607b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 92617b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 9262ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9263ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng subs r1,r1,#1 @ decrement counter 92647b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 9265ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9266ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9267ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9268ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Here, we switch to the debug interpreter to request 9269ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace selection. First, though, check to see if there 9270ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * is already a native translation in place (and, if so, 9271ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * jump to it now). 9272ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9273d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 92747a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 92757b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 9276ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9277ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9278ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 92797a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 92807a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, rPC @ arg1 of translation may need this 92817a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 9282ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 928397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9284ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ jump to the translation 928597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 92869a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 92879a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 92889a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 92899a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 92909a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 92919a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 92929a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r10, r0 @ save target 92939a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 92949a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee cmp r0, r10 @ special case? 92959a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bne dvmJitSelfVerificationStart @ set up self verification 92969a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 92979a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 92989a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 929997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 93009a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 9301ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_selectTrace: 9302ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitTSelectRequest @ ask for trace selection 9303ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 93049c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 93059c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9306ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp 9307ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9308ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 930997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 931097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 931197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 931297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 93139a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * On entry, r10 contains the address of the target translation. 931497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 931597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationStart: 931697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 931797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 931897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 93199a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 932097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9321ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9322ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9323ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 932497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 932597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 932697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 932797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 932897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 932997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationEnd: 93306999d84e2c55dc4a46a6c311b55bd5811336d9c4Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93316999d84e2c55dc4a46a6c311b55bd5811336d9c4Ben Cheng mov r1, #0 93326999d84e2c55dc4a46a6c311b55bd5811336d9c4Ben Cheng str r1, [r10, #offThread_inJitCodeCache] @ Back to the interp land 933397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 933497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9335ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9336ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9337ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9338ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 933997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 934097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 934197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 934297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 934330f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 934430f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 934597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 934697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 934797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 934897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 934997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 935097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 935197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 935297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 935397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 935497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 935597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9356ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9357ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code when a backward branch is taken. 9360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is PC adjustment *in bytes* 9363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_backwardBranch: 9365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryInstr 9366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9367ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9368ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9369ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9370ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9371ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9372ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9373ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9374ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9378ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * activity has begun. 9384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: if JDWP isn't running, zero out pDebuggerActive pointer so we don't 9386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have to do the second ldr. 9387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: reduce this so we're just checking a single location. 9389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is reentry type, e.g. kInterpEntryInstr 9392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is trampoline PC adjustment *in bytes* 9393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_periodicChecks: 9395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 93979c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng @ speculatively store r0 before it is clobbered by dvmCheckSuspendPending 93989c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r0, [rGLUE, #offGlue_entryPoint] 93999c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng 9400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) 9401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_PROFILER) 9404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3] @ r3<- suspendCount (int) 9408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) 9410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r1] @ r1<- debuggerActive (boolean) 9411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined (WITH_PROFILER) 9413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ suspend pending? 9417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 2f @ yes, do full suspension check 9418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# if defined(WITH_DEBUGGER) && defined(WITH_PROFILER) 9421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r1, r1, r2 @ r1<- r1 | r2 9422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ debugger attached or profiler started? 9423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# elif defined(WITH_DEBUGGER) 9424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ debugger attached? 9425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# elif defined(WITH_PROFILER) 9426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ profiler started? 9427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# endif 9428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 3f @ debugger/profiler, switch interp 9429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr @ nothing to do, return 9432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: @ check suspend 9434964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9435964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee /* 9436964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * Refresh the Jit's cached copy of profile table pointer. This pointer 9437964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * doubles as the Jit's on/off switch. 9438964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee */ 9439964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ r10<-&gDvmJit.pJitProfTable 9440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9441964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r10 <- pJitProfTable 9442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC 9443964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh Jit's on/off switch 9444964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#else 9445964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9446964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee EXPORT_PC() @ need for precise GC 9447964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmCheckSuspendPending @ suspend if necessary, then return 9449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: @ debugger/profiler enabled, bail out 9451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, rPC, r9 @ update rPC 9452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ "want switch" = true 9453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail 9454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * State registers will be saved to the "glue" area before bailing. 9460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * other interpreter or just bail all the way out 9464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_gotoBail: 9466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ r0<- glue ptr 9468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r1, r1, #1 @ using (boolean+1) 9471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl _longjmp @ does not return 9473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_abort 9474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation with range. 9478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodRange: 9483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewRange: 9484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- CCCC 9489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r2, r2, #1 @ count-- 9497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r10], #4 @ *outs++ = val 9498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1b @ ...while count != 0 9499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LinvokeArgsDone 9501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation without range. 9504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodNoRange: 9509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewNoRange: 9510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone 9517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNonRange: 9520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vA 9527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r1, #0xf000 @ isolate G 9528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vG 9531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r1, #0x0f00 @ isolate F 9532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vF 9535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r1, #0x00f0 @ isolate E 9536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vE 9539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r1, #0x000f @ isolate D 9540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 9541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vD 9543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: @ fall through to .LinvokeArgsDone 9544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 9546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 9547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 9548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ find space for the new stack frame, check for overflow 9549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 9550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 9551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 9552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@ bl common_dumpRegs 9553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 9554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 9555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, r9 @ bottom < interpStackEnd? 9556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 9557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LstackOverflow @ yes, this frame will overflow stack 9558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ set up newSaveArea 9560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef EASY_GDB 9561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 9562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [r10, #offStackSaveArea_prevSave] 9563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 9565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 9566ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9567ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r9, #0 9568ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r9, [r10, #offStackSaveArea_returnAddr] 9569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r10, #offStackSaveArea_method] 9571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden tst r3, #ACC_NATIVE 9572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LinvokeNative 9573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 9576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 9577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP 9578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 9580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 9581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 9582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 9583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 9584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 9585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 9586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 9587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 9590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 9591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r2 @ publish new rPC 9592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 9593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Update "glue" values for the new method 9595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 9596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 9597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 9598ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9599ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r1 @ fp = newFp 9601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rINST, r9 @ publish new rINST 9603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9604ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9605ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9607ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9608ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rFP, r1 @ fp = newFp 9609ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9610ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rINST, r9 @ publish new rINST 9611ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9612ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 9613ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNative: 9616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Prep for the native call 9617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 9618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9619d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 9620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 9621d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 9622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r3 @ r9<- glue->self (preserve) 9623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ r2<- methodToCall 9625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ r0<- newFp (points to args) 9626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 9627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 9629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 9630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .Lskip 9631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_mterp, %function 9632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_mterp: 9633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 9634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 9635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 9636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lskip: 9637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @mov lr, pc @ set return addr 9640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 9641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 9642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9643964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9644964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ Refresh Jit's on/off status 9645964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9646964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee 9647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ native return; r9=self, r10=newSaveArea 9648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ equivalent to dvmPopJniLocals 9649d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 9650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 9651964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9652964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 9653964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 9655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null? 9656d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 9657964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9658964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh cached on/off switch 9659964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ no, handle exception 9661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 9663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 96666ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 96676ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 9668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 9669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmHandleStackOverflow 9670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 9672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 9673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation, calling through "glue code". 9678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: now that we have range and non-range invoke handlers, this 9680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * needs to be split into two. Maybe just create entry points 9681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that set r9 and jump here? 9682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 9686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeOld: 9689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #8 @ space for args + pad 9690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 9691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ A2<- methodToCall 9692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ A0<- glue 9693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ A1<- methodCallRange 9695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ A3<- AA 9696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #0] @ A4<- ip 9697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 9698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ remove arg area 9699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall @ continue to next instruction 9700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for handling a return instruction. 9706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 9708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_returnFromMethod: 9710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnNew: 9711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryReturn 9712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 9713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 9716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 9717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 9718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 9719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r2<- method we're returning to 9720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is this a break frame? 9722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 9723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 9724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_gotoBail @ break frame, bail out completely 9725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 9727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 9728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 9729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 9730ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 97317a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 9732ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9733ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r9 @ publish new rPC 9734ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_methodClassDex] 97357a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r10, [r3, #offThread_inJitCodeCache] @ may return to JIT'ed land 97367a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng cmp r10, #0 @ caller is compiled code 97377a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng blxne r10 9738ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 9739ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9740ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9741ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 9742ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r9 @ publish new rPC 9745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 9746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9747ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return handling, calls through "glue code". 9751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnOld: 9754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 9756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_returnFromMethod 9757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 9758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Somebody has thrown an exception. Handle it. 9763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If the exception processing code returns to us (instead of falling 9765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out of the interpreter), continue with whatever the next instruction 9766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * now happens to be. 9767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 9769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9770ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmMterpCommonExceptionThrown 9771ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmMterpCommonExceptionThrown: 9772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_exceptionThrown: 9773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionNew: 9774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryThrow 9775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 9776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9778ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9779ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitTSelectAbort @ abandon trace selection in progress 9780ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9781ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9782ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 9784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 9785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 9788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- NULL 9789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 9790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up args and a local for "&fp" */ 9792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 9793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [sp, #-4]! @ *--sp = fp 9794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov ip, sp @ ip<- &fp 9795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- false 9796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #-4]! @ *--sp = &fp 9797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 9798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 9799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 9800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r9 @ r2<- exception 9801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 9802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 9803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 9805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 9806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 9808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 9810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ no, skip ahead 9811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r0 @ save relPc result in rFP 9812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 98134fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden mov r1, r9 @ r1<- exception 9814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCleanupStackOverflow @ call(self) 9815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP @ restore result 9816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 9817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 9819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 9820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is catchRelPc < 0? 9821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ restore stack 9822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi .LnotCaughtLocally 9823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* adjust locals to match self->curFrame and updated PC */ 9825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 9826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 9827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 9828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 9829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 9830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 9831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 9832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 9833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* release the tracked alloc on the exception */ 9835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* restore the exception if the handler wants it */ 9840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 9841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 9843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 9844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 9847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix stack overflow if necessary */ 9848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 9850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, r10 @ if yes: r0<- self 98514fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden movne r1, r9 @ if yes: r1<- exception 9852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 9853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ may want to show "not caught locally" debug messages here 9855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if DVM_SHOW_EXCEPTION >= 2 9856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call __android_log_print(prio, tag, format, ...) */ 9857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* "Exception %s from %s:%d not caught locally" */ 9858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 9859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 9860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_insns] 9861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 9862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden asr r1, r1, #1 9863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLineNumFromPC 9864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 9865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmGetMethodSourceFile(method) 9866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 9867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmGetMethodSourceFile 9868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 9869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ exception->clazz->descriptor 9870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] 9871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_descriptor] 9872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ 9873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, strExceptionNotCaughtLocally 9874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strLogTag 9875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #3 @ LOG_DEBUG 9876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __android_log_print 9877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offThread_exception] @ restore exception 9879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 9883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail @ bail out 9884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exception handling, calls through "glue code". 9888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionOld: 9891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 9893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_exceptionThrown 9894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 9895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * After returning from a "glued" function, pull out the updated 9900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * values and start executing at the next instruction. 9901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_resumeAfterGlueCall: 9903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 9904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 9905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array index. 9910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayIndex: 9912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayIndexException 9914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array value. 9920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayStore: 9922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayStoreException 9924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Integer divide or mod by zero. 9930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errDivideByZero: 9932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArithmeticException 9934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strDivideByZero 9935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Attempt to allocate an array with a negative size. 9940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNegativeArraySize: 9942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNegativeArraySizeException 9944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invocation of a non-existent method. 9950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNoSuchMethod: 9952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNoSuchMethodError 9954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We encountered a null object when we weren't expecting one. We 9960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * export the PC, throw a NullPointerException, and goto the exception 9961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * processing code. 9962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNullObject: 9964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNullPointerException 9966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For debugging, cause an immediate fault. The source address will 9972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be in lr (use a bl instruction to jump here). 9973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_abort: 9975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, .LdeadFood 9976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LdeadFood: 9977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word 0xdeadf00d 9978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out a "we were here", preserving all registers. (The attempt 9981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to save ip won't work, but we need to save an even number of 9982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * registers for EABI 64-bit stack alignment.) 9983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .macro SQUEAK num 9985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_squeak\num: 9986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 9988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #\num 9989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 9990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 9992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endm 9993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 0 9995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 1 9996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 2 9997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 3 9998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 4 9999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 5 10000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out the number in r0, preserving registers. 10003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNum: 10005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 10008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print a newline, preserving registers. 10014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNewline: 10016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNewline 10018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 10024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printHex: 10026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintHex 10029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 10035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printLong: 10037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r1 10039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 10040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintLong 10041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 10047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printMethod: 10049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpPrintMethod 10051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Call a C helper function that dumps regs and possibly some 10056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * additional info. Requires the C function to be compiled in. 10057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_dumpRegs: 10060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpDumpArmRegs 10062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10066d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#if 0 10067d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden/* 10068d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Experiment on VFP mode. 10069d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10070d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 10071d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10072d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 10073d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden */ 10074d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddensetFPSCR: 10075d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r0, r0, r1 @ make sure no stray bits are set 10076d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmrx r2, fpscr @ get VFP reg 10077d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mvn r1, r1 @ bit-invert mask 10078d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r2, r2, r1 @ clear masked bits 10079d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden orr r2, r2, r0 @ set specified bits 10080d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmxr fpscr, r2 @ set VFP reg 10081d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, r2 @ return new value 10082d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bx lr 10083d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10084d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .align 2 10085d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .global dvmConfigureFP 10086d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .type dvmConfigureFP, %function 10087d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddendvmConfigureFP: 10088d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden stmfd sp!, {ip, lr} 10089d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x03000000 sets DN/FZ */ 10090d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x00009f00 clears the six exception enable flags */ 10091d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl common_squeak0 10092d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10093d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10094d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl setFPSCR 10095d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden ldmfd sp!, {ip, pc} 10096d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#endif 10097d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references, must be close to the code that uses them. 10101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 10103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArithmeticException: 10104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArithmeticException 10105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayIndexException: 10106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayIndexException 10107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayStoreException: 10108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayStoreException 10109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrDivideByZero: 10110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrDivideByZero 10111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNegativeArraySizeException: 10112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNegativeArraySizeException 10113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNoSuchMethodError: 10114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNoSuchMethodError 10115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNullPointerException: 10116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNullPointerException 10117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrLogTag: 10119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrLogTag 10120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrExceptionNotCaughtLocally: 10121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrExceptionNotCaughtLocally 10122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNewline: 10124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNewline 10125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrSqueak: 10126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrSqueak 10127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintHex: 10128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintHex 10129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintLong: 10130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintLong 10131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Zero-terminated ASCII string data. 10134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with the address, or use an ADR pseudo-op to get the address 10137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * PC-relative addressing mode and hence has a limited range, which 10139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * makes it not work well with mergeable string sections. 10140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrBadEntryPoint: 10144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Bad entry point %d\n" 10145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArithmeticException: 10146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArithmeticException;" 10147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayIndexException: 10148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayStoreException: 10150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastException: 10152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ClassCastException;" 10153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrDivideByZero: 10154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "divide by zero" 10155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrFilledNewArrayNotImpl: 10156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInternalError: 10158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InternalError;" 10159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationError: 10160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InstantiationError;" 10161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNegativeArraySizeException: 10162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNoSuchMethodError: 10164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNullPointerException: 10166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NullPointerException;" 10167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrLogTag: 10169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "mterp" 10170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrExceptionNotCaughtLocally: 10171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNewline: 10174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "\n" 10175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrSqueak: 10176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%d>" 10177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintHex: 10178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<0x%x>" 10179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintLong: 10180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%lld>" 10181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10183