InterpAsm-armv5te-vfp.S revision 7a2697d327936e20ef5484f7819e2e4bf91c891f
1a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 2a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * --> DO NOT EDIT <-- 5a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/header.S */ 8a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 10a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 11a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 13a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 14a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 15a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 17a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 18a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 21a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 22a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 23c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 24a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 25a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ARMv5 definitions and declarations. 26a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 27a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 28a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 29a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenARM EABI general notes: 30a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 31a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 32a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr4-r8 are available for general use 33a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr9 is given special treatment in some situations, but not for us 34a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr10 (sl) seems to be generally available 35a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr12 (ip) is scratch -- not preserved across method calls 37a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr13 (sp) should be managed carefully in case a signal arrives 38a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr14 (lr) must be preserved 39a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr15 (pc) can be tinkered with directly 40a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 41a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0 holds returns of <= 4 bytes 42a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 43a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 44a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 45a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 47a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 48a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 49a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 50a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden(i.e. the 5th arg). 51a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 52a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenVFP: single-precision results in s0, double-precision results in d0. 53a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 54a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 55a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 56a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 57a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 58a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 59a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMterp and ARM notes: 60a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 61a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenThe following registers have fixed assignments: 62a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 63a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden reg nick purpose 64a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r4 rPC interpreted program counter, used for fetching instructions 65a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 66a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r6 rGLUE MterpGlue pointer 671da12167d913efde56ec3b40491524b051679f2cAndy McFadden r7 rINST first 16-bit code unit of current instruction 681da12167d913efde56ec3b40491524b051679f2cAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 69a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 70a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMacros are provided for common operations. Each macro MUST emit only 71a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 72a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenunspecified registers or condition codes. 73a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 74a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 75a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* single-purpose registers, given names for clarity */ 76a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rPC r4 77a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rFP r5 78a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rGLUE r6 791da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rINST r7 801da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rIBASE r8 81a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 82a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* save/restore the PC and/or FP from the glue struct */ 83a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 84a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 85a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 86a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 87a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 88a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 89a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 90a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 91a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 92a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be done *before* something calls dvmThrowException. 93a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 94a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 97a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * It's okay to do this more than once. 98a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 99a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define EXPORT_PC() \ 100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Given a frame pointer, find the stack save area. 104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_INST() ldrh rINST, [rPC] 114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from the specified offset. Advances rPC 117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Because of the limited size of immediate constants on ARM, this is only 120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with this). 122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This must come AFTER anything that can throw an exception, or the 124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception catch may miss. (This also implies that it must come after 125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * EXPORT_PC().) 126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * here. 145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch a half-word code unit from an offset past the current PC. The 150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The "_S" variant works the same but treats the value as signed. 153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * byte of the halfword you want (lo/hi). 161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the instruction's opcode field into the specified register. 166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the prefetched instruction's opcode field into the specified register. 171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Get/set the 32-bit value from a Dalvik register. 184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 189ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 190d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 192ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert a virtual register index into an address. 195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add _reg, rFP, _vreg, lsl #2 198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is a #include, not a %include, because we want the C pre-processor 201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to expand the macros into assembler assignment statements. 202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#include "../common/asm-constants.h" 204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2057b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#if defined(WITH_JIT) 2067b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#include "../common/jit-config.h" 2077b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#endif 208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/platform.S */ 210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * CPU-version-specific defines 213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * one-way branch. 219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP. Does not modify LR. 221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC source 223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Jump to subroutine. 229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC_LR source 233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov lr, pc 234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDMFD_PC regs 243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {\regs,pc} 244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 246c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* 247c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Macro for data memory barrier; not meaningful pre-ARMv6K. 248c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 2490890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden.macro SMP_DMB 250c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.endm 251c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/entry.S */ 253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Interpreter entry point. 270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't have formal stack frames, so gdb scans upward in the code 274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to find the start of the function (a label with the %function type), 275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and then looks at the next few instructions to figure out what 276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * got pushed onto the stack. From this it figures out how to restore 277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the registers, including PC, for the previous stack frame. If gdb 278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sees a non-function label, it stops scanning, so either we need to 279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have nothing but assembler-local labels between the entry point and 280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the break, or we need to fake it out. 281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * When this is defined, we add some stuff to make gdb less confused. 283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define ASSIST_DEBUGGER 1 285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdRun 289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdRun, %function 290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This function returns a boolean "changeInterp" value. The return comes 296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * via a call to dvmMterpStdBail(). 297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdRun: 299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY1 \ 300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .save {r4-r10,fp,lr}; \ 301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY2 \ 303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .pad #4; \ 304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align 64 305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* save stack pointer, add magic word for debuggerd */ 311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up "named" registers, figure out entry point */ 314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rGLUE, r0 @ set rGLUE 31551ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee ldr r1, [r0, #offGlue_entryPoint] @ enum is 4 bytes in aapcs-EABI 316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryInstr @ usual case? 319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .Lnot_instr @ no, handle it 320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 321ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 322d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng.LentryInstr: 3237a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 324ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng /* Entry is always a possible trace start */ 325ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 326ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 3277a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r1, #0 @ prepare the value for the new state 3287a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r1, [r10, #offThread_inJitCodeCache] @ back to the interp land 3297a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 @ is profiling disabled? 3307a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#if !defined(WITH_SELF_VERIFICATION) 3317a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bne common_updateProfile @ profiling is enabled 3327a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#else 3337a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r2, [r10, #offThread_shadowSpace] @ to find out the jit exit state 3347a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq 1f @ profiling is disabled 3357a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 3367a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r3, #kSVSTraceSelect @ hot trace following? 3377a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng moveq r2,#kJitTSelectRequestHot @ ask for trace selection 3387a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq common_selectTrace @ go build the trace 3397a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r3, #kSVSNoProfile @ don't profile the next instruction? 3407a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq 1f @ intrepret the next instruction 3417a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b common_updateProfile @ collect profiles 3427a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#endif 3437a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng1: 344ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 345ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 346ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* start executing the instruction at rPC */ 348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 351ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_instr: 354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_returnFromMethod 356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_return: 358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown 360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 361ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 362ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lnot_throw: 363d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10,[rGLUE, #offGlue_jitResumeNPC] 364d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r2,[rGLUE, #offGlue_jitResumeDPC] 365ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 366ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lbad_arg 367ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp rPC,r2 368d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne .LentryInstr @ must have branched, don't resume 369d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#if defined(WITH_SELF_VERIFICATION) 370d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ glue->entryPoint will be set in dvmSelfVerificationSaveState 371d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunStart @ re-enter the translation after the 372d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ single-stepped instruction 373d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @noreturn 374d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#endif 375ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1, #kInterpEntryInstr 37651ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee str r1, [rGLUE, #offGlue_entryPoint] 377d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bx r10 @ re-enter the translation 378ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 379ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lbad_arg: 381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strBadEntryPoint 382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r1 holds value of entryPoint 383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAbort 385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdBail 389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdBail, %function 390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Restore the stack pointer and PC from the save point established on entry. 393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * LR to PC. 399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 bool changeInterp 403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdBail: 405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ return the changeInterp value 407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 @ un-align 64 408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references. 413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrBadEntryPoint: 415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrBadEntryPoint 416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionStart 419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmInstructionStart, %function 420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionStart = .L_OP_NOP 421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOP: /* 0x00 */ 426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOP.S */ 427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_inst, %function 434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_inst: 435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE: /* 0x01 */ 444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_16: /* 0x03 */ 473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE.S */ 488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide vA, vB */ 489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/from16 vAA, vBBBB */ 506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- BBBB 508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/16 vAAAA, vBBBB */ 522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- BBBB 524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- AAAA 525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 528445194bc141dc67e2f678aa1bbd5e59ca66254e5Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-result-wide vAA */ 600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-exception vAA */ 629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ r1<- 0 633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN: /* 0x0f */ 648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 64-bit value. Copies the return value into the "glue" 667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* return-wide vAA */ 670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_4: /* 0x12 */ 698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_4.S */ 699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/4 vA, #+B */ 700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_16: /* 0x13 */ 712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_16.S */ 713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/16 vAA, #+BBBB */ 714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST: /* 0x14 */ 724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST.S */ 725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const vAA, #+BBBBbbbb */ 726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/high16 vAA, #+BBBB0000 */ 740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/16 vAA, #+BBBB */ 753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #0 @ r0<- 00000000 804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING: /* 0x1a */ 814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING.S */ 815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBB */ 816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_resolve 823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBBBBBB */ 833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/class vAA, Class@BBBB */ 852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_CLASS_resolve 859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Synchronize on an object. 870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-enter vAA */ 872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null object, throw an exception 878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLockObject @ call(self, obj) 880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ exception raised, bail out 885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlock an object. 895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exceptions that occur when unlocking a monitor need to appear as 897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if they happened at the following instruction. See the Dalvik 898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction spec. 899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-exit vAA */ 901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ before fetch: export the PC 903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 9056bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq 1f @ yes 906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 9106bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq common_exceptionThrown @ yes, exception is pending 911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9136bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee1: 9146bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee FETCH_ADVANCE_INST(1) @ advance before throw 9156bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee b common_errNullObject 916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if a cast from one class to another is allowed. 923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* check-cast vAA, class@BBBB */ 925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r3) @ r9<- object 928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ is object null? 930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolved: 937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_okay: 940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if an object reference is an instance of a class. 950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Most common situation is a non-null object, being compared against 952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an already-resolved class. 953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* instance-of vA, vB, class@CCCC */ 955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- CCCC 963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ARRAY_LENGTH.S */ 977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return the length of an array. 979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yup, fail 986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ vB<- length 990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new instance of a class. 998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-instance vAA, class@BBBB */ 1000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocObject @ r0<- new object 1014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Allocate an array of objects, specified with the array class 1022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and a count. 1023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The verifier guarantees that this is an array class, so we don't 1025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * check for it here. 1026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-array vA, vB, class@CCCC */ 1028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 1029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- CCCC 1030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ check length 1034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_errNegativeArraySize @ negative length, bail 1036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for resolve, alloc 1038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC(); 1109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ 0 means an exception is thrown 1111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ has exception 1112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW: /* 0x27 */ 1119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW.S */ 1120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception object in the current thread. 1122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* throw vAA */ 1124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 11278ba2708ea118381f2df5ca55b9bad2ae4c050504Andy McFadden EXPORT_PC() @ exception handler can throw 1128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 1129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, throw an NPE instead 1130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ bypass dvmSetException, just store it 1131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 1133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO: /* 0x28 */ 1137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO.S */ 1138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 8-bit offset. 1140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto +AA */ 1145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1149ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1150ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1152ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1153ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1156ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1157ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1158ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1159ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1160ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_16: /* 0x29 */ 1165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_16.S */ 1166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 16-bit offset. 1168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/16 +AAAA */ 1173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1176ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1177ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1181ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1182ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1183ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_32: /* 0x2a */ 1192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_32.S */ 1193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 32-bit offset. 1195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction doesn't affect the V flag, so we need to clear it 1202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * explicitly. 1203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/32 +AAAAAAAA */ 1205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, ip @ (clear V flag during stall) 1208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1211ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1212ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1214ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1215ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1218ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1219ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1220ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1221ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1222ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1248ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1249ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1250ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1251ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1252ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1253ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1254ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1255ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1259ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1286ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1287ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1289ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1290ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1293ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1294ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1295ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1296ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1297ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1303968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13228fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13258fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13278fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13368fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1342968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13618fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13648fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13668fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13758fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1381968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14008fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14038fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14058fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14148fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1420968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14398fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14428fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14448fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14538fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * register based on the results of the comparison. 1463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We load the full values with LDM, but in practice many values could 1465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be resolved by only looking at the high word. This could be made 1466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If we just wanted to set condition flags, we could do this: 1469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subs ip, r0, r2 1470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sbcs ip, r1, r3 1471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subeqs ip, r0, r2 1472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * us a constant 5-cycle path plus a branch at the end to the 1476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction epilogue code. The multi-compare approach below needs 1477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in the worst case (the 64-bit values are equal). 1479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* cmp-long vAA, vBB, vCC */ 1481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 1482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 1485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt .LOP_CMP_LONG_greater 1492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CMP_LONG_less 1495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQ: /* 0x32 */ 1500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQ.S */ 1501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1521ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1522ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1523ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1524ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1525ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1526ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1527ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1530ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NE: /* 0x33 */ 1536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NE.S */ 1537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1557ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1558ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1559ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1560ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1561ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1562ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1566ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LT: /* 0x34 */ 1572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LT.S */ 1573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1593ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1594ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1595ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1596ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1597ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1598ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1599ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1602ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GE: /* 0x35 */ 1608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GE.S */ 1609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1629ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1630ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1631ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1632ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1633ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1634ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1635ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1638ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GT: /* 0x36 */ 1644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GT.S */ 1645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1665ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1666ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1667ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1668ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1669ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1670ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1671ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1674ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LE: /* 0x37 */ 1680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LE.S */ 1681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1701ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1702ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1703ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1704ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1705ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1706ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1707ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1710ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1734ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1735ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1736ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1737ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1738ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1739ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1742ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1743ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1744ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1745ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1746ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1770ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1771ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1772ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1773ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1774ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1775ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1778ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1779ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1780ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1781ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1782ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1806ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1807ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1808ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1809ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1810ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1811ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1814ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1815ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1816ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1817ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1818ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1842ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1843ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1844ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1845ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1846ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1847ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1848ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1849ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1850ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1851ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1854ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1878ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1879ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1880ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1881ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1882ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1883ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1884ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1885ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1886ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1887ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1890ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1914ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1915ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1916ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1917ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1918ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1919ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1922ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1923ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1924ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1925ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1926ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET: /* 0x44 */ 1980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 1981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 1983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 1986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 1991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 1993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 1994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 1995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 1996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 1997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aget-wide vAA, vBB, vCC */ 2017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT: /* 0x4b */ 2197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aput-wide vAA, vBB, vCC */ 2234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null array object? 2270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r9) @ r9<- vAA 2271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r3 @ compare unsigned index, length 2275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET: /* 0x52 */ 2410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish @ no, already resolved 2425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish 2431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 2437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Wide 32-bit instance field get. 2439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide vA, vB, field@CCCC */ 2441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish 2455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish 2482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish 2511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish 2540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish 2569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish 2598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT: /* 0x59 */ 2604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2608919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ no, already resolved 2619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ yes, finish up 2625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 2631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide vA, vB, field@CCCC */ 2632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2653919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit instance field put. 2654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2655919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput-object, iput-object-volatile 2656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2683919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2712919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2741919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2770919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET: /* 0x60 */ 2793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_finish: @ field ptr in r0 2807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28080890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SGET handler. 2821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sget-wide vAA, field@BBBB */ 2823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_finish: 2830861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2831861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 2832861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 28336e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2834861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 2835861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2836861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 2837861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2839861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28620890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28890890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29160890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29430890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29700890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT: /* 0x67 */ 2981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 2982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 2984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2985919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 2994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_finish: @ field ptr in r0 2995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 2998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 29990890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SPUT handler. 3009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sput-wide vAA, field@BBBB */ 3011861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 3012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3013861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 3014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3015861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 3016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3017861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 3018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3019861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 3020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3021861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 3022861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 3023861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 3024861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 30256e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 3026861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 3027861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 3028861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 3029861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 3030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3036919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit SPUT handler for objects 3037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3038919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput-object, sput-object-volatile 3039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3046919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_finish @ no, continue 3047919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 3048919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee EXPORT_PC() @ resolve() could throw, so export now 3049919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 3050919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3051919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ success? 3052919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_finish @ yes, finish 3053919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee b common_exceptionThrown @ no, handle exception 3054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3064919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 30780890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3091919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31050890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3118919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31320890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3145919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31590890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_finish: 3252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue on 3254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ yes, continue on 3274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue 3280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3308de75089fb7216d19e9c22cce4dc62a49513477d3Carl Shapiro b common_invokeMethodNoRange @ jump to common handler 3309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue on 3413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ yes, continue on 3435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue 3441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3471de75089fb7216d19e9c22cce4dc62a49513477d3Carl Shapiro b common_invokeMethodRange @ jump to common handler 3472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_INT: /* 0x7b */ 3493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_INT.S */ 3494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_INT: /* 0x7c */ 3520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_INT.S */ 3521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_LONG.S */ 3548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_LONG.S */ 3576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ optional op; may set condition codes 3593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_FLOAT.S */ 3604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_DOUBLE.S */ 3631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_LONG.S */ 3659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3685968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3686968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 369538214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitos s1, s0 @ s1<- op 3701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3710968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3711968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 372038214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitod d0, s0 @ d0<- op 3726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 3738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 3739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 3740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 3745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 3748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopNarrower.S */ 3755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 32-bit quantity in r0. 3759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: long-to-float, double-to-int, double-to-float 3761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (This would work for long-to-int, but that instruction is actually 3763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an exact match for OP_MOVE.) 3764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 3776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3811968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3812968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 382138214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizs s1, s0 @ s1<- op 3827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3865968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3866968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 387538214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtds d0, s0 @ d0<- op 3881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3890968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3891968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 390038214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizd s0, d0 @ s0<- op 3906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3945968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3946968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 395538214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtsd s0, d0 @ s0<- op 3961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_BYTE.S */ 3971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #24 @ optional op; may set condition codes 3986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 3988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 3997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_CHAR.S */ 3998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 4015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_SHORT.S */ 4025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT: /* 0x90 */ 4051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT.S */ 4052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT: /* 0x91 */ 4092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT.S */ 4093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT: /* 0x92 */ 4133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT.S */ 4134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT: /* 0x93 */ 4175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT.S */ 4176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT: /* 0x94 */ 4216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT.S */ 4217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 4251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT: /* 0x95 */ 4258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT.S */ 4259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT: /* 0x96 */ 4299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT.S */ 4300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT: /* 0x97 */ 4340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT.S */ 4341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT: /* 0x98 */ 4381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT.S */ 4382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT: /* 0x99 */ 4422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT.S */ 4423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT: /* 0x9a */ 4463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT.S */ 4464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply. 4595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WX 4598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * x YZ 4599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * -------- 4600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ZW ZX 4601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * YW YX 4602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The low word of the result holds ZX, the high word holds 4604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * it doesn't fit in the low 64 bits. 4606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most ARM math operations, multiply instructions have 4608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * restrictions on using the same register more than once (Rd and Rm 4609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * cannot be the same). 4610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long vAA, vBB, vCC */ 4612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 4620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_MUL_LONG_finish 4627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG: /* 0x9f */ 4675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG.S */ 4676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG.S */ 4721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 4754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG.S */ 4765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long vAA, vBB, vCC */ 4860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_finish 4877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long vAA, vBB, vCC */ 4889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_finish 4906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long vAA, vBB, vCC */ 4918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_finish 4935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4939968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4940968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 4941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 4947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 4949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 495338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 495538214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 4956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 4957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 4960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 4963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 4969968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 4970968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 4971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 4977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 4979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 498338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 498538214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 4986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 4987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 4990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 4993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 4999968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5000968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 501338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 501538214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 5020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5029968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5030968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 504338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 504538214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 5050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 5062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 5065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 5072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 5076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 5083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 5084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 5092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 5096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5101968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5102968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 511538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 511738214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ s2<- op 5122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5131968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5132968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 514538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 514738214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ s2<- op 5152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5161968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5162968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 517538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 517738214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ s2<- op 5182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5191968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5192968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 520538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 520738214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ s2<- op 5212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 5224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 5236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 5257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 5261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_2ADDR.S */ 5424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 5456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_2ADDR.S */ 5464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_2ADDR.S */ 5503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See OP_MUL_LONG for an explanation. 5784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * again we stuff it into rINST. 5787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long/2addr vA, vB */ 5789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 5797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 5923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG_2ADDR.S */ 5934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 5964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 5965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 5975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 6016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long/2addr vA, vB */ 6021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_2ADDR_finish 6037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long/2addr vA, vB */ 6047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_2ADDR_finish 6063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long/2addr vA, vB */ 6073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_2ADDR_finish 6089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6093968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6094968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 610538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 610738214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 6113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6121968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6122968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 613338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 613538214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 6141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6149968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6150968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 616138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 616338214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 6169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6177968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6178968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 618938214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 619138214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 6197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 6208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 6227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 6236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6245968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6246968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 625838214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 626038214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ d2<- op 6266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6274968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6275968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 628738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 628938214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ d2<- op 6295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6303968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6304968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 631638214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 631838214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ d2<- op 6324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6332968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6333968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 634538214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 634738214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ d2<- op 6353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 6394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT16.S */ 6404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT.S */ 6440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT16.S */ 6477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT16.S */ 6514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT16.S */ 6550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT16.S */ 6587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT16.S */ 6623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT16.S */ 6659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 6924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 6925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 6962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 6963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7113c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IGET_VOLATILE: /* 0xe3 */ 7114c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET_VOLATILE.S */ 7115c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET.S */ 7116c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7117c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field get. 7118c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7119c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7120c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7121c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7122c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7123c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7124c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7125c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7126c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7127c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7128c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7129c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_VOLATILE_finish @ no, already resolved 7130c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7131c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7132c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7133c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7134c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 7135c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_VOLATILE_finish 7136c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7141c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7142c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT_VOLATILE.S */ 7143c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT.S */ 7144c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7145c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field put. 7146c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7147919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7148c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7149c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7150c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7151c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7152c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7153c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7154c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7155c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7156c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7157c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 7158c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7159c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7160c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7161c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7162c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 7163c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7164c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7169c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SGET_VOLATILE: /* 0xe5 */ 7170c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET_VOLATILE.S */ 7171c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET.S */ 7172c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7173c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SGET handler. 7174c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7175c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7176c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7177c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7178c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7179c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7180c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7181c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7182c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7183c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7184c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7185c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 71860890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 7187c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7188c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7189c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 7190c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7191c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7196c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7197c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT_VOLATILE.S */ 7198c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT.S */ 7199c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7200c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SPUT handler. 7201c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7202919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7203c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7204c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7205c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7206c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7207c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7208c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7209c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7210c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7211c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7212c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7213c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7214c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 7215c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 72160890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 7217c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 7218c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7223c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7224c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7225c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET.S */ 7226c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7227c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field get. 7228c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7229c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7230c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7231c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7232c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7233c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7234c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7235c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7236c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7237c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7238c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7239c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 7240c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7241c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7242c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7243c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7244c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 7245c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_OBJECT_VOLATILE_finish 7246c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 72515387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 72525387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 72535387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 72545387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72555387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Wide 32-bit instance field get. 72565387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72575387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iget-wide vA, vB, field@CCCC */ 72585387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72595387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72605387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72645387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72655387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 72665387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72675387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72685387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72695387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72705387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 72715387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish 72725387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 72775387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 72785387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 72795387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 72805387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iput-wide vA, vB, field@CCCC */ 72815387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72825387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72835387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72845387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72855387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72865387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72875387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72885387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72895387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72905387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72915387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72925387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72935387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 72945387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 72955387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 73005387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 73015387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 73025387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 73035387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 73045387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SGET handler. 73055387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 73065387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sget-wide vAA, field@BBBB */ 73075387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 73085387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 73095387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 73105387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 73115387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 73125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 73135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_finish: 7314861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7315861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7316861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 73176e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7318861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7319861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7320861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7321861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 73225387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7323861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 73245387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 73255387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 73305387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 73315387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 73325387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 73335387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 73345387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SPUT handler. 73355387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 73365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sput-wide vAA, field@BBBB */ 7337861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 73385387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7339861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 73405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7341861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 73425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7343861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 73445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7345861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 73465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7347861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7348861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 7349861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7350861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 73516e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7352861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7353861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7354861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7355861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 7356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 736096516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 736196516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a throw-verification-error instruction. This throws an 7372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception for an error discovered during verification. The 7373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op AA, ref@BBBB */ 7376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 7378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ export the PC 7379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowVerificationError @ always throws 7381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ handle exception 7382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Execute a "native inline" instruction. 7389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7390b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7391b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7393b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7394b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7395b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ can throw 7401b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 7403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [sp] @ push &glue->retval 7404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ pop stack 7406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ test boolean result of inline 7407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7414b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7415b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7416b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7417b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7418b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7419b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7420b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7421b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7422b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7423b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7424b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7425b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7426b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7427b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7428b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7429b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7430b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7431b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7432b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7433b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7434b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7435b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7436b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7437b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7438b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7439b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7440b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7487b48a4d53bc3349b5c99f8b87a396e7374e2d335cDave Butcher FETCH(ip, 1) @ ip<- field byte offset 7488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7491b48a4d53bc3349b5c99f8b87a396e7374e2d335cDave Butcher ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7524919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee /* For: iput-quick */ 7525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A(+) 7545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 7546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 7547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ check object for null 7550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- field byte offset 7553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7562919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee /* For: iput-object-quick */ 7563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7572919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 7573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7575919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 7576919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card on non-null store 7577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7690c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7691c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7692919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee/* File: armv5te/OP_IPUT_OBJECT.S */ 7693c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7694919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit instance field put. 7695c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7696919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput-object, iput-object-volatile 7697c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7698c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7699c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7700c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7701c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7702c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7703c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7704c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7705c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7706c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 7707c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7708c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7709c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7710c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7711c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 7712c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7713c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7718c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7719c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7720c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET.S */ 7721c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7722c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SGET handler. 7723c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7724c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7725c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7726c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7727c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7728c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7729c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7730c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7731c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7732c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7733c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7734c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 77350890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 7736c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7737c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7738c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 7739c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7740c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7745c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7746c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7747919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee/* File: armv5te/OP_SPUT_OBJECT.S */ 7748c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7749919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit SPUT handler for objects 7750c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7751919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput-object, sput-object-volatile 7752c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7753c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7754c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7755c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7756c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7757c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7758c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7759919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7760919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7761919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee EXPORT_PC() @ resolve() could throw, so export now 7762919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7763919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7764919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ success? 7765919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7766919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee b common_exceptionThrown @ no, handle exception 7767919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee 7768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionEnd 7782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionEnd: 7783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 7785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Sister implementations 7787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterStart 7790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmSisterStart, %function 7791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 7792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 4 7793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterStart: 7794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING */ 7796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (String ref) 7800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_resolve: 7803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBBBBBB (String ref) 7819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_CLASS */ 7834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the Class has not yet been resolved. 7837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (Class ref) 7838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_CLASS_resolve: 7841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- Class reference 7846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CHECK_CAST */ 7854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_fullcheck: 7862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ class of the object that failed to be cast. 7868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ about to throw 7869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .LstrClassCastExceptionPtr 7871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowExceptionWithClassMessage 7873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds BBBB 7879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolve: 7882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- BBBB 7885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastExceptionPtr: 7895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrClassCastException 7896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INSTANCE_OF */ 7898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_fullcheck: 7906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_INSTANCE_OF_store 7908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds boolean result 7911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_store: 7914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test succeeded, save and bail. 7921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_trivial: 7924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ indicate success 7925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r3 holds BBBB 7935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolve: 7938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r3 @ r1<- BBBB 7941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 7948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_INSTANCE */ 7953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 32 @ minimize cache lines 7955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 7962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Class initialization required. 7966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class object 7968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_needinit: 7970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0 @ save r0 7971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInitClass @ initialize class 7972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ check boolean result 7973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ restore r0 7974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ failed, deal with init exception 7976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds BBBB 7981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolve: 7983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 7990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationErrorPtr: 7992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInstantiationError 7993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_ARRAY */ 7995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolve class. (This is an uncommon case.) 7999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 8001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds class ref CCCC 8002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_resolve: 8004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ r9<- length (save) 8006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- CCCC 8007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 8008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 8010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ r1<- length (restore) 8012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 8013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_NEW_ARRAY_finish 8014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Finish allocation. 8017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class 8019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 8020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_finish: 8022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 8023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 8024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 8025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 8027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ vA<- r0 8031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 8034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 8038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 8039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_continue: 8041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8043919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 8044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 8045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 8046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8049919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp rINST, #'I' @ array of ints? 8050919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'L' @ array of objects? 8051919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'[' @ array of arrays? 8052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 8053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 8054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 8056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8059919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8060919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str rINST, [rGLUE, #offGlue_retval+4] @ retval.h <- type 8061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 8063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 8065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 8067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 8069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 8077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 8078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 8079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 8080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 8081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 8082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 8092919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [rGLUE, #offGlue_retval] @ r0<- object 8093919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r1, [rGLUE, #offGlue_retval+4] @ r1<- type 8094919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8095919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8096919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #'I' @ Is int array? 8097919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card if not 8098919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ execute it 8099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 8102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 8103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 8105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 8106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 8108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 8109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) @ define in one or the other, not both 8111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 8112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 8113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 8118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 8122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 8123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 8125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8127919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 8128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 8130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8133919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp rINST, #'I' @ array of ints? 8134919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'L' @ array of objects? 8135919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'[' @ array of arrays? 8136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 8137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 8138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 8140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8143919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8144919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str rINST, [rGLUE, #offGlue_retval+4] @ retval.h <- type 8145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 8147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 8149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 8151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 8161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 8162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 8163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 8164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 8165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 8166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 8176919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [rGLUE, #offGlue_retval] @ r0<- object 8177919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r1, [rGLUE, #offGlue_retval+4] @ r1<- type 8178919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8179919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8180919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #'I' @ Is int array? 8181919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card if not 8182919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ execute it 8183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 8186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 8187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 8190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 8192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 8193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) @ define in one or the other, not both 8195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 8196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 8197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_FLOAT */ 8202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_FLOAT_finish: 8203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_FLOAT */ 8207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_FLOAT_finish: 8208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_DOUBLE */ 8212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_DOUBLE_finish: 8213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_DOUBLE */ 8217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_DOUBLE_finish: 8218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMP_LONG */ 8222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_less: 8224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, #0 @ r1<- -1 8225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ instead, we just replicate the tail end. 8227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_greater: 8233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ r1<- 1 8234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to _finish 8235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_finish: 8237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_AGET_WIDE */ 8243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_AGET_WIDE_finish: 8245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_WIDE */ 8253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_WIDE_finish: 8255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_OBJECT */ 8262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = vBB (arrayObj) 8265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = vAA (obj) 8266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = offset into array (vBB + vCC * width) 8267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_finish: 8269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ storing null reference? 8270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ okay? 8275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errArrayStore @ no 8276919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8277919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ get biased CT base 8278919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r10, #offArrayObject_contents @ r0<- pointer to slot 8279919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 8280919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r9, [r10] @ vBB[vCC]<- vAA 8281919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strb r2, [r2, r10, lsr #GC_CARD_SHIFT] @ mark card 8282919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 8283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_skip_check: 8284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET */ 8290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_finish: 8297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83020890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_WIDE */ 8311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_WIDE_finish: 8318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8321c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 0 8322861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r9, r3 @ r0<- address of field 83236e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 8324861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 8325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8326861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 8327861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8329861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden and r2, r2, #15 @ r2<- A 8330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_OBJECT */ 8336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_OBJECT_finish: 8343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83480890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BOOLEAN */ 8357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BOOLEAN_finish: 8364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83690890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BYTE */ 8378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BYTE_finish: 8385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83900890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_CHAR */ 8399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_CHAR_finish: 8406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 84110890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_SHORT */ 8420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_SHORT_finish: 8427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 84320890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT */ 8441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_finish: 8448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 84570890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_WIDE */ 8462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_WIDE_finish: 8469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8477861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 8478c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 0 8479861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r9, r3 @ r2<- target address 84806e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 8481861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 8482861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 8483861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 8484861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 8485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_OBJECT */ 8487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_OBJECT_finish: 8494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8500919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8503919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r9, r3 @ r9<- direct ptr to target location 8504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85050890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8506919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [r9] @ obj.field (8/16/32 bits)<- r0 8507919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ stored a null reference? 8508919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 8509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BOOLEAN_finish: 8519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85280890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BYTE */ 8533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BYTE_finish: 8540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85490890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_CHAR */ 8554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_CHAR_finish: 8561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85700890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_SHORT */ 8575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_SHORT_finish: 8582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85910890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET */ 8596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_resolve: 8602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_finish @ yes, finish 8608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_WIDE */ 8611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8615861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8616861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 8617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_resolve: 8619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_OBJECT */ 8628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_resolve: 8634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BOOLEAN */ 8643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_resolve: 8649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BYTE */ 8658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_resolve: 8664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_CHAR */ 8673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_resolve: 8679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_SHORT */ 8688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_resolve: 8694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT */ 8703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_resolve: 8709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_finish @ yes, finish 8715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_WIDE */ 8718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: &fp[AA] 8723861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8724861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 8725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_resolve: 8727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8732861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 8733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_OBJECT */ 8737919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee.LOP_SPUT_OBJECT_finish: @ field ptr in r0 8738919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee mov r2, rINST, lsr #8 @ r2<- AA 8739919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8740919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_VREG(r1, r2) @ r1<- fp[AA] 8741919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8742919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 8743919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r0, #offStaticField_value @ r0<- pointer to store target 8744919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee @ no-op @ releasing store 8745919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r1, [r0] @ field<- vAA 8746919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #0 @ stored a null object? 8747919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ mark card if not 8748919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 8749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_resolve: 8757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BYTE */ 8766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_resolve: 8772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_CHAR */ 8781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_resolve: 8787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_SHORT */ 8796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_resolve: 8802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_continue: 8818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER */ 8828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_continue: 8835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_resolve: 8846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_nsm: 8858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT */ 8862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_resolve: 8869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the float in r0 to a long in r0/r1. 8949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenf2l_doconv: 8955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, lr} 8956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0x5f000000 @ (float)maxlong 8957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r4, r0 8958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0xdf000000 @ (float)minlong 8966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (80000000) 8969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r4 8974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpeq @ is arg == self? 8975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmeqfd sp!, {r4, pc} 8978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_f2lz @ convert float to long 8981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, pc} 8982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddend2l_doconv: 8992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, r5, lr} @ save regs 89935162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 89945162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 89955162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align for EABI 89975162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r5, r1 @ and r1 8999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 9000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 9001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 9002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 9003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 9004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 9006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 90075162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 90085162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 90095162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 9010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmple @ is arg <= minlong? 9011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 9012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (8000000000000000) 9013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 9014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 9015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 9017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 9018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r4 @ compare against self 9019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r5 9020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpeq @ is arg == self? 9021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 9022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 9023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f 9024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 9026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 9027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_d2lz @ convert double to long 9028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 9030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 9031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, r5, pc} 9032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_MUL_LONG */ 9034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_MUL_LONG_finish: 9036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 9038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG */ 9041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_finish: 9043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 9044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG */ 9049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_finish: 9051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 9052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG */ 9057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_finish: 9059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 9060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 9065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_2ADDR_finish: 9067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 9072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_2ADDR_finish: 9074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 9079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_2ADDR_finish: 9081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9085c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IGET_VOLATILE */ 9086c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9087c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9088c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9089c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9090c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9091c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9092c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IGET_VOLATILE_finish: 9093c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9094c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9095c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9096c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9097c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 90980890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 9099c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 9100c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9101c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r2, r2, #15 @ r2<- A 9102c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9103c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 9104c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9105c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9106c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IPUT_VOLATILE */ 9107c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9108c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9109c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9110c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9111c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9112c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9113c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IPUT_VOLATILE_finish: 9114c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9115c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 9116c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9117c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r1, r1, #15 @ r1<- A 9118c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9119c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 9120c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9121c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9122c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 91230890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 9124c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 9125c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9126c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9127c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SGET_VOLATILE */ 9128c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9129c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9130c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9131c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9132c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9133c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_VOLATILE_resolve: 9134c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9135c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9136c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9137c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9138c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9139c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SGET_VOLATILE_finish @ yes, finish 9140c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9141c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9142c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SPUT_VOLATILE */ 9143c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9144c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9145c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9146c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9147c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9148c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SPUT_VOLATILE_resolve: 9149c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9150c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9151c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9152c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9153c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9154c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SPUT_VOLATILE_finish @ yes, finish 9155c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9156c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9157c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IGET_OBJECT_VOLATILE */ 9158c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9159c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9160c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9161c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9162c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9163c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9164c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IGET_OBJECT_VOLATILE_finish: 9165c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9166c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9167c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9168c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9169c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 91700890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 9171c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 9172c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9173c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r2, r2, #15 @ r2<- A 9174c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9175c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 9176c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9177c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 91785387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IGET_WIDE_VOLATILE */ 91795387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91805387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 91815387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 91825387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 91835387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 91845387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 91855387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IGET_WIDE_VOLATILE_finish: 91865387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 91875387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 91885387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 9189c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 1 9190861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r9, r3 @ r0<- address of field 91916e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 9192861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 91935387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 9194861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9195861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 91965387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9197861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden and r2, r2, #15 @ r2<- A 91985387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 91995387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 92005387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 92015387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 92025387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92035387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IPUT_WIDE_VOLATILE */ 92045387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92055387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 92065387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 92075387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 92085387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 92095387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 92105387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IPUT_WIDE_VOLATILE_finish: 92115387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 92125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 92135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden and r2, r2, #15 @ r2<- A 92145387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 92155387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 92165387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 92175387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 92185387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 9219861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 9220c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 1 9221861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r9, r3 @ r2<- target address 92226e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 9223861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 9224861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 9225861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9226861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 92275387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92285387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SGET_WIDE_VOLATILE */ 92295387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92305387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 92315387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 92325387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 9233861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9234861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 92355387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 92365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_resolve: 92375387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 92385387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 92395387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 92405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 92415387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 92425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 92435387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 92445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92455387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SPUT_WIDE_VOLATILE */ 92465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 92475387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 92485387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 92495387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 92505387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9: &fp[AA] 9251861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9252861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 92535387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 92545387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SPUT_WIDE_VOLATILE_resolve: 92555387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 92565387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 92575387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 92585387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 92595387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 9260861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 92615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 92625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 92635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 9264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_EXECUTE_INLINE */ 9265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Extract args, call function. 9268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = #of args (0-4) 9269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = call index 9270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Other ideas: 9273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Use a jump table from the main piece to jump directly into the 9274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 9275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Have five separate pieces that do the loading, so we can work the 9276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interleave a little better. Increases code size. 9277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_continue: 9279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r9, 2) @ r9<- FEDC 9281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r9, #0xf000 @ isolate F 9284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 9285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r9, #0x0f00 @ isolate E 9286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 9287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r9, #0x00f0 @ isolate D 9288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 9289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r9, #0x000f @ isolate C 9290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 9291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: 9292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 9293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (not reached) 9295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_table: 9297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word gDvmInlineOpsTable 9298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9299b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 9300b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9301b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 9302b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 9303b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 9304b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 9305b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9306b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 9307b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 9308b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9309b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 9310b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9311b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9312b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 9313b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 9314b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 9315b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 9316b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 9317b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 9318b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 9319b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 9320b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 9321b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 9322b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9323b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 9324b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9325b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 9326b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 9327b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9328c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IPUT_OBJECT_VOLATILE */ 9329c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9330c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9331c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9332c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9333c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9334c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9335c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IPUT_OBJECT_VOLATILE_finish: 9336c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9337c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 9338c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9339c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r1, r1, #15 @ r1<- A 9340c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9341c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 9342919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 9343c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9344c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9345919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r9, r3 @ r9<- direct ptr to target location 9346c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 93470890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 9348919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [r9] @ obj.field (8/16/32 bits)<- r0 9349919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ stored a null reference? 9350919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 9351c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9352c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9353c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SGET_OBJECT_VOLATILE */ 9354c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9355c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9356c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9357c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9358c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9359c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_OBJECT_VOLATILE_resolve: 9360c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9361c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9362c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9363c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9364c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9365c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 9366c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9367c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9368c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SPUT_OBJECT_VOLATILE */ 9369919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 9370919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee mov r2, rINST, lsr #8 @ r2<- AA 9371919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9372919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_VREG(r1, r2) @ r1<- fp[AA] 9373919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 9374919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 9375919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r0, #offStaticField_value @ r0<- pointer to store target 9376919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee SMP_DMB @ releasing store 9377919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r1, [r0] @ field<- vAA 9378919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #0 @ stored a null object? 9379919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ mark card if not 9380919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 9381c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 9383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterEnd 9384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterEnd: 9385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/footer.S */ 9387ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common subroutines and data 9391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9394ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9395ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 9397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 9398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9399ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 940097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 940197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 940297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 9403d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 940497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 9405d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9406d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9407d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 940897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 940997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 941097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 9411d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9412d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 941397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 9414d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 941597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 94167a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng .global dvmJitToInterpNoChainNoProfile 94177a2697d327936e20ef5484f7819e2e4bf91c891fBen ChengdvmJitToInterpNoChainNoProfile: 94187a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94197a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r0,rPC @ pass our target PC 94207a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r2,#kSVSNoProfile @ r2<- interpreter entry point 94217a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 94227a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r3, [r10, #offThread_inJitCodeCache] @ back to the interp land 94237a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b jitSVShadowRunEnd @ doesn't return 94247a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 942540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 942640094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 9427d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 942840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC @ pass our target PC 94297a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 94307a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9431d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9432d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 943340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng 943440094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 943540094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 9436d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94379a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 943897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 94397a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9440d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9441d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 944297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 944340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpBackwardBranch 944440094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpBackwardBranch: 9445d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94469a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 944797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 94487a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9449d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9450d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 945197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 945297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 945397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 9454d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94559a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 945697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 94577a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9458d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9459d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 946097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 946197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 946297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 9463d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 946497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 946597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 94667a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9467d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9468d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 946997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9470ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9471ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter when the compiler is 9472ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * having issues translating/executing a Dalvik instruction. We have to skip 9473ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the code cache lookup otherwise it is possible to indefinitely bouce 9474ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * between the interpreter and the code cache if the instruction that fails 9475ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * to be compiled happens to be at a trace start. 9476ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9477ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpPunt 9478ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpPunt: 94797a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9480ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r0 9481978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9482ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,lr 9483ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpPunt; 9484ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9485ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 94867a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r0, #0 94877a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9488ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9489ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9490ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9491ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9492ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9493ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9494ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return to the interpreter to handle a single instruction. 9495ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * On entry: 9496ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r0 <= PC 9497ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r1 <= PC of resume instruction 9498ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * lr <= resume point in translation 9499ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9500ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpSingleStep 9501ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpSingleStep: 9502d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9503d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 9504ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#kInterpEntryInstr 9505ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ enum is 4 byte in aapcs-EABI 9506ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_entryPoint] 9507ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC,r0 9508ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 95097a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng 9510ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9511ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitSingleStep @ Ask for single step and then revert 9512ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9513ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp to bail to debug interp 9514ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9515ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 951640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 951740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * Return from the translation cache and immediately request 951840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * a translation for the exit target. Commonly used for callees. 951940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 952040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 952140094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 9522978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 952340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmBumpNoChain 952440094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng#endif 952540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 952640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC 952740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 952840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 952940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r1, rPC @ arg1 of translation may need this 953040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 95317a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 @ !0 means translation exists 953240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bxne r0 @ continue native execution if so 95337a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b 2f @ branch over to use the interpreter 9534ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9535ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9536ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache and immediately request 9537ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a translation for the exit target. Commonly used following 9538ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * invokes. 9539ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 954040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 954140094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 95429a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 95437a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 95449a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9545bd0472480c6e876198fe19c4ffa22350c0ce57daBill Buzbee add rINST, #-4 @ .. which is 9 bytes back 9546ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 95477a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 95487a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9549ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9550ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng beq 2f 9551ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9552ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 95539a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 95549a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 955546cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 955646cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 955746cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9558ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9559ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* No translation, so request one if profiling isn't disabled*/ 9560ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng2: 95611da12167d913efde56ec3b40491524b051679f2cAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9562ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9564ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0, #0 956540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng movne r2,#kJitTSelectRequestHot @ ask for trace selection 9566ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_selectTrace 9567ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9568ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9570ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9571ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter. 9572ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * The return was done with a BLX from thumb mode, and 9573ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the following 32-bit word contains the target rPC value. 9574ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Note that lr (r14) will have its low-order bit set to denote 9575ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * its thumb-mode origin. 9576ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 9577ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * We'll need to stash our lr origin away, recover the new 9578ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * target and then check to see if there is a translation available 9579ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * for our new target. If so, we do a translation chain and 9580ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * go back to native execution. Otherwise, it's back to the 9581ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * interpreter (after treating this entry as a potential 9582ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace start). 9583ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9584ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNormal 9585ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNormal: 95869a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 95877a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 95889a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9589bd0472480c6e876198fe19c4ffa22350c0ce57daBill Buzbee add rINST,#-4 @ .. which is 9 bytes back 9590978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9591ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNormal 9592ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9593ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9594ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 95957a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9596ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 959746cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee beq toInterpreter @ go if not, otherwise do chain 9598ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9599ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 96009a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 96019a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 960246cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 960346cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 960446cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9605ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9606ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9607ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter to do method invocation. 9608ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Check if translation exists for the callee, but don't chain to it. 9609ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 96107a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng .global dvmJitToInterpNoChainNoProfile 96117a2697d327936e20ef5484f7819e2e4bf91c891fBen ChengdvmJitToInterpNoChainNoProfile: 96127a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#if defined(WITH_JIT_TUNING) 96137a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bl dvmBumpNoChain 96147a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#endif 96157a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 96167a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r0,rPC 96177a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bl dvmJitGetCodeAddr @ Is there a translation? 96187a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 96197a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r1, rPC @ arg1 of translation may need this 96207a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 96217a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 96227a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bxne r0 @ continue native execution if so 96237a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng EXPORT_PC() 96247a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng adrl rIBASE, dvmAsmInstructionStart 96257a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng FETCH_INST() 96267a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 96277a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng GOTO_OPCODE(ip) @ jump to next instruction 96287a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 96297a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng/* 96307a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng * Return from the translation cache to the interpreter to do method invocation. 96317a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng * Check if translation exists for the callee, but don't chain to it. 96327a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng */ 9633ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNoChain 9634ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNoChain: 9635978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9636ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNoChain 9637ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 96387a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9639ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9640ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 96417a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 96429a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 96439a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9644ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9645ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ continue native execution if so 964697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9647ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9648ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9649ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * No translation, restore interpreter regs and start interpreting. 9650ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * rGLUE & rFP were preserved in the translated code, and rPC has 9651ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * already been restored by the time we get here. We'll need to set 9652ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * up rIBASE & rINST, and load the address of the JitTable into r0. 9653ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 965446cd5b63c29d3284a9ff3e0d0711fb136f409313Bill BuzbeetoInterpreter: 9655ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9656ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9657ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9658ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9659ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ NOTE: intended fallthrough 96607a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 9661ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9662ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Common code to update potential trace start counter, and initiate 9663ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a trace-build if appropriate. On entry, rPC should point to the 9664ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * next instruction to execute, and rINST should be already loaded with 9665ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the next opcode word, and r0 holds a pointer to the jit profile 9666ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * table (pJitProfTable). 9667ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9668ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_testUpdateProfile: 9669ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9670ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9671ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9672ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9673ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_updateProfile: 9674ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 96757b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 96767b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 9677ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9678ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng subs r1,r1,#1 @ decrement counter 96797b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 9680ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9681ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9682ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9683ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Here, we switch to the debug interpreter to request 9684ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace selection. First, though, check to see if there 9685ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * is already a native translation in place (and, if so, 9686ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * jump to it now). 9687ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9688d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 96897a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 96907b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 9691ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9692ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9693ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 96947a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 96957a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, rPC @ arg1 of translation may need this 96967a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 9697ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 969897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9699ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ jump to the translation 970040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r2,#kJitTSelectRequest @ ask for trace selection 970140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng @ fall-through to common_selectTrace 970297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 970340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng moveq r2,#kJitTSelectRequest @ ask for trace selection 97049a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 97059a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 97069a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 97079a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 97089a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 97099a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 9710d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r10, r0 @ save target 97119a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 9712d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng cmp r0, r10 @ special case? 9713d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne jitSVShadowRunStart @ set up self verification shadow space 97149a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 97159a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 97169a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 971797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 97189a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 971940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 972040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * On entry: 972140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 972240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 9723ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_selectTrace: 9724ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 97259c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 97269c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9727ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp 9728ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9729ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 973097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 973197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 973297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 973397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 9734d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * On entry: 9735d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * rPC, rFP, rGLUE: the values that they should contain 9736d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * r10: the address of the target translation. 973797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9738d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunStart: 973997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 974097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 974197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 97429a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 974397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9744ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9745ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9746ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 974797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 974897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 974997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 975097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 975197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9752d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunEnd: 975397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 975497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9755ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9756ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9757ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9758ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 975997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 976097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 976197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 976297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 976330f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 976430f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 976597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 976697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 976797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 976897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 976997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 977097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 977197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 977297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 977397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 977497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 977597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9776ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9777ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code when a backward branch is taken. 9780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9781c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * TODO: we could avoid a branch by just setting r0 and falling through 9782c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * into the common_periodicChecks code, and having a test on r0 at the 9783c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * end determine if we should return to the caller or update & branch to 9784c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * the next instr. 9785c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is PC adjustment *in bytes* 9788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_backwardBranch: 9790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryInstr 9791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9792ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9793ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9794ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9795ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9796ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9797ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9798ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9799ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9803ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9808c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * activity has begun. If so, we suspend the thread or side-exit to 9809c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * the debug interpreter as appropriate. 9810c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9811c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * The common case is no activity on any of these, so we want to figure 9812c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * that out quickly. If something is up, we can then sort out what. 9813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9814c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * We want to be fast if the VM was built without debugger or profiler 9815c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * support, but we also need to recognize that the system is usually 9816c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * shipped with both of these enabled. 9817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: reduce this so we're just checking a single location. 9819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9821c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 9822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is trampoline PC adjustment *in bytes* 9823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_periodicChecks: 9825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) 9828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_PROFILER) 9831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9834c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr ip, [r3] @ ip<- suspendCount (int) 9835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9836c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#if defined(WITH_DEBUGGER) && defined(WITH_PROFILER) 9837c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp r1, #0 @ debugger enabled? 9838c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldrneb r1, [r1] @ yes, r1<- debuggerActive (boolean) 9839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9840c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrne ip, ip, r1 @ ip<- suspendCount | debuggerActive 9841c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrs ip, ip, r2 @ ip<- suspend|debugger|profiler; set Z 9842c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#elif defined(WITH_DEBUGGER) 9843c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp r1, #0 @ debugger enabled? 9844c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldrneb r1, [r1] @ yes, r1<- debuggerActive (boolean) 9845c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrsne ip, ip, r1 @ yes, ip<- suspend | debugger; set Z 9846c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden @ (if not enabled, Z was set by test for r1==0, which is what we want) 9847c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#elif defined (WITH_PROFILER) 9848c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9849c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrs ip, ip, r2 @ ip<- suspendCount | activeProfilers 9850c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#else 9851c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp ip, #0 @ not ORing anything in; set Z 9852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9854c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bxeq lr @ all zero, return 9855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9856c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden /* 9857c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * One or more interesting events have happened. Figure out what. 9858c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9859c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * If debugging or profiling are compiled in, we need to disambiguate. 9860c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9861c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * r0 still holds the reentry type. 9862c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden */ 9863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9864c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr ip, [r3] @ ip<- suspendCount (int) 9865c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp ip, #0 @ want suspend? 9866c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden beq 1f @ no, must be debugger/profiler 9867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9869c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden stmfd sp!, {r0, lr} @ preserve r0 and lr 9870964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9871964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee /* 9872964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * Refresh the Jit's cached copy of profile table pointer. This pointer 9873964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * doubles as the Jit's on/off switch. 9874964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee */ 9875d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 9876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9877d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [r3] @ r3 <- pJitProfTable 9878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC 9879964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh Jit's on/off switch 9880964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#else 9881964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9882964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee EXPORT_PC() @ need for precise GC 9883964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9884c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bl dvmCheckSuspendPending @ do full check, suspend if necessary 9885c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldmfd sp!, {r0, lr} @ restore r0 and lr 9886c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9887c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9888c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9889c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden /* 9890c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * Reload the debugger/profiler enable flags. We're checking to see 9891c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * if either of these got set while we were suspended. 9892c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9893c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * We can't really avoid the #ifdefs here, because the fields don't 9894c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * exist when the feature is disabled. 9895c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden */ 9896c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#if defined(WITH_DEBUGGER) 9897c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9898c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp r1, #0 @ debugger enabled? 9899c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldrneb r1, [r1] @ yes, r1<- debuggerActive (boolean) 9900c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#else 9901c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden mov r1, #0 9902c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#endif 9903c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#if defined(WITH_PROFILER) 9904c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9905c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9906c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#else 9907c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden mov r2, #0 9908c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#endif 9909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9910c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrs r1, r1, r2 9911c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden beq 2f 9912c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9913c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden1: @ debugger/profiler enabled, bail out; glue->entryPoint was set above 9914c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden str r0, [rGLUE, #offGlue_entryPoint] @ store r0, need for debug/prof 9915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, rPC, r9 @ update rPC 9916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ "want switch" = true 9917c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden b common_gotoBail @ side exit 9918c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9919c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden#endif /*WITH_DEBUGGER || WITH_PROFILER*/ 9920c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9921c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden2: 9922c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bx lr @ nothing to do, return 9923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * State registers will be saved to the "glue" area before bailing. 9929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * other interpreter or just bail all the way out 9933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_gotoBail: 9935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ r0<- glue ptr 9937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r1, r1, #1 @ using (boolean+1) 9940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl _longjmp @ does not return 9942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_abort 9943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation with range. 9947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodRange: 9952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewRange: 9953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- CCCC 9958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r2, r2, #1 @ count-- 9966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r10], #4 @ *outs++ = val 9967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1b @ ...while count != 0 9968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LinvokeArgsDone 9970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation without range. 9973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodNoRange: 9978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewNoRange: 9979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone 9986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNonRange: 9989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vA 9996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r1, #0xf000 @ isolate G 9997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vG 10000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r1, #0x0f00 @ isolate F 10001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 10002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 10003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vF 10004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r1, #0x00f0 @ isolate E 10005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 10006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 10007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vE 10008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r1, #0x000f @ isolate D 10009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 10010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 10011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vD 10012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: @ fall through to .LinvokeArgsDone 10013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 10015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 10016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 10017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ find space for the new stack frame, check for overflow 10018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 10019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 10020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 10021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@ bl common_dumpRegs 10022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 10023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 10024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, r9 @ bottom < interpStackEnd? 10025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 100267a44e4ee0782d24b4c6090be1f0a3c66f971f2c1Andy McFadden blo .LstackOverflow @ yes, this frame will overflow stack 10027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ set up newSaveArea 10029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef EASY_GDB 10030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 10031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [r10, #offStackSaveArea_prevSave] 10032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 10034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 10035ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 10036ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r9, #0 10037ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r9, [r10, #offStackSaveArea_returnAddr] 10038ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 10039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r10, #offStackSaveArea_method] 10040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden tst r3, #ACC_NATIVE 10041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LinvokeNative 10042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 10045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 10046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP 10047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 10049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 10050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 10051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 10052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 10053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 10054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 10055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 10056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 10059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 10060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r2 @ publish new rPC 10061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 10062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Update "glue" values for the new method 10064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 10065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 10066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 10067ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 10068ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 10069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r1 @ fp = newFp 10070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 10071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rINST, r9 @ publish new rINST 10072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 10073ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 10074ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 10075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10076ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 10077ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rFP, r1 @ fp = newFp 10078ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 10079ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rINST, r9 @ publish new rINST 10080ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 10081ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 10082ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 10083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNative: 10085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Prep for the native call 10086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 10087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 10088d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 10089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 10090d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 10091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r3 @ r9<- glue->self (preserve) 10092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ r2<- methodToCall 10094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ r0<- newFp (points to args) 10095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 10096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 10098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 10099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .Lskip 10100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_mterp, %function 10101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_mterp: 10102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 10103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 10104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 10105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lskip: 10106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @mov lr, pc @ set return addr 10109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 10110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 10111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10112964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10113964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ Refresh Jit's on/off status 10114964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10115964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee 10116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ native return; r9=self, r10=newSaveArea 10117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ equivalent to dvmPopJniLocals 10118d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 10119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 10120964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10121964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 10122964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 10124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null? 10125d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 10126964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10127964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh cached on/off switch 10128964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ no, handle exception 10130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101356ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 101366ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 10137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 10138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmHandleStackOverflow 10139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 10141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 10142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation, calling through "glue code". 10147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: now that we have range and non-range invoke handlers, this 10149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * needs to be split into two. Maybe just create entry points 10150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that set r9 and jump here? 10151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 10153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 10154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 10155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeOld: 10158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #8 @ space for args + pad 10159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 10160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ A2<- methodToCall 10161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ A0<- glue 10162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 10163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ A1<- methodCallRange 10164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ A3<- AA 10165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #0] @ A4<- ip 10166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 10167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ remove arg area 10168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall @ continue to next instruction 10169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for handling a return instruction. 10175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 10177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_returnFromMethod: 10179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnNew: 10180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryReturn 10181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 10182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 10183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 10185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 10186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 10187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 10188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r2<- method we're returning to 10189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 10190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is this a break frame? 10191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 10192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 10193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_gotoBail @ break frame, bail out completely 10194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 10196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 10197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 10198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 10199ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 102007a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 10201ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r9 @ publish new rPC 10202ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_methodClassDex] 102037a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r10, [r3, #offThread_inJitCodeCache] @ may return to JIT'ed land 102047a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng cmp r10, #0 @ caller is compiled code 102057a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng blxne r10 10206ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 10207ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 10208ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 10209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r9 @ publish new rPC 10211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 10212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10213ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 10214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return handling, calls through "glue code". 10217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnOld: 10220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 10221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 10222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_returnFromMethod 10223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 10224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Somebody has thrown an exception. Handle it. 10229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If the exception processing code returns to us (instead of falling 10231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out of the interpreter), continue with whatever the next instruction 10232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * now happens to be. 10233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 10235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10236ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmMterpCommonExceptionThrown 10237ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmMterpCommonExceptionThrown: 10238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_exceptionThrown: 10239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionNew: 10240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryThrow 10241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 10242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 10243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 10245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 10246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 10247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 10248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 10249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- NULL 10250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 10251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up args and a local for "&fp" */ 10253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 10254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [sp, #-4]! @ *--sp = fp 10255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov ip, sp @ ip<- &fp 10256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- false 10257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #-4]! @ *--sp = &fp 10258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 10259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 10260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 10261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r9 @ r2<- exception 10262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 10263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 10264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 10266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 10267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 10269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 10270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 10271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ no, skip ahead 10272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r0 @ save relPc result in rFP 10273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 102744fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden mov r1, r9 @ r1<- exception 10275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCleanupStackOverflow @ call(self) 10276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP @ restore result 10277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 10278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 10280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 10281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is catchRelPc < 0? 10282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ restore stack 10283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi .LnotCaughtLocally 10284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* adjust locals to match self->curFrame and updated PC */ 10286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 10287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 10288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 10289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 10290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 10291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 10292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 10293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 10294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* release the tracked alloc on the exception */ 10296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 10297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 10298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* restore the exception if the handler wants it */ 10301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 10302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 10304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 10305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 10308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix stack overflow if necessary */ 10309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 10310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 10311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, r10 @ if yes: r0<- self 103124fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden movne r1, r9 @ if yes: r1<- exception 10313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 10314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ may want to show "not caught locally" debug messages here 10316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if DVM_SHOW_EXCEPTION >= 2 10317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call __android_log_print(prio, tag, format, ...) */ 10318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* "Exception %s from %s:%d not caught locally" */ 10319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 10320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 10321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_insns] 10322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 10323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden asr r1, r1, #1 10324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLineNumFromPC 10325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 10326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmGetMethodSourceFile(method) 10327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 10328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmGetMethodSourceFile 10329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 10330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ exception->clazz->descriptor 10331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] 10332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_descriptor] 10333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ 10334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, strExceptionNotCaughtLocally 10335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strLogTag 10336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #3 @ LOG_DEBUG 10337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __android_log_print 10338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 10339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offThread_exception] @ restore exception 10340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 10341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 10342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 10344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail @ bail out 10345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exception handling, calls through "glue code". 10349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionOld: 10352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 10353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 10354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_exceptionThrown 10355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 10356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * After returning from a "glued" function, pull out the updated 10361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * values and start executing at the next instruction. 10362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_resumeAfterGlueCall: 10364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 10365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 10366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array index. 10371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayIndex: 10373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayIndexException 10375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array value. 10381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayStore: 10383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayStoreException 10385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Integer divide or mod by zero. 10391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errDivideByZero: 10393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArithmeticException 10395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strDivideByZero 10396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Attempt to allocate an array with a negative size. 10401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNegativeArraySize: 10403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNegativeArraySizeException 10405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invocation of a non-existent method. 10411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNoSuchMethod: 10413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNoSuchMethodError 10415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We encountered a null object when we weren't expecting one. We 10421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * export the PC, throw a NullPointerException, and goto the exception 10422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * processing code. 10423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNullObject: 10425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 10426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNullPointerException 10427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 10428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 10429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 10430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For debugging, cause an immediate fault. The source address will 10433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be in lr (use a bl instruction to jump here). 10434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_abort: 10436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, .LdeadFood 10437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LdeadFood: 10438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word 0xdeadf00d 10439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out a "we were here", preserving all registers. (The attempt 10442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to save ip won't work, but we need to save an even number of 10443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * registers for EABI 64-bit stack alignment.) 10444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .macro SQUEAK num 10446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_squeak\num: 10447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 10449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #\num 10450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endm 10454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 0 10456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 1 10457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 2 10458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 3 10459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 4 10460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 5 10461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out the number in r0, preserving registers. 10464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNum: 10466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 10469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print a newline, preserving registers. 10475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNewline: 10477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNewline 10479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 10485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printHex: 10487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 10489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintHex 10490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 10496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printLong: 10498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r1 10500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 10501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintLong 10502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 10503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 10508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printMethod: 10510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpPrintMethod 10512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Call a C helper function that dumps regs and possibly some 10517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * additional info. Requires the C function to be compiled in. 10518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_dumpRegs: 10521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpDumpArmRegs 10523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10527d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#if 0 10528d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden/* 10529d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Experiment on VFP mode. 10530d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10531d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 10532d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10533d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 10534d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden */ 10535d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddensetFPSCR: 10536d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r0, r0, r1 @ make sure no stray bits are set 10537d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmrx r2, fpscr @ get VFP reg 10538d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mvn r1, r1 @ bit-invert mask 10539d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r2, r2, r1 @ clear masked bits 10540d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden orr r2, r2, r0 @ set specified bits 10541d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmxr fpscr, r2 @ set VFP reg 10542d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, r2 @ return new value 10543d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bx lr 10544d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10545d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .align 2 10546d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .global dvmConfigureFP 10547d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .type dvmConfigureFP, %function 10548d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddendvmConfigureFP: 10549d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden stmfd sp!, {ip, lr} 10550d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x03000000 sets DN/FZ */ 10551d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x00009f00 clears the six exception enable flags */ 10552d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl common_squeak0 10553d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10554d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10555d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl setFPSCR 10556d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden ldmfd sp!, {ip, pc} 10557d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#endif 10558d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references, must be close to the code that uses them. 10562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 10564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArithmeticException: 10565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArithmeticException 10566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayIndexException: 10567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayIndexException 10568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayStoreException: 10569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayStoreException 10570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrDivideByZero: 10571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrDivideByZero 10572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNegativeArraySizeException: 10573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNegativeArraySizeException 10574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNoSuchMethodError: 10575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNoSuchMethodError 10576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNullPointerException: 10577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNullPointerException 10578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrLogTag: 10580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrLogTag 10581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrExceptionNotCaughtLocally: 10582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrExceptionNotCaughtLocally 10583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNewline: 10585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNewline 10586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrSqueak: 10587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrSqueak 10588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintHex: 10589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintHex 10590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintLong: 10591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintLong 10592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Zero-terminated ASCII string data. 10595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with the address, or use an ADR pseudo-op to get the address 10598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * PC-relative addressing mode and hence has a limited range, which 10600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * makes it not work well with mergeable string sections. 10601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrBadEntryPoint: 10605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Bad entry point %d\n" 10606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArithmeticException: 10607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArithmeticException;" 10608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayIndexException: 10609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayStoreException: 10611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastException: 10613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ClassCastException;" 10614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrDivideByZero: 10615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "divide by zero" 10616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrFilledNewArrayNotImpl: 10617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInternalError: 10619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InternalError;" 10620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationError: 10621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InstantiationError;" 10622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNegativeArraySizeException: 10623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNoSuchMethodError: 10625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNullPointerException: 10627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NullPointerException;" 10628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrLogTag: 10630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "mterp" 10631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrExceptionNotCaughtLocally: 10632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNewline: 10635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "\n" 10636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrSqueak: 10637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%d>" 10638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintHex: 10639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<0x%x>" 10640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintLong: 10641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%lld>" 10642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10643