InterpAsm-armv5te-vfp.S revision 9797a237b48e880c33e2a2f497f48fb6f67c7a16
1a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 2a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * --> DO NOT EDIT <-- 5a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/header.S */ 8a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 10a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 11a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 13a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 14a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 15a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 17a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 18a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 21a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 22a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 23a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 24a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ARMv5 definitions and declarations. 25a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 26a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 27a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 28a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenARM EABI general notes: 29a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 30a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 31a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr4-r8 are available for general use 32a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr9 is given special treatment in some situations, but not for us 33a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr10 (sl) seems to be generally available 34a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 35a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr12 (ip) is scratch -- not preserved across method calls 36a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr13 (sp) should be managed carefully in case a signal arrives 37a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr14 (lr) must be preserved 38a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr15 (pc) can be tinkered with directly 39a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 40a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0 holds returns of <= 4 bytes 41a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 42a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 43a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 44a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 45a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 46a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 47a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 48a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 49a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden(i.e. the 5th arg). 50a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 51a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenVFP: single-precision results in s0, double-precision results in d0. 52a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 53a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 54a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 55a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 56a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 57a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 58a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMterp and ARM notes: 59a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 60a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenThe following registers have fixed assignments: 61a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 62a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden reg nick purpose 63a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r4 rPC interpreted program counter, used for fetching instructions 64a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 65a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden r6 rGLUE MterpGlue pointer 661da12167d913efde56ec3b40491524b051679f2cAndy McFadden r7 rINST first 16-bit code unit of current instruction 671da12167d913efde56ec3b40491524b051679f2cAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 68a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 69a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenMacros are provided for common operations. Each macro MUST emit only 70a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 71a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenunspecified registers or condition codes. 72a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden*/ 73a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 74a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* single-purpose registers, given names for clarity */ 75a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rPC r4 76a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rFP r5 77a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define rGLUE r6 781da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rINST r7 791da12167d913efde56ec3b40491524b051679f2cAndy McFadden#define rIBASE r8 80a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 81a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* save/restore the PC and/or FP from the glue struct */ 82a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 83a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 84a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 85a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 86a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 87a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 88a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 89a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 90a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 91a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be done *before* something calls dvmThrowException. 92a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 93a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 94a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 95a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 96a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * It's okay to do this more than once. 97a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 98a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define EXPORT_PC() \ 99a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Given a frame pointer, find the stack save area. 103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_INST() ldrh rINST, [rPC] 113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from the specified offset. Advances rPC 116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Because of the limited size of immediate constants on ARM, this is only 119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with this). 121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This must come AFTER anything that can throw an exception, or the 123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception catch may miss. (This also implies that it must come after 124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * EXPORT_PC().) 125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * here. 144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch a half-word code unit from an offset past the current PC. The 149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The "_S" variant works the same but treats the value as signed. 152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * byte of the halfword you want (lo/hi). 160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the instruction's opcode field into the specified register. 165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Put the prefetched instruction's opcode field into the specified register. 170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Get/set the 32-bit value from a Dalvik register. 183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 189d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 190ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert a virtual register index into an address. 194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add _reg, rFP, _vreg, lsl #2 197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is a #include, not a %include, because we want the C pre-processor 200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to expand the macros into assembler assignment statements. 201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#include "../common/asm-constants.h" 203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/platform.S */ 206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * CPU-version-specific defines 209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * one-way branch. 215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP. Does not modify LR. 217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC source 219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Jump to subroutine. 225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDR_PC_LR source 229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov lr, pc 230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, \source 231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * May modify IP and LR. 237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.macro LDMFD_PC regs 239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {\regs,pc} 240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.endm 241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/entry.S */ 244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Copyright (C) 2008 The Android Open Source Project 246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * you may not use this file except in compliance with the License. 249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * You may obtain a copy of the License at 250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * http://www.apache.org/licenses/LICENSE-2.0 252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unless required by applicable law or agreed to in writing, software 254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See the License for the specific language governing permissions and 257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * limitations under the License. 258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Interpreter entry point. 261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't have formal stack frames, so gdb scans upward in the code 265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to find the start of the function (a label with the %function type), 266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and then looks at the next few instructions to figure out what 267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * got pushed onto the stack. From this it figures out how to restore 268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the registers, including PC, for the previous stack frame. If gdb 269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sees a non-function label, it stops scanning, so either we need to 270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have nothing but assembler-local labels between the entry point and 271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * the break, or we need to fake it out. 272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * When this is defined, we add some stuff to make gdb less confused. 274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define ASSIST_DEBUGGER 1 276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdRun 280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdRun, %function 281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This function returns a boolean "changeInterp" value. The return comes 287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * via a call to dvmMterpStdBail(). 288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdRun: 290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY1 \ 291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .save {r4-r10,fp,lr}; \ 292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#define MTERP_ENTRY2 \ 294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .pad #4; \ 295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align 64 296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* save stack pointer, add magic word for debuggerd */ 302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up "named" registers, figure out entry point */ 305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rGLUE, r0 @ set rGLUE 306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offGlue_entryPoint] @ InterpEntry enum is char 307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryInstr @ usual case? 310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .Lnot_instr @ no, handle it 311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 312ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 313ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lno_singleStep: 314ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng /* Entry is always a possible trace start */ 315ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 316ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 317ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 318ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 319ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 320ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 321ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* start executing the instruction at rPC */ 323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 326ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_instr: 329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_returnFromMethod 331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lnot_return: 333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown 335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 336ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 337ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.Lnot_throw: 338ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr r0,[rGLUE, #offGlue_jitResume] 339ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr r2,[rGLUE, #offGlue_jitResumePC] 340ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 341ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lbad_arg 342ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp rPC,r2 343ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne .Lno_singleStep @ must have branched, don't resume 344ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1, #kInterpEntryInstr 345ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng strb r1, [rGLUE, #offGlue_entryPoint] 346ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr rINST, .LdvmCompilerTemplate 347ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bx r0 @ re-enter the translation 348ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.LdvmCompilerTemplate: 349ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .word dvmCompilerTemplateStart 350ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 351ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lbad_arg: 353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strBadEntryPoint 354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r1 holds value of entryPoint 355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAbort 357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmMterpStdBail 361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmMterpStdBail, %function 362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Restore the stack pointer and PC from the save point established on entry. 365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * LR to PC. 371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 MterpGlue* glue 374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 bool changeInterp 375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmMterpStdBail: 377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ return the changeInterp value 379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 @ un-align 64 380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references. 385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrBadEntryPoint: 387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrBadEntryPoint 388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionStart 392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmInstructionStart, %function 393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionStart = .L_OP_NOP 394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOP: /* 0x00 */ 399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOP.S */ 400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_inst, %function 407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_inst: 408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE: /* 0x01 */ 418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_16: /* 0x03 */ 449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE.S */ 465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide vA, vB */ 466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/from16 vAA, vBBBB */ 484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- BBBB 486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-wide/16 vAAAA, vBBBB */ 501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- BBBB 503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- AAAA 504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 507445194bc141dc67e2f678aa1bbd5e59ca66254e5Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/from16, move-object/from16 */ 537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBBBB */ 538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_16.S */ 553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move/16, move-object/16 */ 554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAAAA, vBBBB */ 555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB 556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- AAAA 557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-result-wide vAA */ 584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for: move-result, move-result-object */ 600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* move-exception vAA */ 615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ r1<- 0 619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN: /* 0x0f */ 636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 64-bit value. Copies the return value into the "glue" 656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* return-wide vAA */ 659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RETURN.S */ 672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return a 32-bit value. Copies the return value into the "glue" 674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * structure, then jumps to the return handler. 675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: return, return-object 677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA */ 679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vAA 681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_returnFromMethod 683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_4: /* 0x12 */ 689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_4.S */ 690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/4 vA, #+B */ 691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_16: /* 0x13 */ 704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_16.S */ 705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/16 vAA, #+BBBB */ 706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST: /* 0x14 */ 717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST.S */ 718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const vAA, #+BBBBbbbb */ 719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/high16 vAA, #+BBBB0000 */ 734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/16 vAA, #+BBBB */ 748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #0 @ r0<- 00000000 802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING: /* 0x1a */ 813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING.S */ 814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBB */ 815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_resolve 822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/string vAA, String@BBBBBBBB */ 832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* const/class vAA, Class@BBBB */ 851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ not yet resolved? 857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CONST_CLASS_resolve 858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Synchronize on an object. 869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-enter vAA */ 871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null object, throw an exception 877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLockObject @ call(self, obj) 879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ exception raised, bail out 884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlock an object. 895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exceptions that occur when unlocking a monitor need to appear as 897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if they happened at the following instruction. See the Dalvik 898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction spec. 899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* monitor-exit vAA */ 901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ before fetch: export the PC 903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes 906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, exception is pending 910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if a cast from one class to another is allowed. 921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* check-cast vAA, class@BBBB */ 923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r3) @ r9<- object 926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ is object null? 928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolved: 935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_okay: 938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Check to see if an object reference is an instance of a class. 948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Most common situation is a non-null object, being compared against 950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an already-resolved class. 951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* instance-of vA, vB, class@CCCC */ 953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- CCCC 961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ have we resolved this before? 965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r1 @ same class (trivial success)? 968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ARRAY_LENGTH.S */ 975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return the length of an array. 977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is object null? 983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yup, fail 984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r3, r2) @ vB<- length 988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new instance of a class. 997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-instance vAA, class@BBBB */ 999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocObject @ r0<- new object 1013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Allocate an array of objects, specified with the array class 1021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and a count. 1022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The verifier guarantees that this is an array class, so we don't 1024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * check for it here. 1025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* new-array vA, vB, class@CCCC */ 1027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 1028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- CCCC 1029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ check length 1033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_errNegativeArraySize @ negative length, bail 1035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ req'd for resolve, alloc 1037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Create a new array with elements filled from registers. 1074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: filled-new-array, filled-new-array/range 1076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 1081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for resolve and alloc 1083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 1086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 1089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 1092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 1093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC(); 1108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ 0 means an exception is thrown 1110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ has exception 1111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW: /* 0x27 */ 1118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW.S */ 1119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception object in the current thread. 1121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* throw vAA */ 1123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 1126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null object? 1127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, throw an NPE instead 1128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ bypass dvmSetException, just store it 1129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 1131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO: /* 0x28 */ 1136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO.S */ 1137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 8-bit offset. 1139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto +AA */ 1144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1148ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1149ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1151ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1152ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1155ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1156ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1157ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1158ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1159ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_16: /* 0x29 */ 1164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_16.S */ 1165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 16-bit offset. 1167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/16 +AAAA */ 1172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1175ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1176ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1177ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1181ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1182ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1186ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_GOTO_32: /* 0x2a */ 1192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_GOTO_32.S */ 1193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unconditional branch, 32-bit offset. 1195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The branch distance is a signed code-unit offset, which we need to 1197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * double to get a byte offset. 1198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction doesn't affect the V flag, so we need to clear it 1202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * explicitly. 1203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* goto/32 +AAAAAAAA */ 1205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, ip @ (clear V flag during stall) 1208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1211ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1212ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1214ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1215ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1218ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1219ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1220ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1221ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1222ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1248ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1249ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1250ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1251ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1252ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1253ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1254ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1255ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1259ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * we decode it and hand it off to a helper function. 1270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We don't really expect backward branches in a switch statement, but 1272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * they're perfectly legal, so we check for them here. 1273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: packed-switch, sparse-switch 1275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, +BBBB */ 1277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vAA 1282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1287ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1288ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1290ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1291ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1294ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1295ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1296ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1297ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1298ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1305968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13248fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13278fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13298fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13388fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1344968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 13638fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 13668fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13688fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden flds s0, [r2] @ s0<- vBB 1369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s1, [r3] @ s1<- vCC 1370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 13778fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1383968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14028fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14058fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14078fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, #0 @ r0<- -1 (default) 1412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movgt r0, #1 @ (greater than) r1<- 1 1415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14168fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1422968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * destination register based on the results of the comparison. 1426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int compare(x, y) { 1428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * if (x == y) { 1429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 0; 1430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x < y) { 1431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return -1; 1432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else if (x > y) { 1433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } else { 1435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * return 1; 1436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * } 1438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 1440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 14418fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 14448fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14468fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden fldd d0, [r2] @ d0<- vBB 1447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d1, [r3] @ d1<- vCC 1448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ r0<- 1 (default) 1451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmstat @ export status flags 1453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r0, #0 @ (equal) r1<- 0 14558fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * register based on the results of the comparison. 1465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We load the full values with LDM, but in practice many values could 1467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be resolved by only looking at the high word. This could be made 1468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If we just wanted to set condition flags, we could do this: 1471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subs ip, r0, r2 1472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sbcs ip, r1, r3 1473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * subeqs ip, r0, r2 1474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * us a constant 5-cycle path plus a branch at the end to the 1478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instruction epilogue code. The multi-compare approach below needs 1479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * in the worst case (the 64-bit values are equal). 1481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* cmp-long vAA, vBB, vCC */ 1483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 1484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 1486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 1487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt .LOP_CMP_LONG_greater 1494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CMP_LONG_less 1497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQ: /* 0x32 */ 1502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQ.S */ 1503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1523ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1524ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1525ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1526ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1527ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1528ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1529ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1532ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NE: /* 0x33 */ 1539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NE.S */ 1540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1560ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1561ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1562ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1564ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1565ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1566ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LT: /* 0x34 */ 1576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LT.S */ 1577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1597ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1598ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1599ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1600ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1601ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1602ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1603ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1606ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GE: /* 0x35 */ 1613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GE.S */ 1614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1634ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1635ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1636ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1637ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1638ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1639ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1640ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1643ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GT: /* 0x36 */ 1650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GT.S */ 1651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1671ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1672ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1673ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1674ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1675ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1676ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1677ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1680ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LE: /* 0x37 */ 1687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LE.S */ 1688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/bincmp.S */ 1689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vA, vB, +CCCC */ 1697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A+ 1698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 1699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 1700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r1) @ r3<- vB 1701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vA 1702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (vA, vB) 1704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ yes, do periodic checks 1708ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1709ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1710ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1711ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1712ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_testUpdateProfile 1713ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1714ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1717ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ branch to 1 if comparison failed 1739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1742ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1743ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1744ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1745ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1746ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1747ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1750ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1751ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1752ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1753ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1754ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ branch to 1 if comparison failed 1776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1779ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1780ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1781ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1782ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1783ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1784ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1787ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1788ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1789ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1790ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1791ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bge 1f @ branch to 1 if comparison failed 1813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1816ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1817ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1818ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1819ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1820ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1821ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1824ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1825ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1826ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1827ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1828ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt 1f @ branch to 1 if comparison failed 1850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1853ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1854ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1855ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1856ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1857ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1858ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1859ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1860ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1861ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1862ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1865ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ble 1f @ branch to 1 if comparison failed 1887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1890ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1891ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1892ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1893ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1894ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1895ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1896ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1897ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1898ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1899ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1902ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/zcmp.S */ 1911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 1912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for "if-le" you would use "gt". 1915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 1916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 1918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* if-cmp vAA, +BBBB */ 1919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vAA 1921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ compare (vA, 0) 1923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bgt 1f @ branch to 1 if comparison failed 1924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1927ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng1: 1928ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 1929ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 1930ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1931ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 1932ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 1933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1935ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 1936ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1937ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 1938ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 1939ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 1940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 1993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 1994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 1997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 1998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 1999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET: /* 0x44 */ 2000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aget-wide vAA, vBB, vCC */ 2038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AGET.S */ 2192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r9) @ vAA<- r2 2216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT: /* 0x4b */ 2223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* aput-wide vAA, vBB, vCC */ 2261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ May want to swap the order of these two branches depending on how the 2276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ unconditional forward branches. 2278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 2291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 2293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 2294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null array object? 2297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r9) @ r9<- vAA 2298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, r3 @ compare unsigned index, length 2302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errArrayIndex @ index >= length, bail 2304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_APUT.S */ 2410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * instructions. We use a pair of FETCH_Bs instead. 2415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, vBB, vCC */ 2419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null array object? 2425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, bail 2426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, r3 @ compare unsigned index, length 2429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs common_errArrayIndex @ index >= length, bail 2430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r9) @ r2<- vAA 2432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET: /* 0x52 */ 2441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish @ no, already resolved 2456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_finish 2462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 2468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Wide 32-bit instance field get. 2470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide vA, vB, field@CCCC */ 2472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_WIDE_finish 2486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_OBJECT_finish 2513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BOOLEAN_finish 2542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_BYTE_finish 2571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_CHAR_finish 2600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET.S */ 2609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field get. 2611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 2628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IGET_SHORT_finish 2629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT: /* 0x59 */ 2635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ no, already resolved 2650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_finish @ yes, finish up 2656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 2662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide vA, vB, field@CCCC */ 2663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT.S */ 2800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit instance field put. 2802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, field@CCCC */ 2806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 2807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 2816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 2819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 2821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET: /* 0x60 */ 2826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_finish: @ field ptr in r0 2840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SGET handler. 2853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sget-wide vAA, field@BBBB */ 2855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_finish: 2862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 2863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offStaticField_value] @ r2/r3<- field value (aligned) 2864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[AA] 2865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r1, {r2-r3} @ vAA/vAA+1<- r2/r3 2867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 2975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 2976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SGET.S */ 2979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 2980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SGET handler. 2981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 2982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 2984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 2985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 2990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 2999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT: /* 0x67 */ 3003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 3016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_finish: @ field ptr in r0 3017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 64-bit SPUT handler. 3030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* sput-wide vAA, field@BBBB */ 3032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r0, AA in r9 3041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 3043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offStaticField_value] @ field<- vAA/vAA+1 3045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve 3064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_OBJECT_finish: @ field ptr in r0 3065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SPUT.S */ 3156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * General 32-bit SPUT handler. 3158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, field@BBBB */ 3162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is resolved entry null? 3167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_finish: 3265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue on 3267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ yes, continue on 3287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodNoRange @ no, continue 3293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 3310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_invokeMethodNoRange @ jump to common handler 3323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a virtual method call. 3341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-virtual, invoke-virtual/range 3343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a "super" method call. 3373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-super, invoke-super/range 3375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this"? 3388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 3390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a direct method call. 3404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (We could defer the "is 'this' pointer null" test to the common 3406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * method invocation code, and use a flag to indicate that static 3407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * calls don't count. If we do this as part of copying the arguments 3408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out we could avoiding loading the first arg twice.) 3409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-direct, invoke-direct/range 3411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ null "this" ref? 3428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue on 3429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNullObject @ yes, throw exception 3430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a static method call. 3439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-static, invoke-static/range 3441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ already resolved? 3449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ yes, continue on 3451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_STATIC @ resolver method type 3454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 3456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_invokeMethodRange @ no, continue 3457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 3458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an interface method call. 3468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: invoke-interface, invoke-interface/range 3470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 3475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 3476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 3478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 3479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null obj? 3482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ yes, fail 3484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 3487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 3488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_invokeMethodRange @ jump to common handler 3489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 3506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 3507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_INT: /* 0x7b */ 3513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_INT.S */ 3514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_INT: /* 0x7c */ 3540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_INT.S */ 3541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_LONG.S */ 3568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NOT_LONG.S */ 3597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r0, r0 @ optional op; may set condition codes 3614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_FLOAT.S */ 3626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 3630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 3634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 3645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 3647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_NEG_DOUBLE.S */ 3653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_LONG.S */ 3682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3708968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3709968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 371838214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitos s1, s0 @ s1<- op 3724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3733968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3734968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 374338214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsitod d0, s0 @ d0<- op 3749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MOVE.S */ 3761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* for move, move-object, long-to-int */ 3762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB */ 3763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 3768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute next instruction 3771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopNarrower.S */ 3779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 32-bit quantity in r0. 3783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: long-to-float, double-to-int, double-to-float 3785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (This would work for long-to-int, but that instruction is actually 3787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an exact match for OP_MOVE.) 3788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 3800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3836968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3837968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funop.S */ 3838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * line that specifies an instruction that performs "s1 = op s0". 3841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: int-to-float, float-to-int 3843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 384638214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizs s1, s0 @ s1<- op 3852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s1, [r9] @ vA<- s1 3855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWider.S */ 3864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = op r0", where 3867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "result" is a 64-bit quantity in r0/r1. 3868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 3876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-11 instructions */ 3884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3890968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3891968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopWider.S */ 3892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: int-to-double, float-to-double 3897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 390038214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r3] @ s0<- vB 3903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtds d0, s0 @ d0<- op 3906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d0, [r9] @ vA<- d0 3909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3915968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3916968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 392538214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ftosizd s0, d0 @ s0<- op 3931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unopWide.S */ 3943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0/r1". 3946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 3947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 3953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 3954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 3959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-13 instructions */ 3964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3971968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3972968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 3977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: double-to-int, double-to-float 3978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 3979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 3980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 398138214bbeeb2980609919978f17b009d896023491Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r3] @ d0<- vB 3984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 3986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fcvtsd s0, d0 @ s0<- op 3987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s0, [r9] @ vA<- s0 3990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 3993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 3994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 3995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_BYTE.S */ 3997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 3998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 3999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #24 @ optional op; may set condition codes 4012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 4014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 4023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_CHAR.S */ 4024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 4041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INT_TO_SHORT.S */ 4051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unop.S */ 4052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = op r0". 4055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. 4056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * int-to-byte, int-to-char, int-to-short 4059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* unop vA, vB */ 4061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 4062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 4063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB 4064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 4065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl #16 @ optional op; may set condition codes 4066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9-10 instructions */ 4072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT: /* 0x90 */ 4077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT.S */ 4078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT: /* 0x91 */ 4119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT.S */ 4120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT: /* 0x92 */ 4161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT.S */ 4162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT: /* 0x93 */ 4204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT.S */ 4205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT: /* 0x94 */ 4246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT.S */ 4247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 4281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT: /* 0x95 */ 4289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT.S */ 4290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT: /* 0x96 */ 4331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT.S */ 4332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT: /* 0x97 */ 4373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT.S */ 4374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT: /* 0x98 */ 4415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT.S */ 4416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT: /* 0x99 */ 4457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT.S */ 4458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT: /* 0x9a */ 4499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT.S */ 4500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 4501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 4504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 4511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 4515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 4522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 4523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 4525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 4530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 4533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 4535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply. 4634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * WX 4637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * x YZ 4638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * -------- 4639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * ZW ZX 4640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * YW YX 4641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The low word of the result holds ZX, the high word holds 4643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * it doesn't fit in the low 64 bits. 4645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Unlike most ARM math operations, multiply instructions have 4647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * restrictions on using the same register more than once (Rd and Rm 4648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * cannot be the same). 4649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long vAA, vBB, vCC */ 4651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 4659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_MUL_LONG_finish 4666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG: /* 0x9f */ 4715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG.S */ 4716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 4744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 4750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG.S */ 4762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 4795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG.S */ 4807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 4853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 4857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 4858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 4861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 4865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 4869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 4872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 4879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 4881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 4882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 4890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long vAA, vBB, vCC */ 4904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_finish 4921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long vAA, vBB, vCC */ 4933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_finish 4950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift. This is different from the generic 32/64-bit 4957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6 bits of the shift distance. 4960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long vAA, vBB, vCC */ 4962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r0, #255 @ r3<- BB 4965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr #8 @ r0<- CC 4966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r0) @ r2<- vCC 4968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_finish 4979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 4980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 4981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 4982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4983968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4984968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 4985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 4986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 4990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 4991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 4992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 4993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 4994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 4996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 499738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 499938214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 5004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 5013968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 5014968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 502738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 502938214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 5034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 5043968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5044968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 505738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 505938214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 5064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5073968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5074968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop.S */ 5075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float, sub-float, mul-float, div-float 5081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* floatop vAA, vBB, vCC */ 5083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 508738214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 508938214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vCC 5090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r2] @ s0<- vBB 5091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 5094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 5097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop.S */ 5106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0 op r1". 5109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * handles it correctly. 5116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mul-float, div-float, rem-float 5120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vCC 5127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 5128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 5136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 11-14 instructions */ 5140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5146968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5147968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 516038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 516238214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ s2<- op 5167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5176968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5177968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 519038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 519238214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ s2<- op 5197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5206968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5207968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 522038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 522238214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ s2<- op 5227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5236968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5237968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit double-precision floating point binary operation. 5240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Provide an "instr" line that specifies an instruction that performs 5241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 5242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-double, sub-double, mul-double, div-double 5244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* doubleop vAA, vBB, vCC */ 5246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 525038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 525238214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vCC 5253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r2] @ d0<- vBB 5254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ s2<- op 5257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 5260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide.S */ 5269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double 5281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop vAA, vBB, vCC */ 5285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r0, 1) @ r0<- CCBB 5286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r0, #255 @ r2<- BB 5288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r0, lsr #8 @ r3<- CC 5289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 5302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 14-17 instructions */ 5306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_2ADDR.S */ 5474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 5506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_2ADDR.S */ 5515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_2ADDR.S */ 5555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 5716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 5719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 5733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 5735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 5738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 5743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 5746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 5748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * See OP_MUL_LONG for an explanation. 5843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * again we stuff it into rINST. 5846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* mul-long/2addr vA, vB */ 5848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul ip, r2, r1 @ ip<- ZxW 5856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_LONG_2ADDR.S */ 5912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 5937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 5943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_LONG_2ADDR.S */ 5955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 5960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 5961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 5964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 5965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 5969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 5970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 5971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 5972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 5973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 5974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 5979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 5981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 5982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r2 @ optional op; may set condition codes 5985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 5990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 5993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 5994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 5995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_LONG_2ADDR.S */ 5997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 5998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 5999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r2 @ optional op; may set condition codes 6027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 6028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 6038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 6039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 6081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shl-long/2addr vA, vB */ 6086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHL_LONG_2ADDR_finish 6102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* shr-long/2addr vA, vB */ 6112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_SHR_LONG_2ADDR_finish 6128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 32-bit shift distance. 6136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* ushr-long/2addr vA, vB */ 6138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vB 6142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_USHR_LONG_2ADDR_finish 6154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6158968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6159968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 617038214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 617238214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fadds s2, s0, s1 @ s2<- op 6178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6186968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6187968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 619838214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 620038214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubs s2, s0, s1 @ s2<- op 6206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6214968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6215968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 622638214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 622838214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuls s2, s0, s1 @ s2<- op 6234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6242968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6243968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "s2 = s0 op s1". 6248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 625438214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 625638214bbeeb2980609919978f17b009d896023491Andy McFadden flds s1, [r3] @ s1<- vB 6257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden flds s0, [r9] @ s0<- vA 6260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivs s2, s0, s1 @ s2<- op 6262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsts s2, [r9] @ vAA<- s2 6264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binop2addr.S */ 6273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r3) @ r1<- vB 6292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmodf @ r0<- op, r0-r3 changed 6301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6311968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6312968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 632438214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 632638214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden faddd d2, d0, d1 @ d2<- op 6332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6340968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6341968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 635338214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 635538214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fsubd d2, d0, d1 @ d2<- op 6361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6369968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6370968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 638238214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 638438214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fmuld d2, d0, d1 @ d2<- op 6390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6398968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6399968d32c2b6160c19c2308793dca6d747cbfea8feAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * an "instr" line that specifies an instruction that performs 6403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * "d2 = d0 op d1". 6404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * div-double/2addr 6407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 6410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 641138214bbeeb2980609919978f17b009d896023491Andy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 @ r9<- A 641338214bbeeb2980609919978f17b009d896023491Andy McFadden fldd d1, [r3] @ d1<- vB 6414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fldd d0, [r9] @ d0<- vA 6417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fdivd d2, d0, d1 @ d2<- op 6419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden fstd d2, [r9] @ vAA<- d2 6421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopWide2addr.S */ 6430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-double/2addr 6443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/2addr vA, vB */ 6445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 6447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl fmod @ result<- op, r0-r3 changed 6460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 12-15 instructions */ 6464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT16.S */ 6471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT.S */ 6508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT16.S */ 6546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT16.S */ 6584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT16.S */ 6621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT16.S */ 6659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT16.S */ 6696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT16.S */ 6733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit16.S */ 6734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 6749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vB 6751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r9, r9, #15 6752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is second operand zero? 6754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-13 instructions */ 6763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 6949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 6958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 6964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 6965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 6968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 6969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 6971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 6972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 6973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 6976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 6977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 6981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 6985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 6986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 6988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 6989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 6990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 6991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 6993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 6994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 6997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 6999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 7005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 7006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 7033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 7034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 7044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 7045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ optional op; may set condition codes 7072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 7073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/binopLit8.S */ 7163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that specifies an instruction that performs "result = r0 op r1". 7166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This could be an ARM instruction or a function call. (If the result 7167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * comes back in a register other than r0, you can override "result".) 7168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * vCC (r1). Useful for integer division and modulus. 7171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r3, #255 @ r2<- BB 7180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- vBB 7181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @cmp r1, #0 @ is second operand zero? 7184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errDivideByZero 7185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #31 @ optional op; may set condition codes 7189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 10-12 instructions */ 7194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E3: /* 0xe3 */ 7200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E3.S */ 7201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E4: /* 0xe4 */ 7209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E4.S */ 7210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E5: /* 0xe5 */ 7218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E5.S */ 7219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E6: /* 0xe6 */ 7227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E6.S */ 7228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E7: /* 0xe7 */ 7236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E7.S */ 7237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E8: /* 0xe8 */ 7245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E8.S */ 7246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_E9: /* 0xe9 */ 7254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_E9.S */ 7255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_EA: /* 0xea */ 7263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_EA.S */ 7264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_EB: /* 0xeb */ 7272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_EB.S */ 7273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 728096516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 728196516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle a throw-verification-error instruction. This throws an 7293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception for an error discovered during verification. The 7294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op AA, ref@BBBB */ 7297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r2, 1) @ r2<- BBBB 7299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ export the PC 7300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowVerificationError @ always throws 7302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ handle exception 7303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Execute a "native inline" instruction. 7311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7312b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7313b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7315b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7316b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7317b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ can throw 7323b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #12 @ r0<- B 7325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [sp] @ push &glue->retval 7326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ pop stack 7328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ test boolean result of inline 7329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7336b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7337b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7338b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7339b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7340b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7341b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7342b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7343b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7344b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7345b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7346b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7347b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7348b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7349b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7350b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7351b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7352b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7353b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7354b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7355b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7356b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7357b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7358b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7359b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7360b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7361b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7362b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) 7416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iget-quick, iget-object-quick */ 7430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iput-quick, iput-object-quick */ 7451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rINST, lsr #8 @ r0<- A(+) 7472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #12 @ r1<- B 7473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r0, r0, #15 7474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ check object for null 7477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 1) @ r3<- field byte offset 7480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* For: iput-quick, iput-object-quick */ 7492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vA, vB, offset@CCCC */ 7493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #12 @ r2<- B 7494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- field byte offset 7496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ check object for null 7497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 7499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 7500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized virtual method call. 7540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is "this" null? 7552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 7553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ invoke must export 7556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) 7574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 7586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Handle an optimized "super" method call. 7595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) 7603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 1) @ r1<- BBBB 7606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 7608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r10) @ r3<- "this" 7610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ null "this" ref? 7612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ "this" is null, throw exception 7614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 7615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FC: /* 0xfc */ 7621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FC.S */ 7622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FD: /* 0xfd */ 7630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FD.S */ 7631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FE: /* 0xfe */ 7639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FE.S */ 7640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* ------------------------------ */ 7646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/unused.S */ 7650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort 7651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 64 7656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmInstructionEnd 7658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmInstructionEnd: 7659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 7661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Sister implementations 7663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 7664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterStart 7666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dvmAsmSisterStart, %function 7667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 7668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 4 7669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterStart: 7670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING */ 7672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (String ref) 7676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_resolve: 7679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the String has not yet been resolved. 7695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBBBBBB (String ref) 7696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveString @ r0<- String reference 7703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CONST_CLASS */ 7712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the Class has not yet been resolved. 7715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB (Class ref) 7716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: target register 7717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CONST_CLASS_resolve: 7719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 7720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- Class reference 7724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yup, handle the exception 7726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 7729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CHECK_CAST */ 7733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_fullcheck: 7741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ class of the object that failed to be cast. 7747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ about to throw 7748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .LstrClassCastExceptionPtr 7750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowExceptionWithClassMessage 7752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds BBBB 7758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 7759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CHECK_CAST_resolve: 7761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- BBBB 7764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastExceptionPtr: 7774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrClassCastException 7775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INSTANCE_OF */ 7778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test failed, need to perform full check. This is common. 7781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds obj->clazz 7782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds class resolved from BBBB 7783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_fullcheck: 7786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_INSTANCE_OF_store 7788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds boolean result 7791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_store: 7794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Trivial test succeeded, save and bail. 7801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_trivial: 7804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #1 @ indicate success 7805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vA<- r0 7808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r3 holds BBBB 7815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds A 7816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INSTANCE_OF_resolve: 7818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw 7819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r3 @ r1<- BBBB 7821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #1 @ r2<- true 7822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 @ r1<- class resolved from BBB 7827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #12 @ r3<- B 7828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_INSTANCE */ 7834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .balign 32 @ minimize cache lines 7836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r3) @ vAA<- r0 7843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Class initialization required. 7847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class object 7849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_needinit: 7851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r0 @ save r0 7852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmInitClass @ initialize class 7853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ check boolean result 7854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ restore r0 7855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ failed, deal with init exception 7857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolution required. This is the least-likely path. 7860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds BBBB 7862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_INSTANCE_resolve: 7864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 7871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationErrorPtr: 7873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInstantiationError 7874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_NEW_ARRAY */ 7877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Resolve class. (This is an uncommon case.) 7881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 7883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r2 holds class ref CCCC 7884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_resolve: 7886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ r9<- length (save) 7888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r2 @ r1<- CCCC 7889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #0 @ r2<- false 7890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 7892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 7893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ r1<- length (restore) 7894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle exception 7895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to OP_NEW_ARRAY_finish 7896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Finish allocation. 7899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 7900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds class 7901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 holds array length 7902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_NEW_ARRAY_finish: 7904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 7905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 7906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ failed? 7907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 7908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ yes, handle the exception 7909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 7911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ vA<- r0 7913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 7917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 7920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 7921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 7922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_continue: 7924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 7929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 7930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #'I' @ array of ints? 7933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'L' @ array of objects? 7934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'[' @ array of arrays? 7935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 7936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 7937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 7939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 7945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 7947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 7949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 7951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 7954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 7955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 7956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 7957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 7958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 7959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 7960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 7961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 7962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 7963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 7964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 7965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 7966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 7967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 7968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 7969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 7970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 7971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 7974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 7976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 7979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 7980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 7981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 7982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 7983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 7984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 7985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 7986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!0) @ define in one or the other, not both 7988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 7989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 7990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 7991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 7992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 7993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 7996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 7997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 7998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 7999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds array class 8000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 holds AA or BA 8001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 8003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 8006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- AA (length) 8008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #'I' @ array of ints? 8012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'L' @ array of objects? 8013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmpne r3, #'[' @ array of arrays? 8014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r1 @ save length in r9 8015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 8016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8017a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ null return? 8018a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8019a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8020a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8021a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8022a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8023a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ length--, check for neg 8024a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8025a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi 2f @ was zero, bail 8026a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8027a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ copy values from registers into the array 8028a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8029a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 1 8030a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8031a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8032a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8033a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8034a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8035a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8036a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .else 8037a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #4 @ length was initially 5? 8038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r10, #15 @ r2<- A 8039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f @ <= 4 args, branch 8040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vA 8041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r9, r9, #1 @ count-- 8042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0, #16] @ contents[4] = vA 8043a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r9, r9, #1 @ count-- 8047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r0], #4 @ *contents++ = vX 8048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bpl 1b 8049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ continue at 2 8050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: 8053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ execute it 8055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw an exception indicating that we have not implemented this 8058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * mode of filled-new-array. 8059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, .L_strInternalError 8062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 8064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 8065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if (!1) @ define in one or the other, not both 8067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strFilledNewArrayNotImpl: 8068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrFilledNewArrayNotImpl 8069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L_strInternalError: 8070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrInternalError 8071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 8072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_FLOAT */ 8075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_FLOAT_finish: 8076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_FLOAT */ 8081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_FLOAT_finish: 8082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPL_DOUBLE */ 8087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPL_DOUBLE_finish: 8088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMPG_DOUBLE */ 8093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMPG_DOUBLE_finish: 8094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r9) @ vAA<- r0 8095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_CMP_LONG */ 8099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_less: 8101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvn r1, #0 @ r1<- -1 8102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ instead, we just replicate the tail end. 8104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_greater: 8110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ r1<- 1 8111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ fall through to _finish 8112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_CMP_LONG_finish: 8114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r1, r9) @ vAA<- r1 8116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_AGET_WIDE */ 8121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_AGET_WIDE_finish: 8123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_WIDE */ 8132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_WIDE_finish: 8134a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8135a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8136a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8137a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8138a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8139a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8140a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8141a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_APUT_OBJECT */ 8142a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8143a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8144a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = vBB (arrayObj) 8145a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = vAA (obj) 8146a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = offset into array (vBB + vCC * width) 8147a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8148a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_finish: 8149a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ storing null reference? 8150a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8151a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8152a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8153a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8154a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ okay? 8155a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errArrayStore @ no 8156a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_APUT_OBJECT_skip_check: 8157a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8158a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8159a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8160a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8161a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8162a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8163a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET */ 8164a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8165a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8166a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8167a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8168a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8169a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8170a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_finish: 8171a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8172a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8173a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8174a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8175a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8176a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8177a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8178a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8179a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8180a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8181a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8182a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8183a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8184a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_WIDE */ 8185a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8186a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8187a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8188a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8189a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8190a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8191a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_WIDE_finish: 8192a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8193a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8194a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8195a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8196a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8197a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8198a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8199a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8200a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8201a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8202a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8203a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8204a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8205a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_OBJECT */ 8206a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8207a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8208a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8209a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8210a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8211a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8212a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_OBJECT_finish: 8213a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8214a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8215a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8216a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8217a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8218a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8219a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8220a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8221a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8222a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8223a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8224a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8225a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8226a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BOOLEAN */ 8227a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8228a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8229a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8230a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8231a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8232a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8233a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BOOLEAN_finish: 8234a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8235a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8236a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8237a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8238a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8239a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8240a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8241a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8242a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8243a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8244a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8245a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8246a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8247a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_BYTE */ 8248a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8249a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8250a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8251a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8252a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8253a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8254a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_BYTE_finish: 8255a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8256a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8257a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8258a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8259a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8260a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8261a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8262a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8263a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8264a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8265a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8266a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8267a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8268a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_CHAR */ 8269a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8270a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8271a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8272a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8273a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8274a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8275a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_CHAR_finish: 8276a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8277a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8278a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8279a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8280a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8281a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8282a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8283a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8284a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8285a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8286a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8287a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8288a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8289a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IGET_SHORT */ 8290a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8291a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8292a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8293a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8294a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8295a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8296a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IGET_SHORT_finish: 8297a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8298a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8299a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8300a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8301a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8302a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8303a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8304a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8305a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8306a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8307a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8308a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8309a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8310a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT */ 8311a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8312a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8313a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8314a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8315a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8316a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8317a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_finish: 8318a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8319a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8320a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8321a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8322a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8323a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8324a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8325a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8326a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8327a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8328a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8329a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8330a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8331a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_WIDE */ 8332a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8333a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_WIDE_finish: 8339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r2, r2, #15 @ r2<- A 8342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8343a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8344a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8345a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8346a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8347a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8348a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 8349a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8350a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_OBJECT */ 8353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8354a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_OBJECT_finish: 8360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak0 8361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8373a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8374a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8375a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BOOLEAN_finish: 8381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak1 8382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_BYTE */ 8395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_BYTE_finish: 8402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak2 8403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_CHAR */ 8416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_CHAR_finish: 8423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak3 8424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_IPUT_SHORT */ 8437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Currently: 8440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 holds resolved field 8441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 holds object 8442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_IPUT_SHORT_finish: 8444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_squeak4 8445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden and r1, r1, #15 @ r1<- A 8448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r9, #0 @ check object for null 8449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ object was null 8451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET */ 8458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_resolve: 8464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_finish @ yes, finish 8470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_WIDE */ 8474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_WIDE_resolve: 8480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_OBJECT */ 8490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_OBJECT_resolve: 8496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BOOLEAN */ 8506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BOOLEAN_resolve: 8512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_BYTE */ 8522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_BYTE_resolve: 8528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8530a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8531a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8532a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8533a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_CHAR */ 8538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_CHAR_resolve: 8544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SGET_SHORT */ 8554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SGET_SHORT_resolve: 8560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8562a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8563a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8568a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8569a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT */ 8570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8571a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8572a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8573a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8574a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8575a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_resolve: 8576a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8577a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_finish @ yes, finish 8582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8583a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8585a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_WIDE */ 8586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9: &fp[AA] 8591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_WIDE_resolve: 8593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_OBJECT */ 8603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_OBJECT_resolve: 8609a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8613a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_OBJECT_finish @ yes, finish 8615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8620a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8621a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BOOLEAN_resolve: 8625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_BYTE */ 8635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_BYTE_resolve: 8641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_CHAR */ 8651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_CHAR_resolve: 8657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SPUT_SHORT */ 8667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Continuation if the field has not yet been resolved. 8670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1: BBBB field ref 8671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SPUT_SHORT_resolve: 8673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ resolve() could throw, so export now 8675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ success? 8678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ no, handle exception 8680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8684a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8685a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8686a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8687a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8688a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8689a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_continue: 8690a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8691a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8692a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8693a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8694a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8695a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8700a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER */ 8701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_continue: 8708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodNoRange @ continue on 8717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_resolve: 8719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8723a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8724a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_nsm: 8731a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8732a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8733a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8734a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8735a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT */ 8736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_resolve: 8743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ is "this" null? 8764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_errNullObject @ null "this", throw exception 8765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * At this point: 8775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 = method->clazz 8777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ must export for invoke 8783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_invokeMethodRange @ continue on 8788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- method->clazz 8791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Throw a NoSuchMethodError with the method name as the message. 8799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = resolved base method 8800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_errNoSuchMethod 8804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 8810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 = reference (BBBB or CCCC) 8811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = "this" register 8812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ got null? 8819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown @ yes, handle exception 8822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the float in r0 to a long in r0/r1. 8827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenf2l_doconv: 8833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, lr} 8834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0x5f000000 @ (float)maxlong 8835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r4, r0 8836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0xdf000000 @ (float)minlong 8844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (80000000) 8847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmnefd sp!, {r4, pc} 8849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r4 8852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_fcmpeq @ is arg == self? 8853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmeqfd sp!, {r4, pc} 8856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_f2lz @ convert float to long 8859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, pc} 8860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 8864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We have to clip values to long min/max per the specification. The 8867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * expected common case is a "reasonable" value that converts directly 8868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddend2l_doconv: 8871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r4, r5, lr} @ save regs 88725162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 88735162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 88745162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #4 @ align for EABI 88765162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r5, r1 @ and r1 8878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 8879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 8881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mvnne r1, #0x80000000 8882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 8883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 88865162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 88875162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 88885162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 8889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmple @ is arg <= minlong? 8890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ nonzero == yes 8891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, #0 @ return minlong (8000000000000000) 8892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r1, #0x80000000 8893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1f 8894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 8897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r4 @ compare against self 8898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r5 8899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_dcmpeq @ is arg == self? 8900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ zero == no 8901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden moveq r1, #0 @ return zero for NaN 8902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f 8903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r4 @ recover arg 8905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r5 8906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __aeabi_d2lz @ convert double to long 8907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 8909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #4 8910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r4, r5, pc} 8911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_MUL_LONG */ 8914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_MUL_LONG_finish: 8916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 8918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG */ 8922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_finish: 8924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 8925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG */ 8931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_finish: 8933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 8934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG */ 8940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_finish: 8942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 8943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 8949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHL_LONG_2ADDR_finish: 8951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 8957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_SHR_LONG_2ADDR_finish: 8959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 8965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_USHR_LONG_2ADDR_finish: 8967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* continuation for OP_EXECUTE_INLINE */ 8973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 8974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 8975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Extract args, call function. 8976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 = #of args (0-4) 8977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r10 = call index 8978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 8979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 8980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Other ideas: 8981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Use a jump table from the main piece to jump directly into the 8982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 8983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * - Have five separate pieces that do the loading, so we can work the 8984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * interleave a little better. Increases code size. 8985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 8986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_continue: 8987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 8988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r9, 2) @ r9<- FEDC 8989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 8990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 8991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r9, #0xf000 @ isolate F 8992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 8993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r9, #0x0f00 @ isolate E 8994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 8995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r9, #0x00f0 @ isolate D 8996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 8997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r9, #0x000f @ isolate C 8998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 8999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: 9000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 9001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (not reached) 9003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LOP_EXECUTE_INLINE_table: 9005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word gDvmInlineOpsTable 9006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9008b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 9009b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9010b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 9011b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 9012b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 9013b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 9014b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9015b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 9016b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 9017b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9018b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 9019b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9020b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9021b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 9022b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 9023b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 9024b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 9025b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 9026b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 9027b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 9028b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 9029b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 9030b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 9031b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9032b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 9033b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9034b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 9035b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 9036b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9037b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9038a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 9039a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .global dvmAsmSisterEnd 9040a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendvmAsmSisterEnd: 9041a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9042a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* File: armv5te/footer.S */ 9043ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9044a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9045a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9046a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common subroutines and data 9047a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * =========================================================================== 9048a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9050ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9051ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .text 9053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 9054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9055ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 905697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 905797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 905897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 905997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 906097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 906197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 906297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 906397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 906497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 906597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 906697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 906797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToTraceSelect 906897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToTraceSelect: 90699a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 907097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 907197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 907297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 907397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToBackwardBranch 907497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToBackwardBranch: 90759a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 907697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 907797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 907897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 907997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 908097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 90819a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 908297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 908397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 908497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 908597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 908697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 908797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 908897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 908997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 909097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9091ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9092ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter when the compiler is 9093ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * having issues translating/executing a Dalvik instruction. We have to skip 9094ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the code cache lookup otherwise it is possible to indefinitely bouce 9095ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * between the interpreter and the code cache if the instruction that fails 9096ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * to be compiled happens to be at a trace start. 9097ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9098ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpPunt 9099ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpPunt: 9100ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r0 9101ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9102ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,lr 9103ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpPunt; 9104ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9105ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9106ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9107ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9108ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9109ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9110ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9111ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9112ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return to the interpreter to handle a single instruction. 9113ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * On entry: 9114ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r0 <= PC 9115ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * r1 <= PC of resume instruction 9116ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * lr <= resume point in translation 9117ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9118ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpSingleStep 9119ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpSingleStep: 9120ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str lr,[rGLUE,#offGlue_jitResume] 9121ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1,[rGLUE,#offGlue_jitResumePC] 9122ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#kInterpEntryInstr 9123ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ enum is 4 byte in aapcs-EABI 9124ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_entryPoint] 9125ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC,r0 9126ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9127ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9128ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitSingleStep @ Ask for single step and then revert 9129ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9130ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp to bail to debug interp 9131ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9132ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9133ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9134ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9135ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache and immediately request 9136ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a translation for the exit target. Commonly used following 9137ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * invokes. 9138ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9139ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToTraceSelect 9140ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToTraceSelect: 91419a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 91429a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9143ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9144ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 9145ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9146ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng beq 2f 9147ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9148ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 91499a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 91509a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 915146cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 915246cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 915346cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9154ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9155ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* No translation, so request one if profiling isn't disabled*/ 9156ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng2: 91571da12167d913efde56ec3b40491524b051679f2cAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9158ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9159ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9160ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0, #0 9161ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_selectTrace 9162ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9163ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9164ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9165ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9166ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter. 9167ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * The return was done with a BLX from thumb mode, and 9168ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the following 32-bit word contains the target rPC value. 9169ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Note that lr (r14) will have its low-order bit set to denote 9170ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * its thumb-mode origin. 9171ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 9172ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * We'll need to stash our lr origin away, recover the new 9173ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * target and then check to see if there is a translation available 9174ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * for our new target. If so, we do a translation chain and 9175ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * go back to native execution. Otherwise, it's back to the 9176ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * interpreter (after treating this entry as a potential 9177ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace start). 9178ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9179ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNormal 9180ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNormal: 91819a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 91829a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9183ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9184ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNormal 9185ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9186ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9187ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 9188ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 918946cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee beq toInterpreter @ go if not, otherwise do chain 9190ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,rINST 9191ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 91929a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 91939a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 919446cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee cmp r0,#0 @ successful chain? 919546cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee bxne r0 @ continue native execution 919646cd5b63c29d3284a9ff3e0d0711fb136f409313Bill Buzbee b toInterpreter @ didn't chain - resume with interpreter 9197ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9198ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9199ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Return from the translation cache to the interpreter to do method invocation. 9200ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Check if translation exists for the callee, but don't chain to it. 9201ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9202ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmJitToInterpNoChain 9203ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmJitToInterpNoChain: 9204ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#ifdef EXIT_STATS 9205ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmBumpNoChain 9206ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9207ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9208ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 92099a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 92109a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9211ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9212ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ continue native execution if so 921397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9214ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9215ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9216ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * No translation, restore interpreter regs and start interpreting. 9217ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * rGLUE & rFP were preserved in the translated code, and rPC has 9218ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * already been restored by the time we get here. We'll need to set 9219ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * up rIBASE & rINST, and load the address of the JitTable into r0. 9220ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 922146cd5b63c29d3284a9ff3e0d0711fb136f409313Bill BuzbeetoInterpreter: 9222ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9223ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng adrl rIBASE, dvmAsmInstructionStart 9224ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_INST() 9225ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9226ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng @ NOTE: intended fallthrough 9227ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9228ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Common code to update potential trace start counter, and initiate 9229ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * a trace-build if appropriate. On entry, rPC should point to the 9230ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * next instruction to execute, and rINST should be already loaded with 9231ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * the next opcode word, and r0 holds a pointer to the jit profile 9232ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * table (pJitProfTable). 9233ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9234ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_testUpdateProfile: 9235ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9236ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9237ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9238ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9239ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_updateProfile: 9240ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 92419797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee lsl r3,r3,#21 @ shift out excess 2047 92429797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee ldrb r1,[r0,r3,lsr #21] @ get counter 9243ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9244ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng subs r1,r1,#1 @ decrement counter 92459797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee strb r1,[r0,r3,lsr #21] @ and store it 9246ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9247ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9248ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng/* 9249ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Here, we switch to the debug interpreter to request 9250ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * trace selection. First, though, check to see if there 9251ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * is already a native translation in place (and, if so, 9252ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * jump to it now). 9253ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 9254d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 92559797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee strb r1,[r0,r3,lsr #21] @ reset counter 9256ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng EXPORT_PC() 9257ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0,rPC 9258ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 92599a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 92609a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9261ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 926297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9263ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxne r0 @ jump to the translation 926497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 92659a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 92669a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 92679a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 92689a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 92699a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 92709a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 92719a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r10, r0 @ save target 92729a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 92739a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee cmp r0, r10 @ special case? 92749a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bne dvmJitSelfVerificationStart @ set up self verification 92759a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 92769a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 92779a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 927897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 92799a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 9280ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Chengcommon_selectTrace: 9281ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitTSelectRequest @ ask for trace selection 9282ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 92839c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 92849c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9285ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r1,#1 @ set changeInterp 9286ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng b common_gotoBail 9287ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 928897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 928997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 929097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 929197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 92929a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * On entry, r10 contains the address of the target translation. 929397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 929497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationStart: 929597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 929697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 929797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 92989a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 929997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9300ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9301ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9302ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 930397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 930497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 930597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 930697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 930797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 930897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationEnd: 930997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 931097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9311ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9312ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9313ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9314ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 931597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 931697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 931797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 931897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 931930f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 932030f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 932197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 932297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 932397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 932497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 932597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 932697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 932797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 932897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 932997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 933097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 933197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9332ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9333ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9334a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9335a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code when a backward branch is taken. 9336a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9337a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9338a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is PC adjustment *in bytes* 9339a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9340a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_backwardBranch: 9341a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryInstr 9342a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9343ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9344ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9345ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9346ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9347ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9348ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) 9349ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) 9350ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9351a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9352a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9353a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9354ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9355a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9356a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9357a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9358a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9359a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * activity has begun. 9360a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9361a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: if JDWP isn't running, zero out pDebuggerActive pointer so we don't 9362a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * have to do the second ldr. 9363a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9364a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: reduce this so we're just checking a single location. 9365a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9366a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9367a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is reentry type, e.g. kInterpEntryInstr 9368a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is trampoline PC adjustment *in bytes* 9369a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9370a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_periodicChecks: 9371a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9372a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 93739c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng @ speculatively store r0 before it is clobbered by dvmCheckSuspendPending 93749c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r0, [rGLUE, #offGlue_entryPoint] 93759c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng 9376a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) 9377a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9378a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9379a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_PROFILER) 9380a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9381a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9382a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9383a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3] @ r3<- suspendCount (int) 9384a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9385a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) 9386a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r1] @ r1<- debuggerActive (boolean) 9387a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9388a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined (WITH_PROFILER) 9389a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9390a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9391a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9392a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, #0 @ suspend pending? 9393a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 2f @ yes, do full suspension check 9394a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9395a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9396a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# if defined(WITH_DEBUGGER) && defined(WITH_PROFILER) 9397a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden orrs r1, r1, r2 @ r1<- r1 | r2 9398a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ debugger attached or profiler started? 9399a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# elif defined(WITH_DEBUGGER) 9400a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ debugger attached? 9401a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# elif defined(WITH_PROFILER) 9402a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ profiler started? 9403a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden# endif 9404a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 3f @ debugger/profiler, switch interp 9405a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9406a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9407a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr @ nothing to do, return 9408a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9409a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: @ check suspend 9410a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9411a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() @ need for precise GC 9412a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmCheckSuspendPending @ suspend if necessary, then return 9413a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9414a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: @ debugger/profiler enabled, bail out 9415a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, rPC, r9 @ update rPC 9416a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #1 @ "want switch" = true 9417a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail 9418a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9419a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9420a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9421a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9422a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9423a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * State registers will be saved to the "glue" area before bailing. 9424a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9425a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9426a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9427a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * other interpreter or just bail all the way out 9428a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9429a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_gotoBail: 9430a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9431a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ r0<- glue ptr 9432a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9433a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9434a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r1, r1, #1 @ using (boolean+1) 9435a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9436a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl _longjmp @ does not return 9437a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @bl common_abort 9438a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9439a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9440a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9441a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation with range. 9442a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9443a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9444a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9445a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9446a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodRange: 9447a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewRange: 9448a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9449a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9450a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9451a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9452a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- CCCC 9453a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9454a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9455a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9456a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9457a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9458a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9459a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9460a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden subs r2, r2, #1 @ count-- 9461a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r10], #4 @ *outs++ = val 9462a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne 1b @ ...while count != 0 9463a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9464a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .LinvokeArgsDone 9465a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9466a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9467a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation without range. 9468a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9469a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9470a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9471a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9472a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_invokeMethodNoRange: 9473a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNewNoRange: 9474a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ prepare to copy args to "outs" area of current frame 9475a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9476a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9477a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9478a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9479a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9480a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq .LinvokeArgsDone 9481a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9482a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9483a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNonRange: 9484a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9485a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9486a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9487a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9488a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9489a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9490a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vA 9491a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden4: and ip, r1, #0xf000 @ isolate G 9492a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9493a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9494a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vG 9495a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden3: and ip, r1, #0x0f00 @ isolate F 9496a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9497a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9498a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vF 9499a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden2: and ip, r1, #0x00f0 @ isolate E 9500a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9501a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9502a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vE 9503a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: and ip, r1, #0x000f @ isolate D 9504a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 9505a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r0 @ nop 9506a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [r10, #-4]! @ *--outs = vD 9507a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden0: @ fall through to .LinvokeArgsDone 9508a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9509a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 9510a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 9511a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 9512a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ find space for the new stack frame, check for overflow 9513a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 9514a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 9515a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 9516a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden@ bl common_dumpRegs 9517a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 9518a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 9519a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r3, r9 @ bottom < interpStackEnd? 9520a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 9521a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blt .LstackOverflow @ yes, this frame will overflow stack 9522a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9523a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ set up newSaveArea 9524a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef EASY_GDB 9525a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 9526a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [r10, #offStackSaveArea_prevSave] 9527a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9528a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 9529a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 9530ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9531ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r9, #0 9532ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r9, [r10, #offStackSaveArea_returnAddr] 9533ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9534a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [r10, #offStackSaveArea_method] 9535a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden tst r3, #ACC_NATIVE 9536a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne .LinvokeNative 9537a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9538a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9539a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 9540a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 9541a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP 9542a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9543a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 9544a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 9545a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0-r3} 9546a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 9547a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 9548a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmDumpFp 9549a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_printNewline 9550a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0-r3} 9551a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9552a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9553a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 9554a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 9555a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r2 @ publish new rPC 9556a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 9557a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9558a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Update "glue" values for the new method 9559a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 9560a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 9561a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 9562ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9563ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9564a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r1 @ fp = newFp 9565a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9566a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rINST, r9 @ publish new rINST 9567a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9568ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9569ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9570a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9571ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9572ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rFP, r1 @ fp = newFp 9573ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9574ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rINST, r9 @ publish new rINST 9575ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9576ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 9577ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9578a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9579a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeNative: 9580a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ Prep for the native call 9581a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 9582a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9583d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 9584a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 9585d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 9586a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, r3 @ r9<- glue->self (preserve) 9587a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9588a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ r2<- methodToCall 9589a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r1 @ r0<- newFp (points to args) 9590a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 9591a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9592a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 9593a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* insert fake function header to help gdb find the stack frame */ 9594a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b .Lskip 9595a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .type dalvik_mterp, %function 9596a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddendalvik_mterp: 9597a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnstart 9598a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY1 9599a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden MTERP_ENTRY2 9600a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.Lskip: 9601a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9602a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9603a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @mov lr, pc @ set return addr 9604a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 9605a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 9606a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9607a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ native return; r9=self, r10=newSaveArea 9608a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ equivalent to dvmPopJniLocals 9609d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 9610a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 9611a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 9612a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ null? 9613d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 9614a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bne common_exceptionThrown @ no, handle exception 9615a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9616a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 9617a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9618a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9619a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 96206ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 96216ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 9622a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 9623a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmHandleStackOverflow 9624a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9625a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#ifdef ASSIST_DEBUGGER 9626a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .fnend 9627a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9628a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9629a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9630a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9631a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for method invocation, calling through "glue code". 9632a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9633a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * TODO: now that we have range and non-range invoke handlers, this 9634a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * needs to be split into two. Maybe just create entry points 9635a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * that set r9 and jump here? 9636a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9637a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On entry: 9638a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9639a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 9640a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9641a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9642a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LinvokeOld: 9643a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub sp, sp, #8 @ space for args + pad 9644a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 9645a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 @ A2<- methodToCall 9646a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ A0<- glue 9647a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9648a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r9 @ A1<- methodCallRange 9649a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, rINST, lsr #8 @ A3<- AA 9650a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #0] @ A4<- ip 9651a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 9652a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ remove arg area 9653a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall @ continue to next instruction 9654a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9655a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9656a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9657a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9658a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9659a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Common code for handling a return instruction. 9660a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9661a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 9662a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9663a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_returnFromMethod: 9664a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnNew: 9665a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryReturn 9666a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 9667a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9668a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9669a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 9670a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 9671a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 9672a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 9673a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ r2<- method we're returning to 9674a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9675a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r2, #0 @ is this a break frame? 9676a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 9677a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 9678a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq common_gotoBail @ break frame, bail out completely 9679a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9680a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 9681a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 9682a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 9683a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 9684ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9685ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng ldr r3, [r0, #offStackSaveArea_returnAddr] @ r3 = saveArea->returnAddr 9686ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_JIT_PROF_TABLE(r0) 9687ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov rPC, r9 @ publish new rPC 9688ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r1, [rGLUE, #offGlue_methodClassDex] 9689ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r3, #0 @ caller is compiled code 96902717622484eb0f7ad537275f7260b2f93324eda2Bill Buzbee blxne r3 9691ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 9692ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r0,#0 9693ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bne common_updateProfile 9694ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng GOTO_OPCODE(ip) @ jump to next instruction 9695ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#else 9696a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9697a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rPC, r9 @ publish new rPC 9698a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 9699a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9700ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9701a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9702a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9703a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Return handling, calls through "glue code". 9704a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9705a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9706a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LreturnOld: 9707a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9708a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 9709a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_returnFromMethod 9710a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 9711a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9712a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9713a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9714a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9715a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Somebody has thrown an exception. Handle it. 9716a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9717a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * If the exception processing code returns to us (instead of falling 9718a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * out of the interpreter), continue with whatever the next instruction 9719a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * now happens to be. 9720a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 9721a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * This does not return. 9722a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9723ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng .global dvmMterpCommonExceptionThrown 9724ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben ChengdvmMterpCommonExceptionThrown: 9725a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_exceptionThrown: 9726a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionNew: 9727a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #kInterpEntryThrow 9728a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r9, #0 9729a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl common_periodicChecks 9730a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9731ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#if defined(WITH_JIT) 9732ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r2,#kJitTSelectAbort @ abandon trace selection in progress 9733ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng str r2,[rGLUE,#offGlue_jitState] 9734ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng#endif 9735ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng 9736a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 9737a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 9738a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9739a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9740a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 9741a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- NULL 9742a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 9743a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9744a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* set up args and a local for "&fp" */ 9745a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 9746a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str rFP, [sp, #-4]! @ *--sp = fp 9747a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov ip, sp @ ip<- &fp 9748a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, #0 @ r3<- false 9749a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str ip, [sp, #-4]! @ *--sp = &fp 9750a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 9751a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 9752a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 9753a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r9 @ r2<- exception 9754a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 9755a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 9756a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9757a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 9758a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 9759a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9760a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 9761a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9762a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 9763a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden beq 1f @ no, skip ahead 9764a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov rFP, r0 @ save relPc result in rFP 9765a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r10 @ r0<- self 9766a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmCleanupStackOverflow @ call(self) 9767a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rFP @ restore result 9768a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden1: 9769a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9770a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 9771a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 9772a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r0, #0 @ is catchRelPc < 0? 9773a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add sp, sp, #8 @ restore stack 9774a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bmi .LnotCaughtLocally 9775a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9776a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* adjust locals to match self->curFrame and updated PC */ 9777a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 9778a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 9779a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 9780a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 9781a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 9782a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 9783a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 9784a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 9785a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9786a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* release the tracked alloc on the exception */ 9787a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9788a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9789a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9790a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9791a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* restore the exception if the handler wants it */ 9792a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 9793a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9794a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 9795a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 9796a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9797a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9798a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 9799a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* fix stack overflow if necessary */ 9800a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9801a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden cmp r1, #0 @ did we overflow earlier? 9802a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden movne r0, r10 @ if yes: r0<- self 9803a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 9804a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9805a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ may want to show "not caught locally" debug messages here 9806a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#if DVM_SHOW_EXCEPTION >= 2 9807a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* call __android_log_print(prio, tag, format, ...) */ 9808a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* "Exception %s from %s:%d not caught locally" */ 9809a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 9810a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 9811a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, [r0, #offMethod_insns] 9812a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden sub r1, rPC, r1 9813a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden asr r1, r1, #1 9814a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmLineNumFromPC 9815a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 9816a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ dvmGetMethodSourceFile(method) 9817a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, [rGLUE, #offGlue_method] 9818a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmGetMethodSourceFile 9819a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r0, [sp, #-4]! 9820a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ exception->clazz->descriptor 9821a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r9, #offObject_clazz] 9822a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r3, [r3, #offClassObject_descriptor] 9823a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden @ 9824a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r2, strExceptionNotCaughtLocally 9825a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strLogTag 9826a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, #3 @ LOG_DEBUG 9827a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl __android_log_print 9828a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden#endif 9829a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden str r9, [r10, #offThread_exception] @ restore exception 9830a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, r9 @ r0<- exception 9831a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r10 @ r1<- self 9832a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9833a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 @ "want switch" = false 9834a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_gotoBail @ bail out 9835a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9836a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9837a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9838a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Exception handling, calls through "glue code". 9839a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9840a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 9841a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LexceptionOld: 9842a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9843a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r0, rGLUE @ arg to function 9844a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterp_exceptionThrown 9845a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_resumeAfterGlueCall 9846a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 9847a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9848a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9849a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9850a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * After returning from a "glued" function, pull out the updated 9851a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * values and start executing at the next instruction. 9852a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9853a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_resumeAfterGlueCall: 9854a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 9855a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden FETCH_INST() @ load rINST from rPC 9856a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9857a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9858a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9859a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9860a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array index. 9861a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9862a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayIndex: 9863a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9864a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayIndexException 9865a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9866a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9867a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9868a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9869a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9870a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invalid array value. 9871a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9872a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errArrayStore: 9873a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9874a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArrayStoreException 9875a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9876a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9877a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9878a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9879a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9880a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Integer divide or mod by zero. 9881a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9882a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errDivideByZero: 9883a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9884a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strArithmeticException 9885a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r1, strDivideByZero 9886a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9887a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9888a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9889a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9890a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Attempt to allocate an array with a negative size. 9891a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9892a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNegativeArraySize: 9893a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9894a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNegativeArraySizeException 9895a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9896a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9897a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9898a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9899a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9900a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Invocation of a non-existent method. 9901a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9902a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNoSuchMethod: 9903a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9904a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNoSuchMethodError 9905a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9906a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9907a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9908a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9909a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9910a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * We encountered a null object when we weren't expecting one. We 9911a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * export the PC, throw a NullPointerException, and goto the exception 9912a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * processing code. 9913a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9914a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_errNullObject: 9915a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden EXPORT_PC() 9916a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNullPointerException 9917a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #0 9918a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmThrowException 9919a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden b common_exceptionThrown 9920a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9921a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9922a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * For debugging, cause an immediate fault. The source address will 9923a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * be in lr (use a bl instruction to jump here). 9924a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9925a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_abort: 9926a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr pc, .LdeadFood 9927a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LdeadFood: 9928a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word 0xdeadf00d 9929a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9930a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9931a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out a "we were here", preserving all registers. (The attempt 9932a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * to save ip won't work, but we need to save an even number of 9933a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * registers for EABI 64-bit stack alignment.) 9934a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9935a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .macro SQUEAK num 9936a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_squeak\num: 9937a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9938a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 9939a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, #\num 9940a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 9941a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9942a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 9943a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endm 9944a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9945a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 0 9946a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 1 9947a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 2 9948a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 3 9949a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 4 9950a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden SQUEAK 5 9951a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9952a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9953a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Spit out the number in r0, preserving registers. 9954a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9955a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNum: 9956a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9957a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 9958a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strSqueak 9959a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 9960a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9961a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 9962a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9963a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9964a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print a newline, preserving registers. 9965a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9966a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printNewline: 9967a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9968a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strNewline 9969a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 9970a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9971a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 9972a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9973a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden /* 9974a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 9975a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9976a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printHex: 9977a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9978a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r1, r0 9979a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintHex 9980a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 9981a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9982a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 9983a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9984a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9985a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 9986a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9987a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printLong: 9988a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9989a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r3, r1 9990a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden mov r2, r0 9991a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldr r0, strPrintLong 9992a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl printf 9993a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9994a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 9995a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 9996a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 9997a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 9998a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 9999a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_printMethod: 10000a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10001a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpPrintMethod 10002a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10003a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10004a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10005a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10006a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Call a C helper function that dumps regs and possibly some 10007a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * additional info. Requires the C function to be compiled in. 10008a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10009a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .if 0 10010a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddencommon_dumpRegs: 10011a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10012a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bl dvmMterpDumpArmRegs 10013a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10014a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden bx lr 10015a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .endif 10016a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10017d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#if 0 10018d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden/* 10019d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Experiment on VFP mode. 10020d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10021d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 10022d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * 10023d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 10024d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden */ 10025d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddensetFPSCR: 10026d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r0, r0, r1 @ make sure no stray bits are set 10027d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmrx r2, fpscr @ get VFP reg 10028d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mvn r1, r1 @ bit-invert mask 10029d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden and r2, r2, r1 @ clear masked bits 10030d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden orr r2, r2, r0 @ set specified bits 10031d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden fmxr fpscr, r2 @ set VFP reg 10032d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, r2 @ return new value 10033d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bx lr 10034d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10035d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .align 2 10036d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .global dvmConfigureFP 10037d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden .type dvmConfigureFP, %function 10038d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFaddendvmConfigureFP: 10039d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden stmfd sp!, {ip, lr} 10040d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x03000000 sets DN/FZ */ 10041d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden /* 0x00009f00 clears the six exception enable flags */ 10042d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl common_squeak0 10043d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10044d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10045d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden bl setFPSCR 10046d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden ldmfd sp!, {ip, pc} 10047d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden#endif 10048d8125c62642bd71df7485a85f787a1c6e2124c48Andy McFadden 10049a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10050a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10051a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * String references, must be close to the code that uses them. 10052a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10053a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .align 2 10054a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArithmeticException: 10055a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArithmeticException 10056a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayIndexException: 10057a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayIndexException 10058a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrArrayStoreException: 10059a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrArrayStoreException 10060a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrDivideByZero: 10061a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrDivideByZero 10062a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNegativeArraySizeException: 10063a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNegativeArraySizeException 10064a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNoSuchMethodError: 10065a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNoSuchMethodError 10066a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNullPointerException: 10067a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNullPointerException 10068a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10069a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrLogTag: 10070a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrLogTag 10071a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrExceptionNotCaughtLocally: 10072a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrExceptionNotCaughtLocally 10073a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10074a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrNewline: 10075a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrNewline 10076a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrSqueak: 10077a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrSqueak 10078a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintHex: 10079a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintHex 10080a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFaddenstrPrintLong: 10081a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .word .LstrPrintLong 10082a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10083a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden/* 10084a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * Zero-terminated ASCII string data. 10085a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * 10086a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10087a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * with the address, or use an ADR pseudo-op to get the address 10088a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10089a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * PC-relative addressing mode and hence has a limited range, which 10090a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden * makes it not work well with mergeable string sections. 10091a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden */ 10092a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10093a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10094a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrBadEntryPoint: 10095a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Bad entry point %d\n" 10096a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArithmeticException: 10097a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArithmeticException;" 10098a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayIndexException: 10099a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10100a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrArrayStoreException: 10101a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10102a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrClassCastException: 10103a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/ClassCastException;" 10104a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrDivideByZero: 10105a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "divide by zero" 10106a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrFilledNewArrayNotImpl: 10107a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10108a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInternalError: 10109a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InternalError;" 10110a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrInstantiationError: 10111a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/InstantiationError;" 10112a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNegativeArraySizeException: 10113a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10114a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNoSuchMethodError: 10115a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10116a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNullPointerException: 10117a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Ljava/lang/NullPointerException;" 10118a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10119a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrLogTag: 10120a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "mterp" 10121a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrExceptionNotCaughtLocally: 10122a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10123a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10124a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrNewline: 10125a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "\n" 10126a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrSqueak: 10127a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%d>" 10128a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintHex: 10129a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<0x%x>" 10130a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.LstrPrintLong: 10131a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden .asciz "<%lld>" 10132a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10133a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden 10134