InterpAsm-armv5te.S revision 98f3eb12bf2a33c49712e093d5cc2aa713a93aa5
1/* 2 * This file was generated automatically by gen-mterp.py for 'armv5te'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: armv5te/header.S */ 8/* 9 * Copyright (C) 2008 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 * ARMv5 definitions and declarations. 26 */ 27 28/* 29ARM EABI general notes: 30 31r0-r3 hold first 4 args to a method; they are not preserved across method calls 32r4-r8 are available for general use 33r9 is given special treatment in some situations, but not for us 34r10 (sl) seems to be generally available 35r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36r12 (ip) is scratch -- not preserved across method calls 37r13 (sp) should be managed carefully in case a signal arrives 38r14 (lr) must be preserved 39r15 (pc) can be tinkered with directly 40 41r0 holds returns of <= 4 bytes 42r0-r1 hold returns of 8 bytes, low word in r0 43 44Callee must save/restore r4+ (except r12) if it modifies them. If VFP 45is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46s0-s15 (d0-d7, q0-a3) do not need to be. 47 48Stack is "full descending". Only the arguments that don't fit in the first 4 49registers are placed on the stack. "sp" points at the first stacked argument 50(i.e. the 5th arg). 51 52VFP: single-precision results in s0, double-precision results in d0. 53 54In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 5564-bit quantities (long long, double) must be 64-bit aligned. 56*/ 57 58/* 59Mterp and ARM notes: 60 61The following registers have fixed assignments: 62 63 reg nick purpose 64 r4 rPC interpreted program counter, used for fetching instructions 65 r5 rFP interpreted frame pointer, used for accessing locals and args 66 r6 rSELF self (Thread) pointer 67 r7 rINST first 16-bit code unit of current instruction 68 r8 rIBASE interpreted instruction base pointer, used for computed goto 69 70Macros are provided for common operations. Each macro MUST emit only 71one instruction to make instruction-counting easier. They MUST NOT alter 72unspecified registers or condition codes. 73*/ 74 75/* single-purpose registers, given names for clarity */ 76#define rPC r4 77#define rFP r5 78#define rSELF r6 79#define rINST r7 80#define rIBASE r8 81 82/* save/restore the PC and/or FP from the thread struct */ 83#define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc] 84#define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc] 85#define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp] 86#define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp] 87#define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP} 88#define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP} 89 90/* 91 * "export" the PC to the stack frame, f/b/o future exception objects. Must 92 * be done *before* something throws. 93 * 94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96 * 97 * It's okay to do this more than once. 98 */ 99#define EXPORT_PC() \ 100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101 102/* 103 * Given a frame pointer, find the stack save area. 104 * 105 * In C this is "((StackSaveArea*)(_fp) -1)". 106 */ 107#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108 sub _reg, _fpreg, #sizeofStackSaveArea 109 110/* 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112 */ 113#define FETCH_INST() ldrh rINST, [rPC] 114 115/* 116 * Fetch the next instruction from the specified offset. Advances rPC 117 * to point to the next instruction. "_count" is in 16-bit code units. 118 * 119 * Because of the limited size of immediate constants on ARM, this is only 120 * suitable for small forward movements (i.e. don't try to implement "goto" 121 * with this). 122 * 123 * This must come AFTER anything that can throw an exception, or the 124 * exception catch may miss. (This also implies that it must come after 125 * EXPORT_PC().) 126 */ 127#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 128 129/* 130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132 */ 133#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134 ldrh _dreg, [_sreg, #(_count*2)]! 135 136/* 137 * Fetch the next instruction from an offset specified by _reg. Updates 138 * rPC to point to the next instruction. "_reg" must specify the distance 139 * in bytes, *not* 16-bit code units, and may be a signed value. 140 * 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142 * bits that hold the shift distance are used for the half/byte/sign flags. 143 * In some cases we can pre-double _reg for free, so we require a byte offset 144 * here. 145 */ 146#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147 148/* 149 * Fetch a half-word code unit from an offset past the current PC. The 150 * "_count" value is in 16-bit code units. Does not advance rPC. 151 * 152 * The "_S" variant works the same but treats the value as signed. 153 */ 154#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 155#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 156 157/* 158 * Fetch one byte from an offset past the current PC. Pass in the same 159 * "_count" as you would for FETCH, and an additional 0/1 indicating which 160 * byte of the halfword you want (lo/hi). 161 */ 162#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 163 164/* 165 * Put the instruction's opcode field into the specified register. 166 */ 167#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168 169/* 170 * Put the prefetched instruction's opcode field into the specified register. 171 */ 172#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173 174/* 175 * Begin executing the opcode in _reg. Because this only jumps within the 176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177 */ 178#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181 182/* 183 * Get/set the 32-bit value from a Dalvik register. 184 */ 185#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187 188#if defined(WITH_JIT) 189#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable] 190#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold] 191#endif 192 193/* 194 * Convert a virtual register index into an address. 195 */ 196#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197 add _reg, rFP, _vreg, lsl #2 198 199/* 200 * This is a #include, not a %include, because we want the C pre-processor 201 * to expand the macros into assembler assignment statements. 202 */ 203#include "../common/asm-constants.h" 204 205#if defined(WITH_JIT) 206#include "../common/jit-config.h" 207#endif 208 209/* File: armv5te/platform.S */ 210/* 211 * =========================================================================== 212 * CPU-version-specific defines 213 * =========================================================================== 214 */ 215 216/* 217 * Macro for data memory barrier; not meaningful pre-ARMv6K. 218 */ 219.macro SMP_DMB 220.endm 221 222/* 223 * Macro for data memory barrier; not meaningful pre-ARMv6K. 224 */ 225.macro SMP_DMB_ST 226.endm 227 228/* File: armv5te/entry.S */ 229/* 230 * Copyright (C) 2008 The Android Open Source Project 231 * 232 * Licensed under the Apache License, Version 2.0 (the "License"); 233 * you may not use this file except in compliance with the License. 234 * You may obtain a copy of the License at 235 * 236 * http://www.apache.org/licenses/LICENSE-2.0 237 * 238 * Unless required by applicable law or agreed to in writing, software 239 * distributed under the License is distributed on an "AS IS" BASIS, 240 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 241 * See the License for the specific language governing permissions and 242 * limitations under the License. 243 */ 244/* 245 * Interpreter entry point. 246 */ 247 248/* 249 * We don't have formal stack frames, so gdb scans upward in the code 250 * to find the start of the function (a label with the %function type), 251 * and then looks at the next few instructions to figure out what 252 * got pushed onto the stack. From this it figures out how to restore 253 * the registers, including PC, for the previous stack frame. If gdb 254 * sees a non-function label, it stops scanning, so either we need to 255 * have nothing but assembler-local labels between the entry point and 256 * the break, or we need to fake it out. 257 * 258 * When this is defined, we add some stuff to make gdb less confused. 259 */ 260#define ASSIST_DEBUGGER 1 261 262 .text 263 .align 2 264 .global dvmMterpStdRun 265 .type dvmMterpStdRun, %function 266 267/* 268 * On entry: 269 * r0 Thread* self 270 * 271 * This function returns a boolean "changeInterp" value. The return comes 272 * via a call to dvmMterpStdBail(). 273 */ 274dvmMterpStdRun: 275#define MTERP_ENTRY1 \ 276 .save {r4-r10,fp,lr}; \ 277 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 278#define MTERP_ENTRY2 \ 279 .pad #4; \ 280 sub sp, sp, #4 @ align 64 281 282 .fnstart 283 MTERP_ENTRY1 284 MTERP_ENTRY2 285 286 /* save stack pointer, add magic word for debuggerd */ 287 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return 288 289 /* set up "named" registers, figure out entry point */ 290 mov rSELF, r0 @ set rSELF 291 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI 292 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread" 293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE 294 cmp r1, #kInterpEntryInstr @ usual case? 295 bne .Lnot_instr @ no, handle it 296 297#if defined(WITH_JIT) 298.LentryInstr: 299 /* Entry is always a possible trace start */ 300 GET_JIT_PROF_TABLE(r0) 301 FETCH_INST() 302 mov r1, #0 @ prepare the value for the new state 303 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 304 cmp r0,#0 @ is profiling disabled? 305#if !defined(WITH_SELF_VERIFICATION) 306 bne common_updateProfile @ profiling is enabled 307#else 308 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state 309 beq 1f @ profiling is disabled 310 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 311 cmp r3, #kSVSTraceSelect @ hot trace following? 312 moveq r2,#kJitTSelectRequestHot @ ask for trace selection 313 beq common_selectTrace @ go build the trace 314 cmp r3, #kSVSNoProfile @ don't profile the next instruction? 315 beq 1f @ intrepret the next instruction 316 b common_updateProfile @ collect profiles 317#endif 3181: 319 GET_INST_OPCODE(ip) 320 GOTO_OPCODE(ip) 321#else 322 /* start executing the instruction at rPC */ 323 FETCH_INST() @ load rINST from rPC 324 GET_INST_OPCODE(ip) @ extract opcode from rINST 325 GOTO_OPCODE(ip) @ jump to next instruction 326#endif 327 328.Lnot_instr: 329 cmp r1, #kInterpEntryReturn @ were we returning from a method? 330 beq common_returnFromMethod 331 332.Lnot_return: 333 cmp r1, #kInterpEntryThrow @ were we throwing an exception? 334 beq common_exceptionThrown 335 336#if defined(WITH_JIT) 337.Lnot_throw: 338 ldr r10,[rSELF, #offThread_jitResumeNPC] 339 ldr r2,[rSELF, #offThread_jitResumeDPC] 340 cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 341 bne .Lbad_arg 342 cmp rPC,r2 343 bne .LentryInstr @ must have branched, don't resume 344#if defined(WITH_SELF_VERIFICATION) 345 @ self->entryPoint will be set in dvmSelfVerificationSaveState 346 b jitSVShadowRunStart @ re-enter the translation after the 347 @ single-stepped instruction 348 @noreturn 349#endif 350 mov r1, #kInterpEntryInstr 351 str r1, [rSELF, #offThread_entryPoint] 352 bx r10 @ re-enter the translation 353#endif 354 355.Lbad_arg: 356 ldr r0, strBadEntryPoint 357 @ r1 holds value of entryPoint 358 bl printf 359 bl dvmAbort 360 .fnend 361 .size dvmMterpStdRun, .-dvmMterpStdRun 362 363 364 .global dvmMterpStdBail 365 .type dvmMterpStdBail, %function 366 367/* 368 * Restore the stack pointer and PC from the save point established on entry. 369 * This is essentially the same as a longjmp, but should be cheaper. The 370 * last instruction causes us to return to whoever called dvmMterpStdRun. 371 * 372 * We pushed some registers on the stack in dvmMterpStdRun, then saved 373 * SP and LR. Here we restore SP, restore the registers, and then restore 374 * LR to PC. 375 * 376 * On entry: 377 * r0 Thread* self 378 * r1 bool changeInterp 379 */ 380dvmMterpStdBail: 381 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP 382 mov r0, r1 @ return the changeInterp value 383 add sp, sp, #4 @ un-align 64 384 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return 385 386 387/* 388 * String references. 389 */ 390strBadEntryPoint: 391 .word .LstrBadEntryPoint 392 393 394 .global dvmAsmInstructionStart 395 .type dvmAsmInstructionStart, %function 396dvmAsmInstructionStart = .L_OP_NOP 397 .text 398 399/* ------------------------------ */ 400 .balign 64 401.L_OP_NOP: /* 0x00 */ 402/* File: armv5te/OP_NOP.S */ 403 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 404 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 405 GOTO_OPCODE(ip) @ execute it 406 407#ifdef ASSIST_DEBUGGER 408 /* insert fake function header to help gdb find the stack frame */ 409 .type dalvik_inst, %function 410dalvik_inst: 411 .fnstart 412 MTERP_ENTRY1 413 MTERP_ENTRY2 414 .fnend 415#endif 416 417/* ------------------------------ */ 418 .balign 64 419.L_OP_MOVE: /* 0x01 */ 420/* File: armv5te/OP_MOVE.S */ 421 /* for move, move-object, long-to-int */ 422 /* op vA, vB */ 423 mov r1, rINST, lsr #12 @ r1<- B from 15:12 424 mov r0, rINST, lsr #8 @ r0<- A from 11:8 425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 426 GET_VREG(r2, r1) @ r2<- fp[B] 427 and r0, r0, #15 428 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 429 SET_VREG(r2, r0) @ fp[A]<- r2 430 GOTO_OPCODE(ip) @ execute next instruction 431 432/* ------------------------------ */ 433 .balign 64 434.L_OP_MOVE_FROM16: /* 0x02 */ 435/* File: armv5te/OP_MOVE_FROM16.S */ 436 /* for: move/from16, move-object/from16 */ 437 /* op vAA, vBBBB */ 438 FETCH(r1, 1) @ r1<- BBBB 439 mov r0, rINST, lsr #8 @ r0<- AA 440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 441 GET_VREG(r2, r1) @ r2<- fp[BBBB] 442 GET_INST_OPCODE(ip) @ extract opcode from rINST 443 SET_VREG(r2, r0) @ fp[AA]<- r2 444 GOTO_OPCODE(ip) @ jump to next instruction 445 446/* ------------------------------ */ 447 .balign 64 448.L_OP_MOVE_16: /* 0x03 */ 449/* File: armv5te/OP_MOVE_16.S */ 450 /* for: move/16, move-object/16 */ 451 /* op vAAAA, vBBBB */ 452 FETCH(r1, 2) @ r1<- BBBB 453 FETCH(r0, 1) @ r0<- AAAA 454 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 455 GET_VREG(r2, r1) @ r2<- fp[BBBB] 456 GET_INST_OPCODE(ip) @ extract opcode from rINST 457 SET_VREG(r2, r0) @ fp[AAAA]<- r2 458 GOTO_OPCODE(ip) @ jump to next instruction 459 460/* ------------------------------ */ 461 .balign 64 462.L_OP_MOVE_WIDE: /* 0x04 */ 463/* File: armv5te/OP_MOVE_WIDE.S */ 464 /* move-wide vA, vB */ 465 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 466 mov r2, rINST, lsr #8 @ r2<- A(+) 467 mov r3, rINST, lsr #12 @ r3<- B 468 and r2, r2, #15 469 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 470 add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 471 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 472 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 473 GET_INST_OPCODE(ip) @ extract opcode from rINST 474 stmia r2, {r0-r1} @ fp[A]<- r0/r1 475 GOTO_OPCODE(ip) @ jump to next instruction 476 477/* ------------------------------ */ 478 .balign 64 479.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 480/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 481 /* move-wide/from16 vAA, vBBBB */ 482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 483 FETCH(r3, 1) @ r3<- BBBB 484 mov r2, rINST, lsr #8 @ r2<- AA 485 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 486 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 487 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 489 GET_INST_OPCODE(ip) @ extract opcode from rINST 490 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 491 GOTO_OPCODE(ip) @ jump to next instruction 492 493/* ------------------------------ */ 494 .balign 64 495.L_OP_MOVE_WIDE_16: /* 0x06 */ 496/* File: armv5te/OP_MOVE_WIDE_16.S */ 497 /* move-wide/16 vAAAA, vBBBB */ 498 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 499 FETCH(r3, 2) @ r3<- BBBB 500 FETCH(r2, 1) @ r2<- AAAA 501 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 502 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 503 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 504 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 505 GET_INST_OPCODE(ip) @ extract opcode from rINST 506 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 507 GOTO_OPCODE(ip) @ jump to next instruction 508 509/* ------------------------------ */ 510 .balign 64 511.L_OP_MOVE_OBJECT: /* 0x07 */ 512/* File: armv5te/OP_MOVE_OBJECT.S */ 513/* File: armv5te/OP_MOVE.S */ 514 /* for move, move-object, long-to-int */ 515 /* op vA, vB */ 516 mov r1, rINST, lsr #12 @ r1<- B from 15:12 517 mov r0, rINST, lsr #8 @ r0<- A from 11:8 518 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 519 GET_VREG(r2, r1) @ r2<- fp[B] 520 and r0, r0, #15 521 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 522 SET_VREG(r2, r0) @ fp[A]<- r2 523 GOTO_OPCODE(ip) @ execute next instruction 524 525 526/* ------------------------------ */ 527 .balign 64 528.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 529/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 530/* File: armv5te/OP_MOVE_FROM16.S */ 531 /* for: move/from16, move-object/from16 */ 532 /* op vAA, vBBBB */ 533 FETCH(r1, 1) @ r1<- BBBB 534 mov r0, rINST, lsr #8 @ r0<- AA 535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 536 GET_VREG(r2, r1) @ r2<- fp[BBBB] 537 GET_INST_OPCODE(ip) @ extract opcode from rINST 538 SET_VREG(r2, r0) @ fp[AA]<- r2 539 GOTO_OPCODE(ip) @ jump to next instruction 540 541 542/* ------------------------------ */ 543 .balign 64 544.L_OP_MOVE_OBJECT_16: /* 0x09 */ 545/* File: armv5te/OP_MOVE_OBJECT_16.S */ 546/* File: armv5te/OP_MOVE_16.S */ 547 /* for: move/16, move-object/16 */ 548 /* op vAAAA, vBBBB */ 549 FETCH(r1, 2) @ r1<- BBBB 550 FETCH(r0, 1) @ r0<- AAAA 551 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 552 GET_VREG(r2, r1) @ r2<- fp[BBBB] 553 GET_INST_OPCODE(ip) @ extract opcode from rINST 554 SET_VREG(r2, r0) @ fp[AAAA]<- r2 555 GOTO_OPCODE(ip) @ jump to next instruction 556 557 558/* ------------------------------ */ 559 .balign 64 560.L_OP_MOVE_RESULT: /* 0x0a */ 561/* File: armv5te/OP_MOVE_RESULT.S */ 562 /* for: move-result, move-result-object */ 563 /* op vAA */ 564 mov r2, rINST, lsr #8 @ r2<- AA 565 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 566 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 567 GET_INST_OPCODE(ip) @ extract opcode from rINST 568 SET_VREG(r0, r2) @ fp[AA]<- r0 569 GOTO_OPCODE(ip) @ jump to next instruction 570 571/* ------------------------------ */ 572 .balign 64 573.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 574/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 575 /* move-result-wide vAA */ 576 mov r2, rINST, lsr #8 @ r2<- AA 577 add r3, rSELF, #offThread_retval @ r3<- &self->retval 578 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 579 ldmia r3, {r0-r1} @ r0/r1<- retval.j 580 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 581 GET_INST_OPCODE(ip) @ extract opcode from rINST 582 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 583 GOTO_OPCODE(ip) @ jump to next instruction 584 585/* ------------------------------ */ 586 .balign 64 587.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 588/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 589/* File: armv5te/OP_MOVE_RESULT.S */ 590 /* for: move-result, move-result-object */ 591 /* op vAA */ 592 mov r2, rINST, lsr #8 @ r2<- AA 593 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 594 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 595 GET_INST_OPCODE(ip) @ extract opcode from rINST 596 SET_VREG(r0, r2) @ fp[AA]<- r0 597 GOTO_OPCODE(ip) @ jump to next instruction 598 599 600/* ------------------------------ */ 601 .balign 64 602.L_OP_MOVE_EXCEPTION: /* 0x0d */ 603/* File: armv5te/OP_MOVE_EXCEPTION.S */ 604 /* move-exception vAA */ 605 mov r2, rINST, lsr #8 @ r2<- AA 606 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass 607 mov r1, #0 @ r1<- 0 608 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 609 SET_VREG(r3, r2) @ fp[AA]<- exception obj 610 GET_INST_OPCODE(ip) @ extract opcode from rINST 611 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass 612 GOTO_OPCODE(ip) @ jump to next instruction 613 614/* ------------------------------ */ 615 .balign 64 616.L_OP_RETURN_VOID: /* 0x0e */ 617/* File: armv5te/OP_RETURN_VOID.S */ 618 b common_returnFromMethod 619 620/* ------------------------------ */ 621 .balign 64 622.L_OP_RETURN: /* 0x0f */ 623/* File: armv5te/OP_RETURN.S */ 624 /* 625 * Return a 32-bit value. Copies the return value into the "thread" 626 * structure, then jumps to the return handler. 627 * 628 * for: return, return-object 629 */ 630 /* op vAA */ 631 mov r2, rINST, lsr #8 @ r2<- AA 632 GET_VREG(r0, r2) @ r0<- vAA 633 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 634 b common_returnFromMethod 635 636/* ------------------------------ */ 637 .balign 64 638.L_OP_RETURN_WIDE: /* 0x10 */ 639/* File: armv5te/OP_RETURN_WIDE.S */ 640 /* 641 * Return a 64-bit value. Copies the return value into the "thread" 642 * structure, then jumps to the return handler. 643 */ 644 /* return-wide vAA */ 645 mov r2, rINST, lsr #8 @ r2<- AA 646 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 647 add r3, rSELF, #offThread_retval @ r3<- &self->retval 648 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 649 stmia r3, {r0-r1} @ retval<- r0/r1 650 b common_returnFromMethod 651 652/* ------------------------------ */ 653 .balign 64 654.L_OP_RETURN_OBJECT: /* 0x11 */ 655/* File: armv5te/OP_RETURN_OBJECT.S */ 656/* File: armv5te/OP_RETURN.S */ 657 /* 658 * Return a 32-bit value. Copies the return value into the "thread" 659 * structure, then jumps to the return handler. 660 * 661 * for: return, return-object 662 */ 663 /* op vAA */ 664 mov r2, rINST, lsr #8 @ r2<- AA 665 GET_VREG(r0, r2) @ r0<- vAA 666 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 667 b common_returnFromMethod 668 669 670/* ------------------------------ */ 671 .balign 64 672.L_OP_CONST_4: /* 0x12 */ 673/* File: armv5te/OP_CONST_4.S */ 674 /* const/4 vA, #+B */ 675 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 676 mov r0, rINST, lsr #8 @ r0<- A+ 677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 678 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 679 and r0, r0, #15 680 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 681 SET_VREG(r1, r0) @ fp[A]<- r1 682 GOTO_OPCODE(ip) @ execute next instruction 683 684/* ------------------------------ */ 685 .balign 64 686.L_OP_CONST_16: /* 0x13 */ 687/* File: armv5te/OP_CONST_16.S */ 688 /* const/16 vAA, #+BBBB */ 689 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 690 mov r3, rINST, lsr #8 @ r3<- AA 691 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 692 SET_VREG(r0, r3) @ vAA<- r0 693 GET_INST_OPCODE(ip) @ extract opcode from rINST 694 GOTO_OPCODE(ip) @ jump to next instruction 695 696/* ------------------------------ */ 697 .balign 64 698.L_OP_CONST: /* 0x14 */ 699/* File: armv5te/OP_CONST.S */ 700 /* const vAA, #+BBBBbbbb */ 701 mov r3, rINST, lsr #8 @ r3<- AA 702 FETCH(r0, 1) @ r0<- bbbb (low) 703 FETCH(r1, 2) @ r1<- BBBB (high) 704 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 705 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 706 GET_INST_OPCODE(ip) @ extract opcode from rINST 707 SET_VREG(r0, r3) @ vAA<- r0 708 GOTO_OPCODE(ip) @ jump to next instruction 709 710/* ------------------------------ */ 711 .balign 64 712.L_OP_CONST_HIGH16: /* 0x15 */ 713/* File: armv5te/OP_CONST_HIGH16.S */ 714 /* const/high16 vAA, #+BBBB0000 */ 715 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 716 mov r3, rINST, lsr #8 @ r3<- AA 717 mov r0, r0, lsl #16 @ r0<- BBBB0000 718 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 719 SET_VREG(r0, r3) @ vAA<- r0 720 GET_INST_OPCODE(ip) @ extract opcode from rINST 721 GOTO_OPCODE(ip) @ jump to next instruction 722 723/* ------------------------------ */ 724 .balign 64 725.L_OP_CONST_WIDE_16: /* 0x16 */ 726/* File: armv5te/OP_CONST_WIDE_16.S */ 727 /* const-wide/16 vAA, #+BBBB */ 728 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 729 mov r3, rINST, lsr #8 @ r3<- AA 730 mov r1, r0, asr #31 @ r1<- ssssssss 731 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 732 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 733 GET_INST_OPCODE(ip) @ extract opcode from rINST 734 stmia r3, {r0-r1} @ vAA<- r0/r1 735 GOTO_OPCODE(ip) @ jump to next instruction 736 737/* ------------------------------ */ 738 .balign 64 739.L_OP_CONST_WIDE_32: /* 0x17 */ 740/* File: armv5te/OP_CONST_WIDE_32.S */ 741 /* const-wide/32 vAA, #+BBBBbbbb */ 742 FETCH(r0, 1) @ r0<- 0000bbbb (low) 743 mov r3, rINST, lsr #8 @ r3<- AA 744 FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 745 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 746 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 747 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 748 mov r1, r0, asr #31 @ r1<- ssssssss 749 GET_INST_OPCODE(ip) @ extract opcode from rINST 750 stmia r3, {r0-r1} @ vAA<- r0/r1 751 GOTO_OPCODE(ip) @ jump to next instruction 752 753/* ------------------------------ */ 754 .balign 64 755.L_OP_CONST_WIDE: /* 0x18 */ 756/* File: armv5te/OP_CONST_WIDE.S */ 757 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 758 FETCH(r0, 1) @ r0<- bbbb (low) 759 FETCH(r1, 2) @ r1<- BBBB (low middle) 760 FETCH(r2, 3) @ r2<- hhhh (high middle) 761 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 762 FETCH(r3, 4) @ r3<- HHHH (high) 763 mov r9, rINST, lsr #8 @ r9<- AA 764 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 766 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 767 GET_INST_OPCODE(ip) @ extract opcode from rINST 768 stmia r9, {r0-r1} @ vAA<- r0/r1 769 GOTO_OPCODE(ip) @ jump to next instruction 770 771/* ------------------------------ */ 772 .balign 64 773.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 774/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 775 /* const-wide/high16 vAA, #+BBBB000000000000 */ 776 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 777 mov r3, rINST, lsr #8 @ r3<- AA 778 mov r0, #0 @ r0<- 00000000 779 mov r1, r1, lsl #16 @ r1<- BBBB0000 780 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 781 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 782 GET_INST_OPCODE(ip) @ extract opcode from rINST 783 stmia r3, {r0-r1} @ vAA<- r0/r1 784 GOTO_OPCODE(ip) @ jump to next instruction 785 786/* ------------------------------ */ 787 .balign 64 788.L_OP_CONST_STRING: /* 0x1a */ 789/* File: armv5te/OP_CONST_STRING.S */ 790 /* const/string vAA, String@BBBB */ 791 FETCH(r1, 1) @ r1<- BBBB 792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 793 mov r9, rINST, lsr #8 @ r9<- AA 794 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 795 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 796 cmp r0, #0 @ not yet resolved? 797 beq .LOP_CONST_STRING_resolve 798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 799 GET_INST_OPCODE(ip) @ extract opcode from rINST 800 SET_VREG(r0, r9) @ vAA<- r0 801 GOTO_OPCODE(ip) @ jump to next instruction 802 803/* ------------------------------ */ 804 .balign 64 805.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 806/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 807 /* const/string vAA, String@BBBBBBBB */ 808 FETCH(r0, 1) @ r0<- bbbb (low) 809 FETCH(r1, 2) @ r1<- BBBB (high) 810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 811 mov r9, rINST, lsr #8 @ r9<- AA 812 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 813 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 814 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 815 cmp r0, #0 816 beq .LOP_CONST_STRING_JUMBO_resolve 817 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 818 GET_INST_OPCODE(ip) @ extract opcode from rINST 819 SET_VREG(r0, r9) @ vAA<- r0 820 GOTO_OPCODE(ip) @ jump to next instruction 821 822/* ------------------------------ */ 823 .balign 64 824.L_OP_CONST_CLASS: /* 0x1c */ 825/* File: armv5te/OP_CONST_CLASS.S */ 826 /* const/class vAA, Class@BBBB */ 827 FETCH(r1, 1) @ r1<- BBBB 828 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 829 mov r9, rINST, lsr #8 @ r9<- AA 830 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 831 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 832 cmp r0, #0 @ not yet resolved? 833 beq .LOP_CONST_CLASS_resolve 834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 835 GET_INST_OPCODE(ip) @ extract opcode from rINST 836 SET_VREG(r0, r9) @ vAA<- r0 837 GOTO_OPCODE(ip) @ jump to next instruction 838 839/* ------------------------------ */ 840 .balign 64 841.L_OP_MONITOR_ENTER: /* 0x1d */ 842/* File: armv5te/OP_MONITOR_ENTER.S */ 843 /* 844 * Synchronize on an object. 845 */ 846 /* monitor-enter vAA */ 847 mov r2, rINST, lsr #8 @ r2<- AA 848 GET_VREG(r1, r2) @ r1<- vAA (object) 849 mov r0, rSELF @ r0<- self 850 cmp r1, #0 @ null object? 851 EXPORT_PC() @ need for precise GC 852 beq common_errNullObject @ null object, throw an exception 853 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 854 bl dvmLockObject @ call(self, obj) 855 GET_INST_OPCODE(ip) @ extract opcode from rINST 856 GOTO_OPCODE(ip) @ jump to next instruction 857 858/* ------------------------------ */ 859 .balign 64 860.L_OP_MONITOR_EXIT: /* 0x1e */ 861/* File: armv5te/OP_MONITOR_EXIT.S */ 862 /* 863 * Unlock an object. 864 * 865 * Exceptions that occur when unlocking a monitor need to appear as 866 * if they happened at the following instruction. See the Dalvik 867 * instruction spec. 868 */ 869 /* monitor-exit vAA */ 870 mov r2, rINST, lsr #8 @ r2<- AA 871 EXPORT_PC() @ before fetch: export the PC 872 GET_VREG(r1, r2) @ r1<- vAA (object) 873 cmp r1, #0 @ null object? 874 beq 1f @ yes 875 mov r0, rSELF @ r0<- self 876 bl dvmUnlockObject @ r0<- success for unlock(self, obj) 877 cmp r0, #0 @ failed? 878 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 879 beq common_exceptionThrown @ yes, exception is pending 880 GET_INST_OPCODE(ip) @ extract opcode from rINST 881 GOTO_OPCODE(ip) @ jump to next instruction 8821: 883 FETCH_ADVANCE_INST(1) @ advance before throw 884 b common_errNullObject 885 886/* ------------------------------ */ 887 .balign 64 888.L_OP_CHECK_CAST: /* 0x1f */ 889/* File: armv5te/OP_CHECK_CAST.S */ 890 /* 891 * Check to see if a cast from one class to another is allowed. 892 */ 893 /* check-cast vAA, class@BBBB */ 894 mov r3, rINST, lsr #8 @ r3<- AA 895 FETCH(r2, 1) @ r2<- BBBB 896 GET_VREG(r9, r3) @ r9<- object 897 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 898 cmp r9, #0 @ is object null? 899 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 900 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 901 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 903 cmp r1, #0 @ have we resolved this before? 904 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 905.LOP_CHECK_CAST_resolved: 906 cmp r0, r1 @ same class (trivial success)? 907 bne .LOP_CHECK_CAST_fullcheck @ no, do full check 908.LOP_CHECK_CAST_okay: 909 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 910 GET_INST_OPCODE(ip) @ extract opcode from rINST 911 GOTO_OPCODE(ip) @ jump to next instruction 912 913/* ------------------------------ */ 914 .balign 64 915.L_OP_INSTANCE_OF: /* 0x20 */ 916/* File: armv5te/OP_INSTANCE_OF.S */ 917 /* 918 * Check to see if an object reference is an instance of a class. 919 * 920 * Most common situation is a non-null object, being compared against 921 * an already-resolved class. 922 */ 923 /* instance-of vA, vB, class@CCCC */ 924 mov r3, rINST, lsr #12 @ r3<- B 925 mov r9, rINST, lsr #8 @ r9<- A+ 926 GET_VREG(r0, r3) @ r0<- vB (object) 927 and r9, r9, #15 @ r9<- A 928 cmp r0, #0 @ is object null? 929 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 930 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 931 FETCH(r3, 1) @ r3<- CCCC 932 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 933 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 934 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 935 cmp r1, #0 @ have we resolved this before? 936 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 937.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 938 cmp r0, r1 @ same class (trivial success)? 939 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 940 b .LOP_INSTANCE_OF_fullcheck @ no, do full check 941 942/* ------------------------------ */ 943 .balign 64 944.L_OP_ARRAY_LENGTH: /* 0x21 */ 945/* File: armv5te/OP_ARRAY_LENGTH.S */ 946 /* 947 * Return the length of an array. 948 */ 949 mov r1, rINST, lsr #12 @ r1<- B 950 mov r2, rINST, lsr #8 @ r2<- A+ 951 GET_VREG(r0, r1) @ r0<- vB (object ref) 952 and r2, r2, #15 @ r2<- A 953 cmp r0, #0 @ is object null? 954 beq common_errNullObject @ yup, fail 955 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 956 ldr r3, [r0, #offArrayObject_length] @ r3<- array length 957 GET_INST_OPCODE(ip) @ extract opcode from rINST 958 SET_VREG(r3, r2) @ vB<- length 959 GOTO_OPCODE(ip) @ jump to next instruction 960 961/* ------------------------------ */ 962 .balign 64 963.L_OP_NEW_INSTANCE: /* 0x22 */ 964/* File: armv5te/OP_NEW_INSTANCE.S */ 965 /* 966 * Create a new instance of a class. 967 */ 968 /* new-instance vAA, class@BBBB */ 969 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 970 FETCH(r1, 1) @ r1<- BBBB 971 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 972 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 973 EXPORT_PC() @ req'd for init, resolve, alloc 974 cmp r0, #0 @ already resolved? 975 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 976.LOP_NEW_INSTANCE_resolved: @ r0=class 977 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 978 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 979 bne .LOP_NEW_INSTANCE_needinit @ no, init class now 980.LOP_NEW_INSTANCE_initialized: @ r0=class 981 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 982 bl dvmAllocObject @ r0<- new object 983 b .LOP_NEW_INSTANCE_finish @ continue 984 985/* ------------------------------ */ 986 .balign 64 987.L_OP_NEW_ARRAY: /* 0x23 */ 988/* File: armv5te/OP_NEW_ARRAY.S */ 989 /* 990 * Allocate an array of objects, specified with the array class 991 * and a count. 992 * 993 * The verifier guarantees that this is an array class, so we don't 994 * check for it here. 995 */ 996 /* new-array vA, vB, class@CCCC */ 997 mov r0, rINST, lsr #12 @ r0<- B 998 FETCH(r2, 1) @ r2<- CCCC 999 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1000 GET_VREG(r1, r0) @ r1<- vB (array length) 1001 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1002 cmp r1, #0 @ check length 1003 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1004 bmi common_errNegativeArraySize @ negative length, bail - len in r1 1005 cmp r0, #0 @ already resolved? 1006 EXPORT_PC() @ req'd for resolve, alloc 1007 bne .LOP_NEW_ARRAY_finish @ resolved, continue 1008 b .LOP_NEW_ARRAY_resolve @ do resolve now 1009 1010/* ------------------------------ */ 1011 .balign 64 1012.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1013/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1014 /* 1015 * Create a new array with elements filled from registers. 1016 * 1017 * for: filled-new-array, filled-new-array/range 1018 */ 1019 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1020 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1022 FETCH(r1, 1) @ r1<- BBBB 1023 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1024 EXPORT_PC() @ need for resolve and alloc 1025 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1026 mov r10, rINST, lsr #8 @ r10<- AA or BA 1027 cmp r0, #0 @ already resolved? 1028 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 10298: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1030 mov r2, #0 @ r2<- false 1031 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1032 bl dvmResolveClass @ r0<- call(clazz, ref) 1033 cmp r0, #0 @ got null? 1034 beq common_exceptionThrown @ yes, handle exception 1035 b .LOP_FILLED_NEW_ARRAY_continue 1036 1037/* ------------------------------ */ 1038 .balign 64 1039.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1040/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1041/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1042 /* 1043 * Create a new array with elements filled from registers. 1044 * 1045 * for: filled-new-array, filled-new-array/range 1046 */ 1047 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1048 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1050 FETCH(r1, 1) @ r1<- BBBB 1051 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1052 EXPORT_PC() @ need for resolve and alloc 1053 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1054 mov r10, rINST, lsr #8 @ r10<- AA or BA 1055 cmp r0, #0 @ already resolved? 1056 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 10578: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1058 mov r2, #0 @ r2<- false 1059 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1060 bl dvmResolveClass @ r0<- call(clazz, ref) 1061 cmp r0, #0 @ got null? 1062 beq common_exceptionThrown @ yes, handle exception 1063 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1064 1065 1066/* ------------------------------ */ 1067 .balign 64 1068.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1069/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1070 /* fill-array-data vAA, +BBBBBBBB */ 1071 FETCH(r0, 1) @ r0<- bbbb (lo) 1072 FETCH(r1, 2) @ r1<- BBBB (hi) 1073 mov r3, rINST, lsr #8 @ r3<- AA 1074 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1075 GET_VREG(r0, r3) @ r0<- vAA (array object) 1076 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1077 EXPORT_PC(); 1078 bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1079 cmp r0, #0 @ 0 means an exception is thrown 1080 beq common_exceptionThrown @ has exception 1081 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1082 GET_INST_OPCODE(ip) @ extract opcode from rINST 1083 GOTO_OPCODE(ip) @ jump to next instruction 1084 1085/* ------------------------------ */ 1086 .balign 64 1087.L_OP_THROW: /* 0x27 */ 1088/* File: armv5te/OP_THROW.S */ 1089 /* 1090 * Throw an exception object in the current thread. 1091 */ 1092 /* throw vAA */ 1093 mov r2, rINST, lsr #8 @ r2<- AA 1094 GET_VREG(r1, r2) @ r1<- vAA (exception object) 1095 EXPORT_PC() @ exception handler can throw 1096 cmp r1, #0 @ null object? 1097 beq common_errNullObject @ yes, throw an NPE instead 1098 @ bypass dvmSetException, just store it 1099 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj 1100 b common_exceptionThrown 1101 1102/* ------------------------------ */ 1103 .balign 64 1104.L_OP_GOTO: /* 0x28 */ 1105/* File: armv5te/OP_GOTO.S */ 1106 /* 1107 * Unconditional branch, 8-bit offset. 1108 * 1109 * The branch distance is a signed code-unit offset, which we need to 1110 * double to get a byte offset. 1111 */ 1112 /* goto +AA */ 1113 mov r0, rINST, lsl #16 @ r0<- AAxx0000 1114 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1115 mov r9, r9, lsl #1 @ r9<- byte offset 1116 bmi common_backwardBranch @ backward branch, do periodic checks 1117#if defined(WITH_JIT) 1118 GET_JIT_PROF_TABLE(r0) 1119 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1120 cmp r0,#0 1121 bne common_updateProfile 1122 GET_INST_OPCODE(ip) @ extract opcode from rINST 1123 GOTO_OPCODE(ip) @ jump to next instruction 1124#else 1125 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1126 GET_INST_OPCODE(ip) @ extract opcode from rINST 1127 GOTO_OPCODE(ip) @ jump to next instruction 1128#endif 1129 1130/* ------------------------------ */ 1131 .balign 64 1132.L_OP_GOTO_16: /* 0x29 */ 1133/* File: armv5te/OP_GOTO_16.S */ 1134 /* 1135 * Unconditional branch, 16-bit offset. 1136 * 1137 * The branch distance is a signed code-unit offset, which we need to 1138 * double to get a byte offset. 1139 */ 1140 /* goto/16 +AAAA */ 1141 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1142 movs r9, r0, asl #1 @ r9<- byte offset, check sign 1143 bmi common_backwardBranch @ backward branch, do periodic checks 1144#if defined(WITH_JIT) 1145 GET_JIT_PROF_TABLE(r0) 1146 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1147 cmp r0,#0 1148 bne common_updateProfile 1149 GET_INST_OPCODE(ip) @ extract opcode from rINST 1150 GOTO_OPCODE(ip) @ jump to next instruction 1151#else 1152 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1153 GET_INST_OPCODE(ip) @ extract opcode from rINST 1154 GOTO_OPCODE(ip) @ jump to next instruction 1155#endif 1156 1157/* ------------------------------ */ 1158 .balign 64 1159.L_OP_GOTO_32: /* 0x2a */ 1160/* File: armv5te/OP_GOTO_32.S */ 1161 /* 1162 * Unconditional branch, 32-bit offset. 1163 * 1164 * The branch distance is a signed code-unit offset, which we need to 1165 * double to get a byte offset. 1166 * 1167 * Unlike most opcodes, this one is allowed to branch to itself, so 1168 * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1169 * instruction doesn't affect the V flag, so we need to clear it 1170 * explicitly. 1171 */ 1172 /* goto/32 +AAAAAAAA */ 1173 FETCH(r0, 1) @ r0<- aaaa (lo) 1174 FETCH(r1, 2) @ r1<- AAAA (hi) 1175 cmp ip, ip @ (clear V flag during stall) 1176 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1177 mov r9, r0, asl #1 @ r9<- byte offset 1178 ble common_backwardBranch @ backward branch, do periodic checks 1179#if defined(WITH_JIT) 1180 GET_JIT_PROF_TABLE(r0) 1181 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1182 cmp r0,#0 1183 bne common_updateProfile 1184 GET_INST_OPCODE(ip) @ extract opcode from rINST 1185 GOTO_OPCODE(ip) @ jump to next instruction 1186#else 1187 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1188 GET_INST_OPCODE(ip) @ extract opcode from rINST 1189 GOTO_OPCODE(ip) @ jump to next instruction 1190#endif 1191 1192/* ------------------------------ */ 1193 .balign 64 1194.L_OP_PACKED_SWITCH: /* 0x2b */ 1195/* File: armv5te/OP_PACKED_SWITCH.S */ 1196 /* 1197 * Handle a packed-switch or sparse-switch instruction. In both cases 1198 * we decode it and hand it off to a helper function. 1199 * 1200 * We don't really expect backward branches in a switch statement, but 1201 * they're perfectly legal, so we check for them here. 1202 * 1203 * for: packed-switch, sparse-switch 1204 */ 1205 /* op vAA, +BBBB */ 1206 FETCH(r0, 1) @ r0<- bbbb (lo) 1207 FETCH(r1, 2) @ r1<- BBBB (hi) 1208 mov r3, rINST, lsr #8 @ r3<- AA 1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1210 GET_VREG(r1, r3) @ r1<- vAA 1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1212 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1213 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1214 bmi common_backwardBranch @ backward branch, do periodic checks 1215 beq common_backwardBranch @ (want to use BLE but V is unknown) 1216#if defined(WITH_JIT) 1217 GET_JIT_PROF_TABLE(r0) 1218 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1219 cmp r0,#0 1220 bne common_updateProfile 1221 GET_INST_OPCODE(ip) @ extract opcode from rINST 1222 GOTO_OPCODE(ip) @ jump to next instruction 1223#else 1224 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1225 GET_INST_OPCODE(ip) @ extract opcode from rINST 1226 GOTO_OPCODE(ip) @ jump to next instruction 1227#endif 1228 1229/* ------------------------------ */ 1230 .balign 64 1231.L_OP_SPARSE_SWITCH: /* 0x2c */ 1232/* File: armv5te/OP_SPARSE_SWITCH.S */ 1233/* File: armv5te/OP_PACKED_SWITCH.S */ 1234 /* 1235 * Handle a packed-switch or sparse-switch instruction. In both cases 1236 * we decode it and hand it off to a helper function. 1237 * 1238 * We don't really expect backward branches in a switch statement, but 1239 * they're perfectly legal, so we check for them here. 1240 * 1241 * for: packed-switch, sparse-switch 1242 */ 1243 /* op vAA, +BBBB */ 1244 FETCH(r0, 1) @ r0<- bbbb (lo) 1245 FETCH(r1, 2) @ r1<- BBBB (hi) 1246 mov r3, rINST, lsr #8 @ r3<- AA 1247 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1248 GET_VREG(r1, r3) @ r1<- vAA 1249 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1250 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1251 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1252 bmi common_backwardBranch @ backward branch, do periodic checks 1253 beq common_backwardBranch @ (want to use BLE but V is unknown) 1254#if defined(WITH_JIT) 1255 GET_JIT_PROF_TABLE(r0) 1256 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257 cmp r0,#0 1258 bne common_updateProfile 1259 GET_INST_OPCODE(ip) @ extract opcode from rINST 1260 GOTO_OPCODE(ip) @ jump to next instruction 1261#else 1262 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1263 GET_INST_OPCODE(ip) @ extract opcode from rINST 1264 GOTO_OPCODE(ip) @ jump to next instruction 1265#endif 1266 1267 1268/* ------------------------------ */ 1269 .balign 64 1270.L_OP_CMPL_FLOAT: /* 0x2d */ 1271/* File: armv5te/OP_CMPL_FLOAT.S */ 1272 /* 1273 * Compare two floating-point values. Puts 0, 1, or -1 into the 1274 * destination register based on the results of the comparison. 1275 * 1276 * Provide a "naninst" instruction that puts 1 or -1 into r1 depending 1277 * on what value we'd like to return when one of the operands is NaN. 1278 * 1279 * The operation we're implementing is: 1280 * if (x == y) 1281 * return 0; 1282 * else if (x < y) 1283 * return -1; 1284 * else if (x > y) 1285 * return 1; 1286 * else 1287 * return {-1,1}; // one or both operands was NaN 1288 * 1289 * The straightforward implementation requires 3 calls to functions 1290 * that return a result in r0. We can do it with two calls if our 1291 * EABI library supports __aeabi_cfcmple (only one if we want to check 1292 * for NaN directly): 1293 * check x <= y 1294 * if <, return -1 1295 * if ==, return 0 1296 * check y <= x 1297 * if <, return 1 1298 * return {-1,1} 1299 * 1300 * for: cmpl-float, cmpg-float 1301 */ 1302 /* op vAA, vBB, vCC */ 1303 FETCH(r0, 1) @ r0<- CCBB 1304 and r2, r0, #255 @ r2<- BB 1305 mov r3, r0, lsr #8 @ r3<- CC 1306 GET_VREG(r9, r2) @ r9<- vBB 1307 GET_VREG(r10, r3) @ r10<- vCC 1308 mov r0, r9 @ copy to arg registers 1309 mov r1, r10 1310 bl __aeabi_cfcmple @ cmp <=: C clear if <, Z set if eq 1311 bhi .LOP_CMPL_FLOAT_gt_or_nan @ C set and Z clear, disambiguate 1312 mvncc r1, #0 @ (less than) r1<- -1 1313 moveq r1, #0 @ (equal) r1<- 0, trumps less than 1314.LOP_CMPL_FLOAT_finish: 1315 mov r3, rINST, lsr #8 @ r3<- AA 1316 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1317 SET_VREG(r1, r3) @ vAA<- r1 1318 GET_INST_OPCODE(ip) @ extract opcode from rINST 1319 GOTO_OPCODE(ip) @ jump to next instruction 1320 1321/* ------------------------------ */ 1322 .balign 64 1323.L_OP_CMPG_FLOAT: /* 0x2e */ 1324/* File: armv5te/OP_CMPG_FLOAT.S */ 1325/* File: armv5te/OP_CMPL_FLOAT.S */ 1326 /* 1327 * Compare two floating-point values. Puts 0, 1, or -1 into the 1328 * destination register based on the results of the comparison. 1329 * 1330 * Provide a "naninst" instruction that puts 1 or -1 into r1 depending 1331 * on what value we'd like to return when one of the operands is NaN. 1332 * 1333 * The operation we're implementing is: 1334 * if (x == y) 1335 * return 0; 1336 * else if (x < y) 1337 * return -1; 1338 * else if (x > y) 1339 * return 1; 1340 * else 1341 * return {-1,1}; // one or both operands was NaN 1342 * 1343 * The straightforward implementation requires 3 calls to functions 1344 * that return a result in r0. We can do it with two calls if our 1345 * EABI library supports __aeabi_cfcmple (only one if we want to check 1346 * for NaN directly): 1347 * check x <= y 1348 * if <, return -1 1349 * if ==, return 0 1350 * check y <= x 1351 * if <, return 1 1352 * return {-1,1} 1353 * 1354 * for: cmpl-float, cmpg-float 1355 */ 1356 /* op vAA, vBB, vCC */ 1357 FETCH(r0, 1) @ r0<- CCBB 1358 and r2, r0, #255 @ r2<- BB 1359 mov r3, r0, lsr #8 @ r3<- CC 1360 GET_VREG(r9, r2) @ r9<- vBB 1361 GET_VREG(r10, r3) @ r10<- vCC 1362 mov r0, r9 @ copy to arg registers 1363 mov r1, r10 1364 bl __aeabi_cfcmple @ cmp <=: C clear if <, Z set if eq 1365 bhi .LOP_CMPG_FLOAT_gt_or_nan @ C set and Z clear, disambiguate 1366 mvncc r1, #0 @ (less than) r1<- -1 1367 moveq r1, #0 @ (equal) r1<- 0, trumps less than 1368.LOP_CMPG_FLOAT_finish: 1369 mov r3, rINST, lsr #8 @ r3<- AA 1370 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1371 SET_VREG(r1, r3) @ vAA<- r1 1372 GET_INST_OPCODE(ip) @ extract opcode from rINST 1373 GOTO_OPCODE(ip) @ jump to next instruction 1374 1375 1376/* ------------------------------ */ 1377 .balign 64 1378.L_OP_CMPL_DOUBLE: /* 0x2f */ 1379/* File: armv5te/OP_CMPL_DOUBLE.S */ 1380 /* 1381 * Compare two floating-point values. Puts 0, 1, or -1 into the 1382 * destination register based on the results of the comparison. 1383 * 1384 * Provide a "naninst" instruction that puts 1 or -1 into r1 depending 1385 * on what value we'd like to return when one of the operands is NaN. 1386 * 1387 * See OP_CMPL_FLOAT for an explanation. 1388 * 1389 * For: cmpl-double, cmpg-double 1390 */ 1391 /* op vAA, vBB, vCC */ 1392 FETCH(r0, 1) @ r0<- CCBB 1393 and r9, r0, #255 @ r9<- BB 1394 mov r10, r0, lsr #8 @ r10<- CC 1395 add r9, rFP, r9, lsl #2 @ r9<- &fp[BB] 1396 add r10, rFP, r10, lsl #2 @ r10<- &fp[CC] 1397 ldmia r9, {r0-r1} @ r0/r1<- vBB/vBB+1 1398 ldmia r10, {r2-r3} @ r2/r3<- vCC/vCC+1 1399 bl __aeabi_cdcmple @ cmp <=: C clear if <, Z set if eq 1400 bhi .LOP_CMPL_DOUBLE_gt_or_nan @ C set and Z clear, disambiguate 1401 mvncc r1, #0 @ (less than) r1<- -1 1402 moveq r1, #0 @ (equal) r1<- 0, trumps less than 1403.LOP_CMPL_DOUBLE_finish: 1404 mov r3, rINST, lsr #8 @ r3<- AA 1405 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1406 SET_VREG(r1, r3) @ vAA<- r1 1407 GET_INST_OPCODE(ip) @ extract opcode from rINST 1408 GOTO_OPCODE(ip) @ jump to next instruction 1409 1410/* ------------------------------ */ 1411 .balign 64 1412.L_OP_CMPG_DOUBLE: /* 0x30 */ 1413/* File: armv5te/OP_CMPG_DOUBLE.S */ 1414/* File: armv5te/OP_CMPL_DOUBLE.S */ 1415 /* 1416 * Compare two floating-point values. Puts 0, 1, or -1 into the 1417 * destination register based on the results of the comparison. 1418 * 1419 * Provide a "naninst" instruction that puts 1 or -1 into r1 depending 1420 * on what value we'd like to return when one of the operands is NaN. 1421 * 1422 * See OP_CMPL_FLOAT for an explanation. 1423 * 1424 * For: cmpl-double, cmpg-double 1425 */ 1426 /* op vAA, vBB, vCC */ 1427 FETCH(r0, 1) @ r0<- CCBB 1428 and r9, r0, #255 @ r9<- BB 1429 mov r10, r0, lsr #8 @ r10<- CC 1430 add r9, rFP, r9, lsl #2 @ r9<- &fp[BB] 1431 add r10, rFP, r10, lsl #2 @ r10<- &fp[CC] 1432 ldmia r9, {r0-r1} @ r0/r1<- vBB/vBB+1 1433 ldmia r10, {r2-r3} @ r2/r3<- vCC/vCC+1 1434 bl __aeabi_cdcmple @ cmp <=: C clear if <, Z set if eq 1435 bhi .LOP_CMPG_DOUBLE_gt_or_nan @ C set and Z clear, disambiguate 1436 mvncc r1, #0 @ (less than) r1<- -1 1437 moveq r1, #0 @ (equal) r1<- 0, trumps less than 1438.LOP_CMPG_DOUBLE_finish: 1439 mov r3, rINST, lsr #8 @ r3<- AA 1440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1441 SET_VREG(r1, r3) @ vAA<- r1 1442 GET_INST_OPCODE(ip) @ extract opcode from rINST 1443 GOTO_OPCODE(ip) @ jump to next instruction 1444 1445 1446/* ------------------------------ */ 1447 .balign 64 1448.L_OP_CMP_LONG: /* 0x31 */ 1449/* File: armv5te/OP_CMP_LONG.S */ 1450 /* 1451 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1452 * register based on the results of the comparison. 1453 * 1454 * We load the full values with LDM, but in practice many values could 1455 * be resolved by only looking at the high word. This could be made 1456 * faster or slower by splitting the LDM into a pair of LDRs. 1457 * 1458 * If we just wanted to set condition flags, we could do this: 1459 * subs ip, r0, r2 1460 * sbcs ip, r1, r3 1461 * subeqs ip, r0, r2 1462 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1463 * integer value, which we can do with 2 conditional mov/mvn instructions 1464 * (set 1, set -1; if they're equal we already have 0 in ip), giving 1465 * us a constant 5-cycle path plus a branch at the end to the 1466 * instruction epilogue code. The multi-compare approach below needs 1467 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1468 * in the worst case (the 64-bit values are equal). 1469 */ 1470 /* cmp-long vAA, vBB, vCC */ 1471 FETCH(r0, 1) @ r0<- CCBB 1472 mov r9, rINST, lsr #8 @ r9<- AA 1473 and r2, r0, #255 @ r2<- BB 1474 mov r3, r0, lsr #8 @ r3<- CC 1475 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1476 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1477 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1478 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1479 cmp r1, r3 @ compare (vBB+1, vCC+1) 1480 blt .LOP_CMP_LONG_less @ signed compare on high part 1481 bgt .LOP_CMP_LONG_greater 1482 subs r1, r0, r2 @ r1<- r0 - r2 1483 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1484 bne .LOP_CMP_LONG_less 1485 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1486 1487/* ------------------------------ */ 1488 .balign 64 1489.L_OP_IF_EQ: /* 0x32 */ 1490/* File: armv5te/OP_IF_EQ.S */ 1491/* File: armv5te/bincmp.S */ 1492 /* 1493 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1494 * fragment that specifies the *reverse* comparison to perform, e.g. 1495 * for "if-le" you would use "gt". 1496 * 1497 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1498 */ 1499 /* if-cmp vA, vB, +CCCC */ 1500 mov r0, rINST, lsr #8 @ r0<- A+ 1501 mov r1, rINST, lsr #12 @ r1<- B 1502 and r0, r0, #15 1503 GET_VREG(r3, r1) @ r3<- vB 1504 GET_VREG(r2, r0) @ r2<- vA 1505 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1506 cmp r2, r3 @ compare (vA, vB) 1507 bne 1f @ branch to 1 if comparison failed 1508 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1509 movs r9, r9, asl #1 @ convert to bytes, check sign 1510 bmi common_backwardBranch @ yes, do periodic checks 15111: 1512#if defined(WITH_JIT) 1513 GET_JIT_PROF_TABLE(r0) 1514 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1515 b common_testUpdateProfile 1516#else 1517 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1518 GET_INST_OPCODE(ip) @ extract opcode from rINST 1519 GOTO_OPCODE(ip) @ jump to next instruction 1520#endif 1521 1522 1523/* ------------------------------ */ 1524 .balign 64 1525.L_OP_IF_NE: /* 0x33 */ 1526/* File: armv5te/OP_IF_NE.S */ 1527/* File: armv5te/bincmp.S */ 1528 /* 1529 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1530 * fragment that specifies the *reverse* comparison to perform, e.g. 1531 * for "if-le" you would use "gt". 1532 * 1533 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1534 */ 1535 /* if-cmp vA, vB, +CCCC */ 1536 mov r0, rINST, lsr #8 @ r0<- A+ 1537 mov r1, rINST, lsr #12 @ r1<- B 1538 and r0, r0, #15 1539 GET_VREG(r3, r1) @ r3<- vB 1540 GET_VREG(r2, r0) @ r2<- vA 1541 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1542 cmp r2, r3 @ compare (vA, vB) 1543 beq 1f @ branch to 1 if comparison failed 1544 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1545 movs r9, r9, asl #1 @ convert to bytes, check sign 1546 bmi common_backwardBranch @ yes, do periodic checks 15471: 1548#if defined(WITH_JIT) 1549 GET_JIT_PROF_TABLE(r0) 1550 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1551 b common_testUpdateProfile 1552#else 1553 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1554 GET_INST_OPCODE(ip) @ extract opcode from rINST 1555 GOTO_OPCODE(ip) @ jump to next instruction 1556#endif 1557 1558 1559/* ------------------------------ */ 1560 .balign 64 1561.L_OP_IF_LT: /* 0x34 */ 1562/* File: armv5te/OP_IF_LT.S */ 1563/* File: armv5te/bincmp.S */ 1564 /* 1565 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1566 * fragment that specifies the *reverse* comparison to perform, e.g. 1567 * for "if-le" you would use "gt". 1568 * 1569 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1570 */ 1571 /* if-cmp vA, vB, +CCCC */ 1572 mov r0, rINST, lsr #8 @ r0<- A+ 1573 mov r1, rINST, lsr #12 @ r1<- B 1574 and r0, r0, #15 1575 GET_VREG(r3, r1) @ r3<- vB 1576 GET_VREG(r2, r0) @ r2<- vA 1577 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1578 cmp r2, r3 @ compare (vA, vB) 1579 bge 1f @ branch to 1 if comparison failed 1580 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1581 movs r9, r9, asl #1 @ convert to bytes, check sign 1582 bmi common_backwardBranch @ yes, do periodic checks 15831: 1584#if defined(WITH_JIT) 1585 GET_JIT_PROF_TABLE(r0) 1586 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1587 b common_testUpdateProfile 1588#else 1589 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1590 GET_INST_OPCODE(ip) @ extract opcode from rINST 1591 GOTO_OPCODE(ip) @ jump to next instruction 1592#endif 1593 1594 1595/* ------------------------------ */ 1596 .balign 64 1597.L_OP_IF_GE: /* 0x35 */ 1598/* File: armv5te/OP_IF_GE.S */ 1599/* File: armv5te/bincmp.S */ 1600 /* 1601 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1602 * fragment that specifies the *reverse* comparison to perform, e.g. 1603 * for "if-le" you would use "gt". 1604 * 1605 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1606 */ 1607 /* if-cmp vA, vB, +CCCC */ 1608 mov r0, rINST, lsr #8 @ r0<- A+ 1609 mov r1, rINST, lsr #12 @ r1<- B 1610 and r0, r0, #15 1611 GET_VREG(r3, r1) @ r3<- vB 1612 GET_VREG(r2, r0) @ r2<- vA 1613 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1614 cmp r2, r3 @ compare (vA, vB) 1615 blt 1f @ branch to 1 if comparison failed 1616 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1617 movs r9, r9, asl #1 @ convert to bytes, check sign 1618 bmi common_backwardBranch @ yes, do periodic checks 16191: 1620#if defined(WITH_JIT) 1621 GET_JIT_PROF_TABLE(r0) 1622 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1623 b common_testUpdateProfile 1624#else 1625 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1626 GET_INST_OPCODE(ip) @ extract opcode from rINST 1627 GOTO_OPCODE(ip) @ jump to next instruction 1628#endif 1629 1630 1631/* ------------------------------ */ 1632 .balign 64 1633.L_OP_IF_GT: /* 0x36 */ 1634/* File: armv5te/OP_IF_GT.S */ 1635/* File: armv5te/bincmp.S */ 1636 /* 1637 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1638 * fragment that specifies the *reverse* comparison to perform, e.g. 1639 * for "if-le" you would use "gt". 1640 * 1641 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1642 */ 1643 /* if-cmp vA, vB, +CCCC */ 1644 mov r0, rINST, lsr #8 @ r0<- A+ 1645 mov r1, rINST, lsr #12 @ r1<- B 1646 and r0, r0, #15 1647 GET_VREG(r3, r1) @ r3<- vB 1648 GET_VREG(r2, r0) @ r2<- vA 1649 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1650 cmp r2, r3 @ compare (vA, vB) 1651 ble 1f @ branch to 1 if comparison failed 1652 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1653 movs r9, r9, asl #1 @ convert to bytes, check sign 1654 bmi common_backwardBranch @ yes, do periodic checks 16551: 1656#if defined(WITH_JIT) 1657 GET_JIT_PROF_TABLE(r0) 1658 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1659 b common_testUpdateProfile 1660#else 1661 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1662 GET_INST_OPCODE(ip) @ extract opcode from rINST 1663 GOTO_OPCODE(ip) @ jump to next instruction 1664#endif 1665 1666 1667/* ------------------------------ */ 1668 .balign 64 1669.L_OP_IF_LE: /* 0x37 */ 1670/* File: armv5te/OP_IF_LE.S */ 1671/* File: armv5te/bincmp.S */ 1672 /* 1673 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1674 * fragment that specifies the *reverse* comparison to perform, e.g. 1675 * for "if-le" you would use "gt". 1676 * 1677 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1678 */ 1679 /* if-cmp vA, vB, +CCCC */ 1680 mov r0, rINST, lsr #8 @ r0<- A+ 1681 mov r1, rINST, lsr #12 @ r1<- B 1682 and r0, r0, #15 1683 GET_VREG(r3, r1) @ r3<- vB 1684 GET_VREG(r2, r0) @ r2<- vA 1685 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1686 cmp r2, r3 @ compare (vA, vB) 1687 bgt 1f @ branch to 1 if comparison failed 1688 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1689 movs r9, r9, asl #1 @ convert to bytes, check sign 1690 bmi common_backwardBranch @ yes, do periodic checks 16911: 1692#if defined(WITH_JIT) 1693 GET_JIT_PROF_TABLE(r0) 1694 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1695 b common_testUpdateProfile 1696#else 1697 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1698 GET_INST_OPCODE(ip) @ extract opcode from rINST 1699 GOTO_OPCODE(ip) @ jump to next instruction 1700#endif 1701 1702 1703/* ------------------------------ */ 1704 .balign 64 1705.L_OP_IF_EQZ: /* 0x38 */ 1706/* File: armv5te/OP_IF_EQZ.S */ 1707/* File: armv5te/zcmp.S */ 1708 /* 1709 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1710 * fragment that specifies the *reverse* comparison to perform, e.g. 1711 * for "if-le" you would use "gt". 1712 * 1713 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1714 */ 1715 /* if-cmp vAA, +BBBB */ 1716 mov r0, rINST, lsr #8 @ r0<- AA 1717 GET_VREG(r2, r0) @ r2<- vAA 1718 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1719 cmp r2, #0 @ compare (vA, 0) 1720 bne 1f @ branch to 1 if comparison failed 1721 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1722 movs r9, r9, asl #1 @ convert to bytes, check sign 1723 bmi common_backwardBranch @ backward branch, do periodic checks 17241: 1725#if defined(WITH_JIT) 1726 GET_JIT_PROF_TABLE(r0) 1727 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1728 cmp r0,#0 1729 bne common_updateProfile 1730 GET_INST_OPCODE(ip) @ extract opcode from rINST 1731 GOTO_OPCODE(ip) @ jump to next instruction 1732#else 1733 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1734 GET_INST_OPCODE(ip) @ extract opcode from rINST 1735 GOTO_OPCODE(ip) @ jump to next instruction 1736#endif 1737 1738 1739/* ------------------------------ */ 1740 .balign 64 1741.L_OP_IF_NEZ: /* 0x39 */ 1742/* File: armv5te/OP_IF_NEZ.S */ 1743/* File: armv5te/zcmp.S */ 1744 /* 1745 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1746 * fragment that specifies the *reverse* comparison to perform, e.g. 1747 * for "if-le" you would use "gt". 1748 * 1749 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1750 */ 1751 /* if-cmp vAA, +BBBB */ 1752 mov r0, rINST, lsr #8 @ r0<- AA 1753 GET_VREG(r2, r0) @ r2<- vAA 1754 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1755 cmp r2, #0 @ compare (vA, 0) 1756 beq 1f @ branch to 1 if comparison failed 1757 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1758 movs r9, r9, asl #1 @ convert to bytes, check sign 1759 bmi common_backwardBranch @ backward branch, do periodic checks 17601: 1761#if defined(WITH_JIT) 1762 GET_JIT_PROF_TABLE(r0) 1763 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1764 cmp r0,#0 1765 bne common_updateProfile 1766 GET_INST_OPCODE(ip) @ extract opcode from rINST 1767 GOTO_OPCODE(ip) @ jump to next instruction 1768#else 1769 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1770 GET_INST_OPCODE(ip) @ extract opcode from rINST 1771 GOTO_OPCODE(ip) @ jump to next instruction 1772#endif 1773 1774 1775/* ------------------------------ */ 1776 .balign 64 1777.L_OP_IF_LTZ: /* 0x3a */ 1778/* File: armv5te/OP_IF_LTZ.S */ 1779/* File: armv5te/zcmp.S */ 1780 /* 1781 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1782 * fragment that specifies the *reverse* comparison to perform, e.g. 1783 * for "if-le" you would use "gt". 1784 * 1785 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1786 */ 1787 /* if-cmp vAA, +BBBB */ 1788 mov r0, rINST, lsr #8 @ r0<- AA 1789 GET_VREG(r2, r0) @ r2<- vAA 1790 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1791 cmp r2, #0 @ compare (vA, 0) 1792 bge 1f @ branch to 1 if comparison failed 1793 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1794 movs r9, r9, asl #1 @ convert to bytes, check sign 1795 bmi common_backwardBranch @ backward branch, do periodic checks 17961: 1797#if defined(WITH_JIT) 1798 GET_JIT_PROF_TABLE(r0) 1799 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1800 cmp r0,#0 1801 bne common_updateProfile 1802 GET_INST_OPCODE(ip) @ extract opcode from rINST 1803 GOTO_OPCODE(ip) @ jump to next instruction 1804#else 1805 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1806 GET_INST_OPCODE(ip) @ extract opcode from rINST 1807 GOTO_OPCODE(ip) @ jump to next instruction 1808#endif 1809 1810 1811/* ------------------------------ */ 1812 .balign 64 1813.L_OP_IF_GEZ: /* 0x3b */ 1814/* File: armv5te/OP_IF_GEZ.S */ 1815/* File: armv5te/zcmp.S */ 1816 /* 1817 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1818 * fragment that specifies the *reverse* comparison to perform, e.g. 1819 * for "if-le" you would use "gt". 1820 * 1821 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1822 */ 1823 /* if-cmp vAA, +BBBB */ 1824 mov r0, rINST, lsr #8 @ r0<- AA 1825 GET_VREG(r2, r0) @ r2<- vAA 1826 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1827 cmp r2, #0 @ compare (vA, 0) 1828 blt 1f @ branch to 1 if comparison failed 1829 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1830 movs r9, r9, asl #1 @ convert to bytes, check sign 1831 bmi common_backwardBranch @ backward branch, do periodic checks 18321: 1833#if defined(WITH_JIT) 1834 GET_JIT_PROF_TABLE(r0) 1835 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1836 cmp r0,#0 1837 bne common_updateProfile 1838 GET_INST_OPCODE(ip) @ extract opcode from rINST 1839 GOTO_OPCODE(ip) @ jump to next instruction 1840#else 1841 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1842 GET_INST_OPCODE(ip) @ extract opcode from rINST 1843 GOTO_OPCODE(ip) @ jump to next instruction 1844#endif 1845 1846 1847/* ------------------------------ */ 1848 .balign 64 1849.L_OP_IF_GTZ: /* 0x3c */ 1850/* File: armv5te/OP_IF_GTZ.S */ 1851/* File: armv5te/zcmp.S */ 1852 /* 1853 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1854 * fragment that specifies the *reverse* comparison to perform, e.g. 1855 * for "if-le" you would use "gt". 1856 * 1857 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1858 */ 1859 /* if-cmp vAA, +BBBB */ 1860 mov r0, rINST, lsr #8 @ r0<- AA 1861 GET_VREG(r2, r0) @ r2<- vAA 1862 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1863 cmp r2, #0 @ compare (vA, 0) 1864 ble 1f @ branch to 1 if comparison failed 1865 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1866 movs r9, r9, asl #1 @ convert to bytes, check sign 1867 bmi common_backwardBranch @ backward branch, do periodic checks 18681: 1869#if defined(WITH_JIT) 1870 GET_JIT_PROF_TABLE(r0) 1871 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1872 cmp r0,#0 1873 bne common_updateProfile 1874 GET_INST_OPCODE(ip) @ extract opcode from rINST 1875 GOTO_OPCODE(ip) @ jump to next instruction 1876#else 1877 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1878 GET_INST_OPCODE(ip) @ extract opcode from rINST 1879 GOTO_OPCODE(ip) @ jump to next instruction 1880#endif 1881 1882 1883/* ------------------------------ */ 1884 .balign 64 1885.L_OP_IF_LEZ: /* 0x3d */ 1886/* File: armv5te/OP_IF_LEZ.S */ 1887/* File: armv5te/zcmp.S */ 1888 /* 1889 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1890 * fragment that specifies the *reverse* comparison to perform, e.g. 1891 * for "if-le" you would use "gt". 1892 * 1893 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1894 */ 1895 /* if-cmp vAA, +BBBB */ 1896 mov r0, rINST, lsr #8 @ r0<- AA 1897 GET_VREG(r2, r0) @ r2<- vAA 1898 mov r9, #4 @ r0<- BYTE branch dist for not-taken 1899 cmp r2, #0 @ compare (vA, 0) 1900 bgt 1f @ branch to 1 if comparison failed 1901 FETCH_S(r9, 1) @ r9<- branch offset, in code units 1902 movs r9, r9, asl #1 @ convert to bytes, check sign 1903 bmi common_backwardBranch @ backward branch, do periodic checks 19041: 1905#if defined(WITH_JIT) 1906 GET_JIT_PROF_TABLE(r0) 1907 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1908 cmp r0,#0 1909 bne common_updateProfile 1910 GET_INST_OPCODE(ip) @ extract opcode from rINST 1911 GOTO_OPCODE(ip) @ jump to next instruction 1912#else 1913 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1914 GET_INST_OPCODE(ip) @ extract opcode from rINST 1915 GOTO_OPCODE(ip) @ jump to next instruction 1916#endif 1917 1918 1919/* ------------------------------ */ 1920 .balign 64 1921.L_OP_UNUSED_3E: /* 0x3e */ 1922/* File: armv5te/OP_UNUSED_3E.S */ 1923/* File: armv5te/unused.S */ 1924 bl common_abort 1925 1926 1927/* ------------------------------ */ 1928 .balign 64 1929.L_OP_UNUSED_3F: /* 0x3f */ 1930/* File: armv5te/OP_UNUSED_3F.S */ 1931/* File: armv5te/unused.S */ 1932 bl common_abort 1933 1934 1935/* ------------------------------ */ 1936 .balign 64 1937.L_OP_UNUSED_40: /* 0x40 */ 1938/* File: armv5te/OP_UNUSED_40.S */ 1939/* File: armv5te/unused.S */ 1940 bl common_abort 1941 1942 1943/* ------------------------------ */ 1944 .balign 64 1945.L_OP_UNUSED_41: /* 0x41 */ 1946/* File: armv5te/OP_UNUSED_41.S */ 1947/* File: armv5te/unused.S */ 1948 bl common_abort 1949 1950 1951/* ------------------------------ */ 1952 .balign 64 1953.L_OP_UNUSED_42: /* 0x42 */ 1954/* File: armv5te/OP_UNUSED_42.S */ 1955/* File: armv5te/unused.S */ 1956 bl common_abort 1957 1958 1959/* ------------------------------ */ 1960 .balign 64 1961.L_OP_UNUSED_43: /* 0x43 */ 1962/* File: armv5te/OP_UNUSED_43.S */ 1963/* File: armv5te/unused.S */ 1964 bl common_abort 1965 1966 1967/* ------------------------------ */ 1968 .balign 64 1969.L_OP_AGET: /* 0x44 */ 1970/* File: armv5te/OP_AGET.S */ 1971 /* 1972 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1973 * 1974 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1975 * instructions. We use a pair of FETCH_Bs instead. 1976 * 1977 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1978 */ 1979 /* op vAA, vBB, vCC */ 1980 FETCH_B(r2, 1, 0) @ r2<- BB 1981 mov r9, rINST, lsr #8 @ r9<- AA 1982 FETCH_B(r3, 1, 1) @ r3<- CC 1983 GET_VREG(r0, r2) @ r0<- vBB (array object) 1984 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1985 cmp r0, #0 @ null array object? 1986 beq common_errNullObject @ yes, bail 1987 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1988 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1989 cmp r1, r3 @ compare unsigned index, length 1990 bcs common_errArrayIndex @ index >= length, bail 1991 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1992 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1993 GET_INST_OPCODE(ip) @ extract opcode from rINST 1994 SET_VREG(r2, r9) @ vAA<- r2 1995 GOTO_OPCODE(ip) @ jump to next instruction 1996 1997/* ------------------------------ */ 1998 .balign 64 1999.L_OP_AGET_WIDE: /* 0x45 */ 2000/* File: armv5te/OP_AGET_WIDE.S */ 2001 /* 2002 * Array get, 64 bits. vAA <- vBB[vCC]. 2003 * 2004 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2005 */ 2006 /* aget-wide vAA, vBB, vCC */ 2007 FETCH(r0, 1) @ r0<- CCBB 2008 mov r9, rINST, lsr #8 @ r9<- AA 2009 and r2, r0, #255 @ r2<- BB 2010 mov r3, r0, lsr #8 @ r3<- CC 2011 GET_VREG(r0, r2) @ r0<- vBB (array object) 2012 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2013 cmp r0, #0 @ null array object? 2014 beq common_errNullObject @ yes, bail 2015 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2016 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2017 cmp r1, r3 @ compare unsigned index, length 2018 bcc .LOP_AGET_WIDE_finish @ okay, continue below 2019 b common_errArrayIndex @ index >= length, bail 2020 @ May want to swap the order of these two branches depending on how the 2021 @ branch prediction (if any) handles conditional forward branches vs. 2022 @ unconditional forward branches. 2023 2024/* ------------------------------ */ 2025 .balign 64 2026.L_OP_AGET_OBJECT: /* 0x46 */ 2027/* File: armv5te/OP_AGET_OBJECT.S */ 2028/* File: armv5te/OP_AGET.S */ 2029 /* 2030 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2031 * 2032 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2033 * instructions. We use a pair of FETCH_Bs instead. 2034 * 2035 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2036 */ 2037 /* op vAA, vBB, vCC */ 2038 FETCH_B(r2, 1, 0) @ r2<- BB 2039 mov r9, rINST, lsr #8 @ r9<- AA 2040 FETCH_B(r3, 1, 1) @ r3<- CC 2041 GET_VREG(r0, r2) @ r0<- vBB (array object) 2042 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2043 cmp r0, #0 @ null array object? 2044 beq common_errNullObject @ yes, bail 2045 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2046 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2047 cmp r1, r3 @ compare unsigned index, length 2048 bcs common_errArrayIndex @ index >= length, bail 2049 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2050 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2051 GET_INST_OPCODE(ip) @ extract opcode from rINST 2052 SET_VREG(r2, r9) @ vAA<- r2 2053 GOTO_OPCODE(ip) @ jump to next instruction 2054 2055 2056/* ------------------------------ */ 2057 .balign 64 2058.L_OP_AGET_BOOLEAN: /* 0x47 */ 2059/* File: armv5te/OP_AGET_BOOLEAN.S */ 2060/* File: armv5te/OP_AGET.S */ 2061 /* 2062 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2063 * 2064 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2065 * instructions. We use a pair of FETCH_Bs instead. 2066 * 2067 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2068 */ 2069 /* op vAA, vBB, vCC */ 2070 FETCH_B(r2, 1, 0) @ r2<- BB 2071 mov r9, rINST, lsr #8 @ r9<- AA 2072 FETCH_B(r3, 1, 1) @ r3<- CC 2073 GET_VREG(r0, r2) @ r0<- vBB (array object) 2074 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2075 cmp r0, #0 @ null array object? 2076 beq common_errNullObject @ yes, bail 2077 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2078 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2079 cmp r1, r3 @ compare unsigned index, length 2080 bcs common_errArrayIndex @ index >= length, bail 2081 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2082 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2083 GET_INST_OPCODE(ip) @ extract opcode from rINST 2084 SET_VREG(r2, r9) @ vAA<- r2 2085 GOTO_OPCODE(ip) @ jump to next instruction 2086 2087 2088/* ------------------------------ */ 2089 .balign 64 2090.L_OP_AGET_BYTE: /* 0x48 */ 2091/* File: armv5te/OP_AGET_BYTE.S */ 2092/* File: armv5te/OP_AGET.S */ 2093 /* 2094 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2095 * 2096 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2097 * instructions. We use a pair of FETCH_Bs instead. 2098 * 2099 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2100 */ 2101 /* op vAA, vBB, vCC */ 2102 FETCH_B(r2, 1, 0) @ r2<- BB 2103 mov r9, rINST, lsr #8 @ r9<- AA 2104 FETCH_B(r3, 1, 1) @ r3<- CC 2105 GET_VREG(r0, r2) @ r0<- vBB (array object) 2106 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2107 cmp r0, #0 @ null array object? 2108 beq common_errNullObject @ yes, bail 2109 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2110 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2111 cmp r1, r3 @ compare unsigned index, length 2112 bcs common_errArrayIndex @ index >= length, bail 2113 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2114 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2115 GET_INST_OPCODE(ip) @ extract opcode from rINST 2116 SET_VREG(r2, r9) @ vAA<- r2 2117 GOTO_OPCODE(ip) @ jump to next instruction 2118 2119 2120/* ------------------------------ */ 2121 .balign 64 2122.L_OP_AGET_CHAR: /* 0x49 */ 2123/* File: armv5te/OP_AGET_CHAR.S */ 2124/* File: armv5te/OP_AGET.S */ 2125 /* 2126 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2127 * 2128 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2129 * instructions. We use a pair of FETCH_Bs instead. 2130 * 2131 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2132 */ 2133 /* op vAA, vBB, vCC */ 2134 FETCH_B(r2, 1, 0) @ r2<- BB 2135 mov r9, rINST, lsr #8 @ r9<- AA 2136 FETCH_B(r3, 1, 1) @ r3<- CC 2137 GET_VREG(r0, r2) @ r0<- vBB (array object) 2138 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2139 cmp r0, #0 @ null array object? 2140 beq common_errNullObject @ yes, bail 2141 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2142 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2143 cmp r1, r3 @ compare unsigned index, length 2144 bcs common_errArrayIndex @ index >= length, bail 2145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2146 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2147 GET_INST_OPCODE(ip) @ extract opcode from rINST 2148 SET_VREG(r2, r9) @ vAA<- r2 2149 GOTO_OPCODE(ip) @ jump to next instruction 2150 2151 2152/* ------------------------------ */ 2153 .balign 64 2154.L_OP_AGET_SHORT: /* 0x4a */ 2155/* File: armv5te/OP_AGET_SHORT.S */ 2156/* File: armv5te/OP_AGET.S */ 2157 /* 2158 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2159 * 2160 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2161 * instructions. We use a pair of FETCH_Bs instead. 2162 * 2163 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2164 */ 2165 /* op vAA, vBB, vCC */ 2166 FETCH_B(r2, 1, 0) @ r2<- BB 2167 mov r9, rINST, lsr #8 @ r9<- AA 2168 FETCH_B(r3, 1, 1) @ r3<- CC 2169 GET_VREG(r0, r2) @ r0<- vBB (array object) 2170 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2171 cmp r0, #0 @ null array object? 2172 beq common_errNullObject @ yes, bail 2173 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2174 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2175 cmp r1, r3 @ compare unsigned index, length 2176 bcs common_errArrayIndex @ index >= length, bail 2177 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2178 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2179 GET_INST_OPCODE(ip) @ extract opcode from rINST 2180 SET_VREG(r2, r9) @ vAA<- r2 2181 GOTO_OPCODE(ip) @ jump to next instruction 2182 2183 2184/* ------------------------------ */ 2185 .balign 64 2186.L_OP_APUT: /* 0x4b */ 2187/* File: armv5te/OP_APUT.S */ 2188 /* 2189 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2190 * 2191 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2192 * instructions. We use a pair of FETCH_Bs instead. 2193 * 2194 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2195 */ 2196 /* op vAA, vBB, vCC */ 2197 FETCH_B(r2, 1, 0) @ r2<- BB 2198 mov r9, rINST, lsr #8 @ r9<- AA 2199 FETCH_B(r3, 1, 1) @ r3<- CC 2200 GET_VREG(r0, r2) @ r0<- vBB (array object) 2201 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2202 cmp r0, #0 @ null array object? 2203 beq common_errNullObject @ yes, bail 2204 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2205 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2206 cmp r1, r3 @ compare unsigned index, length 2207 bcs common_errArrayIndex @ index >= length, bail 2208 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2209 GET_VREG(r2, r9) @ r2<- vAA 2210 GET_INST_OPCODE(ip) @ extract opcode from rINST 2211 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2212 GOTO_OPCODE(ip) @ jump to next instruction 2213 2214/* ------------------------------ */ 2215 .balign 64 2216.L_OP_APUT_WIDE: /* 0x4c */ 2217/* File: armv5te/OP_APUT_WIDE.S */ 2218 /* 2219 * Array put, 64 bits. vBB[vCC] <- vAA. 2220 * 2221 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2222 */ 2223 /* aput-wide vAA, vBB, vCC */ 2224 FETCH(r0, 1) @ r0<- CCBB 2225 mov r9, rINST, lsr #8 @ r9<- AA 2226 and r2, r0, #255 @ r2<- BB 2227 mov r3, r0, lsr #8 @ r3<- CC 2228 GET_VREG(r0, r2) @ r0<- vBB (array object) 2229 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2230 cmp r0, #0 @ null array object? 2231 beq common_errNullObject @ yes, bail 2232 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2233 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2234 cmp r1, r3 @ compare unsigned index, length 2235 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2236 bcc .LOP_APUT_WIDE_finish @ okay, continue below 2237 b common_errArrayIndex @ index >= length, bail 2238 @ May want to swap the order of these two branches depending on how the 2239 @ branch prediction (if any) handles conditional forward branches vs. 2240 @ unconditional forward branches. 2241 2242/* ------------------------------ */ 2243 .balign 64 2244.L_OP_APUT_OBJECT: /* 0x4d */ 2245/* File: armv5te/OP_APUT_OBJECT.S */ 2246 /* 2247 * Store an object into an array. vBB[vCC] <- vAA. 2248 */ 2249 /* op vAA, vBB, vCC */ 2250 FETCH(r0, 1) @ r0<- CCBB 2251 mov r9, rINST, lsr #8 @ r9<- AA 2252 and r2, r0, #255 @ r2<- BB 2253 mov r3, r0, lsr #8 @ r3<- CC 2254 GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2255 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2256 cmp rINST, #0 @ null array object? 2257 GET_VREG(r9, r9) @ r9<- vAA 2258 beq common_errNullObject @ yes, bail 2259 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2260 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 2261 cmp r1, r3 @ compare unsigned index, length 2262 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2263 b common_errArrayIndex @ index >= length, bail 2264 2265 2266/* ------------------------------ */ 2267 .balign 64 2268.L_OP_APUT_BOOLEAN: /* 0x4e */ 2269/* File: armv5te/OP_APUT_BOOLEAN.S */ 2270/* File: armv5te/OP_APUT.S */ 2271 /* 2272 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2273 * 2274 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2275 * instructions. We use a pair of FETCH_Bs instead. 2276 * 2277 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2278 */ 2279 /* op vAA, vBB, vCC */ 2280 FETCH_B(r2, 1, 0) @ r2<- BB 2281 mov r9, rINST, lsr #8 @ r9<- AA 2282 FETCH_B(r3, 1, 1) @ r3<- CC 2283 GET_VREG(r0, r2) @ r0<- vBB (array object) 2284 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2285 cmp r0, #0 @ null array object? 2286 beq common_errNullObject @ yes, bail 2287 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2288 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2289 cmp r1, r3 @ compare unsigned index, length 2290 bcs common_errArrayIndex @ index >= length, bail 2291 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2292 GET_VREG(r2, r9) @ r2<- vAA 2293 GET_INST_OPCODE(ip) @ extract opcode from rINST 2294 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2295 GOTO_OPCODE(ip) @ jump to next instruction 2296 2297 2298/* ------------------------------ */ 2299 .balign 64 2300.L_OP_APUT_BYTE: /* 0x4f */ 2301/* File: armv5te/OP_APUT_BYTE.S */ 2302/* File: armv5te/OP_APUT.S */ 2303 /* 2304 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2305 * 2306 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2307 * instructions. We use a pair of FETCH_Bs instead. 2308 * 2309 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2310 */ 2311 /* op vAA, vBB, vCC */ 2312 FETCH_B(r2, 1, 0) @ r2<- BB 2313 mov r9, rINST, lsr #8 @ r9<- AA 2314 FETCH_B(r3, 1, 1) @ r3<- CC 2315 GET_VREG(r0, r2) @ r0<- vBB (array object) 2316 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2317 cmp r0, #0 @ null array object? 2318 beq common_errNullObject @ yes, bail 2319 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2320 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2321 cmp r1, r3 @ compare unsigned index, length 2322 bcs common_errArrayIndex @ index >= length, bail 2323 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2324 GET_VREG(r2, r9) @ r2<- vAA 2325 GET_INST_OPCODE(ip) @ extract opcode from rINST 2326 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2327 GOTO_OPCODE(ip) @ jump to next instruction 2328 2329 2330/* ------------------------------ */ 2331 .balign 64 2332.L_OP_APUT_CHAR: /* 0x50 */ 2333/* File: armv5te/OP_APUT_CHAR.S */ 2334/* File: armv5te/OP_APUT.S */ 2335 /* 2336 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2337 * 2338 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2339 * instructions. We use a pair of FETCH_Bs instead. 2340 * 2341 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2342 */ 2343 /* op vAA, vBB, vCC */ 2344 FETCH_B(r2, 1, 0) @ r2<- BB 2345 mov r9, rINST, lsr #8 @ r9<- AA 2346 FETCH_B(r3, 1, 1) @ r3<- CC 2347 GET_VREG(r0, r2) @ r0<- vBB (array object) 2348 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2349 cmp r0, #0 @ null array object? 2350 beq common_errNullObject @ yes, bail 2351 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2352 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2353 cmp r1, r3 @ compare unsigned index, length 2354 bcs common_errArrayIndex @ index >= length, bail 2355 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2356 GET_VREG(r2, r9) @ r2<- vAA 2357 GET_INST_OPCODE(ip) @ extract opcode from rINST 2358 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2359 GOTO_OPCODE(ip) @ jump to next instruction 2360 2361 2362/* ------------------------------ */ 2363 .balign 64 2364.L_OP_APUT_SHORT: /* 0x51 */ 2365/* File: armv5te/OP_APUT_SHORT.S */ 2366/* File: armv5te/OP_APUT.S */ 2367 /* 2368 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2369 * 2370 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2371 * instructions. We use a pair of FETCH_Bs instead. 2372 * 2373 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2374 */ 2375 /* op vAA, vBB, vCC */ 2376 FETCH_B(r2, 1, 0) @ r2<- BB 2377 mov r9, rINST, lsr #8 @ r9<- AA 2378 FETCH_B(r3, 1, 1) @ r3<- CC 2379 GET_VREG(r0, r2) @ r0<- vBB (array object) 2380 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2381 cmp r0, #0 @ null array object? 2382 beq common_errNullObject @ yes, bail 2383 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2384 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2385 cmp r1, r3 @ compare unsigned index, length 2386 bcs common_errArrayIndex @ index >= length, bail 2387 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2388 GET_VREG(r2, r9) @ r2<- vAA 2389 GET_INST_OPCODE(ip) @ extract opcode from rINST 2390 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2391 GOTO_OPCODE(ip) @ jump to next instruction 2392 2393 2394/* ------------------------------ */ 2395 .balign 64 2396.L_OP_IGET: /* 0x52 */ 2397/* File: armv5te/OP_IGET.S */ 2398 /* 2399 * General 32-bit instance field get. 2400 * 2401 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2402 */ 2403 /* op vA, vB, field@CCCC */ 2404 mov r0, rINST, lsr #12 @ r0<- B 2405 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2406 FETCH(r1, 1) @ r1<- field ref CCCC 2407 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2408 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2409 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2410 cmp r0, #0 @ is resolved entry null? 2411 bne .LOP_IGET_finish @ no, already resolved 24128: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2413 EXPORT_PC() @ resolve() could throw 2414 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2415 bl dvmResolveInstField @ r0<- resolved InstField ptr 2416 cmp r0, #0 2417 bne .LOP_IGET_finish 2418 b common_exceptionThrown 2419 2420/* ------------------------------ */ 2421 .balign 64 2422.L_OP_IGET_WIDE: /* 0x53 */ 2423/* File: armv5te/OP_IGET_WIDE.S */ 2424 /* 2425 * Wide 32-bit instance field get. 2426 */ 2427 /* iget-wide vA, vB, field@CCCC */ 2428 mov r0, rINST, lsr #12 @ r0<- B 2429 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2430 FETCH(r1, 1) @ r1<- field ref CCCC 2431 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2432 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2433 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2434 cmp r0, #0 @ is resolved entry null? 2435 bne .LOP_IGET_WIDE_finish @ no, already resolved 24368: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2437 EXPORT_PC() @ resolve() could throw 2438 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2439 bl dvmResolveInstField @ r0<- resolved InstField ptr 2440 cmp r0, #0 2441 bne .LOP_IGET_WIDE_finish 2442 b common_exceptionThrown 2443 2444/* ------------------------------ */ 2445 .balign 64 2446.L_OP_IGET_OBJECT: /* 0x54 */ 2447/* File: armv5te/OP_IGET_OBJECT.S */ 2448/* File: armv5te/OP_IGET.S */ 2449 /* 2450 * General 32-bit instance field get. 2451 * 2452 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2453 */ 2454 /* op vA, vB, field@CCCC */ 2455 mov r0, rINST, lsr #12 @ r0<- B 2456 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2457 FETCH(r1, 1) @ r1<- field ref CCCC 2458 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2459 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2460 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2461 cmp r0, #0 @ is resolved entry null? 2462 bne .LOP_IGET_OBJECT_finish @ no, already resolved 24638: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2464 EXPORT_PC() @ resolve() could throw 2465 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2466 bl dvmResolveInstField @ r0<- resolved InstField ptr 2467 cmp r0, #0 2468 bne .LOP_IGET_OBJECT_finish 2469 b common_exceptionThrown 2470 2471 2472/* ------------------------------ */ 2473 .balign 64 2474.L_OP_IGET_BOOLEAN: /* 0x55 */ 2475/* File: armv5te/OP_IGET_BOOLEAN.S */ 2476@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2477/* File: armv5te/OP_IGET.S */ 2478 /* 2479 * General 32-bit instance field get. 2480 * 2481 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2482 */ 2483 /* op vA, vB, field@CCCC */ 2484 mov r0, rINST, lsr #12 @ r0<- B 2485 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2486 FETCH(r1, 1) @ r1<- field ref CCCC 2487 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2488 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2489 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2490 cmp r0, #0 @ is resolved entry null? 2491 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 24928: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2493 EXPORT_PC() @ resolve() could throw 2494 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2495 bl dvmResolveInstField @ r0<- resolved InstField ptr 2496 cmp r0, #0 2497 bne .LOP_IGET_BOOLEAN_finish 2498 b common_exceptionThrown 2499 2500 2501/* ------------------------------ */ 2502 .balign 64 2503.L_OP_IGET_BYTE: /* 0x56 */ 2504/* File: armv5te/OP_IGET_BYTE.S */ 2505@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2506/* File: armv5te/OP_IGET.S */ 2507 /* 2508 * General 32-bit instance field get. 2509 * 2510 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2511 */ 2512 /* op vA, vB, field@CCCC */ 2513 mov r0, rINST, lsr #12 @ r0<- B 2514 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2515 FETCH(r1, 1) @ r1<- field ref CCCC 2516 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2517 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2518 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2519 cmp r0, #0 @ is resolved entry null? 2520 bne .LOP_IGET_BYTE_finish @ no, already resolved 25218: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2522 EXPORT_PC() @ resolve() could throw 2523 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2524 bl dvmResolveInstField @ r0<- resolved InstField ptr 2525 cmp r0, #0 2526 bne .LOP_IGET_BYTE_finish 2527 b common_exceptionThrown 2528 2529 2530/* ------------------------------ */ 2531 .balign 64 2532.L_OP_IGET_CHAR: /* 0x57 */ 2533/* File: armv5te/OP_IGET_CHAR.S */ 2534@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2535/* File: armv5te/OP_IGET.S */ 2536 /* 2537 * General 32-bit instance field get. 2538 * 2539 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2540 */ 2541 /* op vA, vB, field@CCCC */ 2542 mov r0, rINST, lsr #12 @ r0<- B 2543 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2544 FETCH(r1, 1) @ r1<- field ref CCCC 2545 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2546 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2547 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2548 cmp r0, #0 @ is resolved entry null? 2549 bne .LOP_IGET_CHAR_finish @ no, already resolved 25508: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2551 EXPORT_PC() @ resolve() could throw 2552 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2553 bl dvmResolveInstField @ r0<- resolved InstField ptr 2554 cmp r0, #0 2555 bne .LOP_IGET_CHAR_finish 2556 b common_exceptionThrown 2557 2558 2559/* ------------------------------ */ 2560 .balign 64 2561.L_OP_IGET_SHORT: /* 0x58 */ 2562/* File: armv5te/OP_IGET_SHORT.S */ 2563@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2564/* File: armv5te/OP_IGET.S */ 2565 /* 2566 * General 32-bit instance field get. 2567 * 2568 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2569 */ 2570 /* op vA, vB, field@CCCC */ 2571 mov r0, rINST, lsr #12 @ r0<- B 2572 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2573 FETCH(r1, 1) @ r1<- field ref CCCC 2574 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2575 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2576 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2577 cmp r0, #0 @ is resolved entry null? 2578 bne .LOP_IGET_SHORT_finish @ no, already resolved 25798: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2580 EXPORT_PC() @ resolve() could throw 2581 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2582 bl dvmResolveInstField @ r0<- resolved InstField ptr 2583 cmp r0, #0 2584 bne .LOP_IGET_SHORT_finish 2585 b common_exceptionThrown 2586 2587 2588/* ------------------------------ */ 2589 .balign 64 2590.L_OP_IPUT: /* 0x59 */ 2591/* File: armv5te/OP_IPUT.S */ 2592 /* 2593 * General 32-bit instance field put. 2594 * 2595 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2596 */ 2597 /* op vA, vB, field@CCCC */ 2598 mov r0, rINST, lsr #12 @ r0<- B 2599 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2600 FETCH(r1, 1) @ r1<- field ref CCCC 2601 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2602 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2603 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2604 cmp r0, #0 @ is resolved entry null? 2605 bne .LOP_IPUT_finish @ no, already resolved 26068: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2607 EXPORT_PC() @ resolve() could throw 2608 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2609 bl dvmResolveInstField @ r0<- resolved InstField ptr 2610 cmp r0, #0 @ success? 2611 bne .LOP_IPUT_finish @ yes, finish up 2612 b common_exceptionThrown 2613 2614/* ------------------------------ */ 2615 .balign 64 2616.L_OP_IPUT_WIDE: /* 0x5a */ 2617/* File: armv5te/OP_IPUT_WIDE.S */ 2618 /* iput-wide vA, vB, field@CCCC */ 2619 mov r0, rINST, lsr #12 @ r0<- B 2620 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2621 FETCH(r1, 1) @ r1<- field ref CCCC 2622 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2623 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2624 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2625 cmp r0, #0 @ is resolved entry null? 2626 bne .LOP_IPUT_WIDE_finish @ no, already resolved 26278: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2628 EXPORT_PC() @ resolve() could throw 2629 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2630 bl dvmResolveInstField @ r0<- resolved InstField ptr 2631 cmp r0, #0 @ success? 2632 bne .LOP_IPUT_WIDE_finish @ yes, finish up 2633 b common_exceptionThrown 2634 2635/* ------------------------------ */ 2636 .balign 64 2637.L_OP_IPUT_OBJECT: /* 0x5b */ 2638/* File: armv5te/OP_IPUT_OBJECT.S */ 2639 /* 2640 * 32-bit instance field put. 2641 * 2642 * for: iput-object, iput-object-volatile 2643 */ 2644 /* op vA, vB, field@CCCC */ 2645 mov r0, rINST, lsr #12 @ r0<- B 2646 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2647 FETCH(r1, 1) @ r1<- field ref CCCC 2648 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2649 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2650 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2651 cmp r0, #0 @ is resolved entry null? 2652 bne .LOP_IPUT_OBJECT_finish @ no, already resolved 26538: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2654 EXPORT_PC() @ resolve() could throw 2655 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2656 bl dvmResolveInstField @ r0<- resolved InstField ptr 2657 cmp r0, #0 @ success? 2658 bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2659 b common_exceptionThrown 2660 2661/* ------------------------------ */ 2662 .balign 64 2663.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2664/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2665@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2666/* File: armv5te/OP_IPUT.S */ 2667 /* 2668 * General 32-bit instance field put. 2669 * 2670 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2671 */ 2672 /* op vA, vB, field@CCCC */ 2673 mov r0, rINST, lsr #12 @ r0<- B 2674 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2675 FETCH(r1, 1) @ r1<- field ref CCCC 2676 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2677 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2678 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2679 cmp r0, #0 @ is resolved entry null? 2680 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 26818: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2682 EXPORT_PC() @ resolve() could throw 2683 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2684 bl dvmResolveInstField @ r0<- resolved InstField ptr 2685 cmp r0, #0 @ success? 2686 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2687 b common_exceptionThrown 2688 2689 2690/* ------------------------------ */ 2691 .balign 64 2692.L_OP_IPUT_BYTE: /* 0x5d */ 2693/* File: armv5te/OP_IPUT_BYTE.S */ 2694@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2695/* File: armv5te/OP_IPUT.S */ 2696 /* 2697 * General 32-bit instance field put. 2698 * 2699 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2700 */ 2701 /* op vA, vB, field@CCCC */ 2702 mov r0, rINST, lsr #12 @ r0<- B 2703 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2704 FETCH(r1, 1) @ r1<- field ref CCCC 2705 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2706 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2707 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2708 cmp r0, #0 @ is resolved entry null? 2709 bne .LOP_IPUT_BYTE_finish @ no, already resolved 27108: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2711 EXPORT_PC() @ resolve() could throw 2712 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2713 bl dvmResolveInstField @ r0<- resolved InstField ptr 2714 cmp r0, #0 @ success? 2715 bne .LOP_IPUT_BYTE_finish @ yes, finish up 2716 b common_exceptionThrown 2717 2718 2719/* ------------------------------ */ 2720 .balign 64 2721.L_OP_IPUT_CHAR: /* 0x5e */ 2722/* File: armv5te/OP_IPUT_CHAR.S */ 2723@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2724/* File: armv5te/OP_IPUT.S */ 2725 /* 2726 * General 32-bit instance field put. 2727 * 2728 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2729 */ 2730 /* op vA, vB, field@CCCC */ 2731 mov r0, rINST, lsr #12 @ r0<- B 2732 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2733 FETCH(r1, 1) @ r1<- field ref CCCC 2734 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2735 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2736 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2737 cmp r0, #0 @ is resolved entry null? 2738 bne .LOP_IPUT_CHAR_finish @ no, already resolved 27398: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2740 EXPORT_PC() @ resolve() could throw 2741 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2742 bl dvmResolveInstField @ r0<- resolved InstField ptr 2743 cmp r0, #0 @ success? 2744 bne .LOP_IPUT_CHAR_finish @ yes, finish up 2745 b common_exceptionThrown 2746 2747 2748/* ------------------------------ */ 2749 .balign 64 2750.L_OP_IPUT_SHORT: /* 0x5f */ 2751/* File: armv5te/OP_IPUT_SHORT.S */ 2752@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2753/* File: armv5te/OP_IPUT.S */ 2754 /* 2755 * General 32-bit instance field put. 2756 * 2757 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2758 */ 2759 /* op vA, vB, field@CCCC */ 2760 mov r0, rINST, lsr #12 @ r0<- B 2761 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2762 FETCH(r1, 1) @ r1<- field ref CCCC 2763 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2764 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2765 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2766 cmp r0, #0 @ is resolved entry null? 2767 bne .LOP_IPUT_SHORT_finish @ no, already resolved 27688: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2769 EXPORT_PC() @ resolve() could throw 2770 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2771 bl dvmResolveInstField @ r0<- resolved InstField ptr 2772 cmp r0, #0 @ success? 2773 bne .LOP_IPUT_SHORT_finish @ yes, finish up 2774 b common_exceptionThrown 2775 2776 2777/* ------------------------------ */ 2778 .balign 64 2779.L_OP_SGET: /* 0x60 */ 2780/* File: armv5te/OP_SGET.S */ 2781 /* 2782 * General 32-bit SGET handler. 2783 * 2784 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2785 */ 2786 /* op vAA, field@BBBB */ 2787 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2788 FETCH(r1, 1) @ r1<- field ref BBBB 2789 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2790 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2791 cmp r0, #0 @ is resolved entry null? 2792 beq .LOP_SGET_resolve @ yes, do resolve 2793.LOP_SGET_finish: @ field ptr in r0 2794 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2795 @ no-op @ acquiring load 2796 mov r2, rINST, lsr #8 @ r2<- AA 2797 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2798 SET_VREG(r1, r2) @ fp[AA]<- r1 2799 GET_INST_OPCODE(ip) @ extract opcode from rINST 2800 GOTO_OPCODE(ip) @ jump to next instruction 2801 2802/* ------------------------------ */ 2803 .balign 64 2804.L_OP_SGET_WIDE: /* 0x61 */ 2805/* File: armv5te/OP_SGET_WIDE.S */ 2806 /* 2807 * 64-bit SGET handler. 2808 */ 2809 /* sget-wide vAA, field@BBBB */ 2810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2811 FETCH(r1, 1) @ r1<- field ref BBBB 2812 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2813 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2814 cmp r0, #0 @ is resolved entry null? 2815 beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2816.LOP_SGET_WIDE_finish: 2817 mov r9, rINST, lsr #8 @ r9<- AA 2818 .if 0 2819 add r0, r0, #offStaticField_value @ r0<- pointer to data 2820 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2821 .else 2822 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2823 .endif 2824 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2825 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2826 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2827 GET_INST_OPCODE(ip) @ extract opcode from rINST 2828 GOTO_OPCODE(ip) @ jump to next instruction 2829 2830/* ------------------------------ */ 2831 .balign 64 2832.L_OP_SGET_OBJECT: /* 0x62 */ 2833/* File: armv5te/OP_SGET_OBJECT.S */ 2834/* File: armv5te/OP_SGET.S */ 2835 /* 2836 * General 32-bit SGET handler. 2837 * 2838 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2839 */ 2840 /* op vAA, field@BBBB */ 2841 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2842 FETCH(r1, 1) @ r1<- field ref BBBB 2843 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2844 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2845 cmp r0, #0 @ is resolved entry null? 2846 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2847.LOP_SGET_OBJECT_finish: @ field ptr in r0 2848 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2849 @ no-op @ acquiring load 2850 mov r2, rINST, lsr #8 @ r2<- AA 2851 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2852 SET_VREG(r1, r2) @ fp[AA]<- r1 2853 GET_INST_OPCODE(ip) @ extract opcode from rINST 2854 GOTO_OPCODE(ip) @ jump to next instruction 2855 2856 2857/* ------------------------------ */ 2858 .balign 64 2859.L_OP_SGET_BOOLEAN: /* 0x63 */ 2860/* File: armv5te/OP_SGET_BOOLEAN.S */ 2861/* File: armv5te/OP_SGET.S */ 2862 /* 2863 * General 32-bit SGET handler. 2864 * 2865 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2866 */ 2867 /* op vAA, field@BBBB */ 2868 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2869 FETCH(r1, 1) @ r1<- field ref BBBB 2870 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2871 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2872 cmp r0, #0 @ is resolved entry null? 2873 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2874.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2875 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2876 @ no-op @ acquiring load 2877 mov r2, rINST, lsr #8 @ r2<- AA 2878 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2879 SET_VREG(r1, r2) @ fp[AA]<- r1 2880 GET_INST_OPCODE(ip) @ extract opcode from rINST 2881 GOTO_OPCODE(ip) @ jump to next instruction 2882 2883 2884/* ------------------------------ */ 2885 .balign 64 2886.L_OP_SGET_BYTE: /* 0x64 */ 2887/* File: armv5te/OP_SGET_BYTE.S */ 2888/* File: armv5te/OP_SGET.S */ 2889 /* 2890 * General 32-bit SGET handler. 2891 * 2892 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2893 */ 2894 /* op vAA, field@BBBB */ 2895 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2896 FETCH(r1, 1) @ r1<- field ref BBBB 2897 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2898 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2899 cmp r0, #0 @ is resolved entry null? 2900 beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2901.LOP_SGET_BYTE_finish: @ field ptr in r0 2902 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2903 @ no-op @ acquiring load 2904 mov r2, rINST, lsr #8 @ r2<- AA 2905 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2906 SET_VREG(r1, r2) @ fp[AA]<- r1 2907 GET_INST_OPCODE(ip) @ extract opcode from rINST 2908 GOTO_OPCODE(ip) @ jump to next instruction 2909 2910 2911/* ------------------------------ */ 2912 .balign 64 2913.L_OP_SGET_CHAR: /* 0x65 */ 2914/* File: armv5te/OP_SGET_CHAR.S */ 2915/* File: armv5te/OP_SGET.S */ 2916 /* 2917 * General 32-bit SGET handler. 2918 * 2919 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2920 */ 2921 /* op vAA, field@BBBB */ 2922 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2923 FETCH(r1, 1) @ r1<- field ref BBBB 2924 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2925 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2926 cmp r0, #0 @ is resolved entry null? 2927 beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2928.LOP_SGET_CHAR_finish: @ field ptr in r0 2929 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2930 @ no-op @ acquiring load 2931 mov r2, rINST, lsr #8 @ r2<- AA 2932 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2933 SET_VREG(r1, r2) @ fp[AA]<- r1 2934 GET_INST_OPCODE(ip) @ extract opcode from rINST 2935 GOTO_OPCODE(ip) @ jump to next instruction 2936 2937 2938/* ------------------------------ */ 2939 .balign 64 2940.L_OP_SGET_SHORT: /* 0x66 */ 2941/* File: armv5te/OP_SGET_SHORT.S */ 2942/* File: armv5te/OP_SGET.S */ 2943 /* 2944 * General 32-bit SGET handler. 2945 * 2946 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2947 */ 2948 /* op vAA, field@BBBB */ 2949 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2950 FETCH(r1, 1) @ r1<- field ref BBBB 2951 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2952 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2953 cmp r0, #0 @ is resolved entry null? 2954 beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2955.LOP_SGET_SHORT_finish: @ field ptr in r0 2956 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2957 @ no-op @ acquiring load 2958 mov r2, rINST, lsr #8 @ r2<- AA 2959 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2960 SET_VREG(r1, r2) @ fp[AA]<- r1 2961 GET_INST_OPCODE(ip) @ extract opcode from rINST 2962 GOTO_OPCODE(ip) @ jump to next instruction 2963 2964 2965/* ------------------------------ */ 2966 .balign 64 2967.L_OP_SPUT: /* 0x67 */ 2968/* File: armv5te/OP_SPUT.S */ 2969 /* 2970 * General 32-bit SPUT handler. 2971 * 2972 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2973 */ 2974 /* op vAA, field@BBBB */ 2975 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2976 FETCH(r1, 1) @ r1<- field ref BBBB 2977 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2978 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2979 cmp r0, #0 @ is resolved entry null? 2980 beq .LOP_SPUT_resolve @ yes, do resolve 2981.LOP_SPUT_finish: @ field ptr in r0 2982 mov r2, rINST, lsr #8 @ r2<- AA 2983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2984 GET_VREG(r1, r2) @ r1<- fp[AA] 2985 GET_INST_OPCODE(ip) @ extract opcode from rINST 2986 @ no-op @ releasing store 2987 str r1, [r0, #offStaticField_value] @ field<- vAA 2988 GOTO_OPCODE(ip) @ jump to next instruction 2989 2990/* ------------------------------ */ 2991 .balign 64 2992.L_OP_SPUT_WIDE: /* 0x68 */ 2993/* File: armv5te/OP_SPUT_WIDE.S */ 2994 /* 2995 * 64-bit SPUT handler. 2996 */ 2997 /* sput-wide vAA, field@BBBB */ 2998 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 2999 FETCH(r1, 1) @ r1<- field ref BBBB 3000 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 3001 mov r9, rINST, lsr #8 @ r9<- AA 3002 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 3003 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3004 cmp r2, #0 @ is resolved entry null? 3005 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3006.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 3007 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3008 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 3009 GET_INST_OPCODE(r10) @ extract opcode from rINST 3010 .if 0 3011 add r2, r2, #offStaticField_value @ r2<- pointer to data 3012 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 3013 .else 3014 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 3015 .endif 3016 GOTO_OPCODE(r10) @ jump to next instruction 3017 3018/* ------------------------------ */ 3019 .balign 64 3020.L_OP_SPUT_OBJECT: /* 0x69 */ 3021/* File: armv5te/OP_SPUT_OBJECT.S */ 3022 /* 3023 * 32-bit SPUT handler for objects 3024 * 3025 * for: sput-object, sput-object-volatile 3026 */ 3027 /* op vAA, field@BBBB */ 3028 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3029 FETCH(r1, 1) @ r1<- field ref BBBB 3030 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3031 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3032 cmp r0, #0 @ is resolved entry null? 3033 bne .LOP_SPUT_OBJECT_finish @ no, continue 3034 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3035 EXPORT_PC() @ resolve() could throw, so export now 3036 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 3037 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3038 cmp r0, #0 @ success? 3039 bne .LOP_SPUT_OBJECT_finish @ yes, finish 3040 b common_exceptionThrown @ no, handle exception 3041 3042 3043/* ------------------------------ */ 3044 .balign 64 3045.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3046/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3047/* File: armv5te/OP_SPUT.S */ 3048 /* 3049 * General 32-bit SPUT handler. 3050 * 3051 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3052 */ 3053 /* op vAA, field@BBBB */ 3054 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3055 FETCH(r1, 1) @ r1<- field ref BBBB 3056 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3057 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3058 cmp r0, #0 @ is resolved entry null? 3059 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3060.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3061 mov r2, rINST, lsr #8 @ r2<- AA 3062 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3063 GET_VREG(r1, r2) @ r1<- fp[AA] 3064 GET_INST_OPCODE(ip) @ extract opcode from rINST 3065 @ no-op @ releasing store 3066 str r1, [r0, #offStaticField_value] @ field<- vAA 3067 GOTO_OPCODE(ip) @ jump to next instruction 3068 3069 3070/* ------------------------------ */ 3071 .balign 64 3072.L_OP_SPUT_BYTE: /* 0x6b */ 3073/* File: armv5te/OP_SPUT_BYTE.S */ 3074/* File: armv5te/OP_SPUT.S */ 3075 /* 3076 * General 32-bit SPUT handler. 3077 * 3078 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3079 */ 3080 /* op vAA, field@BBBB */ 3081 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3082 FETCH(r1, 1) @ r1<- field ref BBBB 3083 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3084 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3085 cmp r0, #0 @ is resolved entry null? 3086 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3087.LOP_SPUT_BYTE_finish: @ field ptr in r0 3088 mov r2, rINST, lsr #8 @ r2<- AA 3089 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3090 GET_VREG(r1, r2) @ r1<- fp[AA] 3091 GET_INST_OPCODE(ip) @ extract opcode from rINST 3092 @ no-op @ releasing store 3093 str r1, [r0, #offStaticField_value] @ field<- vAA 3094 GOTO_OPCODE(ip) @ jump to next instruction 3095 3096 3097/* ------------------------------ */ 3098 .balign 64 3099.L_OP_SPUT_CHAR: /* 0x6c */ 3100/* File: armv5te/OP_SPUT_CHAR.S */ 3101/* File: armv5te/OP_SPUT.S */ 3102 /* 3103 * General 32-bit SPUT handler. 3104 * 3105 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3106 */ 3107 /* op vAA, field@BBBB */ 3108 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3109 FETCH(r1, 1) @ r1<- field ref BBBB 3110 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3111 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3112 cmp r0, #0 @ is resolved entry null? 3113 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3114.LOP_SPUT_CHAR_finish: @ field ptr in r0 3115 mov r2, rINST, lsr #8 @ r2<- AA 3116 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3117 GET_VREG(r1, r2) @ r1<- fp[AA] 3118 GET_INST_OPCODE(ip) @ extract opcode from rINST 3119 @ no-op @ releasing store 3120 str r1, [r0, #offStaticField_value] @ field<- vAA 3121 GOTO_OPCODE(ip) @ jump to next instruction 3122 3123 3124/* ------------------------------ */ 3125 .balign 64 3126.L_OP_SPUT_SHORT: /* 0x6d */ 3127/* File: armv5te/OP_SPUT_SHORT.S */ 3128/* File: armv5te/OP_SPUT.S */ 3129 /* 3130 * General 32-bit SPUT handler. 3131 * 3132 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3133 */ 3134 /* op vAA, field@BBBB */ 3135 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3136 FETCH(r1, 1) @ r1<- field ref BBBB 3137 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3138 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3139 cmp r0, #0 @ is resolved entry null? 3140 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3141.LOP_SPUT_SHORT_finish: @ field ptr in r0 3142 mov r2, rINST, lsr #8 @ r2<- AA 3143 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3144 GET_VREG(r1, r2) @ r1<- fp[AA] 3145 GET_INST_OPCODE(ip) @ extract opcode from rINST 3146 @ no-op @ releasing store 3147 str r1, [r0, #offStaticField_value] @ field<- vAA 3148 GOTO_OPCODE(ip) @ jump to next instruction 3149 3150 3151/* ------------------------------ */ 3152 .balign 64 3153.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3154/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3155 /* 3156 * Handle a virtual method call. 3157 * 3158 * for: invoke-virtual, invoke-virtual/range 3159 */ 3160 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3161 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3162 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3163 FETCH(r1, 1) @ r1<- BBBB 3164 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3165 FETCH(r10, 2) @ r10<- GFED or CCCC 3166 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3167 .if (!0) 3168 and r10, r10, #15 @ r10<- D (or stays CCCC) 3169 .endif 3170 cmp r0, #0 @ already resolved? 3171 EXPORT_PC() @ must export for invoke 3172 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3173 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3174 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3175 mov r2, #METHOD_VIRTUAL @ resolver method type 3176 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3177 cmp r0, #0 @ got null? 3178 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3179 b common_exceptionThrown @ yes, handle exception 3180 3181/* ------------------------------ */ 3182 .balign 64 3183.L_OP_INVOKE_SUPER: /* 0x6f */ 3184/* File: armv5te/OP_INVOKE_SUPER.S */ 3185 /* 3186 * Handle a "super" method call. 3187 * 3188 * for: invoke-super, invoke-super/range 3189 */ 3190 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3191 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3192 FETCH(r10, 2) @ r10<- GFED or CCCC 3193 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3194 .if (!0) 3195 and r10, r10, #15 @ r10<- D (or stays CCCC) 3196 .endif 3197 FETCH(r1, 1) @ r1<- BBBB 3198 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3199 GET_VREG(r2, r10) @ r2<- "this" ptr 3200 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3201 cmp r2, #0 @ null "this"? 3202 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3203 beq common_errNullObject @ null "this", throw exception 3204 cmp r0, #0 @ already resolved? 3205 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3206 EXPORT_PC() @ must export for invoke 3207 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3208 b .LOP_INVOKE_SUPER_resolve @ do resolve now 3209 3210/* ------------------------------ */ 3211 .balign 64 3212.L_OP_INVOKE_DIRECT: /* 0x70 */ 3213/* File: armv5te/OP_INVOKE_DIRECT.S */ 3214 /* 3215 * Handle a direct method call. 3216 * 3217 * (We could defer the "is 'this' pointer null" test to the common 3218 * method invocation code, and use a flag to indicate that static 3219 * calls don't count. If we do this as part of copying the arguments 3220 * out we could avoiding loading the first arg twice.) 3221 * 3222 * for: invoke-direct, invoke-direct/range 3223 */ 3224 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3225 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3226 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3227 FETCH(r1, 1) @ r1<- BBBB 3228 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3229 FETCH(r10, 2) @ r10<- GFED or CCCC 3230 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3231 .if (!0) 3232 and r10, r10, #15 @ r10<- D (or stays CCCC) 3233 .endif 3234 cmp r0, #0 @ already resolved? 3235 EXPORT_PC() @ must export for invoke 3236 GET_VREG(r2, r10) @ r2<- "this" ptr 3237 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3238.LOP_INVOKE_DIRECT_finish: 3239 cmp r2, #0 @ null "this" ref? 3240 bne common_invokeMethodNoRange @ no, continue on 3241 b common_errNullObject @ yes, throw exception 3242 3243/* ------------------------------ */ 3244 .balign 64 3245.L_OP_INVOKE_STATIC: /* 0x71 */ 3246/* File: armv5te/OP_INVOKE_STATIC.S */ 3247 /* 3248 * Handle a static method call. 3249 * 3250 * for: invoke-static, invoke-static/range 3251 */ 3252 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3253 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3254 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3255 FETCH(r1, 1) @ r1<- BBBB 3256 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3257 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3258 cmp r0, #0 @ already resolved? 3259 EXPORT_PC() @ must export for invoke 3260 bne common_invokeMethodNoRange @ yes, continue on 32610: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3262 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3263 mov r2, #METHOD_STATIC @ resolver method type 3264 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3265 cmp r0, #0 @ got null? 3266 bne common_invokeMethodNoRange @ no, continue 3267 b common_exceptionThrown @ yes, handle exception 3268 3269/* ------------------------------ */ 3270 .balign 64 3271.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3272/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3273 /* 3274 * Handle an interface method call. 3275 * 3276 * for: invoke-interface, invoke-interface/range 3277 */ 3278 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3279 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3280 FETCH(r2, 2) @ r2<- FEDC or CCCC 3281 FETCH(r1, 1) @ r1<- BBBB 3282 .if (!0) 3283 and r2, r2, #15 @ r2<- C (or stays CCCC) 3284 .endif 3285 EXPORT_PC() @ must export for invoke 3286 GET_VREG(r0, r2) @ r0<- first arg ("this") 3287 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3288 cmp r0, #0 @ null obj? 3289 ldr r2, [rSELF, #offThread_method] @ r2<- method 3290 beq common_errNullObject @ yes, fail 3291 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3292 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3293 cmp r0, #0 @ failed? 3294 beq common_exceptionThrown @ yes, handle exception 3295 b common_invokeMethodNoRange @ jump to common handler 3296 3297/* ------------------------------ */ 3298 .balign 64 3299.L_OP_UNUSED_73: /* 0x73 */ 3300/* File: armv5te/OP_UNUSED_73.S */ 3301/* File: armv5te/unused.S */ 3302 bl common_abort 3303 3304 3305/* ------------------------------ */ 3306 .balign 64 3307.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3308/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3309/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3310 /* 3311 * Handle a virtual method call. 3312 * 3313 * for: invoke-virtual, invoke-virtual/range 3314 */ 3315 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3316 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3317 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3318 FETCH(r1, 1) @ r1<- BBBB 3319 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3320 FETCH(r10, 2) @ r10<- GFED or CCCC 3321 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3322 .if (!1) 3323 and r10, r10, #15 @ r10<- D (or stays CCCC) 3324 .endif 3325 cmp r0, #0 @ already resolved? 3326 EXPORT_PC() @ must export for invoke 3327 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3328 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3329 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3330 mov r2, #METHOD_VIRTUAL @ resolver method type 3331 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3332 cmp r0, #0 @ got null? 3333 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3334 b common_exceptionThrown @ yes, handle exception 3335 3336 3337/* ------------------------------ */ 3338 .balign 64 3339.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3340/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3341/* File: armv5te/OP_INVOKE_SUPER.S */ 3342 /* 3343 * Handle a "super" method call. 3344 * 3345 * for: invoke-super, invoke-super/range 3346 */ 3347 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3348 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3349 FETCH(r10, 2) @ r10<- GFED or CCCC 3350 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3351 .if (!1) 3352 and r10, r10, #15 @ r10<- D (or stays CCCC) 3353 .endif 3354 FETCH(r1, 1) @ r1<- BBBB 3355 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3356 GET_VREG(r2, r10) @ r2<- "this" ptr 3357 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3358 cmp r2, #0 @ null "this"? 3359 ldr r9, [rSELF, #offThread_method] @ r9<- current method 3360 beq common_errNullObject @ null "this", throw exception 3361 cmp r0, #0 @ already resolved? 3362 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3363 EXPORT_PC() @ must export for invoke 3364 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3365 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3366 3367 3368/* ------------------------------ */ 3369 .balign 64 3370.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3371/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3372/* File: armv5te/OP_INVOKE_DIRECT.S */ 3373 /* 3374 * Handle a direct method call. 3375 * 3376 * (We could defer the "is 'this' pointer null" test to the common 3377 * method invocation code, and use a flag to indicate that static 3378 * calls don't count. If we do this as part of copying the arguments 3379 * out we could avoiding loading the first arg twice.) 3380 * 3381 * for: invoke-direct, invoke-direct/range 3382 */ 3383 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3384 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3385 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3386 FETCH(r1, 1) @ r1<- BBBB 3387 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3388 FETCH(r10, 2) @ r10<- GFED or CCCC 3389 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3390 .if (!1) 3391 and r10, r10, #15 @ r10<- D (or stays CCCC) 3392 .endif 3393 cmp r0, #0 @ already resolved? 3394 EXPORT_PC() @ must export for invoke 3395 GET_VREG(r2, r10) @ r2<- "this" ptr 3396 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3397.LOP_INVOKE_DIRECT_RANGE_finish: 3398 cmp r2, #0 @ null "this" ref? 3399 bne common_invokeMethodRange @ no, continue on 3400 b common_errNullObject @ yes, throw exception 3401 3402 3403/* ------------------------------ */ 3404 .balign 64 3405.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3406/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3407/* File: armv5te/OP_INVOKE_STATIC.S */ 3408 /* 3409 * Handle a static method call. 3410 * 3411 * for: invoke-static, invoke-static/range 3412 */ 3413 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3414 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3415 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3416 FETCH(r1, 1) @ r1<- BBBB 3417 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3418 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3419 cmp r0, #0 @ already resolved? 3420 EXPORT_PC() @ must export for invoke 3421 bne common_invokeMethodRange @ yes, continue on 34220: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3423 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3424 mov r2, #METHOD_STATIC @ resolver method type 3425 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3426 cmp r0, #0 @ got null? 3427 bne common_invokeMethodRange @ no, continue 3428 b common_exceptionThrown @ yes, handle exception 3429 3430 3431/* ------------------------------ */ 3432 .balign 64 3433.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3434/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3435/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3436 /* 3437 * Handle an interface method call. 3438 * 3439 * for: invoke-interface, invoke-interface/range 3440 */ 3441 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3442 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3443 FETCH(r2, 2) @ r2<- FEDC or CCCC 3444 FETCH(r1, 1) @ r1<- BBBB 3445 .if (!1) 3446 and r2, r2, #15 @ r2<- C (or stays CCCC) 3447 .endif 3448 EXPORT_PC() @ must export for invoke 3449 GET_VREG(r0, r2) @ r0<- first arg ("this") 3450 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3451 cmp r0, #0 @ null obj? 3452 ldr r2, [rSELF, #offThread_method] @ r2<- method 3453 beq common_errNullObject @ yes, fail 3454 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3455 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3456 cmp r0, #0 @ failed? 3457 beq common_exceptionThrown @ yes, handle exception 3458 b common_invokeMethodRange @ jump to common handler 3459 3460 3461/* ------------------------------ */ 3462 .balign 64 3463.L_OP_UNUSED_79: /* 0x79 */ 3464/* File: armv5te/OP_UNUSED_79.S */ 3465/* File: armv5te/unused.S */ 3466 bl common_abort 3467 3468 3469/* ------------------------------ */ 3470 .balign 64 3471.L_OP_UNUSED_7A: /* 0x7a */ 3472/* File: armv5te/OP_UNUSED_7A.S */ 3473/* File: armv5te/unused.S */ 3474 bl common_abort 3475 3476 3477/* ------------------------------ */ 3478 .balign 64 3479.L_OP_NEG_INT: /* 0x7b */ 3480/* File: armv5te/OP_NEG_INT.S */ 3481/* File: armv5te/unop.S */ 3482 /* 3483 * Generic 32-bit unary operation. Provide an "instr" line that 3484 * specifies an instruction that performs "result = op r0". 3485 * This could be an ARM instruction or a function call. 3486 * 3487 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3488 * int-to-byte, int-to-char, int-to-short 3489 */ 3490 /* unop vA, vB */ 3491 mov r3, rINST, lsr #12 @ r3<- B 3492 mov r9, rINST, lsr #8 @ r9<- A+ 3493 GET_VREG(r0, r3) @ r0<- vB 3494 and r9, r9, #15 3495 @ optional op; may set condition codes 3496 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3497 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3498 GET_INST_OPCODE(ip) @ extract opcode from rINST 3499 SET_VREG(r0, r9) @ vAA<- r0 3500 GOTO_OPCODE(ip) @ jump to next instruction 3501 /* 9-10 instructions */ 3502 3503 3504/* ------------------------------ */ 3505 .balign 64 3506.L_OP_NOT_INT: /* 0x7c */ 3507/* File: armv5te/OP_NOT_INT.S */ 3508/* File: armv5te/unop.S */ 3509 /* 3510 * Generic 32-bit unary operation. Provide an "instr" line that 3511 * specifies an instruction that performs "result = op r0". 3512 * This could be an ARM instruction or a function call. 3513 * 3514 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3515 * int-to-byte, int-to-char, int-to-short 3516 */ 3517 /* unop vA, vB */ 3518 mov r3, rINST, lsr #12 @ r3<- B 3519 mov r9, rINST, lsr #8 @ r9<- A+ 3520 GET_VREG(r0, r3) @ r0<- vB 3521 and r9, r9, #15 3522 @ optional op; may set condition codes 3523 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3524 mvn r0, r0 @ r0<- op, r0-r3 changed 3525 GET_INST_OPCODE(ip) @ extract opcode from rINST 3526 SET_VREG(r0, r9) @ vAA<- r0 3527 GOTO_OPCODE(ip) @ jump to next instruction 3528 /* 9-10 instructions */ 3529 3530 3531/* ------------------------------ */ 3532 .balign 64 3533.L_OP_NEG_LONG: /* 0x7d */ 3534/* File: armv5te/OP_NEG_LONG.S */ 3535/* File: armv5te/unopWide.S */ 3536 /* 3537 * Generic 64-bit unary operation. Provide an "instr" line that 3538 * specifies an instruction that performs "result = op r0/r1". 3539 * This could be an ARM instruction or a function call. 3540 * 3541 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3542 */ 3543 /* unop vA, vB */ 3544 mov r9, rINST, lsr #8 @ r9<- A+ 3545 mov r3, rINST, lsr #12 @ r3<- B 3546 and r9, r9, #15 3547 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3548 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3549 ldmia r3, {r0-r1} @ r0/r1<- vAA 3550 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3551 rsbs r0, r0, #0 @ optional op; may set condition codes 3552 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3553 GET_INST_OPCODE(ip) @ extract opcode from rINST 3554 stmia r9, {r0-r1} @ vAA<- r0/r1 3555 GOTO_OPCODE(ip) @ jump to next instruction 3556 /* 12-13 instructions */ 3557 3558 3559/* ------------------------------ */ 3560 .balign 64 3561.L_OP_NOT_LONG: /* 0x7e */ 3562/* File: armv5te/OP_NOT_LONG.S */ 3563/* File: armv5te/unopWide.S */ 3564 /* 3565 * Generic 64-bit unary operation. Provide an "instr" line that 3566 * specifies an instruction that performs "result = op r0/r1". 3567 * This could be an ARM instruction or a function call. 3568 * 3569 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3570 */ 3571 /* unop vA, vB */ 3572 mov r9, rINST, lsr #8 @ r9<- A+ 3573 mov r3, rINST, lsr #12 @ r3<- B 3574 and r9, r9, #15 3575 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3576 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3577 ldmia r3, {r0-r1} @ r0/r1<- vAA 3578 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3579 mvn r0, r0 @ optional op; may set condition codes 3580 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3581 GET_INST_OPCODE(ip) @ extract opcode from rINST 3582 stmia r9, {r0-r1} @ vAA<- r0/r1 3583 GOTO_OPCODE(ip) @ jump to next instruction 3584 /* 12-13 instructions */ 3585 3586 3587/* ------------------------------ */ 3588 .balign 64 3589.L_OP_NEG_FLOAT: /* 0x7f */ 3590/* File: armv5te/OP_NEG_FLOAT.S */ 3591/* File: armv5te/unop.S */ 3592 /* 3593 * Generic 32-bit unary operation. Provide an "instr" line that 3594 * specifies an instruction that performs "result = op r0". 3595 * This could be an ARM instruction or a function call. 3596 * 3597 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3598 * int-to-byte, int-to-char, int-to-short 3599 */ 3600 /* unop vA, vB */ 3601 mov r3, rINST, lsr #12 @ r3<- B 3602 mov r9, rINST, lsr #8 @ r9<- A+ 3603 GET_VREG(r0, r3) @ r0<- vB 3604 and r9, r9, #15 3605 @ optional op; may set condition codes 3606 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3607 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3608 GET_INST_OPCODE(ip) @ extract opcode from rINST 3609 SET_VREG(r0, r9) @ vAA<- r0 3610 GOTO_OPCODE(ip) @ jump to next instruction 3611 /* 9-10 instructions */ 3612 3613 3614/* ------------------------------ */ 3615 .balign 64 3616.L_OP_NEG_DOUBLE: /* 0x80 */ 3617/* File: armv5te/OP_NEG_DOUBLE.S */ 3618/* File: armv5te/unopWide.S */ 3619 /* 3620 * Generic 64-bit unary operation. Provide an "instr" line that 3621 * specifies an instruction that performs "result = op r0/r1". 3622 * This could be an ARM instruction or a function call. 3623 * 3624 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3625 */ 3626 /* unop vA, vB */ 3627 mov r9, rINST, lsr #8 @ r9<- A+ 3628 mov r3, rINST, lsr #12 @ r3<- B 3629 and r9, r9, #15 3630 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3631 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3632 ldmia r3, {r0-r1} @ r0/r1<- vAA 3633 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3634 @ optional op; may set condition codes 3635 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3636 GET_INST_OPCODE(ip) @ extract opcode from rINST 3637 stmia r9, {r0-r1} @ vAA<- r0/r1 3638 GOTO_OPCODE(ip) @ jump to next instruction 3639 /* 12-13 instructions */ 3640 3641 3642/* ------------------------------ */ 3643 .balign 64 3644.L_OP_INT_TO_LONG: /* 0x81 */ 3645/* File: armv5te/OP_INT_TO_LONG.S */ 3646/* File: armv5te/unopWider.S */ 3647 /* 3648 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3649 * that specifies an instruction that performs "result = op r0", where 3650 * "result" is a 64-bit quantity in r0/r1. 3651 * 3652 * For: int-to-long, int-to-double, float-to-long, float-to-double 3653 */ 3654 /* unop vA, vB */ 3655 mov r9, rINST, lsr #8 @ r9<- A+ 3656 mov r3, rINST, lsr #12 @ r3<- B 3657 and r9, r9, #15 3658 GET_VREG(r0, r3) @ r0<- vB 3659 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3660 @ optional op; may set condition codes 3661 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3662 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3663 GET_INST_OPCODE(ip) @ extract opcode from rINST 3664 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3665 GOTO_OPCODE(ip) @ jump to next instruction 3666 /* 10-11 instructions */ 3667 3668 3669/* ------------------------------ */ 3670 .balign 64 3671.L_OP_INT_TO_FLOAT: /* 0x82 */ 3672/* File: armv5te/OP_INT_TO_FLOAT.S */ 3673/* File: armv5te/unop.S */ 3674 /* 3675 * Generic 32-bit unary operation. Provide an "instr" line that 3676 * specifies an instruction that performs "result = op r0". 3677 * This could be an ARM instruction or a function call. 3678 * 3679 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3680 * int-to-byte, int-to-char, int-to-short 3681 */ 3682 /* unop vA, vB */ 3683 mov r3, rINST, lsr #12 @ r3<- B 3684 mov r9, rINST, lsr #8 @ r9<- A+ 3685 GET_VREG(r0, r3) @ r0<- vB 3686 and r9, r9, #15 3687 @ optional op; may set condition codes 3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3689 bl __aeabi_i2f @ r0<- op, r0-r3 changed 3690 GET_INST_OPCODE(ip) @ extract opcode from rINST 3691 SET_VREG(r0, r9) @ vAA<- r0 3692 GOTO_OPCODE(ip) @ jump to next instruction 3693 /* 9-10 instructions */ 3694 3695 3696/* ------------------------------ */ 3697 .balign 64 3698.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3699/* File: armv5te/OP_INT_TO_DOUBLE.S */ 3700/* File: armv5te/unopWider.S */ 3701 /* 3702 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3703 * that specifies an instruction that performs "result = op r0", where 3704 * "result" is a 64-bit quantity in r0/r1. 3705 * 3706 * For: int-to-long, int-to-double, float-to-long, float-to-double 3707 */ 3708 /* unop vA, vB */ 3709 mov r9, rINST, lsr #8 @ r9<- A+ 3710 mov r3, rINST, lsr #12 @ r3<- B 3711 and r9, r9, #15 3712 GET_VREG(r0, r3) @ r0<- vB 3713 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3714 @ optional op; may set condition codes 3715 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3716 bl __aeabi_i2d @ r0<- op, r0-r3 changed 3717 GET_INST_OPCODE(ip) @ extract opcode from rINST 3718 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3719 GOTO_OPCODE(ip) @ jump to next instruction 3720 /* 10-11 instructions */ 3721 3722 3723/* ------------------------------ */ 3724 .balign 64 3725.L_OP_LONG_TO_INT: /* 0x84 */ 3726/* File: armv5te/OP_LONG_TO_INT.S */ 3727/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3728/* File: armv5te/OP_MOVE.S */ 3729 /* for move, move-object, long-to-int */ 3730 /* op vA, vB */ 3731 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3732 mov r0, rINST, lsr #8 @ r0<- A from 11:8 3733 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3734 GET_VREG(r2, r1) @ r2<- fp[B] 3735 and r0, r0, #15 3736 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3737 SET_VREG(r2, r0) @ fp[A]<- r2 3738 GOTO_OPCODE(ip) @ execute next instruction 3739 3740 3741/* ------------------------------ */ 3742 .balign 64 3743.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3744/* File: armv5te/OP_LONG_TO_FLOAT.S */ 3745/* File: armv5te/unopNarrower.S */ 3746 /* 3747 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3748 * that specifies an instruction that performs "result = op r0/r1", where 3749 * "result" is a 32-bit quantity in r0. 3750 * 3751 * For: long-to-float, double-to-int, double-to-float 3752 * 3753 * (This would work for long-to-int, but that instruction is actually 3754 * an exact match for OP_MOVE.) 3755 */ 3756 /* unop vA, vB */ 3757 mov r3, rINST, lsr #12 @ r3<- B 3758 mov r9, rINST, lsr #8 @ r9<- A+ 3759 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3760 and r9, r9, #15 3761 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3762 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3763 @ optional op; may set condition codes 3764 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3765 GET_INST_OPCODE(ip) @ extract opcode from rINST 3766 SET_VREG(r0, r9) @ vA<- r0 3767 GOTO_OPCODE(ip) @ jump to next instruction 3768 /* 10-11 instructions */ 3769 3770 3771/* ------------------------------ */ 3772 .balign 64 3773.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3774/* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3775/* File: armv5te/unopWide.S */ 3776 /* 3777 * Generic 64-bit unary operation. Provide an "instr" line that 3778 * specifies an instruction that performs "result = op r0/r1". 3779 * This could be an ARM instruction or a function call. 3780 * 3781 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3782 */ 3783 /* unop vA, vB */ 3784 mov r9, rINST, lsr #8 @ r9<- A+ 3785 mov r3, rINST, lsr #12 @ r3<- B 3786 and r9, r9, #15 3787 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3788 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3789 ldmia r3, {r0-r1} @ r0/r1<- vAA 3790 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3791 @ optional op; may set condition codes 3792 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3793 GET_INST_OPCODE(ip) @ extract opcode from rINST 3794 stmia r9, {r0-r1} @ vAA<- r0/r1 3795 GOTO_OPCODE(ip) @ jump to next instruction 3796 /* 12-13 instructions */ 3797 3798 3799/* ------------------------------ */ 3800 .balign 64 3801.L_OP_FLOAT_TO_INT: /* 0x87 */ 3802/* File: armv5te/OP_FLOAT_TO_INT.S */ 3803/* EABI appears to have Java-style conversions of +inf/-inf/NaN */ 3804/* File: armv5te/unop.S */ 3805 /* 3806 * Generic 32-bit unary operation. Provide an "instr" line that 3807 * specifies an instruction that performs "result = op r0". 3808 * This could be an ARM instruction or a function call. 3809 * 3810 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3811 * int-to-byte, int-to-char, int-to-short 3812 */ 3813 /* unop vA, vB */ 3814 mov r3, rINST, lsr #12 @ r3<- B 3815 mov r9, rINST, lsr #8 @ r9<- A+ 3816 GET_VREG(r0, r3) @ r0<- vB 3817 and r9, r9, #15 3818 @ optional op; may set condition codes 3819 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3820 bl __aeabi_f2iz @ r0<- op, r0-r3 changed 3821 GET_INST_OPCODE(ip) @ extract opcode from rINST 3822 SET_VREG(r0, r9) @ vAA<- r0 3823 GOTO_OPCODE(ip) @ jump to next instruction 3824 /* 9-10 instructions */ 3825 3826 3827#if 0 3828@include "armv5te/unop.S" {"instr":"bl f2i_doconv"} 3829@break 3830/* 3831 * Convert the float in r0 to an int in r0. 3832 * 3833 * We have to clip values to int min/max per the specification. The 3834 * expected common case is a "reasonable" value that converts directly 3835 * to modest integer. The EABI convert function isn't doing this for us. 3836 */ 3837f2i_doconv: 3838 stmfd sp!, {r4, lr} 3839 mov r1, #0x4f000000 @ (float)maxint 3840 mov r4, r0 3841 bl __aeabi_fcmpge @ is arg >= maxint? 3842 cmp r0, #0 @ nonzero == yes 3843 mvnne r0, #0x80000000 @ return maxint (7fffffff) 3844 ldmnefd sp!, {r4, pc} 3845 3846 mov r0, r4 @ recover arg 3847 mov r1, #0xcf000000 @ (float)minint 3848 bl __aeabi_fcmple @ is arg <= minint? 3849 cmp r0, #0 @ nonzero == yes 3850 movne r0, #0x80000000 @ return minint (80000000) 3851 ldmnefd sp!, {r4, pc} 3852 3853 mov r0, r4 @ recover arg 3854 mov r1, r4 3855 bl __aeabi_fcmpeq @ is arg == self? 3856 cmp r0, #0 @ zero == no 3857 ldmeqfd sp!, {r4, pc} @ return zero for NaN 3858 3859 mov r0, r4 @ recover arg 3860 bl __aeabi_f2iz @ convert float to int 3861 ldmfd sp!, {r4, pc} 3862#endif 3863 3864/* ------------------------------ */ 3865 .balign 64 3866.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3867/* File: armv5te/OP_FLOAT_TO_LONG.S */ 3868@include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3869/* File: armv5te/unopWider.S */ 3870 /* 3871 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3872 * that specifies an instruction that performs "result = op r0", where 3873 * "result" is a 64-bit quantity in r0/r1. 3874 * 3875 * For: int-to-long, int-to-double, float-to-long, float-to-double 3876 */ 3877 /* unop vA, vB */ 3878 mov r9, rINST, lsr #8 @ r9<- A+ 3879 mov r3, rINST, lsr #12 @ r3<- B 3880 and r9, r9, #15 3881 GET_VREG(r0, r3) @ r0<- vB 3882 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3883 @ optional op; may set condition codes 3884 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3885 bl f2l_doconv @ r0<- op, r0-r3 changed 3886 GET_INST_OPCODE(ip) @ extract opcode from rINST 3887 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3888 GOTO_OPCODE(ip) @ jump to next instruction 3889 /* 10-11 instructions */ 3890 3891 3892 3893/* ------------------------------ */ 3894 .balign 64 3895.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3896/* File: armv5te/OP_FLOAT_TO_DOUBLE.S */ 3897/* File: armv5te/unopWider.S */ 3898 /* 3899 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3900 * that specifies an instruction that performs "result = op r0", where 3901 * "result" is a 64-bit quantity in r0/r1. 3902 * 3903 * For: int-to-long, int-to-double, float-to-long, float-to-double 3904 */ 3905 /* unop vA, vB */ 3906 mov r9, rINST, lsr #8 @ r9<- A+ 3907 mov r3, rINST, lsr #12 @ r3<- B 3908 and r9, r9, #15 3909 GET_VREG(r0, r3) @ r0<- vB 3910 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3911 @ optional op; may set condition codes 3912 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3913 bl __aeabi_f2d @ r0<- op, r0-r3 changed 3914 GET_INST_OPCODE(ip) @ extract opcode from rINST 3915 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3916 GOTO_OPCODE(ip) @ jump to next instruction 3917 /* 10-11 instructions */ 3918 3919 3920/* ------------------------------ */ 3921 .balign 64 3922.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3923/* File: armv5te/OP_DOUBLE_TO_INT.S */ 3924/* EABI appears to have Java-style conversions of +inf/-inf/NaN */ 3925/* File: armv5te/unopNarrower.S */ 3926 /* 3927 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3928 * that specifies an instruction that performs "result = op r0/r1", where 3929 * "result" is a 32-bit quantity in r0. 3930 * 3931 * For: long-to-float, double-to-int, double-to-float 3932 * 3933 * (This would work for long-to-int, but that instruction is actually 3934 * an exact match for OP_MOVE.) 3935 */ 3936 /* unop vA, vB */ 3937 mov r3, rINST, lsr #12 @ r3<- B 3938 mov r9, rINST, lsr #8 @ r9<- A+ 3939 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3940 and r9, r9, #15 3941 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3942 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3943 @ optional op; may set condition codes 3944 bl __aeabi_d2iz @ r0<- op, r0-r3 changed 3945 GET_INST_OPCODE(ip) @ extract opcode from rINST 3946 SET_VREG(r0, r9) @ vA<- r0 3947 GOTO_OPCODE(ip) @ jump to next instruction 3948 /* 10-11 instructions */ 3949 3950 3951#if 0 3952@include "armv5te/unopNarrower.S" {"instr":"bl d2i_doconv"} 3953@break 3954/* 3955 * Convert the double in r0/r1 to an int in r0. 3956 * 3957 * We have to clip values to int min/max per the specification. The 3958 * expected common case is a "reasonable" value that converts directly 3959 * to modest integer. The EABI convert function isn't doing this for us. 3960 */ 3961d2i_doconv: 3962 stmfd sp!, {r4, r5, lr} @ save regs 3963 mov r2, #0x80000000 @ maxint, as a double (low word) 3964 mov r2, r2, asr #9 @ 0xffc00000 3965 sub sp, sp, #4 @ align for EABI 3966 mvn r3, #0xbe000000 @ maxint, as a double (high word) 3967 sub r3, r3, #0x00200000 @ 0x41dfffff 3968 mov r4, r0 @ save a copy of r0 3969 mov r5, r1 @ and r1 3970 bl __aeabi_dcmpge @ is arg >= maxint? 3971 cmp r0, #0 @ nonzero == yes 3972 mvnne r0, #0x80000000 @ return maxint (0x7fffffff) 3973 bne 1f 3974 3975 mov r0, r4 @ recover arg 3976 mov r1, r5 3977 mov r3, #0xc1000000 @ minint, as a double (high word) 3978 add r3, r3, #0x00e00000 @ 0xc1e00000 3979 mov r2, #0 @ minint, as a double (low word) 3980 bl __aeabi_dcmple @ is arg <= minint? 3981 cmp r0, #0 @ nonzero == yes 3982 movne r0, #0x80000000 @ return minint (80000000) 3983 bne 1f 3984 3985 mov r0, r4 @ recover arg 3986 mov r1, r5 3987 mov r2, r4 @ compare against self 3988 mov r3, r5 3989 bl __aeabi_dcmpeq @ is arg == self? 3990 cmp r0, #0 @ zero == no 3991 beq 1f @ return zero for NaN 3992 3993 mov r0, r4 @ recover arg 3994 mov r1, r5 3995 bl __aeabi_d2iz @ convert double to int 3996 39971: 3998 add sp, sp, #4 3999 ldmfd sp!, {r4, r5, pc} 4000#endif 4001 4002/* ------------------------------ */ 4003 .balign 64 4004.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 4005/* File: armv5te/OP_DOUBLE_TO_LONG.S */ 4006@include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 4007/* File: armv5te/unopWide.S */ 4008 /* 4009 * Generic 64-bit unary operation. Provide an "instr" line that 4010 * specifies an instruction that performs "result = op r0/r1". 4011 * This could be an ARM instruction or a function call. 4012 * 4013 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 4014 */ 4015 /* unop vA, vB */ 4016 mov r9, rINST, lsr #8 @ r9<- A+ 4017 mov r3, rINST, lsr #12 @ r3<- B 4018 and r9, r9, #15 4019 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 4020 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 4021 ldmia r3, {r0-r1} @ r0/r1<- vAA 4022 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4023 @ optional op; may set condition codes 4024 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 4025 GET_INST_OPCODE(ip) @ extract opcode from rINST 4026 stmia r9, {r0-r1} @ vAA<- r0/r1 4027 GOTO_OPCODE(ip) @ jump to next instruction 4028 /* 12-13 instructions */ 4029 4030 4031 4032/* ------------------------------ */ 4033 .balign 64 4034.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 4035/* File: armv5te/OP_DOUBLE_TO_FLOAT.S */ 4036/* File: armv5te/unopNarrower.S */ 4037 /* 4038 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 4039 * that specifies an instruction that performs "result = op r0/r1", where 4040 * "result" is a 32-bit quantity in r0. 4041 * 4042 * For: long-to-float, double-to-int, double-to-float 4043 * 4044 * (This would work for long-to-int, but that instruction is actually 4045 * an exact match for OP_MOVE.) 4046 */ 4047 /* unop vA, vB */ 4048 mov r3, rINST, lsr #12 @ r3<- B 4049 mov r9, rINST, lsr #8 @ r9<- A+ 4050 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 4051 and r9, r9, #15 4052 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 4053 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4054 @ optional op; may set condition codes 4055 bl __aeabi_d2f @ r0<- op, r0-r3 changed 4056 GET_INST_OPCODE(ip) @ extract opcode from rINST 4057 SET_VREG(r0, r9) @ vA<- r0 4058 GOTO_OPCODE(ip) @ jump to next instruction 4059 /* 10-11 instructions */ 4060 4061 4062/* ------------------------------ */ 4063 .balign 64 4064.L_OP_INT_TO_BYTE: /* 0x8d */ 4065/* File: armv5te/OP_INT_TO_BYTE.S */ 4066/* File: armv5te/unop.S */ 4067 /* 4068 * Generic 32-bit unary operation. Provide an "instr" line that 4069 * specifies an instruction that performs "result = op r0". 4070 * This could be an ARM instruction or a function call. 4071 * 4072 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4073 * int-to-byte, int-to-char, int-to-short 4074 */ 4075 /* unop vA, vB */ 4076 mov r3, rINST, lsr #12 @ r3<- B 4077 mov r9, rINST, lsr #8 @ r9<- A+ 4078 GET_VREG(r0, r3) @ r0<- vB 4079 and r9, r9, #15 4080 mov r0, r0, asl #24 @ optional op; may set condition codes 4081 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4082 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 4083 GET_INST_OPCODE(ip) @ extract opcode from rINST 4084 SET_VREG(r0, r9) @ vAA<- r0 4085 GOTO_OPCODE(ip) @ jump to next instruction 4086 /* 9-10 instructions */ 4087 4088 4089/* ------------------------------ */ 4090 .balign 64 4091.L_OP_INT_TO_CHAR: /* 0x8e */ 4092/* File: armv5te/OP_INT_TO_CHAR.S */ 4093/* File: armv5te/unop.S */ 4094 /* 4095 * Generic 32-bit unary operation. Provide an "instr" line that 4096 * specifies an instruction that performs "result = op r0". 4097 * This could be an ARM instruction or a function call. 4098 * 4099 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4100 * int-to-byte, int-to-char, int-to-short 4101 */ 4102 /* unop vA, vB */ 4103 mov r3, rINST, lsr #12 @ r3<- B 4104 mov r9, rINST, lsr #8 @ r9<- A+ 4105 GET_VREG(r0, r3) @ r0<- vB 4106 and r9, r9, #15 4107 mov r0, r0, asl #16 @ optional op; may set condition codes 4108 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4109 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 4110 GET_INST_OPCODE(ip) @ extract opcode from rINST 4111 SET_VREG(r0, r9) @ vAA<- r0 4112 GOTO_OPCODE(ip) @ jump to next instruction 4113 /* 9-10 instructions */ 4114 4115 4116/* ------------------------------ */ 4117 .balign 64 4118.L_OP_INT_TO_SHORT: /* 0x8f */ 4119/* File: armv5te/OP_INT_TO_SHORT.S */ 4120/* File: armv5te/unop.S */ 4121 /* 4122 * Generic 32-bit unary operation. Provide an "instr" line that 4123 * specifies an instruction that performs "result = op r0". 4124 * This could be an ARM instruction or a function call. 4125 * 4126 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4127 * int-to-byte, int-to-char, int-to-short 4128 */ 4129 /* unop vA, vB */ 4130 mov r3, rINST, lsr #12 @ r3<- B 4131 mov r9, rINST, lsr #8 @ r9<- A+ 4132 GET_VREG(r0, r3) @ r0<- vB 4133 and r9, r9, #15 4134 mov r0, r0, asl #16 @ optional op; may set condition codes 4135 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4136 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 4137 GET_INST_OPCODE(ip) @ extract opcode from rINST 4138 SET_VREG(r0, r9) @ vAA<- r0 4139 GOTO_OPCODE(ip) @ jump to next instruction 4140 /* 9-10 instructions */ 4141 4142 4143/* ------------------------------ */ 4144 .balign 64 4145.L_OP_ADD_INT: /* 0x90 */ 4146/* File: armv5te/OP_ADD_INT.S */ 4147/* File: armv5te/binop.S */ 4148 /* 4149 * Generic 32-bit binary operation. Provide an "instr" line that 4150 * specifies an instruction that performs "result = r0 op r1". 4151 * This could be an ARM instruction or a function call. (If the result 4152 * comes back in a register other than r0, you can override "result".) 4153 * 4154 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4155 * vCC (r1). Useful for integer division and modulus. Note that we 4156 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4157 * handles it correctly. 4158 * 4159 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4160 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4161 * mul-float, div-float, rem-float 4162 */ 4163 /* binop vAA, vBB, vCC */ 4164 FETCH(r0, 1) @ r0<- CCBB 4165 mov r9, rINST, lsr #8 @ r9<- AA 4166 mov r3, r0, lsr #8 @ r3<- CC 4167 and r2, r0, #255 @ r2<- BB 4168 GET_VREG(r1, r3) @ r1<- vCC 4169 GET_VREG(r0, r2) @ r0<- vBB 4170 .if 0 4171 cmp r1, #0 @ is second operand zero? 4172 beq common_errDivideByZero 4173 .endif 4174 4175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4176 @ optional op; may set condition codes 4177 add r0, r0, r1 @ r0<- op, r0-r3 changed 4178 GET_INST_OPCODE(ip) @ extract opcode from rINST 4179 SET_VREG(r0, r9) @ vAA<- r0 4180 GOTO_OPCODE(ip) @ jump to next instruction 4181 /* 11-14 instructions */ 4182 4183 4184/* ------------------------------ */ 4185 .balign 64 4186.L_OP_SUB_INT: /* 0x91 */ 4187/* File: armv5te/OP_SUB_INT.S */ 4188/* File: armv5te/binop.S */ 4189 /* 4190 * Generic 32-bit binary operation. Provide an "instr" line that 4191 * specifies an instruction that performs "result = r0 op r1". 4192 * This could be an ARM instruction or a function call. (If the result 4193 * comes back in a register other than r0, you can override "result".) 4194 * 4195 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4196 * vCC (r1). Useful for integer division and modulus. Note that we 4197 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4198 * handles it correctly. 4199 * 4200 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4201 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4202 * mul-float, div-float, rem-float 4203 */ 4204 /* binop vAA, vBB, vCC */ 4205 FETCH(r0, 1) @ r0<- CCBB 4206 mov r9, rINST, lsr #8 @ r9<- AA 4207 mov r3, r0, lsr #8 @ r3<- CC 4208 and r2, r0, #255 @ r2<- BB 4209 GET_VREG(r1, r3) @ r1<- vCC 4210 GET_VREG(r0, r2) @ r0<- vBB 4211 .if 0 4212 cmp r1, #0 @ is second operand zero? 4213 beq common_errDivideByZero 4214 .endif 4215 4216 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4217 @ optional op; may set condition codes 4218 sub r0, r0, r1 @ r0<- op, r0-r3 changed 4219 GET_INST_OPCODE(ip) @ extract opcode from rINST 4220 SET_VREG(r0, r9) @ vAA<- r0 4221 GOTO_OPCODE(ip) @ jump to next instruction 4222 /* 11-14 instructions */ 4223 4224 4225/* ------------------------------ */ 4226 .balign 64 4227.L_OP_MUL_INT: /* 0x92 */ 4228/* File: armv5te/OP_MUL_INT.S */ 4229/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4230/* File: armv5te/binop.S */ 4231 /* 4232 * Generic 32-bit binary operation. Provide an "instr" line that 4233 * specifies an instruction that performs "result = r0 op r1". 4234 * This could be an ARM instruction or a function call. (If the result 4235 * comes back in a register other than r0, you can override "result".) 4236 * 4237 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4238 * vCC (r1). Useful for integer division and modulus. Note that we 4239 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4240 * handles it correctly. 4241 * 4242 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4243 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4244 * mul-float, div-float, rem-float 4245 */ 4246 /* binop vAA, vBB, vCC */ 4247 FETCH(r0, 1) @ r0<- CCBB 4248 mov r9, rINST, lsr #8 @ r9<- AA 4249 mov r3, r0, lsr #8 @ r3<- CC 4250 and r2, r0, #255 @ r2<- BB 4251 GET_VREG(r1, r3) @ r1<- vCC 4252 GET_VREG(r0, r2) @ r0<- vBB 4253 .if 0 4254 cmp r1, #0 @ is second operand zero? 4255 beq common_errDivideByZero 4256 .endif 4257 4258 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4259 @ optional op; may set condition codes 4260 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4261 GET_INST_OPCODE(ip) @ extract opcode from rINST 4262 SET_VREG(r0, r9) @ vAA<- r0 4263 GOTO_OPCODE(ip) @ jump to next instruction 4264 /* 11-14 instructions */ 4265 4266 4267/* ------------------------------ */ 4268 .balign 64 4269.L_OP_DIV_INT: /* 0x93 */ 4270/* File: armv5te/OP_DIV_INT.S */ 4271/* File: armv5te/binop.S */ 4272 /* 4273 * Generic 32-bit binary operation. Provide an "instr" line that 4274 * specifies an instruction that performs "result = r0 op r1". 4275 * This could be an ARM instruction or a function call. (If the result 4276 * comes back in a register other than r0, you can override "result".) 4277 * 4278 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4279 * vCC (r1). Useful for integer division and modulus. Note that we 4280 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4281 * handles it correctly. 4282 * 4283 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4284 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4285 * mul-float, div-float, rem-float 4286 */ 4287 /* binop vAA, vBB, vCC */ 4288 FETCH(r0, 1) @ r0<- CCBB 4289 mov r9, rINST, lsr #8 @ r9<- AA 4290 mov r3, r0, lsr #8 @ r3<- CC 4291 and r2, r0, #255 @ r2<- BB 4292 GET_VREG(r1, r3) @ r1<- vCC 4293 GET_VREG(r0, r2) @ r0<- vBB 4294 .if 1 4295 cmp r1, #0 @ is second operand zero? 4296 beq common_errDivideByZero 4297 .endif 4298 4299 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4300 @ optional op; may set condition codes 4301 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4302 GET_INST_OPCODE(ip) @ extract opcode from rINST 4303 SET_VREG(r0, r9) @ vAA<- r0 4304 GOTO_OPCODE(ip) @ jump to next instruction 4305 /* 11-14 instructions */ 4306 4307 4308/* ------------------------------ */ 4309 .balign 64 4310.L_OP_REM_INT: /* 0x94 */ 4311/* File: armv5te/OP_REM_INT.S */ 4312/* idivmod returns quotient in r0 and remainder in r1 */ 4313/* File: armv5te/binop.S */ 4314 /* 4315 * Generic 32-bit binary operation. Provide an "instr" line that 4316 * specifies an instruction that performs "result = r0 op r1". 4317 * This could be an ARM instruction or a function call. (If the result 4318 * comes back in a register other than r0, you can override "result".) 4319 * 4320 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4321 * vCC (r1). Useful for integer division and modulus. Note that we 4322 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4323 * handles it correctly. 4324 * 4325 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4326 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4327 * mul-float, div-float, rem-float 4328 */ 4329 /* binop vAA, vBB, vCC */ 4330 FETCH(r0, 1) @ r0<- CCBB 4331 mov r9, rINST, lsr #8 @ r9<- AA 4332 mov r3, r0, lsr #8 @ r3<- CC 4333 and r2, r0, #255 @ r2<- BB 4334 GET_VREG(r1, r3) @ r1<- vCC 4335 GET_VREG(r0, r2) @ r0<- vBB 4336 .if 1 4337 cmp r1, #0 @ is second operand zero? 4338 beq common_errDivideByZero 4339 .endif 4340 4341 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4342 @ optional op; may set condition codes 4343 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4344 GET_INST_OPCODE(ip) @ extract opcode from rINST 4345 SET_VREG(r1, r9) @ vAA<- r1 4346 GOTO_OPCODE(ip) @ jump to next instruction 4347 /* 11-14 instructions */ 4348 4349 4350/* ------------------------------ */ 4351 .balign 64 4352.L_OP_AND_INT: /* 0x95 */ 4353/* File: armv5te/OP_AND_INT.S */ 4354/* File: armv5te/binop.S */ 4355 /* 4356 * Generic 32-bit binary operation. Provide an "instr" line that 4357 * specifies an instruction that performs "result = r0 op r1". 4358 * This could be an ARM instruction or a function call. (If the result 4359 * comes back in a register other than r0, you can override "result".) 4360 * 4361 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4362 * vCC (r1). Useful for integer division and modulus. Note that we 4363 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4364 * handles it correctly. 4365 * 4366 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4367 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4368 * mul-float, div-float, rem-float 4369 */ 4370 /* binop vAA, vBB, vCC */ 4371 FETCH(r0, 1) @ r0<- CCBB 4372 mov r9, rINST, lsr #8 @ r9<- AA 4373 mov r3, r0, lsr #8 @ r3<- CC 4374 and r2, r0, #255 @ r2<- BB 4375 GET_VREG(r1, r3) @ r1<- vCC 4376 GET_VREG(r0, r2) @ r0<- vBB 4377 .if 0 4378 cmp r1, #0 @ is second operand zero? 4379 beq common_errDivideByZero 4380 .endif 4381 4382 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4383 @ optional op; may set condition codes 4384 and r0, r0, r1 @ r0<- op, r0-r3 changed 4385 GET_INST_OPCODE(ip) @ extract opcode from rINST 4386 SET_VREG(r0, r9) @ vAA<- r0 4387 GOTO_OPCODE(ip) @ jump to next instruction 4388 /* 11-14 instructions */ 4389 4390 4391/* ------------------------------ */ 4392 .balign 64 4393.L_OP_OR_INT: /* 0x96 */ 4394/* File: armv5te/OP_OR_INT.S */ 4395/* File: armv5te/binop.S */ 4396 /* 4397 * Generic 32-bit binary operation. Provide an "instr" line that 4398 * specifies an instruction that performs "result = r0 op r1". 4399 * This could be an ARM instruction or a function call. (If the result 4400 * comes back in a register other than r0, you can override "result".) 4401 * 4402 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4403 * vCC (r1). Useful for integer division and modulus. Note that we 4404 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4405 * handles it correctly. 4406 * 4407 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4408 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4409 * mul-float, div-float, rem-float 4410 */ 4411 /* binop vAA, vBB, vCC */ 4412 FETCH(r0, 1) @ r0<- CCBB 4413 mov r9, rINST, lsr #8 @ r9<- AA 4414 mov r3, r0, lsr #8 @ r3<- CC 4415 and r2, r0, #255 @ r2<- BB 4416 GET_VREG(r1, r3) @ r1<- vCC 4417 GET_VREG(r0, r2) @ r0<- vBB 4418 .if 0 4419 cmp r1, #0 @ is second operand zero? 4420 beq common_errDivideByZero 4421 .endif 4422 4423 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4424 @ optional op; may set condition codes 4425 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4426 GET_INST_OPCODE(ip) @ extract opcode from rINST 4427 SET_VREG(r0, r9) @ vAA<- r0 4428 GOTO_OPCODE(ip) @ jump to next instruction 4429 /* 11-14 instructions */ 4430 4431 4432/* ------------------------------ */ 4433 .balign 64 4434.L_OP_XOR_INT: /* 0x97 */ 4435/* File: armv5te/OP_XOR_INT.S */ 4436/* File: armv5te/binop.S */ 4437 /* 4438 * Generic 32-bit binary operation. Provide an "instr" line that 4439 * specifies an instruction that performs "result = r0 op r1". 4440 * This could be an ARM instruction or a function call. (If the result 4441 * comes back in a register other than r0, you can override "result".) 4442 * 4443 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4444 * vCC (r1). Useful for integer division and modulus. Note that we 4445 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4446 * handles it correctly. 4447 * 4448 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4449 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4450 * mul-float, div-float, rem-float 4451 */ 4452 /* binop vAA, vBB, vCC */ 4453 FETCH(r0, 1) @ r0<- CCBB 4454 mov r9, rINST, lsr #8 @ r9<- AA 4455 mov r3, r0, lsr #8 @ r3<- CC 4456 and r2, r0, #255 @ r2<- BB 4457 GET_VREG(r1, r3) @ r1<- vCC 4458 GET_VREG(r0, r2) @ r0<- vBB 4459 .if 0 4460 cmp r1, #0 @ is second operand zero? 4461 beq common_errDivideByZero 4462 .endif 4463 4464 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4465 @ optional op; may set condition codes 4466 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4467 GET_INST_OPCODE(ip) @ extract opcode from rINST 4468 SET_VREG(r0, r9) @ vAA<- r0 4469 GOTO_OPCODE(ip) @ jump to next instruction 4470 /* 11-14 instructions */ 4471 4472 4473/* ------------------------------ */ 4474 .balign 64 4475.L_OP_SHL_INT: /* 0x98 */ 4476/* File: armv5te/OP_SHL_INT.S */ 4477/* File: armv5te/binop.S */ 4478 /* 4479 * Generic 32-bit binary operation. Provide an "instr" line that 4480 * specifies an instruction that performs "result = r0 op r1". 4481 * This could be an ARM instruction or a function call. (If the result 4482 * comes back in a register other than r0, you can override "result".) 4483 * 4484 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4485 * vCC (r1). Useful for integer division and modulus. Note that we 4486 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4487 * handles it correctly. 4488 * 4489 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4490 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4491 * mul-float, div-float, rem-float 4492 */ 4493 /* binop vAA, vBB, vCC */ 4494 FETCH(r0, 1) @ r0<- CCBB 4495 mov r9, rINST, lsr #8 @ r9<- AA 4496 mov r3, r0, lsr #8 @ r3<- CC 4497 and r2, r0, #255 @ r2<- BB 4498 GET_VREG(r1, r3) @ r1<- vCC 4499 GET_VREG(r0, r2) @ r0<- vBB 4500 .if 0 4501 cmp r1, #0 @ is second operand zero? 4502 beq common_errDivideByZero 4503 .endif 4504 4505 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4506 and r1, r1, #31 @ optional op; may set condition codes 4507 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4508 GET_INST_OPCODE(ip) @ extract opcode from rINST 4509 SET_VREG(r0, r9) @ vAA<- r0 4510 GOTO_OPCODE(ip) @ jump to next instruction 4511 /* 11-14 instructions */ 4512 4513 4514/* ------------------------------ */ 4515 .balign 64 4516.L_OP_SHR_INT: /* 0x99 */ 4517/* File: armv5te/OP_SHR_INT.S */ 4518/* File: armv5te/binop.S */ 4519 /* 4520 * Generic 32-bit binary operation. Provide an "instr" line that 4521 * specifies an instruction that performs "result = r0 op r1". 4522 * This could be an ARM instruction or a function call. (If the result 4523 * comes back in a register other than r0, you can override "result".) 4524 * 4525 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4526 * vCC (r1). Useful for integer division and modulus. Note that we 4527 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4528 * handles it correctly. 4529 * 4530 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4531 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4532 * mul-float, div-float, rem-float 4533 */ 4534 /* binop vAA, vBB, vCC */ 4535 FETCH(r0, 1) @ r0<- CCBB 4536 mov r9, rINST, lsr #8 @ r9<- AA 4537 mov r3, r0, lsr #8 @ r3<- CC 4538 and r2, r0, #255 @ r2<- BB 4539 GET_VREG(r1, r3) @ r1<- vCC 4540 GET_VREG(r0, r2) @ r0<- vBB 4541 .if 0 4542 cmp r1, #0 @ is second operand zero? 4543 beq common_errDivideByZero 4544 .endif 4545 4546 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4547 and r1, r1, #31 @ optional op; may set condition codes 4548 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4549 GET_INST_OPCODE(ip) @ extract opcode from rINST 4550 SET_VREG(r0, r9) @ vAA<- r0 4551 GOTO_OPCODE(ip) @ jump to next instruction 4552 /* 11-14 instructions */ 4553 4554 4555/* ------------------------------ */ 4556 .balign 64 4557.L_OP_USHR_INT: /* 0x9a */ 4558/* File: armv5te/OP_USHR_INT.S */ 4559/* File: armv5te/binop.S */ 4560 /* 4561 * Generic 32-bit binary operation. Provide an "instr" line that 4562 * specifies an instruction that performs "result = r0 op r1". 4563 * This could be an ARM instruction or a function call. (If the result 4564 * comes back in a register other than r0, you can override "result".) 4565 * 4566 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4567 * vCC (r1). Useful for integer division and modulus. Note that we 4568 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4569 * handles it correctly. 4570 * 4571 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4572 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4573 * mul-float, div-float, rem-float 4574 */ 4575 /* binop vAA, vBB, vCC */ 4576 FETCH(r0, 1) @ r0<- CCBB 4577 mov r9, rINST, lsr #8 @ r9<- AA 4578 mov r3, r0, lsr #8 @ r3<- CC 4579 and r2, r0, #255 @ r2<- BB 4580 GET_VREG(r1, r3) @ r1<- vCC 4581 GET_VREG(r0, r2) @ r0<- vBB 4582 .if 0 4583 cmp r1, #0 @ is second operand zero? 4584 beq common_errDivideByZero 4585 .endif 4586 4587 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4588 and r1, r1, #31 @ optional op; may set condition codes 4589 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4590 GET_INST_OPCODE(ip) @ extract opcode from rINST 4591 SET_VREG(r0, r9) @ vAA<- r0 4592 GOTO_OPCODE(ip) @ jump to next instruction 4593 /* 11-14 instructions */ 4594 4595 4596/* ------------------------------ */ 4597 .balign 64 4598.L_OP_ADD_LONG: /* 0x9b */ 4599/* File: armv5te/OP_ADD_LONG.S */ 4600/* File: armv5te/binopWide.S */ 4601 /* 4602 * Generic 64-bit binary operation. Provide an "instr" line that 4603 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4604 * This could be an ARM instruction or a function call. (If the result 4605 * comes back in a register other than r0, you can override "result".) 4606 * 4607 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4608 * vCC (r1). Useful for integer division and modulus. 4609 * 4610 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4611 * xor-long, add-double, sub-double, mul-double, div-double, 4612 * rem-double 4613 * 4614 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4615 */ 4616 /* binop vAA, vBB, vCC */ 4617 FETCH(r0, 1) @ r0<- CCBB 4618 mov r9, rINST, lsr #8 @ r9<- AA 4619 and r2, r0, #255 @ r2<- BB 4620 mov r3, r0, lsr #8 @ r3<- CC 4621 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4622 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4623 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4624 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4625 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4626 .if 0 4627 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4628 beq common_errDivideByZero 4629 .endif 4630 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4631 4632 adds r0, r0, r2 @ optional op; may set condition codes 4633 adc r1, r1, r3 @ result<- op, r0-r3 changed 4634 GET_INST_OPCODE(ip) @ extract opcode from rINST 4635 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4636 GOTO_OPCODE(ip) @ jump to next instruction 4637 /* 14-17 instructions */ 4638 4639 4640/* ------------------------------ */ 4641 .balign 64 4642.L_OP_SUB_LONG: /* 0x9c */ 4643/* File: armv5te/OP_SUB_LONG.S */ 4644/* File: armv5te/binopWide.S */ 4645 /* 4646 * Generic 64-bit binary operation. Provide an "instr" line that 4647 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4648 * This could be an ARM instruction or a function call. (If the result 4649 * comes back in a register other than r0, you can override "result".) 4650 * 4651 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4652 * vCC (r1). Useful for integer division and modulus. 4653 * 4654 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4655 * xor-long, add-double, sub-double, mul-double, div-double, 4656 * rem-double 4657 * 4658 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4659 */ 4660 /* binop vAA, vBB, vCC */ 4661 FETCH(r0, 1) @ r0<- CCBB 4662 mov r9, rINST, lsr #8 @ r9<- AA 4663 and r2, r0, #255 @ r2<- BB 4664 mov r3, r0, lsr #8 @ r3<- CC 4665 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4666 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4667 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4668 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4669 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4670 .if 0 4671 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4672 beq common_errDivideByZero 4673 .endif 4674 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4675 4676 subs r0, r0, r2 @ optional op; may set condition codes 4677 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4678 GET_INST_OPCODE(ip) @ extract opcode from rINST 4679 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4680 GOTO_OPCODE(ip) @ jump to next instruction 4681 /* 14-17 instructions */ 4682 4683 4684/* ------------------------------ */ 4685 .balign 64 4686.L_OP_MUL_LONG: /* 0x9d */ 4687/* File: armv5te/OP_MUL_LONG.S */ 4688 /* 4689 * Signed 64-bit integer multiply. 4690 * 4691 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4692 * WX 4693 * x YZ 4694 * -------- 4695 * ZW ZX 4696 * YW YX 4697 * 4698 * The low word of the result holds ZX, the high word holds 4699 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4700 * it doesn't fit in the low 64 bits. 4701 * 4702 * Unlike most ARM math operations, multiply instructions have 4703 * restrictions on using the same register more than once (Rd and Rm 4704 * cannot be the same). 4705 */ 4706 /* mul-long vAA, vBB, vCC */ 4707 FETCH(r0, 1) @ r0<- CCBB 4708 and r2, r0, #255 @ r2<- BB 4709 mov r3, r0, lsr #8 @ r3<- CC 4710 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4711 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4712 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4713 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4714 mul ip, r2, r1 @ ip<- ZxW 4715 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4716 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4717 mov r0, rINST, lsr #8 @ r0<- AA 4718 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4719 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4720 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4721 b .LOP_MUL_LONG_finish 4722 4723/* ------------------------------ */ 4724 .balign 64 4725.L_OP_DIV_LONG: /* 0x9e */ 4726/* File: armv5te/OP_DIV_LONG.S */ 4727/* File: armv5te/binopWide.S */ 4728 /* 4729 * Generic 64-bit binary operation. Provide an "instr" line that 4730 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4731 * This could be an ARM instruction or a function call. (If the result 4732 * comes back in a register other than r0, you can override "result".) 4733 * 4734 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4735 * vCC (r1). Useful for integer division and modulus. 4736 * 4737 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4738 * xor-long, add-double, sub-double, mul-double, div-double, 4739 * rem-double 4740 * 4741 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4742 */ 4743 /* binop vAA, vBB, vCC */ 4744 FETCH(r0, 1) @ r0<- CCBB 4745 mov r9, rINST, lsr #8 @ r9<- AA 4746 and r2, r0, #255 @ r2<- BB 4747 mov r3, r0, lsr #8 @ r3<- CC 4748 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4749 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4750 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4751 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4752 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4753 .if 1 4754 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4755 beq common_errDivideByZero 4756 .endif 4757 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4758 4759 @ optional op; may set condition codes 4760 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4761 GET_INST_OPCODE(ip) @ extract opcode from rINST 4762 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4763 GOTO_OPCODE(ip) @ jump to next instruction 4764 /* 14-17 instructions */ 4765 4766 4767/* ------------------------------ */ 4768 .balign 64 4769.L_OP_REM_LONG: /* 0x9f */ 4770/* File: armv5te/OP_REM_LONG.S */ 4771/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4772/* File: armv5te/binopWide.S */ 4773 /* 4774 * Generic 64-bit binary operation. Provide an "instr" line that 4775 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4776 * This could be an ARM instruction or a function call. (If the result 4777 * comes back in a register other than r0, you can override "result".) 4778 * 4779 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4780 * vCC (r1). Useful for integer division and modulus. 4781 * 4782 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4783 * xor-long, add-double, sub-double, mul-double, div-double, 4784 * rem-double 4785 * 4786 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4787 */ 4788 /* binop vAA, vBB, vCC */ 4789 FETCH(r0, 1) @ r0<- CCBB 4790 mov r9, rINST, lsr #8 @ r9<- AA 4791 and r2, r0, #255 @ r2<- BB 4792 mov r3, r0, lsr #8 @ r3<- CC 4793 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4794 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4795 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4796 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4797 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4798 .if 1 4799 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4800 beq common_errDivideByZero 4801 .endif 4802 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4803 4804 @ optional op; may set condition codes 4805 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4806 GET_INST_OPCODE(ip) @ extract opcode from rINST 4807 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4808 GOTO_OPCODE(ip) @ jump to next instruction 4809 /* 14-17 instructions */ 4810 4811 4812/* ------------------------------ */ 4813 .balign 64 4814.L_OP_AND_LONG: /* 0xa0 */ 4815/* File: armv5te/OP_AND_LONG.S */ 4816/* File: armv5te/binopWide.S */ 4817 /* 4818 * Generic 64-bit binary operation. Provide an "instr" line that 4819 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4820 * This could be an ARM instruction or a function call. (If the result 4821 * comes back in a register other than r0, you can override "result".) 4822 * 4823 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4824 * vCC (r1). Useful for integer division and modulus. 4825 * 4826 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4827 * xor-long, add-double, sub-double, mul-double, div-double, 4828 * rem-double 4829 * 4830 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4831 */ 4832 /* binop vAA, vBB, vCC */ 4833 FETCH(r0, 1) @ r0<- CCBB 4834 mov r9, rINST, lsr #8 @ r9<- AA 4835 and r2, r0, #255 @ r2<- BB 4836 mov r3, r0, lsr #8 @ r3<- CC 4837 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4838 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4839 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4840 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4841 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4842 .if 0 4843 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4844 beq common_errDivideByZero 4845 .endif 4846 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4847 4848 and r0, r0, r2 @ optional op; may set condition codes 4849 and r1, r1, r3 @ result<- op, r0-r3 changed 4850 GET_INST_OPCODE(ip) @ extract opcode from rINST 4851 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4852 GOTO_OPCODE(ip) @ jump to next instruction 4853 /* 14-17 instructions */ 4854 4855 4856/* ------------------------------ */ 4857 .balign 64 4858.L_OP_OR_LONG: /* 0xa1 */ 4859/* File: armv5te/OP_OR_LONG.S */ 4860/* File: armv5te/binopWide.S */ 4861 /* 4862 * Generic 64-bit binary operation. Provide an "instr" line that 4863 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4864 * This could be an ARM instruction or a function call. (If the result 4865 * comes back in a register other than r0, you can override "result".) 4866 * 4867 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4868 * vCC (r1). Useful for integer division and modulus. 4869 * 4870 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4871 * xor-long, add-double, sub-double, mul-double, div-double, 4872 * rem-double 4873 * 4874 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4875 */ 4876 /* binop vAA, vBB, vCC */ 4877 FETCH(r0, 1) @ r0<- CCBB 4878 mov r9, rINST, lsr #8 @ r9<- AA 4879 and r2, r0, #255 @ r2<- BB 4880 mov r3, r0, lsr #8 @ r3<- CC 4881 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4882 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4883 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4884 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4885 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4886 .if 0 4887 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4888 beq common_errDivideByZero 4889 .endif 4890 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4891 4892 orr r0, r0, r2 @ optional op; may set condition codes 4893 orr r1, r1, r3 @ result<- op, r0-r3 changed 4894 GET_INST_OPCODE(ip) @ extract opcode from rINST 4895 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4896 GOTO_OPCODE(ip) @ jump to next instruction 4897 /* 14-17 instructions */ 4898 4899 4900/* ------------------------------ */ 4901 .balign 64 4902.L_OP_XOR_LONG: /* 0xa2 */ 4903/* File: armv5te/OP_XOR_LONG.S */ 4904/* File: armv5te/binopWide.S */ 4905 /* 4906 * Generic 64-bit binary operation. Provide an "instr" line that 4907 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4908 * This could be an ARM instruction or a function call. (If the result 4909 * comes back in a register other than r0, you can override "result".) 4910 * 4911 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4912 * vCC (r1). Useful for integer division and modulus. 4913 * 4914 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4915 * xor-long, add-double, sub-double, mul-double, div-double, 4916 * rem-double 4917 * 4918 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4919 */ 4920 /* binop vAA, vBB, vCC */ 4921 FETCH(r0, 1) @ r0<- CCBB 4922 mov r9, rINST, lsr #8 @ r9<- AA 4923 and r2, r0, #255 @ r2<- BB 4924 mov r3, r0, lsr #8 @ r3<- CC 4925 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4926 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4927 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4928 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4929 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4930 .if 0 4931 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4932 beq common_errDivideByZero 4933 .endif 4934 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4935 4936 eor r0, r0, r2 @ optional op; may set condition codes 4937 eor r1, r1, r3 @ result<- op, r0-r3 changed 4938 GET_INST_OPCODE(ip) @ extract opcode from rINST 4939 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4940 GOTO_OPCODE(ip) @ jump to next instruction 4941 /* 14-17 instructions */ 4942 4943 4944/* ------------------------------ */ 4945 .balign 64 4946.L_OP_SHL_LONG: /* 0xa3 */ 4947/* File: armv5te/OP_SHL_LONG.S */ 4948 /* 4949 * Long integer shift. This is different from the generic 32/64-bit 4950 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4951 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4952 * 6 bits of the shift distance. 4953 */ 4954 /* shl-long vAA, vBB, vCC */ 4955 FETCH(r0, 1) @ r0<- CCBB 4956 mov r9, rINST, lsr #8 @ r9<- AA 4957 and r3, r0, #255 @ r3<- BB 4958 mov r0, r0, lsr #8 @ r0<- CC 4959 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4960 GET_VREG(r2, r0) @ r2<- vCC 4961 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4962 and r2, r2, #63 @ r2<- r2 & 0x3f 4963 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4964 4965 mov r1, r1, asl r2 @ r1<- r1 << r2 4966 rsb r3, r2, #32 @ r3<- 32 - r2 4967 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4968 subs ip, r2, #32 @ ip<- r2 - 32 4969 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4970 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4971 b .LOP_SHL_LONG_finish 4972 4973/* ------------------------------ */ 4974 .balign 64 4975.L_OP_SHR_LONG: /* 0xa4 */ 4976/* File: armv5te/OP_SHR_LONG.S */ 4977 /* 4978 * Long integer shift. This is different from the generic 32/64-bit 4979 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4980 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4981 * 6 bits of the shift distance. 4982 */ 4983 /* shr-long vAA, vBB, vCC */ 4984 FETCH(r0, 1) @ r0<- CCBB 4985 mov r9, rINST, lsr #8 @ r9<- AA 4986 and r3, r0, #255 @ r3<- BB 4987 mov r0, r0, lsr #8 @ r0<- CC 4988 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4989 GET_VREG(r2, r0) @ r2<- vCC 4990 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4991 and r2, r2, #63 @ r0<- r0 & 0x3f 4992 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4993 4994 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4995 rsb r3, r2, #32 @ r3<- 32 - r2 4996 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4997 subs ip, r2, #32 @ ip<- r2 - 32 4998 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4999 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5000 b .LOP_SHR_LONG_finish 5001 5002/* ------------------------------ */ 5003 .balign 64 5004.L_OP_USHR_LONG: /* 0xa5 */ 5005/* File: armv5te/OP_USHR_LONG.S */ 5006 /* 5007 * Long integer shift. This is different from the generic 32/64-bit 5008 * binary operations because vAA/vBB are 64-bit but vCC (the shift 5009 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5010 * 6 bits of the shift distance. 5011 */ 5012 /* ushr-long vAA, vBB, vCC */ 5013 FETCH(r0, 1) @ r0<- CCBB 5014 mov r9, rINST, lsr #8 @ r9<- AA 5015 and r3, r0, #255 @ r3<- BB 5016 mov r0, r0, lsr #8 @ r0<- CC 5017 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 5018 GET_VREG(r2, r0) @ r2<- vCC 5019 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 5020 and r2, r2, #63 @ r0<- r0 & 0x3f 5021 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5022 5023 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5024 rsb r3, r2, #32 @ r3<- 32 - r2 5025 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5026 subs ip, r2, #32 @ ip<- r2 - 32 5027 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 5028 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5029 b .LOP_USHR_LONG_finish 5030 5031/* ------------------------------ */ 5032 .balign 64 5033.L_OP_ADD_FLOAT: /* 0xa6 */ 5034/* File: armv5te/OP_ADD_FLOAT.S */ 5035/* File: armv5te/binop.S */ 5036 /* 5037 * Generic 32-bit binary operation. Provide an "instr" line that 5038 * specifies an instruction that performs "result = r0 op r1". 5039 * This could be an ARM instruction or a function call. (If the result 5040 * comes back in a register other than r0, you can override "result".) 5041 * 5042 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5043 * vCC (r1). Useful for integer division and modulus. Note that we 5044 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5045 * handles it correctly. 5046 * 5047 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5048 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5049 * mul-float, div-float, rem-float 5050 */ 5051 /* binop vAA, vBB, vCC */ 5052 FETCH(r0, 1) @ r0<- CCBB 5053 mov r9, rINST, lsr #8 @ r9<- AA 5054 mov r3, r0, lsr #8 @ r3<- CC 5055 and r2, r0, #255 @ r2<- BB 5056 GET_VREG(r1, r3) @ r1<- vCC 5057 GET_VREG(r0, r2) @ r0<- vBB 5058 .if 0 5059 cmp r1, #0 @ is second operand zero? 5060 beq common_errDivideByZero 5061 .endif 5062 5063 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5064 @ optional op; may set condition codes 5065 bl __aeabi_fadd @ r0<- op, r0-r3 changed 5066 GET_INST_OPCODE(ip) @ extract opcode from rINST 5067 SET_VREG(r0, r9) @ vAA<- r0 5068 GOTO_OPCODE(ip) @ jump to next instruction 5069 /* 11-14 instructions */ 5070 5071 5072/* ------------------------------ */ 5073 .balign 64 5074.L_OP_SUB_FLOAT: /* 0xa7 */ 5075/* File: armv5te/OP_SUB_FLOAT.S */ 5076/* File: armv5te/binop.S */ 5077 /* 5078 * Generic 32-bit binary operation. Provide an "instr" line that 5079 * specifies an instruction that performs "result = r0 op r1". 5080 * This could be an ARM instruction or a function call. (If the result 5081 * comes back in a register other than r0, you can override "result".) 5082 * 5083 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5084 * vCC (r1). Useful for integer division and modulus. Note that we 5085 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5086 * handles it correctly. 5087 * 5088 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5089 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5090 * mul-float, div-float, rem-float 5091 */ 5092 /* binop vAA, vBB, vCC */ 5093 FETCH(r0, 1) @ r0<- CCBB 5094 mov r9, rINST, lsr #8 @ r9<- AA 5095 mov r3, r0, lsr #8 @ r3<- CC 5096 and r2, r0, #255 @ r2<- BB 5097 GET_VREG(r1, r3) @ r1<- vCC 5098 GET_VREG(r0, r2) @ r0<- vBB 5099 .if 0 5100 cmp r1, #0 @ is second operand zero? 5101 beq common_errDivideByZero 5102 .endif 5103 5104 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5105 @ optional op; may set condition codes 5106 bl __aeabi_fsub @ r0<- op, r0-r3 changed 5107 GET_INST_OPCODE(ip) @ extract opcode from rINST 5108 SET_VREG(r0, r9) @ vAA<- r0 5109 GOTO_OPCODE(ip) @ jump to next instruction 5110 /* 11-14 instructions */ 5111 5112 5113/* ------------------------------ */ 5114 .balign 64 5115.L_OP_MUL_FLOAT: /* 0xa8 */ 5116/* File: armv5te/OP_MUL_FLOAT.S */ 5117/* File: armv5te/binop.S */ 5118 /* 5119 * Generic 32-bit binary operation. Provide an "instr" line that 5120 * specifies an instruction that performs "result = r0 op r1". 5121 * This could be an ARM instruction or a function call. (If the result 5122 * comes back in a register other than r0, you can override "result".) 5123 * 5124 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5125 * vCC (r1). Useful for integer division and modulus. Note that we 5126 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5127 * handles it correctly. 5128 * 5129 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5130 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5131 * mul-float, div-float, rem-float 5132 */ 5133 /* binop vAA, vBB, vCC */ 5134 FETCH(r0, 1) @ r0<- CCBB 5135 mov r9, rINST, lsr #8 @ r9<- AA 5136 mov r3, r0, lsr #8 @ r3<- CC 5137 and r2, r0, #255 @ r2<- BB 5138 GET_VREG(r1, r3) @ r1<- vCC 5139 GET_VREG(r0, r2) @ r0<- vBB 5140 .if 0 5141 cmp r1, #0 @ is second operand zero? 5142 beq common_errDivideByZero 5143 .endif 5144 5145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5146 @ optional op; may set condition codes 5147 bl __aeabi_fmul @ r0<- op, r0-r3 changed 5148 GET_INST_OPCODE(ip) @ extract opcode from rINST 5149 SET_VREG(r0, r9) @ vAA<- r0 5150 GOTO_OPCODE(ip) @ jump to next instruction 5151 /* 11-14 instructions */ 5152 5153 5154/* ------------------------------ */ 5155 .balign 64 5156.L_OP_DIV_FLOAT: /* 0xa9 */ 5157/* File: armv5te/OP_DIV_FLOAT.S */ 5158/* File: armv5te/binop.S */ 5159 /* 5160 * Generic 32-bit binary operation. Provide an "instr" line that 5161 * specifies an instruction that performs "result = r0 op r1". 5162 * This could be an ARM instruction or a function call. (If the result 5163 * comes back in a register other than r0, you can override "result".) 5164 * 5165 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5166 * vCC (r1). Useful for integer division and modulus. Note that we 5167 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5168 * handles it correctly. 5169 * 5170 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5171 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5172 * mul-float, div-float, rem-float 5173 */ 5174 /* binop vAA, vBB, vCC */ 5175 FETCH(r0, 1) @ r0<- CCBB 5176 mov r9, rINST, lsr #8 @ r9<- AA 5177 mov r3, r0, lsr #8 @ r3<- CC 5178 and r2, r0, #255 @ r2<- BB 5179 GET_VREG(r1, r3) @ r1<- vCC 5180 GET_VREG(r0, r2) @ r0<- vBB 5181 .if 0 5182 cmp r1, #0 @ is second operand zero? 5183 beq common_errDivideByZero 5184 .endif 5185 5186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5187 @ optional op; may set condition codes 5188 bl __aeabi_fdiv @ r0<- op, r0-r3 changed 5189 GET_INST_OPCODE(ip) @ extract opcode from rINST 5190 SET_VREG(r0, r9) @ vAA<- r0 5191 GOTO_OPCODE(ip) @ jump to next instruction 5192 /* 11-14 instructions */ 5193 5194 5195/* ------------------------------ */ 5196 .balign 64 5197.L_OP_REM_FLOAT: /* 0xaa */ 5198/* File: armv5te/OP_REM_FLOAT.S */ 5199/* EABI doesn't define a float remainder function, but libm does */ 5200/* File: armv5te/binop.S */ 5201 /* 5202 * Generic 32-bit binary operation. Provide an "instr" line that 5203 * specifies an instruction that performs "result = r0 op r1". 5204 * This could be an ARM instruction or a function call. (If the result 5205 * comes back in a register other than r0, you can override "result".) 5206 * 5207 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5208 * vCC (r1). Useful for integer division and modulus. Note that we 5209 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5210 * handles it correctly. 5211 * 5212 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5213 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5214 * mul-float, div-float, rem-float 5215 */ 5216 /* binop vAA, vBB, vCC */ 5217 FETCH(r0, 1) @ r0<- CCBB 5218 mov r9, rINST, lsr #8 @ r9<- AA 5219 mov r3, r0, lsr #8 @ r3<- CC 5220 and r2, r0, #255 @ r2<- BB 5221 GET_VREG(r1, r3) @ r1<- vCC 5222 GET_VREG(r0, r2) @ r0<- vBB 5223 .if 0 5224 cmp r1, #0 @ is second operand zero? 5225 beq common_errDivideByZero 5226 .endif 5227 5228 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5229 @ optional op; may set condition codes 5230 bl fmodf @ r0<- op, r0-r3 changed 5231 GET_INST_OPCODE(ip) @ extract opcode from rINST 5232 SET_VREG(r0, r9) @ vAA<- r0 5233 GOTO_OPCODE(ip) @ jump to next instruction 5234 /* 11-14 instructions */ 5235 5236 5237/* ------------------------------ */ 5238 .balign 64 5239.L_OP_ADD_DOUBLE: /* 0xab */ 5240/* File: armv5te/OP_ADD_DOUBLE.S */ 5241/* File: armv5te/binopWide.S */ 5242 /* 5243 * Generic 64-bit binary operation. Provide an "instr" line that 5244 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5245 * This could be an ARM instruction or a function call. (If the result 5246 * comes back in a register other than r0, you can override "result".) 5247 * 5248 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5249 * vCC (r1). Useful for integer division and modulus. 5250 * 5251 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5252 * xor-long, add-double, sub-double, mul-double, div-double, 5253 * rem-double 5254 * 5255 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5256 */ 5257 /* binop vAA, vBB, vCC */ 5258 FETCH(r0, 1) @ r0<- CCBB 5259 mov r9, rINST, lsr #8 @ r9<- AA 5260 and r2, r0, #255 @ r2<- BB 5261 mov r3, r0, lsr #8 @ r3<- CC 5262 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5263 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5264 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5265 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5266 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5267 .if 0 5268 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5269 beq common_errDivideByZero 5270 .endif 5271 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5272 5273 @ optional op; may set condition codes 5274 bl __aeabi_dadd @ result<- op, r0-r3 changed 5275 GET_INST_OPCODE(ip) @ extract opcode from rINST 5276 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5277 GOTO_OPCODE(ip) @ jump to next instruction 5278 /* 14-17 instructions */ 5279 5280 5281/* ------------------------------ */ 5282 .balign 64 5283.L_OP_SUB_DOUBLE: /* 0xac */ 5284/* File: armv5te/OP_SUB_DOUBLE.S */ 5285/* File: armv5te/binopWide.S */ 5286 /* 5287 * Generic 64-bit binary operation. Provide an "instr" line that 5288 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5289 * This could be an ARM instruction or a function call. (If the result 5290 * comes back in a register other than r0, you can override "result".) 5291 * 5292 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5293 * vCC (r1). Useful for integer division and modulus. 5294 * 5295 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5296 * xor-long, add-double, sub-double, mul-double, div-double, 5297 * rem-double 5298 * 5299 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5300 */ 5301 /* binop vAA, vBB, vCC */ 5302 FETCH(r0, 1) @ r0<- CCBB 5303 mov r9, rINST, lsr #8 @ r9<- AA 5304 and r2, r0, #255 @ r2<- BB 5305 mov r3, r0, lsr #8 @ r3<- CC 5306 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5307 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5308 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5309 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5310 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5311 .if 0 5312 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5313 beq common_errDivideByZero 5314 .endif 5315 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5316 5317 @ optional op; may set condition codes 5318 bl __aeabi_dsub @ result<- op, r0-r3 changed 5319 GET_INST_OPCODE(ip) @ extract opcode from rINST 5320 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5321 GOTO_OPCODE(ip) @ jump to next instruction 5322 /* 14-17 instructions */ 5323 5324 5325/* ------------------------------ */ 5326 .balign 64 5327.L_OP_MUL_DOUBLE: /* 0xad */ 5328/* File: armv5te/OP_MUL_DOUBLE.S */ 5329/* File: armv5te/binopWide.S */ 5330 /* 5331 * Generic 64-bit binary operation. Provide an "instr" line that 5332 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5333 * This could be an ARM instruction or a function call. (If the result 5334 * comes back in a register other than r0, you can override "result".) 5335 * 5336 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5337 * vCC (r1). Useful for integer division and modulus. 5338 * 5339 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5340 * xor-long, add-double, sub-double, mul-double, div-double, 5341 * rem-double 5342 * 5343 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5344 */ 5345 /* binop vAA, vBB, vCC */ 5346 FETCH(r0, 1) @ r0<- CCBB 5347 mov r9, rINST, lsr #8 @ r9<- AA 5348 and r2, r0, #255 @ r2<- BB 5349 mov r3, r0, lsr #8 @ r3<- CC 5350 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5351 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5352 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5353 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5354 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5355 .if 0 5356 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5357 beq common_errDivideByZero 5358 .endif 5359 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5360 5361 @ optional op; may set condition codes 5362 bl __aeabi_dmul @ result<- op, r0-r3 changed 5363 GET_INST_OPCODE(ip) @ extract opcode from rINST 5364 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5365 GOTO_OPCODE(ip) @ jump to next instruction 5366 /* 14-17 instructions */ 5367 5368 5369/* ------------------------------ */ 5370 .balign 64 5371.L_OP_DIV_DOUBLE: /* 0xae */ 5372/* File: armv5te/OP_DIV_DOUBLE.S */ 5373/* File: armv5te/binopWide.S */ 5374 /* 5375 * Generic 64-bit binary operation. Provide an "instr" line that 5376 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5377 * This could be an ARM instruction or a function call. (If the result 5378 * comes back in a register other than r0, you can override "result".) 5379 * 5380 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5381 * vCC (r1). Useful for integer division and modulus. 5382 * 5383 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5384 * xor-long, add-double, sub-double, mul-double, div-double, 5385 * rem-double 5386 * 5387 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5388 */ 5389 /* binop vAA, vBB, vCC */ 5390 FETCH(r0, 1) @ r0<- CCBB 5391 mov r9, rINST, lsr #8 @ r9<- AA 5392 and r2, r0, #255 @ r2<- BB 5393 mov r3, r0, lsr #8 @ r3<- CC 5394 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5395 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5396 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5397 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5398 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5399 .if 0 5400 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5401 beq common_errDivideByZero 5402 .endif 5403 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5404 5405 @ optional op; may set condition codes 5406 bl __aeabi_ddiv @ result<- op, r0-r3 changed 5407 GET_INST_OPCODE(ip) @ extract opcode from rINST 5408 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5409 GOTO_OPCODE(ip) @ jump to next instruction 5410 /* 14-17 instructions */ 5411 5412 5413/* ------------------------------ */ 5414 .balign 64 5415.L_OP_REM_DOUBLE: /* 0xaf */ 5416/* File: armv5te/OP_REM_DOUBLE.S */ 5417/* EABI doesn't define a double remainder function, but libm does */ 5418/* File: armv5te/binopWide.S */ 5419 /* 5420 * Generic 64-bit binary operation. Provide an "instr" line that 5421 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5422 * This could be an ARM instruction or a function call. (If the result 5423 * comes back in a register other than r0, you can override "result".) 5424 * 5425 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5426 * vCC (r1). Useful for integer division and modulus. 5427 * 5428 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5429 * xor-long, add-double, sub-double, mul-double, div-double, 5430 * rem-double 5431 * 5432 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5433 */ 5434 /* binop vAA, vBB, vCC */ 5435 FETCH(r0, 1) @ r0<- CCBB 5436 mov r9, rINST, lsr #8 @ r9<- AA 5437 and r2, r0, #255 @ r2<- BB 5438 mov r3, r0, lsr #8 @ r3<- CC 5439 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5440 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5441 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5442 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5443 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5444 .if 0 5445 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5446 beq common_errDivideByZero 5447 .endif 5448 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5449 5450 @ optional op; may set condition codes 5451 bl fmod @ result<- op, r0-r3 changed 5452 GET_INST_OPCODE(ip) @ extract opcode from rINST 5453 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5454 GOTO_OPCODE(ip) @ jump to next instruction 5455 /* 14-17 instructions */ 5456 5457 5458/* ------------------------------ */ 5459 .balign 64 5460.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5461/* File: armv5te/OP_ADD_INT_2ADDR.S */ 5462/* File: armv5te/binop2addr.S */ 5463 /* 5464 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5465 * that specifies an instruction that performs "result = r0 op r1". 5466 * This could be an ARM instruction or a function call. (If the result 5467 * comes back in a register other than r0, you can override "result".) 5468 * 5469 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5470 * vCC (r1). Useful for integer division and modulus. 5471 * 5472 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5473 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5474 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5475 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5476 */ 5477 /* binop/2addr vA, vB */ 5478 mov r9, rINST, lsr #8 @ r9<- A+ 5479 mov r3, rINST, lsr #12 @ r3<- B 5480 and r9, r9, #15 5481 GET_VREG(r1, r3) @ r1<- vB 5482 GET_VREG(r0, r9) @ r0<- vA 5483 .if 0 5484 cmp r1, #0 @ is second operand zero? 5485 beq common_errDivideByZero 5486 .endif 5487 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5488 5489 @ optional op; may set condition codes 5490 add r0, r0, r1 @ r0<- op, r0-r3 changed 5491 GET_INST_OPCODE(ip) @ extract opcode from rINST 5492 SET_VREG(r0, r9) @ vAA<- r0 5493 GOTO_OPCODE(ip) @ jump to next instruction 5494 /* 10-13 instructions */ 5495 5496 5497/* ------------------------------ */ 5498 .balign 64 5499.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5500/* File: armv5te/OP_SUB_INT_2ADDR.S */ 5501/* File: armv5te/binop2addr.S */ 5502 /* 5503 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5504 * that specifies an instruction that performs "result = r0 op r1". 5505 * This could be an ARM instruction or a function call. (If the result 5506 * comes back in a register other than r0, you can override "result".) 5507 * 5508 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5509 * vCC (r1). Useful for integer division and modulus. 5510 * 5511 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5512 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5513 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5514 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5515 */ 5516 /* binop/2addr vA, vB */ 5517 mov r9, rINST, lsr #8 @ r9<- A+ 5518 mov r3, rINST, lsr #12 @ r3<- B 5519 and r9, r9, #15 5520 GET_VREG(r1, r3) @ r1<- vB 5521 GET_VREG(r0, r9) @ r0<- vA 5522 .if 0 5523 cmp r1, #0 @ is second operand zero? 5524 beq common_errDivideByZero 5525 .endif 5526 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5527 5528 @ optional op; may set condition codes 5529 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5530 GET_INST_OPCODE(ip) @ extract opcode from rINST 5531 SET_VREG(r0, r9) @ vAA<- r0 5532 GOTO_OPCODE(ip) @ jump to next instruction 5533 /* 10-13 instructions */ 5534 5535 5536/* ------------------------------ */ 5537 .balign 64 5538.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5539/* File: armv5te/OP_MUL_INT_2ADDR.S */ 5540/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5541/* File: armv5te/binop2addr.S */ 5542 /* 5543 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5544 * that specifies an instruction that performs "result = r0 op r1". 5545 * This could be an ARM instruction or a function call. (If the result 5546 * comes back in a register other than r0, you can override "result".) 5547 * 5548 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5549 * vCC (r1). Useful for integer division and modulus. 5550 * 5551 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5552 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5553 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5554 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5555 */ 5556 /* binop/2addr vA, vB */ 5557 mov r9, rINST, lsr #8 @ r9<- A+ 5558 mov r3, rINST, lsr #12 @ r3<- B 5559 and r9, r9, #15 5560 GET_VREG(r1, r3) @ r1<- vB 5561 GET_VREG(r0, r9) @ r0<- vA 5562 .if 0 5563 cmp r1, #0 @ is second operand zero? 5564 beq common_errDivideByZero 5565 .endif 5566 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5567 5568 @ optional op; may set condition codes 5569 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5570 GET_INST_OPCODE(ip) @ extract opcode from rINST 5571 SET_VREG(r0, r9) @ vAA<- r0 5572 GOTO_OPCODE(ip) @ jump to next instruction 5573 /* 10-13 instructions */ 5574 5575 5576/* ------------------------------ */ 5577 .balign 64 5578.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5579/* File: armv5te/OP_DIV_INT_2ADDR.S */ 5580/* File: armv5te/binop2addr.S */ 5581 /* 5582 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5583 * that specifies an instruction that performs "result = r0 op r1". 5584 * This could be an ARM instruction or a function call. (If the result 5585 * comes back in a register other than r0, you can override "result".) 5586 * 5587 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5588 * vCC (r1). Useful for integer division and modulus. 5589 * 5590 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5591 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5592 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5593 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5594 */ 5595 /* binop/2addr vA, vB */ 5596 mov r9, rINST, lsr #8 @ r9<- A+ 5597 mov r3, rINST, lsr #12 @ r3<- B 5598 and r9, r9, #15 5599 GET_VREG(r1, r3) @ r1<- vB 5600 GET_VREG(r0, r9) @ r0<- vA 5601 .if 1 5602 cmp r1, #0 @ is second operand zero? 5603 beq common_errDivideByZero 5604 .endif 5605 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5606 5607 @ optional op; may set condition codes 5608 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5609 GET_INST_OPCODE(ip) @ extract opcode from rINST 5610 SET_VREG(r0, r9) @ vAA<- r0 5611 GOTO_OPCODE(ip) @ jump to next instruction 5612 /* 10-13 instructions */ 5613 5614 5615/* ------------------------------ */ 5616 .balign 64 5617.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5618/* File: armv5te/OP_REM_INT_2ADDR.S */ 5619/* idivmod returns quotient in r0 and remainder in r1 */ 5620/* File: armv5te/binop2addr.S */ 5621 /* 5622 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5623 * that specifies an instruction that performs "result = r0 op r1". 5624 * This could be an ARM instruction or a function call. (If the result 5625 * comes back in a register other than r0, you can override "result".) 5626 * 5627 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5628 * vCC (r1). Useful for integer division and modulus. 5629 * 5630 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5631 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5632 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5633 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5634 */ 5635 /* binop/2addr vA, vB */ 5636 mov r9, rINST, lsr #8 @ r9<- A+ 5637 mov r3, rINST, lsr #12 @ r3<- B 5638 and r9, r9, #15 5639 GET_VREG(r1, r3) @ r1<- vB 5640 GET_VREG(r0, r9) @ r0<- vA 5641 .if 1 5642 cmp r1, #0 @ is second operand zero? 5643 beq common_errDivideByZero 5644 .endif 5645 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5646 5647 @ optional op; may set condition codes 5648 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5649 GET_INST_OPCODE(ip) @ extract opcode from rINST 5650 SET_VREG(r1, r9) @ vAA<- r1 5651 GOTO_OPCODE(ip) @ jump to next instruction 5652 /* 10-13 instructions */ 5653 5654 5655/* ------------------------------ */ 5656 .balign 64 5657.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5658/* File: armv5te/OP_AND_INT_2ADDR.S */ 5659/* File: armv5te/binop2addr.S */ 5660 /* 5661 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5662 * that specifies an instruction that performs "result = r0 op r1". 5663 * This could be an ARM instruction or a function call. (If the result 5664 * comes back in a register other than r0, you can override "result".) 5665 * 5666 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5667 * vCC (r1). Useful for integer division and modulus. 5668 * 5669 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5670 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5671 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5672 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5673 */ 5674 /* binop/2addr vA, vB */ 5675 mov r9, rINST, lsr #8 @ r9<- A+ 5676 mov r3, rINST, lsr #12 @ r3<- B 5677 and r9, r9, #15 5678 GET_VREG(r1, r3) @ r1<- vB 5679 GET_VREG(r0, r9) @ r0<- vA 5680 .if 0 5681 cmp r1, #0 @ is second operand zero? 5682 beq common_errDivideByZero 5683 .endif 5684 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5685 5686 @ optional op; may set condition codes 5687 and r0, r0, r1 @ r0<- op, r0-r3 changed 5688 GET_INST_OPCODE(ip) @ extract opcode from rINST 5689 SET_VREG(r0, r9) @ vAA<- r0 5690 GOTO_OPCODE(ip) @ jump to next instruction 5691 /* 10-13 instructions */ 5692 5693 5694/* ------------------------------ */ 5695 .balign 64 5696.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5697/* File: armv5te/OP_OR_INT_2ADDR.S */ 5698/* File: armv5te/binop2addr.S */ 5699 /* 5700 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5701 * that specifies an instruction that performs "result = r0 op r1". 5702 * This could be an ARM instruction or a function call. (If the result 5703 * comes back in a register other than r0, you can override "result".) 5704 * 5705 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5706 * vCC (r1). Useful for integer division and modulus. 5707 * 5708 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5709 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5710 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5711 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5712 */ 5713 /* binop/2addr vA, vB */ 5714 mov r9, rINST, lsr #8 @ r9<- A+ 5715 mov r3, rINST, lsr #12 @ r3<- B 5716 and r9, r9, #15 5717 GET_VREG(r1, r3) @ r1<- vB 5718 GET_VREG(r0, r9) @ r0<- vA 5719 .if 0 5720 cmp r1, #0 @ is second operand zero? 5721 beq common_errDivideByZero 5722 .endif 5723 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5724 5725 @ optional op; may set condition codes 5726 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5727 GET_INST_OPCODE(ip) @ extract opcode from rINST 5728 SET_VREG(r0, r9) @ vAA<- r0 5729 GOTO_OPCODE(ip) @ jump to next instruction 5730 /* 10-13 instructions */ 5731 5732 5733/* ------------------------------ */ 5734 .balign 64 5735.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5736/* File: armv5te/OP_XOR_INT_2ADDR.S */ 5737/* File: armv5te/binop2addr.S */ 5738 /* 5739 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5740 * that specifies an instruction that performs "result = r0 op r1". 5741 * This could be an ARM instruction or a function call. (If the result 5742 * comes back in a register other than r0, you can override "result".) 5743 * 5744 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5745 * vCC (r1). Useful for integer division and modulus. 5746 * 5747 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5748 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5749 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5750 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5751 */ 5752 /* binop/2addr vA, vB */ 5753 mov r9, rINST, lsr #8 @ r9<- A+ 5754 mov r3, rINST, lsr #12 @ r3<- B 5755 and r9, r9, #15 5756 GET_VREG(r1, r3) @ r1<- vB 5757 GET_VREG(r0, r9) @ r0<- vA 5758 .if 0 5759 cmp r1, #0 @ is second operand zero? 5760 beq common_errDivideByZero 5761 .endif 5762 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5763 5764 @ optional op; may set condition codes 5765 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5766 GET_INST_OPCODE(ip) @ extract opcode from rINST 5767 SET_VREG(r0, r9) @ vAA<- r0 5768 GOTO_OPCODE(ip) @ jump to next instruction 5769 /* 10-13 instructions */ 5770 5771 5772/* ------------------------------ */ 5773 .balign 64 5774.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5775/* File: armv5te/OP_SHL_INT_2ADDR.S */ 5776/* File: armv5te/binop2addr.S */ 5777 /* 5778 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5779 * that specifies an instruction that performs "result = r0 op r1". 5780 * This could be an ARM instruction or a function call. (If the result 5781 * comes back in a register other than r0, you can override "result".) 5782 * 5783 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5784 * vCC (r1). Useful for integer division and modulus. 5785 * 5786 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5787 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5788 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5789 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5790 */ 5791 /* binop/2addr vA, vB */ 5792 mov r9, rINST, lsr #8 @ r9<- A+ 5793 mov r3, rINST, lsr #12 @ r3<- B 5794 and r9, r9, #15 5795 GET_VREG(r1, r3) @ r1<- vB 5796 GET_VREG(r0, r9) @ r0<- vA 5797 .if 0 5798 cmp r1, #0 @ is second operand zero? 5799 beq common_errDivideByZero 5800 .endif 5801 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5802 5803 and r1, r1, #31 @ optional op; may set condition codes 5804 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5805 GET_INST_OPCODE(ip) @ extract opcode from rINST 5806 SET_VREG(r0, r9) @ vAA<- r0 5807 GOTO_OPCODE(ip) @ jump to next instruction 5808 /* 10-13 instructions */ 5809 5810 5811/* ------------------------------ */ 5812 .balign 64 5813.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5814/* File: armv5te/OP_SHR_INT_2ADDR.S */ 5815/* File: armv5te/binop2addr.S */ 5816 /* 5817 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5818 * that specifies an instruction that performs "result = r0 op r1". 5819 * This could be an ARM instruction or a function call. (If the result 5820 * comes back in a register other than r0, you can override "result".) 5821 * 5822 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5823 * vCC (r1). Useful for integer division and modulus. 5824 * 5825 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5826 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5827 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5828 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5829 */ 5830 /* binop/2addr vA, vB */ 5831 mov r9, rINST, lsr #8 @ r9<- A+ 5832 mov r3, rINST, lsr #12 @ r3<- B 5833 and r9, r9, #15 5834 GET_VREG(r1, r3) @ r1<- vB 5835 GET_VREG(r0, r9) @ r0<- vA 5836 .if 0 5837 cmp r1, #0 @ is second operand zero? 5838 beq common_errDivideByZero 5839 .endif 5840 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5841 5842 and r1, r1, #31 @ optional op; may set condition codes 5843 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5844 GET_INST_OPCODE(ip) @ extract opcode from rINST 5845 SET_VREG(r0, r9) @ vAA<- r0 5846 GOTO_OPCODE(ip) @ jump to next instruction 5847 /* 10-13 instructions */ 5848 5849 5850/* ------------------------------ */ 5851 .balign 64 5852.L_OP_USHR_INT_2ADDR: /* 0xba */ 5853/* File: armv5te/OP_USHR_INT_2ADDR.S */ 5854/* File: armv5te/binop2addr.S */ 5855 /* 5856 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5857 * that specifies an instruction that performs "result = r0 op r1". 5858 * This could be an ARM instruction or a function call. (If the result 5859 * comes back in a register other than r0, you can override "result".) 5860 * 5861 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5862 * vCC (r1). Useful for integer division and modulus. 5863 * 5864 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5865 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5866 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5867 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5868 */ 5869 /* binop/2addr vA, vB */ 5870 mov r9, rINST, lsr #8 @ r9<- A+ 5871 mov r3, rINST, lsr #12 @ r3<- B 5872 and r9, r9, #15 5873 GET_VREG(r1, r3) @ r1<- vB 5874 GET_VREG(r0, r9) @ r0<- vA 5875 .if 0 5876 cmp r1, #0 @ is second operand zero? 5877 beq common_errDivideByZero 5878 .endif 5879 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5880 5881 and r1, r1, #31 @ optional op; may set condition codes 5882 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5883 GET_INST_OPCODE(ip) @ extract opcode from rINST 5884 SET_VREG(r0, r9) @ vAA<- r0 5885 GOTO_OPCODE(ip) @ jump to next instruction 5886 /* 10-13 instructions */ 5887 5888 5889/* ------------------------------ */ 5890 .balign 64 5891.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5892/* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5893/* File: armv5te/binopWide2addr.S */ 5894 /* 5895 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5896 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5897 * This could be an ARM instruction or a function call. (If the result 5898 * comes back in a register other than r0, you can override "result".) 5899 * 5900 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5901 * vCC (r1). Useful for integer division and modulus. 5902 * 5903 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5904 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5905 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5906 * rem-double/2addr 5907 */ 5908 /* binop/2addr vA, vB */ 5909 mov r9, rINST, lsr #8 @ r9<- A+ 5910 mov r1, rINST, lsr #12 @ r1<- B 5911 and r9, r9, #15 5912 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5913 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5914 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5915 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5916 .if 0 5917 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5918 beq common_errDivideByZero 5919 .endif 5920 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5921 5922 adds r0, r0, r2 @ optional op; may set condition codes 5923 adc r1, r1, r3 @ result<- op, r0-r3 changed 5924 GET_INST_OPCODE(ip) @ extract opcode from rINST 5925 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5926 GOTO_OPCODE(ip) @ jump to next instruction 5927 /* 12-15 instructions */ 5928 5929 5930/* ------------------------------ */ 5931 .balign 64 5932.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5933/* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5934/* File: armv5te/binopWide2addr.S */ 5935 /* 5936 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5937 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5938 * This could be an ARM instruction or a function call. (If the result 5939 * comes back in a register other than r0, you can override "result".) 5940 * 5941 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5942 * vCC (r1). Useful for integer division and modulus. 5943 * 5944 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5945 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5946 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5947 * rem-double/2addr 5948 */ 5949 /* binop/2addr vA, vB */ 5950 mov r9, rINST, lsr #8 @ r9<- A+ 5951 mov r1, rINST, lsr #12 @ r1<- B 5952 and r9, r9, #15 5953 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5954 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5955 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5956 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5957 .if 0 5958 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5959 beq common_errDivideByZero 5960 .endif 5961 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5962 5963 subs r0, r0, r2 @ optional op; may set condition codes 5964 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5965 GET_INST_OPCODE(ip) @ extract opcode from rINST 5966 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5967 GOTO_OPCODE(ip) @ jump to next instruction 5968 /* 12-15 instructions */ 5969 5970 5971/* ------------------------------ */ 5972 .balign 64 5973.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5974/* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5975 /* 5976 * Signed 64-bit integer multiply, "/2addr" version. 5977 * 5978 * See OP_MUL_LONG for an explanation. 5979 * 5980 * We get a little tight on registers, so to avoid looking up &fp[A] 5981 * again we stuff it into rINST. 5982 */ 5983 /* mul-long/2addr vA, vB */ 5984 mov r9, rINST, lsr #8 @ r9<- A+ 5985 mov r1, rINST, lsr #12 @ r1<- B 5986 and r9, r9, #15 5987 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5988 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5989 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5990 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5991 mul ip, r2, r1 @ ip<- ZxW 5992 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5993 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5994 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5995 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5996 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5997 GET_INST_OPCODE(ip) @ extract opcode from rINST 5998 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5999 GOTO_OPCODE(ip) @ jump to next instruction 6000 6001/* ------------------------------ */ 6002 .balign 64 6003.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 6004/* File: armv5te/OP_DIV_LONG_2ADDR.S */ 6005/* File: armv5te/binopWide2addr.S */ 6006 /* 6007 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6008 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6009 * This could be an ARM instruction or a function call. (If the result 6010 * comes back in a register other than r0, you can override "result".) 6011 * 6012 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6013 * vCC (r1). Useful for integer division and modulus. 6014 * 6015 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6016 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6017 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6018 * rem-double/2addr 6019 */ 6020 /* binop/2addr vA, vB */ 6021 mov r9, rINST, lsr #8 @ r9<- A+ 6022 mov r1, rINST, lsr #12 @ r1<- B 6023 and r9, r9, #15 6024 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6025 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6026 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6027 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6028 .if 1 6029 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6030 beq common_errDivideByZero 6031 .endif 6032 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6033 6034 @ optional op; may set condition codes 6035 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 6036 GET_INST_OPCODE(ip) @ extract opcode from rINST 6037 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6038 GOTO_OPCODE(ip) @ jump to next instruction 6039 /* 12-15 instructions */ 6040 6041 6042/* ------------------------------ */ 6043 .balign 64 6044.L_OP_REM_LONG_2ADDR: /* 0xbf */ 6045/* File: armv5te/OP_REM_LONG_2ADDR.S */ 6046/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 6047/* File: armv5te/binopWide2addr.S */ 6048 /* 6049 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6050 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6051 * This could be an ARM instruction or a function call. (If the result 6052 * comes back in a register other than r0, you can override "result".) 6053 * 6054 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6055 * vCC (r1). Useful for integer division and modulus. 6056 * 6057 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6058 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6059 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6060 * rem-double/2addr 6061 */ 6062 /* binop/2addr vA, vB */ 6063 mov r9, rINST, lsr #8 @ r9<- A+ 6064 mov r1, rINST, lsr #12 @ r1<- B 6065 and r9, r9, #15 6066 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6067 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6068 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6069 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6070 .if 1 6071 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6072 beq common_errDivideByZero 6073 .endif 6074 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6075 6076 @ optional op; may set condition codes 6077 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 6078 GET_INST_OPCODE(ip) @ extract opcode from rINST 6079 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 6080 GOTO_OPCODE(ip) @ jump to next instruction 6081 /* 12-15 instructions */ 6082 6083 6084/* ------------------------------ */ 6085 .balign 64 6086.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 6087/* File: armv5te/OP_AND_LONG_2ADDR.S */ 6088/* File: armv5te/binopWide2addr.S */ 6089 /* 6090 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6091 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6092 * This could be an ARM instruction or a function call. (If the result 6093 * comes back in a register other than r0, you can override "result".) 6094 * 6095 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6096 * vCC (r1). Useful for integer division and modulus. 6097 * 6098 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6099 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6100 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6101 * rem-double/2addr 6102 */ 6103 /* binop/2addr vA, vB */ 6104 mov r9, rINST, lsr #8 @ r9<- A+ 6105 mov r1, rINST, lsr #12 @ r1<- B 6106 and r9, r9, #15 6107 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6108 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6109 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6110 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6111 .if 0 6112 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6113 beq common_errDivideByZero 6114 .endif 6115 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6116 6117 and r0, r0, r2 @ optional op; may set condition codes 6118 and r1, r1, r3 @ result<- op, r0-r3 changed 6119 GET_INST_OPCODE(ip) @ extract opcode from rINST 6120 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6121 GOTO_OPCODE(ip) @ jump to next instruction 6122 /* 12-15 instructions */ 6123 6124 6125/* ------------------------------ */ 6126 .balign 64 6127.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 6128/* File: armv5te/OP_OR_LONG_2ADDR.S */ 6129/* File: armv5te/binopWide2addr.S */ 6130 /* 6131 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6132 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6133 * This could be an ARM instruction or a function call. (If the result 6134 * comes back in a register other than r0, you can override "result".) 6135 * 6136 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6137 * vCC (r1). Useful for integer division and modulus. 6138 * 6139 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6140 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6141 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6142 * rem-double/2addr 6143 */ 6144 /* binop/2addr vA, vB */ 6145 mov r9, rINST, lsr #8 @ r9<- A+ 6146 mov r1, rINST, lsr #12 @ r1<- B 6147 and r9, r9, #15 6148 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6149 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6150 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6151 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6152 .if 0 6153 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6154 beq common_errDivideByZero 6155 .endif 6156 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6157 6158 orr r0, r0, r2 @ optional op; may set condition codes 6159 orr r1, r1, r3 @ result<- op, r0-r3 changed 6160 GET_INST_OPCODE(ip) @ extract opcode from rINST 6161 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6162 GOTO_OPCODE(ip) @ jump to next instruction 6163 /* 12-15 instructions */ 6164 6165 6166/* ------------------------------ */ 6167 .balign 64 6168.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 6169/* File: armv5te/OP_XOR_LONG_2ADDR.S */ 6170/* File: armv5te/binopWide2addr.S */ 6171 /* 6172 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6173 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6174 * This could be an ARM instruction or a function call. (If the result 6175 * comes back in a register other than r0, you can override "result".) 6176 * 6177 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6178 * vCC (r1). Useful for integer division and modulus. 6179 * 6180 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6181 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6182 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6183 * rem-double/2addr 6184 */ 6185 /* binop/2addr vA, vB */ 6186 mov r9, rINST, lsr #8 @ r9<- A+ 6187 mov r1, rINST, lsr #12 @ r1<- B 6188 and r9, r9, #15 6189 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6190 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6191 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6192 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6193 .if 0 6194 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6195 beq common_errDivideByZero 6196 .endif 6197 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6198 6199 eor r0, r0, r2 @ optional op; may set condition codes 6200 eor r1, r1, r3 @ result<- op, r0-r3 changed 6201 GET_INST_OPCODE(ip) @ extract opcode from rINST 6202 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6203 GOTO_OPCODE(ip) @ jump to next instruction 6204 /* 12-15 instructions */ 6205 6206 6207/* ------------------------------ */ 6208 .balign 64 6209.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6210/* File: armv5te/OP_SHL_LONG_2ADDR.S */ 6211 /* 6212 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6213 * 32-bit shift distance. 6214 */ 6215 /* shl-long/2addr vA, vB */ 6216 mov r9, rINST, lsr #8 @ r9<- A+ 6217 mov r3, rINST, lsr #12 @ r3<- B 6218 and r9, r9, #15 6219 GET_VREG(r2, r3) @ r2<- vB 6220 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6221 and r2, r2, #63 @ r2<- r2 & 0x3f 6222 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6223 6224 mov r1, r1, asl r2 @ r1<- r1 << r2 6225 rsb r3, r2, #32 @ r3<- 32 - r2 6226 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6227 subs ip, r2, #32 @ ip<- r2 - 32 6228 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6229 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6230 mov r0, r0, asl r2 @ r0<- r0 << r2 6231 b .LOP_SHL_LONG_2ADDR_finish 6232 6233/* ------------------------------ */ 6234 .balign 64 6235.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6236/* File: armv5te/OP_SHR_LONG_2ADDR.S */ 6237 /* 6238 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6239 * 32-bit shift distance. 6240 */ 6241 /* shr-long/2addr vA, vB */ 6242 mov r9, rINST, lsr #8 @ r9<- A+ 6243 mov r3, rINST, lsr #12 @ r3<- B 6244 and r9, r9, #15 6245 GET_VREG(r2, r3) @ r2<- vB 6246 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6247 and r2, r2, #63 @ r2<- r2 & 0x3f 6248 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6249 6250 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6251 rsb r3, r2, #32 @ r3<- 32 - r2 6252 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6253 subs ip, r2, #32 @ ip<- r2 - 32 6254 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6255 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6256 mov r1, r1, asr r2 @ r1<- r1 >> r2 6257 b .LOP_SHR_LONG_2ADDR_finish 6258 6259/* ------------------------------ */ 6260 .balign 64 6261.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6262/* File: armv5te/OP_USHR_LONG_2ADDR.S */ 6263 /* 6264 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6265 * 32-bit shift distance. 6266 */ 6267 /* ushr-long/2addr vA, vB */ 6268 mov r9, rINST, lsr #8 @ r9<- A+ 6269 mov r3, rINST, lsr #12 @ r3<- B 6270 and r9, r9, #15 6271 GET_VREG(r2, r3) @ r2<- vB 6272 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6273 and r2, r2, #63 @ r2<- r2 & 0x3f 6274 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6275 6276 mov r0, r0, lsr r2 @ r0<- r2 >> r2 6277 rsb r3, r2, #32 @ r3<- 32 - r2 6278 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6279 subs ip, r2, #32 @ ip<- r2 - 32 6280 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6281 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6282 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6283 b .LOP_USHR_LONG_2ADDR_finish 6284 6285/* ------------------------------ */ 6286 .balign 64 6287.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6288/* File: armv5te/OP_ADD_FLOAT_2ADDR.S */ 6289/* File: armv5te/binop2addr.S */ 6290 /* 6291 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6292 * that specifies an instruction that performs "result = r0 op r1". 6293 * This could be an ARM instruction or a function call. (If the result 6294 * comes back in a register other than r0, you can override "result".) 6295 * 6296 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6297 * vCC (r1). Useful for integer division and modulus. 6298 * 6299 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6300 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6301 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6302 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6303 */ 6304 /* binop/2addr vA, vB */ 6305 mov r9, rINST, lsr #8 @ r9<- A+ 6306 mov r3, rINST, lsr #12 @ r3<- B 6307 and r9, r9, #15 6308 GET_VREG(r1, r3) @ r1<- vB 6309 GET_VREG(r0, r9) @ r0<- vA 6310 .if 0 6311 cmp r1, #0 @ is second operand zero? 6312 beq common_errDivideByZero 6313 .endif 6314 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6315 6316 @ optional op; may set condition codes 6317 bl __aeabi_fadd @ r0<- op, r0-r3 changed 6318 GET_INST_OPCODE(ip) @ extract opcode from rINST 6319 SET_VREG(r0, r9) @ vAA<- r0 6320 GOTO_OPCODE(ip) @ jump to next instruction 6321 /* 10-13 instructions */ 6322 6323 6324/* ------------------------------ */ 6325 .balign 64 6326.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6327/* File: armv5te/OP_SUB_FLOAT_2ADDR.S */ 6328/* File: armv5te/binop2addr.S */ 6329 /* 6330 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6331 * that specifies an instruction that performs "result = r0 op r1". 6332 * This could be an ARM instruction or a function call. (If the result 6333 * comes back in a register other than r0, you can override "result".) 6334 * 6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6336 * vCC (r1). Useful for integer division and modulus. 6337 * 6338 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6339 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6340 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6341 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6342 */ 6343 /* binop/2addr vA, vB */ 6344 mov r9, rINST, lsr #8 @ r9<- A+ 6345 mov r3, rINST, lsr #12 @ r3<- B 6346 and r9, r9, #15 6347 GET_VREG(r1, r3) @ r1<- vB 6348 GET_VREG(r0, r9) @ r0<- vA 6349 .if 0 6350 cmp r1, #0 @ is second operand zero? 6351 beq common_errDivideByZero 6352 .endif 6353 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6354 6355 @ optional op; may set condition codes 6356 bl __aeabi_fsub @ r0<- op, r0-r3 changed 6357 GET_INST_OPCODE(ip) @ extract opcode from rINST 6358 SET_VREG(r0, r9) @ vAA<- r0 6359 GOTO_OPCODE(ip) @ jump to next instruction 6360 /* 10-13 instructions */ 6361 6362 6363/* ------------------------------ */ 6364 .balign 64 6365.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6366/* File: armv5te/OP_MUL_FLOAT_2ADDR.S */ 6367/* File: armv5te/binop2addr.S */ 6368 /* 6369 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6370 * that specifies an instruction that performs "result = r0 op r1". 6371 * This could be an ARM instruction or a function call. (If the result 6372 * comes back in a register other than r0, you can override "result".) 6373 * 6374 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6375 * vCC (r1). Useful for integer division and modulus. 6376 * 6377 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6378 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6379 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6380 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6381 */ 6382 /* binop/2addr vA, vB */ 6383 mov r9, rINST, lsr #8 @ r9<- A+ 6384 mov r3, rINST, lsr #12 @ r3<- B 6385 and r9, r9, #15 6386 GET_VREG(r1, r3) @ r1<- vB 6387 GET_VREG(r0, r9) @ r0<- vA 6388 .if 0 6389 cmp r1, #0 @ is second operand zero? 6390 beq common_errDivideByZero 6391 .endif 6392 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6393 6394 @ optional op; may set condition codes 6395 bl __aeabi_fmul @ r0<- op, r0-r3 changed 6396 GET_INST_OPCODE(ip) @ extract opcode from rINST 6397 SET_VREG(r0, r9) @ vAA<- r0 6398 GOTO_OPCODE(ip) @ jump to next instruction 6399 /* 10-13 instructions */ 6400 6401 6402/* ------------------------------ */ 6403 .balign 64 6404.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6405/* File: armv5te/OP_DIV_FLOAT_2ADDR.S */ 6406/* File: armv5te/binop2addr.S */ 6407 /* 6408 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6409 * that specifies an instruction that performs "result = r0 op r1". 6410 * This could be an ARM instruction or a function call. (If the result 6411 * comes back in a register other than r0, you can override "result".) 6412 * 6413 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6414 * vCC (r1). Useful for integer division and modulus. 6415 * 6416 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6417 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6418 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6419 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6420 */ 6421 /* binop/2addr vA, vB */ 6422 mov r9, rINST, lsr #8 @ r9<- A+ 6423 mov r3, rINST, lsr #12 @ r3<- B 6424 and r9, r9, #15 6425 GET_VREG(r1, r3) @ r1<- vB 6426 GET_VREG(r0, r9) @ r0<- vA 6427 .if 0 6428 cmp r1, #0 @ is second operand zero? 6429 beq common_errDivideByZero 6430 .endif 6431 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6432 6433 @ optional op; may set condition codes 6434 bl __aeabi_fdiv @ r0<- op, r0-r3 changed 6435 GET_INST_OPCODE(ip) @ extract opcode from rINST 6436 SET_VREG(r0, r9) @ vAA<- r0 6437 GOTO_OPCODE(ip) @ jump to next instruction 6438 /* 10-13 instructions */ 6439 6440 6441/* ------------------------------ */ 6442 .balign 64 6443.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6444/* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6445/* EABI doesn't define a float remainder function, but libm does */ 6446/* File: armv5te/binop2addr.S */ 6447 /* 6448 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6449 * that specifies an instruction that performs "result = r0 op r1". 6450 * This could be an ARM instruction or a function call. (If the result 6451 * comes back in a register other than r0, you can override "result".) 6452 * 6453 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6454 * vCC (r1). Useful for integer division and modulus. 6455 * 6456 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6457 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6458 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6459 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6460 */ 6461 /* binop/2addr vA, vB */ 6462 mov r9, rINST, lsr #8 @ r9<- A+ 6463 mov r3, rINST, lsr #12 @ r3<- B 6464 and r9, r9, #15 6465 GET_VREG(r1, r3) @ r1<- vB 6466 GET_VREG(r0, r9) @ r0<- vA 6467 .if 0 6468 cmp r1, #0 @ is second operand zero? 6469 beq common_errDivideByZero 6470 .endif 6471 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6472 6473 @ optional op; may set condition codes 6474 bl fmodf @ r0<- op, r0-r3 changed 6475 GET_INST_OPCODE(ip) @ extract opcode from rINST 6476 SET_VREG(r0, r9) @ vAA<- r0 6477 GOTO_OPCODE(ip) @ jump to next instruction 6478 /* 10-13 instructions */ 6479 6480 6481/* ------------------------------ */ 6482 .balign 64 6483.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6484/* File: armv5te/OP_ADD_DOUBLE_2ADDR.S */ 6485/* File: armv5te/binopWide2addr.S */ 6486 /* 6487 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6488 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6489 * This could be an ARM instruction or a function call. (If the result 6490 * comes back in a register other than r0, you can override "result".) 6491 * 6492 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6493 * vCC (r1). Useful for integer division and modulus. 6494 * 6495 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6496 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6497 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6498 * rem-double/2addr 6499 */ 6500 /* binop/2addr vA, vB */ 6501 mov r9, rINST, lsr #8 @ r9<- A+ 6502 mov r1, rINST, lsr #12 @ r1<- B 6503 and r9, r9, #15 6504 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6505 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6506 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6507 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6508 .if 0 6509 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6510 beq common_errDivideByZero 6511 .endif 6512 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6513 6514 @ optional op; may set condition codes 6515 bl __aeabi_dadd @ result<- op, r0-r3 changed 6516 GET_INST_OPCODE(ip) @ extract opcode from rINST 6517 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6518 GOTO_OPCODE(ip) @ jump to next instruction 6519 /* 12-15 instructions */ 6520 6521 6522/* ------------------------------ */ 6523 .balign 64 6524.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6525/* File: armv5te/OP_SUB_DOUBLE_2ADDR.S */ 6526/* File: armv5te/binopWide2addr.S */ 6527 /* 6528 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6529 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6530 * This could be an ARM instruction or a function call. (If the result 6531 * comes back in a register other than r0, you can override "result".) 6532 * 6533 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6534 * vCC (r1). Useful for integer division and modulus. 6535 * 6536 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6537 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6538 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6539 * rem-double/2addr 6540 */ 6541 /* binop/2addr vA, vB */ 6542 mov r9, rINST, lsr #8 @ r9<- A+ 6543 mov r1, rINST, lsr #12 @ r1<- B 6544 and r9, r9, #15 6545 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6546 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6547 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6548 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6549 .if 0 6550 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6551 beq common_errDivideByZero 6552 .endif 6553 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6554 6555 @ optional op; may set condition codes 6556 bl __aeabi_dsub @ result<- op, r0-r3 changed 6557 GET_INST_OPCODE(ip) @ extract opcode from rINST 6558 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6559 GOTO_OPCODE(ip) @ jump to next instruction 6560 /* 12-15 instructions */ 6561 6562 6563/* ------------------------------ */ 6564 .balign 64 6565.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6566/* File: armv5te/OP_MUL_DOUBLE_2ADDR.S */ 6567/* File: armv5te/binopWide2addr.S */ 6568 /* 6569 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6570 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6571 * This could be an ARM instruction or a function call. (If the result 6572 * comes back in a register other than r0, you can override "result".) 6573 * 6574 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6575 * vCC (r1). Useful for integer division and modulus. 6576 * 6577 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6578 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6579 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6580 * rem-double/2addr 6581 */ 6582 /* binop/2addr vA, vB */ 6583 mov r9, rINST, lsr #8 @ r9<- A+ 6584 mov r1, rINST, lsr #12 @ r1<- B 6585 and r9, r9, #15 6586 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6587 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6588 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6589 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6590 .if 0 6591 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6592 beq common_errDivideByZero 6593 .endif 6594 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6595 6596 @ optional op; may set condition codes 6597 bl __aeabi_dmul @ result<- op, r0-r3 changed 6598 GET_INST_OPCODE(ip) @ extract opcode from rINST 6599 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6600 GOTO_OPCODE(ip) @ jump to next instruction 6601 /* 12-15 instructions */ 6602 6603 6604/* ------------------------------ */ 6605 .balign 64 6606.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6607/* File: armv5te/OP_DIV_DOUBLE_2ADDR.S */ 6608/* File: armv5te/binopWide2addr.S */ 6609 /* 6610 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6611 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6612 * This could be an ARM instruction or a function call. (If the result 6613 * comes back in a register other than r0, you can override "result".) 6614 * 6615 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6616 * vCC (r1). Useful for integer division and modulus. 6617 * 6618 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6619 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6620 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6621 * rem-double/2addr 6622 */ 6623 /* binop/2addr vA, vB */ 6624 mov r9, rINST, lsr #8 @ r9<- A+ 6625 mov r1, rINST, lsr #12 @ r1<- B 6626 and r9, r9, #15 6627 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6628 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6629 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6630 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6631 .if 0 6632 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6633 beq common_errDivideByZero 6634 .endif 6635 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6636 6637 @ optional op; may set condition codes 6638 bl __aeabi_ddiv @ result<- op, r0-r3 changed 6639 GET_INST_OPCODE(ip) @ extract opcode from rINST 6640 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6641 GOTO_OPCODE(ip) @ jump to next instruction 6642 /* 12-15 instructions */ 6643 6644 6645/* ------------------------------ */ 6646 .balign 64 6647.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6648/* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6649/* EABI doesn't define a double remainder function, but libm does */ 6650/* File: armv5te/binopWide2addr.S */ 6651 /* 6652 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6653 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6654 * This could be an ARM instruction or a function call. (If the result 6655 * comes back in a register other than r0, you can override "result".) 6656 * 6657 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6658 * vCC (r1). Useful for integer division and modulus. 6659 * 6660 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6661 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6662 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6663 * rem-double/2addr 6664 */ 6665 /* binop/2addr vA, vB */ 6666 mov r9, rINST, lsr #8 @ r9<- A+ 6667 mov r1, rINST, lsr #12 @ r1<- B 6668 and r9, r9, #15 6669 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6670 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6671 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6672 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6673 .if 0 6674 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6675 beq common_errDivideByZero 6676 .endif 6677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6678 6679 @ optional op; may set condition codes 6680 bl fmod @ result<- op, r0-r3 changed 6681 GET_INST_OPCODE(ip) @ extract opcode from rINST 6682 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6683 GOTO_OPCODE(ip) @ jump to next instruction 6684 /* 12-15 instructions */ 6685 6686 6687/* ------------------------------ */ 6688 .balign 64 6689.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6690/* File: armv5te/OP_ADD_INT_LIT16.S */ 6691/* File: armv5te/binopLit16.S */ 6692 /* 6693 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6694 * that specifies an instruction that performs "result = r0 op r1". 6695 * This could be an ARM instruction or a function call. (If the result 6696 * comes back in a register other than r0, you can override "result".) 6697 * 6698 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6699 * vCC (r1). Useful for integer division and modulus. 6700 * 6701 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6702 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6703 */ 6704 /* binop/lit16 vA, vB, #+CCCC */ 6705 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6706 mov r2, rINST, lsr #12 @ r2<- B 6707 mov r9, rINST, lsr #8 @ r9<- A+ 6708 GET_VREG(r0, r2) @ r0<- vB 6709 and r9, r9, #15 6710 .if 0 6711 cmp r1, #0 @ is second operand zero? 6712 beq common_errDivideByZero 6713 .endif 6714 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6715 6716 add r0, r0, r1 @ r0<- op, r0-r3 changed 6717 GET_INST_OPCODE(ip) @ extract opcode from rINST 6718 SET_VREG(r0, r9) @ vAA<- r0 6719 GOTO_OPCODE(ip) @ jump to next instruction 6720 /* 10-13 instructions */ 6721 6722 6723/* ------------------------------ */ 6724 .balign 64 6725.L_OP_RSUB_INT: /* 0xd1 */ 6726/* File: armv5te/OP_RSUB_INT.S */ 6727/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6728/* File: armv5te/binopLit16.S */ 6729 /* 6730 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6731 * that specifies an instruction that performs "result = r0 op r1". 6732 * This could be an ARM instruction or a function call. (If the result 6733 * comes back in a register other than r0, you can override "result".) 6734 * 6735 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6736 * vCC (r1). Useful for integer division and modulus. 6737 * 6738 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6739 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6740 */ 6741 /* binop/lit16 vA, vB, #+CCCC */ 6742 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6743 mov r2, rINST, lsr #12 @ r2<- B 6744 mov r9, rINST, lsr #8 @ r9<- A+ 6745 GET_VREG(r0, r2) @ r0<- vB 6746 and r9, r9, #15 6747 .if 0 6748 cmp r1, #0 @ is second operand zero? 6749 beq common_errDivideByZero 6750 .endif 6751 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6752 6753 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6754 GET_INST_OPCODE(ip) @ extract opcode from rINST 6755 SET_VREG(r0, r9) @ vAA<- r0 6756 GOTO_OPCODE(ip) @ jump to next instruction 6757 /* 10-13 instructions */ 6758 6759 6760/* ------------------------------ */ 6761 .balign 64 6762.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6763/* File: armv5te/OP_MUL_INT_LIT16.S */ 6764/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6765/* File: armv5te/binopLit16.S */ 6766 /* 6767 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6768 * that specifies an instruction that performs "result = r0 op r1". 6769 * This could be an ARM instruction or a function call. (If the result 6770 * comes back in a register other than r0, you can override "result".) 6771 * 6772 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6773 * vCC (r1). Useful for integer division and modulus. 6774 * 6775 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6776 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6777 */ 6778 /* binop/lit16 vA, vB, #+CCCC */ 6779 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6780 mov r2, rINST, lsr #12 @ r2<- B 6781 mov r9, rINST, lsr #8 @ r9<- A+ 6782 GET_VREG(r0, r2) @ r0<- vB 6783 and r9, r9, #15 6784 .if 0 6785 cmp r1, #0 @ is second operand zero? 6786 beq common_errDivideByZero 6787 .endif 6788 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6789 6790 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6791 GET_INST_OPCODE(ip) @ extract opcode from rINST 6792 SET_VREG(r0, r9) @ vAA<- r0 6793 GOTO_OPCODE(ip) @ jump to next instruction 6794 /* 10-13 instructions */ 6795 6796 6797/* ------------------------------ */ 6798 .balign 64 6799.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6800/* File: armv5te/OP_DIV_INT_LIT16.S */ 6801/* File: armv5te/binopLit16.S */ 6802 /* 6803 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6804 * that specifies an instruction that performs "result = r0 op r1". 6805 * This could be an ARM instruction or a function call. (If the result 6806 * comes back in a register other than r0, you can override "result".) 6807 * 6808 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6809 * vCC (r1). Useful for integer division and modulus. 6810 * 6811 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6812 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6813 */ 6814 /* binop/lit16 vA, vB, #+CCCC */ 6815 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6816 mov r2, rINST, lsr #12 @ r2<- B 6817 mov r9, rINST, lsr #8 @ r9<- A+ 6818 GET_VREG(r0, r2) @ r0<- vB 6819 and r9, r9, #15 6820 .if 1 6821 cmp r1, #0 @ is second operand zero? 6822 beq common_errDivideByZero 6823 .endif 6824 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6825 6826 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6827 GET_INST_OPCODE(ip) @ extract opcode from rINST 6828 SET_VREG(r0, r9) @ vAA<- r0 6829 GOTO_OPCODE(ip) @ jump to next instruction 6830 /* 10-13 instructions */ 6831 6832 6833/* ------------------------------ */ 6834 .balign 64 6835.L_OP_REM_INT_LIT16: /* 0xd4 */ 6836/* File: armv5te/OP_REM_INT_LIT16.S */ 6837/* idivmod returns quotient in r0 and remainder in r1 */ 6838/* File: armv5te/binopLit16.S */ 6839 /* 6840 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6841 * that specifies an instruction that performs "result = r0 op r1". 6842 * This could be an ARM instruction or a function call. (If the result 6843 * comes back in a register other than r0, you can override "result".) 6844 * 6845 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6846 * vCC (r1). Useful for integer division and modulus. 6847 * 6848 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6849 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6850 */ 6851 /* binop/lit16 vA, vB, #+CCCC */ 6852 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6853 mov r2, rINST, lsr #12 @ r2<- B 6854 mov r9, rINST, lsr #8 @ r9<- A+ 6855 GET_VREG(r0, r2) @ r0<- vB 6856 and r9, r9, #15 6857 .if 1 6858 cmp r1, #0 @ is second operand zero? 6859 beq common_errDivideByZero 6860 .endif 6861 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6862 6863 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6864 GET_INST_OPCODE(ip) @ extract opcode from rINST 6865 SET_VREG(r1, r9) @ vAA<- r1 6866 GOTO_OPCODE(ip) @ jump to next instruction 6867 /* 10-13 instructions */ 6868 6869 6870/* ------------------------------ */ 6871 .balign 64 6872.L_OP_AND_INT_LIT16: /* 0xd5 */ 6873/* File: armv5te/OP_AND_INT_LIT16.S */ 6874/* File: armv5te/binopLit16.S */ 6875 /* 6876 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6877 * that specifies an instruction that performs "result = r0 op r1". 6878 * This could be an ARM instruction or a function call. (If the result 6879 * comes back in a register other than r0, you can override "result".) 6880 * 6881 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6882 * vCC (r1). Useful for integer division and modulus. 6883 * 6884 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6885 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6886 */ 6887 /* binop/lit16 vA, vB, #+CCCC */ 6888 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6889 mov r2, rINST, lsr #12 @ r2<- B 6890 mov r9, rINST, lsr #8 @ r9<- A+ 6891 GET_VREG(r0, r2) @ r0<- vB 6892 and r9, r9, #15 6893 .if 0 6894 cmp r1, #0 @ is second operand zero? 6895 beq common_errDivideByZero 6896 .endif 6897 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6898 6899 and r0, r0, r1 @ r0<- op, r0-r3 changed 6900 GET_INST_OPCODE(ip) @ extract opcode from rINST 6901 SET_VREG(r0, r9) @ vAA<- r0 6902 GOTO_OPCODE(ip) @ jump to next instruction 6903 /* 10-13 instructions */ 6904 6905 6906/* ------------------------------ */ 6907 .balign 64 6908.L_OP_OR_INT_LIT16: /* 0xd6 */ 6909/* File: armv5te/OP_OR_INT_LIT16.S */ 6910/* File: armv5te/binopLit16.S */ 6911 /* 6912 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6913 * that specifies an instruction that performs "result = r0 op r1". 6914 * This could be an ARM instruction or a function call. (If the result 6915 * comes back in a register other than r0, you can override "result".) 6916 * 6917 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6918 * vCC (r1). Useful for integer division and modulus. 6919 * 6920 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6921 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6922 */ 6923 /* binop/lit16 vA, vB, #+CCCC */ 6924 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6925 mov r2, rINST, lsr #12 @ r2<- B 6926 mov r9, rINST, lsr #8 @ r9<- A+ 6927 GET_VREG(r0, r2) @ r0<- vB 6928 and r9, r9, #15 6929 .if 0 6930 cmp r1, #0 @ is second operand zero? 6931 beq common_errDivideByZero 6932 .endif 6933 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6934 6935 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6936 GET_INST_OPCODE(ip) @ extract opcode from rINST 6937 SET_VREG(r0, r9) @ vAA<- r0 6938 GOTO_OPCODE(ip) @ jump to next instruction 6939 /* 10-13 instructions */ 6940 6941 6942/* ------------------------------ */ 6943 .balign 64 6944.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6945/* File: armv5te/OP_XOR_INT_LIT16.S */ 6946/* File: armv5te/binopLit16.S */ 6947 /* 6948 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6949 * that specifies an instruction that performs "result = r0 op r1". 6950 * This could be an ARM instruction or a function call. (If the result 6951 * comes back in a register other than r0, you can override "result".) 6952 * 6953 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6954 * vCC (r1). Useful for integer division and modulus. 6955 * 6956 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6957 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6958 */ 6959 /* binop/lit16 vA, vB, #+CCCC */ 6960 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6961 mov r2, rINST, lsr #12 @ r2<- B 6962 mov r9, rINST, lsr #8 @ r9<- A+ 6963 GET_VREG(r0, r2) @ r0<- vB 6964 and r9, r9, #15 6965 .if 0 6966 cmp r1, #0 @ is second operand zero? 6967 beq common_errDivideByZero 6968 .endif 6969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6970 6971 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6972 GET_INST_OPCODE(ip) @ extract opcode from rINST 6973 SET_VREG(r0, r9) @ vAA<- r0 6974 GOTO_OPCODE(ip) @ jump to next instruction 6975 /* 10-13 instructions */ 6976 6977 6978/* ------------------------------ */ 6979 .balign 64 6980.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6981/* File: armv5te/OP_ADD_INT_LIT8.S */ 6982/* File: armv5te/binopLit8.S */ 6983 /* 6984 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6985 * that specifies an instruction that performs "result = r0 op r1". 6986 * This could be an ARM instruction or a function call. (If the result 6987 * comes back in a register other than r0, you can override "result".) 6988 * 6989 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6990 * vCC (r1). Useful for integer division and modulus. 6991 * 6992 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6993 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6994 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6995 */ 6996 /* binop/lit8 vAA, vBB, #+CC */ 6997 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6998 mov r9, rINST, lsr #8 @ r9<- AA 6999 and r2, r3, #255 @ r2<- BB 7000 GET_VREG(r0, r2) @ r0<- vBB 7001 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7002 .if 0 7003 @cmp r1, #0 @ is second operand zero? 7004 beq common_errDivideByZero 7005 .endif 7006 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7007 7008 @ optional op; may set condition codes 7009 add r0, r0, r1 @ r0<- op, r0-r3 changed 7010 GET_INST_OPCODE(ip) @ extract opcode from rINST 7011 SET_VREG(r0, r9) @ vAA<- r0 7012 GOTO_OPCODE(ip) @ jump to next instruction 7013 /* 10-12 instructions */ 7014 7015 7016/* ------------------------------ */ 7017 .balign 64 7018.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 7019/* File: armv5te/OP_RSUB_INT_LIT8.S */ 7020/* File: armv5te/binopLit8.S */ 7021 /* 7022 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7023 * that specifies an instruction that performs "result = r0 op r1". 7024 * This could be an ARM instruction or a function call. (If the result 7025 * comes back in a register other than r0, you can override "result".) 7026 * 7027 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7028 * vCC (r1). Useful for integer division and modulus. 7029 * 7030 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7031 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7032 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7033 */ 7034 /* binop/lit8 vAA, vBB, #+CC */ 7035 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7036 mov r9, rINST, lsr #8 @ r9<- AA 7037 and r2, r3, #255 @ r2<- BB 7038 GET_VREG(r0, r2) @ r0<- vBB 7039 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7040 .if 0 7041 @cmp r1, #0 @ is second operand zero? 7042 beq common_errDivideByZero 7043 .endif 7044 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7045 7046 @ optional op; may set condition codes 7047 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 7048 GET_INST_OPCODE(ip) @ extract opcode from rINST 7049 SET_VREG(r0, r9) @ vAA<- r0 7050 GOTO_OPCODE(ip) @ jump to next instruction 7051 /* 10-12 instructions */ 7052 7053 7054/* ------------------------------ */ 7055 .balign 64 7056.L_OP_MUL_INT_LIT8: /* 0xda */ 7057/* File: armv5te/OP_MUL_INT_LIT8.S */ 7058/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 7059/* File: armv5te/binopLit8.S */ 7060 /* 7061 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7062 * that specifies an instruction that performs "result = r0 op r1". 7063 * This could be an ARM instruction or a function call. (If the result 7064 * comes back in a register other than r0, you can override "result".) 7065 * 7066 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7067 * vCC (r1). Useful for integer division and modulus. 7068 * 7069 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7070 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7071 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7072 */ 7073 /* binop/lit8 vAA, vBB, #+CC */ 7074 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7075 mov r9, rINST, lsr #8 @ r9<- AA 7076 and r2, r3, #255 @ r2<- BB 7077 GET_VREG(r0, r2) @ r0<- vBB 7078 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7079 .if 0 7080 @cmp r1, #0 @ is second operand zero? 7081 beq common_errDivideByZero 7082 .endif 7083 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7084 7085 @ optional op; may set condition codes 7086 mul r0, r1, r0 @ r0<- op, r0-r3 changed 7087 GET_INST_OPCODE(ip) @ extract opcode from rINST 7088 SET_VREG(r0, r9) @ vAA<- r0 7089 GOTO_OPCODE(ip) @ jump to next instruction 7090 /* 10-12 instructions */ 7091 7092 7093/* ------------------------------ */ 7094 .balign 64 7095.L_OP_DIV_INT_LIT8: /* 0xdb */ 7096/* File: armv5te/OP_DIV_INT_LIT8.S */ 7097/* File: armv5te/binopLit8.S */ 7098 /* 7099 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7100 * that specifies an instruction that performs "result = r0 op r1". 7101 * This could be an ARM instruction or a function call. (If the result 7102 * comes back in a register other than r0, you can override "result".) 7103 * 7104 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7105 * vCC (r1). Useful for integer division and modulus. 7106 * 7107 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7108 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7109 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7110 */ 7111 /* binop/lit8 vAA, vBB, #+CC */ 7112 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7113 mov r9, rINST, lsr #8 @ r9<- AA 7114 and r2, r3, #255 @ r2<- BB 7115 GET_VREG(r0, r2) @ r0<- vBB 7116 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7117 .if 1 7118 @cmp r1, #0 @ is second operand zero? 7119 beq common_errDivideByZero 7120 .endif 7121 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7122 7123 @ optional op; may set condition codes 7124 bl __aeabi_idiv @ r0<- op, r0-r3 changed 7125 GET_INST_OPCODE(ip) @ extract opcode from rINST 7126 SET_VREG(r0, r9) @ vAA<- r0 7127 GOTO_OPCODE(ip) @ jump to next instruction 7128 /* 10-12 instructions */ 7129 7130 7131/* ------------------------------ */ 7132 .balign 64 7133.L_OP_REM_INT_LIT8: /* 0xdc */ 7134/* File: armv5te/OP_REM_INT_LIT8.S */ 7135/* idivmod returns quotient in r0 and remainder in r1 */ 7136/* File: armv5te/binopLit8.S */ 7137 /* 7138 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7139 * that specifies an instruction that performs "result = r0 op r1". 7140 * This could be an ARM instruction or a function call. (If the result 7141 * comes back in a register other than r0, you can override "result".) 7142 * 7143 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7144 * vCC (r1). Useful for integer division and modulus. 7145 * 7146 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7147 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7148 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7149 */ 7150 /* binop/lit8 vAA, vBB, #+CC */ 7151 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7152 mov r9, rINST, lsr #8 @ r9<- AA 7153 and r2, r3, #255 @ r2<- BB 7154 GET_VREG(r0, r2) @ r0<- vBB 7155 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7156 .if 1 7157 @cmp r1, #0 @ is second operand zero? 7158 beq common_errDivideByZero 7159 .endif 7160 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7161 7162 @ optional op; may set condition codes 7163 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 7164 GET_INST_OPCODE(ip) @ extract opcode from rINST 7165 SET_VREG(r1, r9) @ vAA<- r1 7166 GOTO_OPCODE(ip) @ jump to next instruction 7167 /* 10-12 instructions */ 7168 7169 7170/* ------------------------------ */ 7171 .balign 64 7172.L_OP_AND_INT_LIT8: /* 0xdd */ 7173/* File: armv5te/OP_AND_INT_LIT8.S */ 7174/* File: armv5te/binopLit8.S */ 7175 /* 7176 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7177 * that specifies an instruction that performs "result = r0 op r1". 7178 * This could be an ARM instruction or a function call. (If the result 7179 * comes back in a register other than r0, you can override "result".) 7180 * 7181 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7182 * vCC (r1). Useful for integer division and modulus. 7183 * 7184 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7185 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7186 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7187 */ 7188 /* binop/lit8 vAA, vBB, #+CC */ 7189 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7190 mov r9, rINST, lsr #8 @ r9<- AA 7191 and r2, r3, #255 @ r2<- BB 7192 GET_VREG(r0, r2) @ r0<- vBB 7193 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7194 .if 0 7195 @cmp r1, #0 @ is second operand zero? 7196 beq common_errDivideByZero 7197 .endif 7198 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7199 7200 @ optional op; may set condition codes 7201 and r0, r0, r1 @ r0<- op, r0-r3 changed 7202 GET_INST_OPCODE(ip) @ extract opcode from rINST 7203 SET_VREG(r0, r9) @ vAA<- r0 7204 GOTO_OPCODE(ip) @ jump to next instruction 7205 /* 10-12 instructions */ 7206 7207 7208/* ------------------------------ */ 7209 .balign 64 7210.L_OP_OR_INT_LIT8: /* 0xde */ 7211/* File: armv5te/OP_OR_INT_LIT8.S */ 7212/* File: armv5te/binopLit8.S */ 7213 /* 7214 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7215 * that specifies an instruction that performs "result = r0 op r1". 7216 * This could be an ARM instruction or a function call. (If the result 7217 * comes back in a register other than r0, you can override "result".) 7218 * 7219 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7220 * vCC (r1). Useful for integer division and modulus. 7221 * 7222 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7223 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7224 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7225 */ 7226 /* binop/lit8 vAA, vBB, #+CC */ 7227 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7228 mov r9, rINST, lsr #8 @ r9<- AA 7229 and r2, r3, #255 @ r2<- BB 7230 GET_VREG(r0, r2) @ r0<- vBB 7231 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7232 .if 0 7233 @cmp r1, #0 @ is second operand zero? 7234 beq common_errDivideByZero 7235 .endif 7236 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7237 7238 @ optional op; may set condition codes 7239 orr r0, r0, r1 @ r0<- op, r0-r3 changed 7240 GET_INST_OPCODE(ip) @ extract opcode from rINST 7241 SET_VREG(r0, r9) @ vAA<- r0 7242 GOTO_OPCODE(ip) @ jump to next instruction 7243 /* 10-12 instructions */ 7244 7245 7246/* ------------------------------ */ 7247 .balign 64 7248.L_OP_XOR_INT_LIT8: /* 0xdf */ 7249/* File: armv5te/OP_XOR_INT_LIT8.S */ 7250/* File: armv5te/binopLit8.S */ 7251 /* 7252 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7253 * that specifies an instruction that performs "result = r0 op r1". 7254 * This could be an ARM instruction or a function call. (If the result 7255 * comes back in a register other than r0, you can override "result".) 7256 * 7257 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7258 * vCC (r1). Useful for integer division and modulus. 7259 * 7260 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7261 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7262 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7263 */ 7264 /* binop/lit8 vAA, vBB, #+CC */ 7265 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7266 mov r9, rINST, lsr #8 @ r9<- AA 7267 and r2, r3, #255 @ r2<- BB 7268 GET_VREG(r0, r2) @ r0<- vBB 7269 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7270 .if 0 7271 @cmp r1, #0 @ is second operand zero? 7272 beq common_errDivideByZero 7273 .endif 7274 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7275 7276 @ optional op; may set condition codes 7277 eor r0, r0, r1 @ r0<- op, r0-r3 changed 7278 GET_INST_OPCODE(ip) @ extract opcode from rINST 7279 SET_VREG(r0, r9) @ vAA<- r0 7280 GOTO_OPCODE(ip) @ jump to next instruction 7281 /* 10-12 instructions */ 7282 7283 7284/* ------------------------------ */ 7285 .balign 64 7286.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7287/* File: armv5te/OP_SHL_INT_LIT8.S */ 7288/* File: armv5te/binopLit8.S */ 7289 /* 7290 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7291 * that specifies an instruction that performs "result = r0 op r1". 7292 * This could be an ARM instruction or a function call. (If the result 7293 * comes back in a register other than r0, you can override "result".) 7294 * 7295 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7296 * vCC (r1). Useful for integer division and modulus. 7297 * 7298 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7299 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7300 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7301 */ 7302 /* binop/lit8 vAA, vBB, #+CC */ 7303 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7304 mov r9, rINST, lsr #8 @ r9<- AA 7305 and r2, r3, #255 @ r2<- BB 7306 GET_VREG(r0, r2) @ r0<- vBB 7307 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7308 .if 0 7309 @cmp r1, #0 @ is second operand zero? 7310 beq common_errDivideByZero 7311 .endif 7312 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7313 7314 and r1, r1, #31 @ optional op; may set condition codes 7315 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7316 GET_INST_OPCODE(ip) @ extract opcode from rINST 7317 SET_VREG(r0, r9) @ vAA<- r0 7318 GOTO_OPCODE(ip) @ jump to next instruction 7319 /* 10-12 instructions */ 7320 7321 7322/* ------------------------------ */ 7323 .balign 64 7324.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7325/* File: armv5te/OP_SHR_INT_LIT8.S */ 7326/* File: armv5te/binopLit8.S */ 7327 /* 7328 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7329 * that specifies an instruction that performs "result = r0 op r1". 7330 * This could be an ARM instruction or a function call. (If the result 7331 * comes back in a register other than r0, you can override "result".) 7332 * 7333 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7334 * vCC (r1). Useful for integer division and modulus. 7335 * 7336 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7337 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7338 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7339 */ 7340 /* binop/lit8 vAA, vBB, #+CC */ 7341 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7342 mov r9, rINST, lsr #8 @ r9<- AA 7343 and r2, r3, #255 @ r2<- BB 7344 GET_VREG(r0, r2) @ r0<- vBB 7345 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7346 .if 0 7347 @cmp r1, #0 @ is second operand zero? 7348 beq common_errDivideByZero 7349 .endif 7350 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7351 7352 and r1, r1, #31 @ optional op; may set condition codes 7353 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7354 GET_INST_OPCODE(ip) @ extract opcode from rINST 7355 SET_VREG(r0, r9) @ vAA<- r0 7356 GOTO_OPCODE(ip) @ jump to next instruction 7357 /* 10-12 instructions */ 7358 7359 7360/* ------------------------------ */ 7361 .balign 64 7362.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7363/* File: armv5te/OP_USHR_INT_LIT8.S */ 7364/* File: armv5te/binopLit8.S */ 7365 /* 7366 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7367 * that specifies an instruction that performs "result = r0 op r1". 7368 * This could be an ARM instruction or a function call. (If the result 7369 * comes back in a register other than r0, you can override "result".) 7370 * 7371 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7372 * vCC (r1). Useful for integer division and modulus. 7373 * 7374 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7375 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7376 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7377 */ 7378 /* binop/lit8 vAA, vBB, #+CC */ 7379 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7380 mov r9, rINST, lsr #8 @ r9<- AA 7381 and r2, r3, #255 @ r2<- BB 7382 GET_VREG(r0, r2) @ r0<- vBB 7383 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7384 .if 0 7385 @cmp r1, #0 @ is second operand zero? 7386 beq common_errDivideByZero 7387 .endif 7388 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7389 7390 and r1, r1, #31 @ optional op; may set condition codes 7391 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7392 GET_INST_OPCODE(ip) @ extract opcode from rINST 7393 SET_VREG(r0, r9) @ vAA<- r0 7394 GOTO_OPCODE(ip) @ jump to next instruction 7395 /* 10-12 instructions */ 7396 7397 7398/* ------------------------------ */ 7399 .balign 64 7400.L_OP_IGET_VOLATILE: /* 0xe3 */ 7401/* File: armv5te/OP_IGET_VOLATILE.S */ 7402/* File: armv5te/OP_IGET.S */ 7403 /* 7404 * General 32-bit instance field get. 7405 * 7406 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7407 */ 7408 /* op vA, vB, field@CCCC */ 7409 mov r0, rINST, lsr #12 @ r0<- B 7410 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7411 FETCH(r1, 1) @ r1<- field ref CCCC 7412 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7413 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7414 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7415 cmp r0, #0 @ is resolved entry null? 7416 bne .LOP_IGET_VOLATILE_finish @ no, already resolved 74178: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7418 EXPORT_PC() @ resolve() could throw 7419 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7420 bl dvmResolveInstField @ r0<- resolved InstField ptr 7421 cmp r0, #0 7422 bne .LOP_IGET_VOLATILE_finish 7423 b common_exceptionThrown 7424 7425 7426/* ------------------------------ */ 7427 .balign 64 7428.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7429/* File: armv5te/OP_IPUT_VOLATILE.S */ 7430/* File: armv5te/OP_IPUT.S */ 7431 /* 7432 * General 32-bit instance field put. 7433 * 7434 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7435 */ 7436 /* op vA, vB, field@CCCC */ 7437 mov r0, rINST, lsr #12 @ r0<- B 7438 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7439 FETCH(r1, 1) @ r1<- field ref CCCC 7440 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7441 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7442 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7443 cmp r0, #0 @ is resolved entry null? 7444 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 74458: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7446 EXPORT_PC() @ resolve() could throw 7447 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7448 bl dvmResolveInstField @ r0<- resolved InstField ptr 7449 cmp r0, #0 @ success? 7450 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7451 b common_exceptionThrown 7452 7453 7454/* ------------------------------ */ 7455 .balign 64 7456.L_OP_SGET_VOLATILE: /* 0xe5 */ 7457/* File: armv5te/OP_SGET_VOLATILE.S */ 7458/* File: armv5te/OP_SGET.S */ 7459 /* 7460 * General 32-bit SGET handler. 7461 * 7462 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7463 */ 7464 /* op vAA, field@BBBB */ 7465 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7466 FETCH(r1, 1) @ r1<- field ref BBBB 7467 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7468 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7469 cmp r0, #0 @ is resolved entry null? 7470 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7471.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7472 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7473 SMP_DMB @ acquiring load 7474 mov r2, rINST, lsr #8 @ r2<- AA 7475 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7476 SET_VREG(r1, r2) @ fp[AA]<- r1 7477 GET_INST_OPCODE(ip) @ extract opcode from rINST 7478 GOTO_OPCODE(ip) @ jump to next instruction 7479 7480 7481/* ------------------------------ */ 7482 .balign 64 7483.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7484/* File: armv5te/OP_SPUT_VOLATILE.S */ 7485/* File: armv5te/OP_SPUT.S */ 7486 /* 7487 * General 32-bit SPUT handler. 7488 * 7489 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7490 */ 7491 /* op vAA, field@BBBB */ 7492 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7493 FETCH(r1, 1) @ r1<- field ref BBBB 7494 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7495 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7496 cmp r0, #0 @ is resolved entry null? 7497 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7498.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7499 mov r2, rINST, lsr #8 @ r2<- AA 7500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7501 GET_VREG(r1, r2) @ r1<- fp[AA] 7502 GET_INST_OPCODE(ip) @ extract opcode from rINST 7503 SMP_DMB @ releasing store 7504 str r1, [r0, #offStaticField_value] @ field<- vAA 7505 GOTO_OPCODE(ip) @ jump to next instruction 7506 7507 7508/* ------------------------------ */ 7509 .balign 64 7510.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7511/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7512/* File: armv5te/OP_IGET.S */ 7513 /* 7514 * General 32-bit instance field get. 7515 * 7516 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7517 */ 7518 /* op vA, vB, field@CCCC */ 7519 mov r0, rINST, lsr #12 @ r0<- B 7520 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7521 FETCH(r1, 1) @ r1<- field ref CCCC 7522 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7523 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7524 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7525 cmp r0, #0 @ is resolved entry null? 7526 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 75278: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7528 EXPORT_PC() @ resolve() could throw 7529 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7530 bl dvmResolveInstField @ r0<- resolved InstField ptr 7531 cmp r0, #0 7532 bne .LOP_IGET_OBJECT_VOLATILE_finish 7533 b common_exceptionThrown 7534 7535 7536/* ------------------------------ */ 7537 .balign 64 7538.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 7539/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 7540/* File: armv5te/OP_IGET_WIDE.S */ 7541 /* 7542 * Wide 32-bit instance field get. 7543 */ 7544 /* iget-wide vA, vB, field@CCCC */ 7545 mov r0, rINST, lsr #12 @ r0<- B 7546 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7547 FETCH(r1, 1) @ r1<- field ref CCCC 7548 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7549 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7550 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7551 cmp r0, #0 @ is resolved entry null? 7552 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 75538: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7554 EXPORT_PC() @ resolve() could throw 7555 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7556 bl dvmResolveInstField @ r0<- resolved InstField ptr 7557 cmp r0, #0 7558 bne .LOP_IGET_WIDE_VOLATILE_finish 7559 b common_exceptionThrown 7560 7561 7562/* ------------------------------ */ 7563 .balign 64 7564.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 7565/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 7566/* File: armv5te/OP_IPUT_WIDE.S */ 7567 /* iput-wide vA, vB, field@CCCC */ 7568 mov r0, rINST, lsr #12 @ r0<- B 7569 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7570 FETCH(r1, 1) @ r1<- field ref CCCC 7571 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7572 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7573 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7574 cmp r0, #0 @ is resolved entry null? 7575 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 75768: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7577 EXPORT_PC() @ resolve() could throw 7578 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7579 bl dvmResolveInstField @ r0<- resolved InstField ptr 7580 cmp r0, #0 @ success? 7581 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 7582 b common_exceptionThrown 7583 7584 7585/* ------------------------------ */ 7586 .balign 64 7587.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 7588/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 7589/* File: armv5te/OP_SGET_WIDE.S */ 7590 /* 7591 * 64-bit SGET handler. 7592 */ 7593 /* sget-wide vAA, field@BBBB */ 7594 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7595 FETCH(r1, 1) @ r1<- field ref BBBB 7596 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7597 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7598 cmp r0, #0 @ is resolved entry null? 7599 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 7600.LOP_SGET_WIDE_VOLATILE_finish: 7601 mov r9, rINST, lsr #8 @ r9<- AA 7602 .if 1 7603 add r0, r0, #offStaticField_value @ r0<- pointer to data 7604 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7605 .else 7606 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7607 .endif 7608 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7609 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7610 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 7611 GET_INST_OPCODE(ip) @ extract opcode from rINST 7612 GOTO_OPCODE(ip) @ jump to next instruction 7613 7614 7615/* ------------------------------ */ 7616 .balign 64 7617.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 7618/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 7619/* File: armv5te/OP_SPUT_WIDE.S */ 7620 /* 7621 * 64-bit SPUT handler. 7622 */ 7623 /* sput-wide vAA, field@BBBB */ 7624 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 7625 FETCH(r1, 1) @ r1<- field ref BBBB 7626 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 7627 mov r9, rINST, lsr #8 @ r9<- AA 7628 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 7629 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7630 cmp r2, #0 @ is resolved entry null? 7631 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7632.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 7633 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7634 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7635 GET_INST_OPCODE(r10) @ extract opcode from rINST 7636 .if 1 7637 add r2, r2, #offStaticField_value @ r2<- pointer to data 7638 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7639 .else 7640 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7641 .endif 7642 GOTO_OPCODE(r10) @ jump to next instruction 7643 7644 7645/* ------------------------------ */ 7646 .balign 64 7647.L_OP_BREAKPOINT: /* 0xec */ 7648/* File: armv5te/OP_BREAKPOINT.S */ 7649/* File: armv5te/unused.S */ 7650 bl common_abort 7651 7652 7653/* ------------------------------ */ 7654 .balign 64 7655.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7656/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7657 /* 7658 * Handle a throw-verification-error instruction. This throws an 7659 * exception for an error discovered during verification. The 7660 * exception is indicated by AA, with some detail provided by BBBB. 7661 */ 7662 /* op AA, ref@BBBB */ 7663 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 7664 FETCH(r2, 1) @ r2<- BBBB 7665 EXPORT_PC() @ export the PC 7666 mov r1, rINST, lsr #8 @ r1<- AA 7667 bl dvmThrowVerificationError @ always throws 7668 b common_exceptionThrown @ handle exception 7669 7670/* ------------------------------ */ 7671 .balign 64 7672.L_OP_EXECUTE_INLINE: /* 0xee */ 7673/* File: armv5te/OP_EXECUTE_INLINE.S */ 7674 /* 7675 * Execute a "native inline" instruction. 7676 * 7677 * We need to call an InlineOp4Func: 7678 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7679 * 7680 * The first four args are in r0-r3, pointer to return value storage 7681 * is on the stack. The function's return value is a flag that tells 7682 * us if an exception was thrown. 7683 */ 7684 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7685 FETCH(r10, 1) @ r10<- BBBB 7686 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7687 EXPORT_PC() @ can throw 7688 sub sp, sp, #8 @ make room for arg, +64 bit align 7689 mov r0, rINST, lsr #12 @ r0<- B 7690 str r1, [sp] @ push &self->retval 7691 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7692 add sp, sp, #8 @ pop stack 7693 cmp r0, #0 @ test boolean result of inline 7694 beq common_exceptionThrown @ returned false, handle exception 7695 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7696 GET_INST_OPCODE(ip) @ extract opcode from rINST 7697 GOTO_OPCODE(ip) @ jump to next instruction 7698 7699/* ------------------------------ */ 7700 .balign 64 7701.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7702/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7703 /* 7704 * Execute a "native inline" instruction, using "/range" semantics. 7705 * Same idea as execute-inline, but we get the args differently. 7706 * 7707 * We need to call an InlineOp4Func: 7708 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7709 * 7710 * The first four args are in r0-r3, pointer to return value storage 7711 * is on the stack. The function's return value is a flag that tells 7712 * us if an exception was thrown. 7713 */ 7714 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7715 FETCH(r10, 1) @ r10<- BBBB 7716 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7717 EXPORT_PC() @ can throw 7718 sub sp, sp, #8 @ make room for arg, +64 bit align 7719 mov r0, rINST, lsr #8 @ r0<- AA 7720 str r1, [sp] @ push &self->retval 7721 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7722 add sp, sp, #8 @ pop stack 7723 cmp r0, #0 @ test boolean result of inline 7724 beq common_exceptionThrown @ returned false, handle exception 7725 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7726 GET_INST_OPCODE(ip) @ extract opcode from rINST 7727 GOTO_OPCODE(ip) @ jump to next instruction 7728 7729/* ------------------------------ */ 7730 .balign 64 7731.L_OP_INVOKE_OBJECT_INIT: /* 0xf0 */ 7732/* File: armv5te/OP_INVOKE_OBJECT_INIT.S */ 7733 /* 7734 * Invoke Object.<init> on an object. In practice we know that 7735 * Object's nullary constructor doesn't do anything, so we just 7736 * skip it (we know a debugger isn't active). 7737 */ 7738 FETCH(r0, 2) @ r0<- GFED 7739 and r1, r0, #15 @ r1<- D 7740 GET_VREG(r0, r1) @ r0<- "this" ptr 7741 cmp r0, #0 @ check for NULL 7742 beq common_errNullObject @ export PC and throw NPE 7743 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 7744 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 7745 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 7746 beq 1f @ nope, done 7747 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 77481: FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7749 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7750 GOTO_OPCODE(ip) @ execute it 7751 7752/* ------------------------------ */ 7753 .balign 64 7754.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7755/* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 7756 SMP_DMB_ST 7757 b common_returnFromMethod 7758 7759/* ------------------------------ */ 7760 .balign 64 7761.L_OP_IGET_QUICK: /* 0xf2 */ 7762/* File: armv5te/OP_IGET_QUICK.S */ 7763 /* For: iget-quick, iget-object-quick */ 7764 /* op vA, vB, offset@CCCC */ 7765 mov r2, rINST, lsr #12 @ r2<- B 7766 GET_VREG(r3, r2) @ r3<- object we're operating on 7767 FETCH(r1, 1) @ r1<- field byte offset 7768 cmp r3, #0 @ check object for null 7769 mov r2, rINST, lsr #8 @ r2<- A(+) 7770 beq common_errNullObject @ object was null 7771 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7772 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7773 and r2, r2, #15 7774 GET_INST_OPCODE(ip) @ extract opcode from rINST 7775 SET_VREG(r0, r2) @ fp[A]<- r0 7776 GOTO_OPCODE(ip) @ jump to next instruction 7777 7778/* ------------------------------ */ 7779 .balign 64 7780.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7781/* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7782 /* iget-wide-quick vA, vB, offset@CCCC */ 7783 mov r2, rINST, lsr #12 @ r2<- B 7784 GET_VREG(r3, r2) @ r3<- object we're operating on 7785 FETCH(ip, 1) @ ip<- field byte offset 7786 cmp r3, #0 @ check object for null 7787 mov r2, rINST, lsr #8 @ r2<- A(+) 7788 beq common_errNullObject @ object was null 7789 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7790 and r2, r2, #15 7791 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7792 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7793 GET_INST_OPCODE(ip) @ extract opcode from rINST 7794 stmia r3, {r0-r1} @ fp[A]<- r0/r1 7795 GOTO_OPCODE(ip) @ jump to next instruction 7796 7797/* ------------------------------ */ 7798 .balign 64 7799.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7800/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7801/* File: armv5te/OP_IGET_QUICK.S */ 7802 /* For: iget-quick, iget-object-quick */ 7803 /* op vA, vB, offset@CCCC */ 7804 mov r2, rINST, lsr #12 @ r2<- B 7805 GET_VREG(r3, r2) @ r3<- object we're operating on 7806 FETCH(r1, 1) @ r1<- field byte offset 7807 cmp r3, #0 @ check object for null 7808 mov r2, rINST, lsr #8 @ r2<- A(+) 7809 beq common_errNullObject @ object was null 7810 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7811 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7812 and r2, r2, #15 7813 GET_INST_OPCODE(ip) @ extract opcode from rINST 7814 SET_VREG(r0, r2) @ fp[A]<- r0 7815 GOTO_OPCODE(ip) @ jump to next instruction 7816 7817 7818/* ------------------------------ */ 7819 .balign 64 7820.L_OP_IPUT_QUICK: /* 0xf5 */ 7821/* File: armv5te/OP_IPUT_QUICK.S */ 7822 /* For: iput-quick */ 7823 /* op vA, vB, offset@CCCC */ 7824 mov r2, rINST, lsr #12 @ r2<- B 7825 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7826 FETCH(r1, 1) @ r1<- field byte offset 7827 cmp r3, #0 @ check object for null 7828 mov r2, rINST, lsr #8 @ r2<- A(+) 7829 beq common_errNullObject @ object was null 7830 and r2, r2, #15 7831 GET_VREG(r0, r2) @ r0<- fp[A] 7832 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7833 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7834 GET_INST_OPCODE(ip) @ extract opcode from rINST 7835 GOTO_OPCODE(ip) @ jump to next instruction 7836 7837/* ------------------------------ */ 7838 .balign 64 7839.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7840/* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7841 /* iput-wide-quick vA, vB, offset@CCCC */ 7842 mov r0, rINST, lsr #8 @ r0<- A(+) 7843 mov r1, rINST, lsr #12 @ r1<- B 7844 and r0, r0, #15 7845 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7846 add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7847 cmp r2, #0 @ check object for null 7848 ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7849 beq common_errNullObject @ object was null 7850 FETCH(r3, 1) @ r3<- field byte offset 7851 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7852 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7853 GET_INST_OPCODE(ip) @ extract opcode from rINST 7854 GOTO_OPCODE(ip) @ jump to next instruction 7855 7856/* ------------------------------ */ 7857 .balign 64 7858.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7859/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7860 /* For: iput-object-quick */ 7861 /* op vA, vB, offset@CCCC */ 7862 mov r2, rINST, lsr #12 @ r2<- B 7863 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7864 FETCH(r1, 1) @ r1<- field byte offset 7865 cmp r3, #0 @ check object for null 7866 mov r2, rINST, lsr #8 @ r2<- A(+) 7867 beq common_errNullObject @ object was null 7868 and r2, r2, #15 7869 GET_VREG(r0, r2) @ r0<- fp[A] 7870 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7871 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7872 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7873 cmp r0, #0 7874 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7875 GET_INST_OPCODE(ip) @ extract opcode from rINST 7876 GOTO_OPCODE(ip) @ jump to next instruction 7877 7878/* ------------------------------ */ 7879 .balign 64 7880.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7881/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7882 /* 7883 * Handle an optimized virtual method call. 7884 * 7885 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7886 */ 7887 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7888 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7889 FETCH(r3, 2) @ r3<- FEDC or CCCC 7890 FETCH(r1, 1) @ r1<- BBBB 7891 .if (!0) 7892 and r3, r3, #15 @ r3<- C (or stays CCCC) 7893 .endif 7894 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7895 cmp r2, #0 @ is "this" null? 7896 beq common_errNullObject @ null "this", throw exception 7897 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7898 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7899 EXPORT_PC() @ invoke must export 7900 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7901 bl common_invokeMethodNoRange @ continue on 7902 7903/* ------------------------------ */ 7904 .balign 64 7905.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7906/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7907/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7908 /* 7909 * Handle an optimized virtual method call. 7910 * 7911 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7912 */ 7913 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7914 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7915 FETCH(r3, 2) @ r3<- FEDC or CCCC 7916 FETCH(r1, 1) @ r1<- BBBB 7917 .if (!1) 7918 and r3, r3, #15 @ r3<- C (or stays CCCC) 7919 .endif 7920 GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7921 cmp r2, #0 @ is "this" null? 7922 beq common_errNullObject @ null "this", throw exception 7923 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7924 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7925 EXPORT_PC() @ invoke must export 7926 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7927 bl common_invokeMethodRange @ continue on 7928 7929 7930/* ------------------------------ */ 7931 .balign 64 7932.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7933/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7934 /* 7935 * Handle an optimized "super" method call. 7936 * 7937 * for: [opt] invoke-super-quick, invoke-super-quick/range 7938 */ 7939 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7940 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7941 FETCH(r10, 2) @ r10<- GFED or CCCC 7942 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7943 .if (!0) 7944 and r10, r10, #15 @ r10<- D (or stays CCCC) 7945 .endif 7946 FETCH(r1, 1) @ r1<- BBBB 7947 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7948 EXPORT_PC() @ must export for invoke 7949 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7950 GET_VREG(r3, r10) @ r3<- "this" 7951 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7952 cmp r3, #0 @ null "this" ref? 7953 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7954 beq common_errNullObject @ "this" is null, throw exception 7955 bl common_invokeMethodNoRange @ continue on 7956 7957/* ------------------------------ */ 7958 .balign 64 7959.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7960/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7961/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7962 /* 7963 * Handle an optimized "super" method call. 7964 * 7965 * for: [opt] invoke-super-quick, invoke-super-quick/range 7966 */ 7967 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7968 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7969 FETCH(r10, 2) @ r10<- GFED or CCCC 7970 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7971 .if (!1) 7972 and r10, r10, #15 @ r10<- D (or stays CCCC) 7973 .endif 7974 FETCH(r1, 1) @ r1<- BBBB 7975 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7976 EXPORT_PC() @ must export for invoke 7977 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7978 GET_VREG(r3, r10) @ r3<- "this" 7979 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7980 cmp r3, #0 @ null "this" ref? 7981 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7982 beq common_errNullObject @ "this" is null, throw exception 7983 bl common_invokeMethodRange @ continue on 7984 7985 7986/* ------------------------------ */ 7987 .balign 64 7988.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7989/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7990/* File: armv5te/OP_IPUT_OBJECT.S */ 7991 /* 7992 * 32-bit instance field put. 7993 * 7994 * for: iput-object, iput-object-volatile 7995 */ 7996 /* op vA, vB, field@CCCC */ 7997 mov r0, rINST, lsr #12 @ r0<- B 7998 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7999 FETCH(r1, 1) @ r1<- field ref CCCC 8000 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8001 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8002 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8003 cmp r0, #0 @ is resolved entry null? 8004 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 80058: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8006 EXPORT_PC() @ resolve() could throw 8007 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8008 bl dvmResolveInstField @ r0<- resolved InstField ptr 8009 cmp r0, #0 @ success? 8010 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 8011 b common_exceptionThrown 8012 8013 8014/* ------------------------------ */ 8015 .balign 64 8016.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 8017/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 8018/* File: armv5te/OP_SGET.S */ 8019 /* 8020 * General 32-bit SGET handler. 8021 * 8022 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 8023 */ 8024 /* op vAA, field@BBBB */ 8025 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8026 FETCH(r1, 1) @ r1<- field ref BBBB 8027 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8028 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8029 cmp r0, #0 @ is resolved entry null? 8030 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 8031.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 8032 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8033 SMP_DMB @ acquiring load 8034 mov r2, rINST, lsr #8 @ r2<- AA 8035 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8036 SET_VREG(r1, r2) @ fp[AA]<- r1 8037 GET_INST_OPCODE(ip) @ extract opcode from rINST 8038 GOTO_OPCODE(ip) @ jump to next instruction 8039 8040 8041/* ------------------------------ */ 8042 .balign 64 8043.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 8044/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 8045/* File: armv5te/OP_SPUT_OBJECT.S */ 8046 /* 8047 * 32-bit SPUT handler for objects 8048 * 8049 * for: sput-object, sput-object-volatile 8050 */ 8051 /* op vAA, field@BBBB */ 8052 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8053 FETCH(r1, 1) @ r1<- field ref BBBB 8054 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8055 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8056 cmp r0, #0 @ is resolved entry null? 8057 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 8058 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8059 EXPORT_PC() @ resolve() could throw, so export now 8060 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 8061 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8062 cmp r0, #0 @ success? 8063 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 8064 b common_exceptionThrown @ no, handle exception 8065 8066 8067 8068/* ------------------------------ */ 8069 .balign 64 8070.L_OP_DISPATCH_FF: /* 0xff */ 8071/* File: armv5te/OP_DISPATCH_FF.S */ 8072 mov ip, rINST, lsr #8 @ ip<- extended opcode 8073 add ip, ip, #256 @ add offset for extended opcodes 8074 GOTO_OPCODE(ip) @ go to proper extended handler 8075 8076 8077/* ------------------------------ */ 8078 .balign 64 8079.L_OP_CONST_CLASS_JUMBO: /* 0x100 */ 8080/* File: armv5te/OP_CONST_CLASS_JUMBO.S */ 8081 /* const-class/jumbo vBBBB, Class@AAAAAAAA */ 8082 FETCH(r0, 1) @ r0<- aaaa (lo) 8083 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex 8084 FETCH(r1, 2) @ r1<- AAAA (hi) 8085 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 8086 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8087 FETCH(r9, 3) @ r9<- BBBB 8088 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa] 8089 cmp r0, #0 @ not yet resolved? 8090 beq .LOP_CONST_CLASS_JUMBO_resolve 8091 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8092 GET_INST_OPCODE(ip) @ extract opcode from rINST 8093 SET_VREG(r0, r9) @ vBBBB<- r0 8094 GOTO_OPCODE(ip) @ jump to next instruction 8095 8096/* ------------------------------ */ 8097 .balign 64 8098.L_OP_CHECK_CAST_JUMBO: /* 0x101 */ 8099/* File: armv5te/OP_CHECK_CAST_JUMBO.S */ 8100 /* 8101 * Check to see if a cast from one class to another is allowed. 8102 */ 8103 /* check-cast/jumbo vBBBB, class@AAAAAAAA */ 8104 FETCH(r0, 1) @ r0<- aaaa (lo) 8105 FETCH(r2, 2) @ r2<- AAAA (hi) 8106 FETCH(r3, 3) @ r3<- BBBB 8107 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa 8108 GET_VREG(r9, r3) @ r9<- object 8109 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 8110 cmp r9, #0 @ is object null? 8111 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 8112 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds 8113 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 8114 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8115 cmp r1, #0 @ have we resolved this before? 8116 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now 8117.LOP_CHECK_CAST_JUMBO_resolved: 8118 cmp r0, r1 @ same class (trivial success)? 8119 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check 8120 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up 8121 8122/* ------------------------------ */ 8123 .balign 64 8124.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 8125/* File: armv5te/OP_INSTANCE_OF_JUMBO.S */ 8126 /* 8127 * Check to see if an object reference is an instance of a class. 8128 * 8129 * Most common situation is a non-null object, being compared against 8130 * an already-resolved class. 8131 * 8132 * TODO: convert most of this into a common subroutine, shared with 8133 * OP_INSTANCE_OF.S. 8134 */ 8135 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 8136 FETCH(r3, 4) @ r3<- vCCCC 8137 FETCH(r9, 3) @ r9<- vBBBB 8138 GET_VREG(r0, r3) @ r0<- vCCCC (object) 8139 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 8140 cmp r0, #0 @ is object null? 8141 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0 8142 FETCH(r1, 1) @ r1<- aaaa (lo) 8143 FETCH(r3, 2) @ r3<- AAAA (hi) 8144 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 8145 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa 8146 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 8147 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 8148 cmp r1, #0 @ have we resolved this before? 8149 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now 8150 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue 8151 8152/* ------------------------------ */ 8153 .balign 64 8154.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 8155/* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */ 8156 /* 8157 * Create a new instance of a class. 8158 */ 8159 /* new-instance/jumbo vBBBB, class@AAAAAAAA */ 8160 FETCH(r0, 1) @ r0<- aaaa (lo) 8161 FETCH(r1, 2) @ r1<- AAAA (hi) 8162 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8163 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8164 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 8165 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 8166 EXPORT_PC() @ req'd for init, resolve, alloc 8167 cmp r0, #0 @ already resolved? 8168 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now 8169.LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class 8170 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 8171 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 8172 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now 8173.LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class 8174 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 8175 bl dvmAllocObject @ r0<- new object 8176 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue 8177 8178/* ------------------------------ */ 8179 .balign 64 8180.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 8181/* File: armv5te/OP_NEW_ARRAY_JUMBO.S */ 8182 /* 8183 * Allocate an array of objects, specified with the array class 8184 * and a count. 8185 * 8186 * The verifier guarantees that this is an array class, so we don't 8187 * check for it here. 8188 */ 8189 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 8190 FETCH(r2, 1) @ r2<- aaaa (lo) 8191 FETCH(r3, 2) @ r3<- AAAA (hi) 8192 FETCH(r0, 4) @ r0<- vCCCC 8193 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa 8194 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8195 GET_VREG(r1, r0) @ r1<- vCCCC (array length) 8196 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 8197 cmp r1, #0 @ check length 8198 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 8199 bmi common_errNegativeArraySize @ negative length, bail - len in r1 8200 cmp r0, #0 @ already resolved? 8201 EXPORT_PC() @ req'd for resolve, alloc 8202 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue 8203 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now 8204 8205/* ------------------------------ */ 8206 .balign 64 8207.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 8208/* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */ 8209 /* 8210 * Create a new array with elements filled from registers. 8211 * 8212 * TODO: convert most of this into a common subroutine, shared with 8213 * OP_FILLED_NEW_ARRAY.S. 8214 */ 8215 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */ 8216 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8217 FETCH(r0, 1) @ r0<- aaaa (lo) 8218 FETCH(r1, 2) @ r1<- AAAA (hi) 8219 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 8220 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8221 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 8222 EXPORT_PC() @ need for resolve and alloc 8223 cmp r0, #0 @ already resolved? 8224 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on 82258: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8226 mov r2, #0 @ r2<- false 8227 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8228 bl dvmResolveClass @ r0<- call(clazz, ref) 8229 cmp r0, #0 @ got null? 8230 beq common_exceptionThrown @ yes, handle exception 8231 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue 8232 8233/* ------------------------------ */ 8234 .balign 64 8235.L_OP_IGET_JUMBO: /* 0x106 */ 8236/* File: armv5te/OP_IGET_JUMBO.S */ 8237 /* 8238 * Jumbo 32-bit instance field get. 8239 * 8240 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8241 * iget-char/jumbo, iget-short/jumbo 8242 */ 8243 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8244 FETCH(r1, 1) @ r1<- aaaa (lo) 8245 FETCH(r2, 2) @ r2<- AAAA (hi) 8246 FETCH(r0, 4) @ r0<- CCCC 8247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8248 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8250 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8252 cmp r0, #0 @ is resolved entry null? 8253 bne .LOP_IGET_JUMBO_finish @ no, already resolved 82548: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8255 EXPORT_PC() @ resolve() could throw 8256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8257 bl dvmResolveInstField @ r0<- resolved InstField ptr 8258 b .LOP_IGET_JUMBO_resolved @ resolved, continue 8259 8260/* ------------------------------ */ 8261 .balign 64 8262.L_OP_IGET_WIDE_JUMBO: /* 0x107 */ 8263/* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 8264 /* 8265 * Jumbo 64-bit instance field get. 8266 */ 8267 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8268 FETCH(r1, 1) @ r1<- aaaa (lo) 8269 FETCH(r2, 2) @ r2<- AAAA (hi) 8270 FETCH(r0, 4) @ r0<- CCCC 8271 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8272 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8273 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8274 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8275 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8276 cmp r0, #0 @ is resolved entry null? 8277 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved 82788: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8279 EXPORT_PC() @ resolve() could throw 8280 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8281 bl dvmResolveInstField @ r0<- resolved InstField ptr 8282 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue 8283 8284/* ------------------------------ */ 8285 .balign 64 8286.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 8287/* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 8288/* File: armv5te/OP_IGET_JUMBO.S */ 8289 /* 8290 * Jumbo 32-bit instance field get. 8291 * 8292 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8293 * iget-char/jumbo, iget-short/jumbo 8294 */ 8295 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8296 FETCH(r1, 1) @ r1<- aaaa (lo) 8297 FETCH(r2, 2) @ r2<- AAAA (hi) 8298 FETCH(r0, 4) @ r0<- CCCC 8299 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8300 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8301 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8302 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8303 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8304 cmp r0, #0 @ is resolved entry null? 8305 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved 83068: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8307 EXPORT_PC() @ resolve() could throw 8308 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8309 bl dvmResolveInstField @ r0<- resolved InstField ptr 8310 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue 8311 8312 8313/* ------------------------------ */ 8314 .balign 64 8315.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 8316/* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */ 8317@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" } 8318/* File: armv5te/OP_IGET_JUMBO.S */ 8319 /* 8320 * Jumbo 32-bit instance field get. 8321 * 8322 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8323 * iget-char/jumbo, iget-short/jumbo 8324 */ 8325 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8326 FETCH(r1, 1) @ r1<- aaaa (lo) 8327 FETCH(r2, 2) @ r2<- AAAA (hi) 8328 FETCH(r0, 4) @ r0<- CCCC 8329 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8330 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8331 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8332 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8333 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8334 cmp r0, #0 @ is resolved entry null? 8335 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved 83368: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8337 EXPORT_PC() @ resolve() could throw 8338 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8339 bl dvmResolveInstField @ r0<- resolved InstField ptr 8340 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue 8341 8342 8343/* ------------------------------ */ 8344 .balign 64 8345.L_OP_IGET_BYTE_JUMBO: /* 0x10a */ 8346/* File: armv5te/OP_IGET_BYTE_JUMBO.S */ 8347@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" } 8348/* File: armv5te/OP_IGET_JUMBO.S */ 8349 /* 8350 * Jumbo 32-bit instance field get. 8351 * 8352 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8353 * iget-char/jumbo, iget-short/jumbo 8354 */ 8355 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8356 FETCH(r1, 1) @ r1<- aaaa (lo) 8357 FETCH(r2, 2) @ r2<- AAAA (hi) 8358 FETCH(r0, 4) @ r0<- CCCC 8359 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8360 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8361 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8362 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8363 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8364 cmp r0, #0 @ is resolved entry null? 8365 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved 83668: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8367 EXPORT_PC() @ resolve() could throw 8368 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8369 bl dvmResolveInstField @ r0<- resolved InstField ptr 8370 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue 8371 8372 8373/* ------------------------------ */ 8374 .balign 64 8375.L_OP_IGET_CHAR_JUMBO: /* 0x10b */ 8376/* File: armv5te/OP_IGET_CHAR_JUMBO.S */ 8377@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" } 8378/* File: armv5te/OP_IGET_JUMBO.S */ 8379 /* 8380 * Jumbo 32-bit instance field get. 8381 * 8382 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8383 * iget-char/jumbo, iget-short/jumbo 8384 */ 8385 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8386 FETCH(r1, 1) @ r1<- aaaa (lo) 8387 FETCH(r2, 2) @ r2<- AAAA (hi) 8388 FETCH(r0, 4) @ r0<- CCCC 8389 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8390 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8391 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8392 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8393 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8394 cmp r0, #0 @ is resolved entry null? 8395 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved 83968: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8397 EXPORT_PC() @ resolve() could throw 8398 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8399 bl dvmResolveInstField @ r0<- resolved InstField ptr 8400 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue 8401 8402 8403/* ------------------------------ */ 8404 .balign 64 8405.L_OP_IGET_SHORT_JUMBO: /* 0x10c */ 8406/* File: armv5te/OP_IGET_SHORT_JUMBO.S */ 8407@include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" } 8408/* File: armv5te/OP_IGET_JUMBO.S */ 8409 /* 8410 * Jumbo 32-bit instance field get. 8411 * 8412 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8413 * iget-char/jumbo, iget-short/jumbo 8414 */ 8415 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8416 FETCH(r1, 1) @ r1<- aaaa (lo) 8417 FETCH(r2, 2) @ r2<- AAAA (hi) 8418 FETCH(r0, 4) @ r0<- CCCC 8419 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8420 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8421 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8422 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8423 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8424 cmp r0, #0 @ is resolved entry null? 8425 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved 84268: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8427 EXPORT_PC() @ resolve() could throw 8428 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8429 bl dvmResolveInstField @ r0<- resolved InstField ptr 8430 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue 8431 8432 8433/* ------------------------------ */ 8434 .balign 64 8435.L_OP_IPUT_JUMBO: /* 0x10d */ 8436/* File: armv5te/OP_IPUT_JUMBO.S */ 8437 /* 8438 * Jumbo 32-bit instance field put. 8439 * 8440 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8441 * iput-short/jumbo 8442 */ 8443 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8444 FETCH(r1, 1) @ r1<- aaaa (lo) 8445 FETCH(r2, 2) @ r2<- AAAA (hi) 8446 FETCH(r0, 4) @ r0<- CCCC 8447 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8448 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8449 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8450 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8451 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8452 cmp r0, #0 @ is resolved entry null? 8453 bne .LOP_IPUT_JUMBO_finish @ no, already resolved 84548: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8455 EXPORT_PC() @ resolve() could throw 8456 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8457 bl dvmResolveInstField @ r0<- resolved InstField ptr 8458 b .LOP_IPUT_JUMBO_resolved @ resolved, continue 8459 8460/* ------------------------------ */ 8461 .balign 64 8462.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 8463/* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 8464 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8465 FETCH(r1, 1) @ r1<- aaaa (lo) 8466 FETCH(r2, 2) @ r2<- AAAA (hi) 8467 FETCH(r0, 4) @ r0<- CCCC 8468 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8469 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8470 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8471 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8472 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8473 cmp r0, #0 @ is resolved entry null? 8474 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved 84758: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8476 EXPORT_PC() @ resolve() could throw 8477 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8478 bl dvmResolveInstField @ r0<- resolved InstField ptr 8479 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue 8480 8481/* ------------------------------ */ 8482 .balign 64 8483.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 8484/* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 8485 /* 8486 * Jumbo 32-bit instance field put. 8487 */ 8488 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8489 FETCH(r1, 1) @ r1<- aaaa (lo) 8490 FETCH(r2, 2) @ r2<- AAAA (hi) 8491 FETCH(r0, 4) @ r0<- CCCC 8492 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8493 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8494 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8495 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8496 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8497 cmp r0, #0 @ is resolved entry null? 8498 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved 84998: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8500 EXPORT_PC() @ resolve() could throw 8501 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8502 bl dvmResolveInstField @ r0<- resolved InstField ptr 8503 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue 8504 8505/* ------------------------------ */ 8506 .balign 64 8507.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 8508/* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */ 8509@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" } 8510/* File: armv5te/OP_IPUT_JUMBO.S */ 8511 /* 8512 * Jumbo 32-bit instance field put. 8513 * 8514 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8515 * iput-short/jumbo 8516 */ 8517 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8518 FETCH(r1, 1) @ r1<- aaaa (lo) 8519 FETCH(r2, 2) @ r2<- AAAA (hi) 8520 FETCH(r0, 4) @ r0<- CCCC 8521 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8522 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8523 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8524 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8526 cmp r0, #0 @ is resolved entry null? 8527 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved 85288: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8529 EXPORT_PC() @ resolve() could throw 8530 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8531 bl dvmResolveInstField @ r0<- resolved InstField ptr 8532 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue 8533 8534 8535/* ------------------------------ */ 8536 .balign 64 8537.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 8538/* File: armv5te/OP_IPUT_BYTE_JUMBO.S */ 8539@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" } 8540/* File: armv5te/OP_IPUT_JUMBO.S */ 8541 /* 8542 * Jumbo 32-bit instance field put. 8543 * 8544 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8545 * iput-short/jumbo 8546 */ 8547 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8548 FETCH(r1, 1) @ r1<- aaaa (lo) 8549 FETCH(r2, 2) @ r2<- AAAA (hi) 8550 FETCH(r0, 4) @ r0<- CCCC 8551 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8552 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8553 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8554 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8555 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8556 cmp r0, #0 @ is resolved entry null? 8557 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved 85588: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8559 EXPORT_PC() @ resolve() could throw 8560 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8561 bl dvmResolveInstField @ r0<- resolved InstField ptr 8562 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue 8563 8564 8565/* ------------------------------ */ 8566 .balign 64 8567.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 8568/* File: armv5te/OP_IPUT_CHAR_JUMBO.S */ 8569@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" } 8570/* File: armv5te/OP_IPUT_JUMBO.S */ 8571 /* 8572 * Jumbo 32-bit instance field put. 8573 * 8574 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8575 * iput-short/jumbo 8576 */ 8577 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8578 FETCH(r1, 1) @ r1<- aaaa (lo) 8579 FETCH(r2, 2) @ r2<- AAAA (hi) 8580 FETCH(r0, 4) @ r0<- CCCC 8581 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8582 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8583 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8584 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8585 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8586 cmp r0, #0 @ is resolved entry null? 8587 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved 85888: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8589 EXPORT_PC() @ resolve() could throw 8590 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8591 bl dvmResolveInstField @ r0<- resolved InstField ptr 8592 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue 8593 8594 8595/* ------------------------------ */ 8596 .balign 64 8597.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 8598/* File: armv5te/OP_IPUT_SHORT_JUMBO.S */ 8599@include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" } 8600/* File: armv5te/OP_IPUT_JUMBO.S */ 8601 /* 8602 * Jumbo 32-bit instance field put. 8603 * 8604 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8605 * iput-short/jumbo 8606 */ 8607 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8608 FETCH(r1, 1) @ r1<- aaaa (lo) 8609 FETCH(r2, 2) @ r2<- AAAA (hi) 8610 FETCH(r0, 4) @ r0<- CCCC 8611 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8612 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8613 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8614 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8615 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8616 cmp r0, #0 @ is resolved entry null? 8617 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved 86188: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8619 EXPORT_PC() @ resolve() could throw 8620 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8621 bl dvmResolveInstField @ r0<- resolved InstField ptr 8622 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue 8623 8624 8625/* ------------------------------ */ 8626 .balign 64 8627.L_OP_SGET_JUMBO: /* 0x114 */ 8628/* File: armv5te/OP_SGET_JUMBO.S */ 8629 /* 8630 * Jumbo 32-bit SGET handler. 8631 * 8632 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8633 * sget-char/jumbo, sget-short/jumbo 8634 */ 8635 /* exop vBBBB, field@AAAAAAAA */ 8636 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8637 FETCH(r0, 1) @ r0<- aaaa (lo) 8638 FETCH(r1, 2) @ r1<- AAAA (hi) 8639 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8640 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8641 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8642 cmp r0, #0 @ is resolved entry null? 8643 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve 8644.LOP_SGET_JUMBO_finish: @ field ptr in r0 8645 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8646 @ no-op @ acquiring load 8647 FETCH(r2, 3) @ r2<- BBBB 8648 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8649 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8650 GET_INST_OPCODE(ip) @ extract opcode from rINST 8651 GOTO_OPCODE(ip) @ jump to next instruction 8652 8653/* ------------------------------ */ 8654 .balign 64 8655.L_OP_SGET_WIDE_JUMBO: /* 0x115 */ 8656/* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 8657 /* 8658 * Jumbo 64-bit SGET handler. 8659 */ 8660 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 8661 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8662 FETCH(r0, 1) @ r0<- aaaa (lo) 8663 FETCH(r1, 2) @ r1<- AAAA (hi) 8664 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8665 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8666 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8667 cmp r0, #0 @ is resolved entry null? 8668 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve 8669.LOP_SGET_WIDE_JUMBO_finish: 8670 FETCH(r9, 3) @ r9<- BBBB 8671 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 8672 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8673 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8674 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 8675 GET_INST_OPCODE(ip) @ extract opcode from rINST 8676 GOTO_OPCODE(ip) @ jump to next instruction 8677 8678/* ------------------------------ */ 8679 .balign 64 8680.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 8681/* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 8682/* File: armv5te/OP_SGET_JUMBO.S */ 8683 /* 8684 * Jumbo 32-bit SGET handler. 8685 * 8686 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8687 * sget-char/jumbo, sget-short/jumbo 8688 */ 8689 /* exop vBBBB, field@AAAAAAAA */ 8690 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8691 FETCH(r0, 1) @ r0<- aaaa (lo) 8692 FETCH(r1, 2) @ r1<- AAAA (hi) 8693 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8694 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8695 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8696 cmp r0, #0 @ is resolved entry null? 8697 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve 8698.LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0 8699 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8700 @ no-op @ acquiring load 8701 FETCH(r2, 3) @ r2<- BBBB 8702 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8703 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8704 GET_INST_OPCODE(ip) @ extract opcode from rINST 8705 GOTO_OPCODE(ip) @ jump to next instruction 8706 8707 8708/* ------------------------------ */ 8709 .balign 64 8710.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 8711/* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */ 8712/* File: armv5te/OP_SGET_JUMBO.S */ 8713 /* 8714 * Jumbo 32-bit SGET handler. 8715 * 8716 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8717 * sget-char/jumbo, sget-short/jumbo 8718 */ 8719 /* exop vBBBB, field@AAAAAAAA */ 8720 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8721 FETCH(r0, 1) @ r0<- aaaa (lo) 8722 FETCH(r1, 2) @ r1<- AAAA (hi) 8723 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8724 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8725 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8726 cmp r0, #0 @ is resolved entry null? 8727 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve 8728.LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0 8729 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8730 @ no-op @ acquiring load 8731 FETCH(r2, 3) @ r2<- BBBB 8732 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8733 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8734 GET_INST_OPCODE(ip) @ extract opcode from rINST 8735 GOTO_OPCODE(ip) @ jump to next instruction 8736 8737 8738/* ------------------------------ */ 8739 .balign 64 8740.L_OP_SGET_BYTE_JUMBO: /* 0x118 */ 8741/* File: armv5te/OP_SGET_BYTE_JUMBO.S */ 8742/* File: armv5te/OP_SGET_JUMBO.S */ 8743 /* 8744 * Jumbo 32-bit SGET handler. 8745 * 8746 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8747 * sget-char/jumbo, sget-short/jumbo 8748 */ 8749 /* exop vBBBB, field@AAAAAAAA */ 8750 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8751 FETCH(r0, 1) @ r0<- aaaa (lo) 8752 FETCH(r1, 2) @ r1<- AAAA (hi) 8753 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8754 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8755 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8756 cmp r0, #0 @ is resolved entry null? 8757 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve 8758.LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0 8759 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8760 @ no-op @ acquiring load 8761 FETCH(r2, 3) @ r2<- BBBB 8762 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8763 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8764 GET_INST_OPCODE(ip) @ extract opcode from rINST 8765 GOTO_OPCODE(ip) @ jump to next instruction 8766 8767 8768/* ------------------------------ */ 8769 .balign 64 8770.L_OP_SGET_CHAR_JUMBO: /* 0x119 */ 8771/* File: armv5te/OP_SGET_CHAR_JUMBO.S */ 8772/* File: armv5te/OP_SGET_JUMBO.S */ 8773 /* 8774 * Jumbo 32-bit SGET handler. 8775 * 8776 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8777 * sget-char/jumbo, sget-short/jumbo 8778 */ 8779 /* exop vBBBB, field@AAAAAAAA */ 8780 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8781 FETCH(r0, 1) @ r0<- aaaa (lo) 8782 FETCH(r1, 2) @ r1<- AAAA (hi) 8783 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8784 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8785 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8786 cmp r0, #0 @ is resolved entry null? 8787 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve 8788.LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0 8789 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8790 @ no-op @ acquiring load 8791 FETCH(r2, 3) @ r2<- BBBB 8792 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8793 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8794 GET_INST_OPCODE(ip) @ extract opcode from rINST 8795 GOTO_OPCODE(ip) @ jump to next instruction 8796 8797 8798/* ------------------------------ */ 8799 .balign 64 8800.L_OP_SGET_SHORT_JUMBO: /* 0x11a */ 8801/* File: armv5te/OP_SGET_SHORT_JUMBO.S */ 8802/* File: armv5te/OP_SGET_JUMBO.S */ 8803 /* 8804 * Jumbo 32-bit SGET handler. 8805 * 8806 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8807 * sget-char/jumbo, sget-short/jumbo 8808 */ 8809 /* exop vBBBB, field@AAAAAAAA */ 8810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8811 FETCH(r0, 1) @ r0<- aaaa (lo) 8812 FETCH(r1, 2) @ r1<- AAAA (hi) 8813 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8814 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8815 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8816 cmp r0, #0 @ is resolved entry null? 8817 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve 8818.LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0 8819 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8820 @ no-op @ acquiring load 8821 FETCH(r2, 3) @ r2<- BBBB 8822 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8823 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8824 GET_INST_OPCODE(ip) @ extract opcode from rINST 8825 GOTO_OPCODE(ip) @ jump to next instruction 8826 8827 8828/* ------------------------------ */ 8829 .balign 64 8830.L_OP_SPUT_JUMBO: /* 0x11b */ 8831/* File: armv5te/OP_SPUT_JUMBO.S */ 8832 /* 8833 * Jumbo 32-bit SPUT handler. 8834 * 8835 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8836 * sput-short/jumbo 8837 */ 8838 /* exop vBBBB, field@AAAAAAAA */ 8839 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8840 FETCH(r0, 1) @ r0<- aaaa (lo) 8841 FETCH(r1, 2) @ r1<- AAAA (hi) 8842 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8843 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8844 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8845 cmp r0, #0 @ is resolved entry null? 8846 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve 8847.LOP_SPUT_JUMBO_finish: @ field ptr in r0 8848 FETCH(r2, 3) @ r2<- BBBB 8849 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8850 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8851 GET_INST_OPCODE(ip) @ extract opcode from rINST 8852 @ no-op @ releasing store 8853 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8854 GOTO_OPCODE(ip) @ jump to next instruction 8855 8856/* ------------------------------ */ 8857 .balign 64 8858.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 8859/* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 8860 /* 8861 * Jumbo 64-bit SPUT handler. 8862 */ 8863 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 8864 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 8865 FETCH(r1, 1) @ r1<- aaaa (lo) 8866 FETCH(r2, 2) @ r2<- AAAA (hi) 8867 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 8868 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8869 FETCH(r9, 3) @ r9<- BBBB 8870 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 8871 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8872 cmp r2, #0 @ is resolved entry null? 8873 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve 8874.LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9 8875 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8876 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 8877 GET_INST_OPCODE(r10) @ extract opcode from rINST 8878 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 8879 GOTO_OPCODE(r10) @ jump to next instruction 8880 8881/* ------------------------------ */ 8882 .balign 64 8883.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 8884/* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 8885 /* 8886 * Jumbo 32-bit SPUT handler for objects 8887 */ 8888 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 8889 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8890 FETCH(r0, 1) @ r0<- aaaa (lo) 8891 FETCH(r1, 2) @ r1<- AAAA (hi) 8892 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8893 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8894 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8895 cmp r0, #0 @ is resolved entry null? 8896 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue 8897 ldr r9, [rSELF, #offThread_method] @ r9<- current method 8898 EXPORT_PC() @ resolve() could throw, so export now 8899 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 8900 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8901 cmp r0, #0 @ success? 8902 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish 8903 b common_exceptionThrown @ no, handle exception 8904 8905/* ------------------------------ */ 8906 .balign 64 8907.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 8908/* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */ 8909/* File: armv5te/OP_SPUT_JUMBO.S */ 8910 /* 8911 * Jumbo 32-bit SPUT handler. 8912 * 8913 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8914 * sput-short/jumbo 8915 */ 8916 /* exop vBBBB, field@AAAAAAAA */ 8917 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8918 FETCH(r0, 1) @ r0<- aaaa (lo) 8919 FETCH(r1, 2) @ r1<- AAAA (hi) 8920 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8921 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8922 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8923 cmp r0, #0 @ is resolved entry null? 8924 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve 8925.LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0 8926 FETCH(r2, 3) @ r2<- BBBB 8927 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8928 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8929 GET_INST_OPCODE(ip) @ extract opcode from rINST 8930 @ no-op @ releasing store 8931 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8932 GOTO_OPCODE(ip) @ jump to next instruction 8933 8934 8935/* ------------------------------ */ 8936 .balign 64 8937.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 8938/* File: armv5te/OP_SPUT_BYTE_JUMBO.S */ 8939/* File: armv5te/OP_SPUT_JUMBO.S */ 8940 /* 8941 * Jumbo 32-bit SPUT handler. 8942 * 8943 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8944 * sput-short/jumbo 8945 */ 8946 /* exop vBBBB, field@AAAAAAAA */ 8947 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8948 FETCH(r0, 1) @ r0<- aaaa (lo) 8949 FETCH(r1, 2) @ r1<- AAAA (hi) 8950 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8951 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8952 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8953 cmp r0, #0 @ is resolved entry null? 8954 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve 8955.LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0 8956 FETCH(r2, 3) @ r2<- BBBB 8957 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8958 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8959 GET_INST_OPCODE(ip) @ extract opcode from rINST 8960 @ no-op @ releasing store 8961 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8962 GOTO_OPCODE(ip) @ jump to next instruction 8963 8964 8965/* ------------------------------ */ 8966 .balign 64 8967.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 8968/* File: armv5te/OP_SPUT_CHAR_JUMBO.S */ 8969/* File: armv5te/OP_SPUT_JUMBO.S */ 8970 /* 8971 * Jumbo 32-bit SPUT handler. 8972 * 8973 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8974 * sput-short/jumbo 8975 */ 8976 /* exop vBBBB, field@AAAAAAAA */ 8977 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8978 FETCH(r0, 1) @ r0<- aaaa (lo) 8979 FETCH(r1, 2) @ r1<- AAAA (hi) 8980 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8981 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8982 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8983 cmp r0, #0 @ is resolved entry null? 8984 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve 8985.LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0 8986 FETCH(r2, 3) @ r2<- BBBB 8987 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8988 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8989 GET_INST_OPCODE(ip) @ extract opcode from rINST 8990 @ no-op @ releasing store 8991 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8992 GOTO_OPCODE(ip) @ jump to next instruction 8993 8994 8995/* ------------------------------ */ 8996 .balign 64 8997.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 8998/* File: armv5te/OP_SPUT_SHORT_JUMBO.S */ 8999/* File: armv5te/OP_SPUT_JUMBO.S */ 9000 /* 9001 * Jumbo 32-bit SPUT handler. 9002 * 9003 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 9004 * sput-short/jumbo 9005 */ 9006 /* exop vBBBB, field@AAAAAAAA */ 9007 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 9008 FETCH(r0, 1) @ r0<- aaaa (lo) 9009 FETCH(r1, 2) @ r1<- AAAA (hi) 9010 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 9011 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 9012 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 9013 cmp r0, #0 @ is resolved entry null? 9014 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve 9015.LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0 9016 FETCH(r2, 3) @ r2<- BBBB 9017 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 9018 GET_VREG(r1, r2) @ r1<- fp[BBBB] 9019 GET_INST_OPCODE(ip) @ extract opcode from rINST 9020 @ no-op @ releasing store 9021 str r1, [r0, #offStaticField_value] @ field<- vBBBB 9022 GOTO_OPCODE(ip) @ jump to next instruction 9023 9024 9025/* ------------------------------ */ 9026 .balign 64 9027.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 9028/* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */ 9029 /* 9030 * Handle a virtual method call. 9031 */ 9032 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 9033 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 9034 FETCH(r0, 1) @ r1<- aaaa (lo) 9035 FETCH(r1, 2) @ r1<- AAAA (hi) 9036 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 9037 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 9038 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 9039 cmp r0, #0 @ already resolved? 9040 EXPORT_PC() @ must export for invoke 9041 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on 9042 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 9043 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 9044 mov r2, #METHOD_VIRTUAL @ resolver method type 9045 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 9046 cmp r0, #0 @ got null? 9047 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue 9048 b common_exceptionThrown @ yes, handle exception 9049 9050/* ------------------------------ */ 9051 .balign 64 9052.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 9053/* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */ 9054 /* 9055 * Handle a "super" method call. 9056 */ 9057 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 9058 FETCH(r10, 4) @ r10<- CCCC 9059 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 9060 FETCH(r0, 1) @ r1<- aaaa (lo) 9061 FETCH(r1, 2) @ r1<- AAAA (hi) 9062 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 9063 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 9064 GET_VREG(r2, r10) @ r2<- "this" ptr 9065 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 9066 cmp r2, #0 @ null "this"? 9067 ldr r9, [rSELF, #offThread_method] @ r9<- current method 9068 beq common_errNullObject @ null "this", throw exception 9069 cmp r0, #0 @ already resolved? 9070 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 9071 EXPORT_PC() @ must export for invoke 9072 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on 9073 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now 9074 9075/* ------------------------------ */ 9076 .balign 64 9077.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 9078/* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */ 9079 /* 9080 * Handle a direct method call. 9081 * 9082 * (We could defer the "is 'this' pointer null" test to the common 9083 * method invocation code, and use a flag to indicate that static 9084 * calls don't count. If we do this as part of copying the arguments 9085 * out we could avoiding loading the first arg twice.) 9086 * 9087 */ 9088 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 9089 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 9090 FETCH(r0, 1) @ r1<- aaaa (lo) 9091 FETCH(r1, 2) @ r1<- AAAA (hi) 9092 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 9093 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 9094 FETCH(r10, 4) @ r10<- CCCC 9095 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 9096 cmp r0, #0 @ already resolved? 9097 EXPORT_PC() @ must export for invoke 9098 GET_VREG(r2, r10) @ r2<- "this" ptr 9099 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now 9100.LOP_INVOKE_DIRECT_JUMBO_finish: 9101 cmp r2, #0 @ null "this" ref? 9102 bne common_invokeMethodJumbo @ no, continue on 9103 b common_errNullObject @ yes, throw exception 9104 9105/* ------------------------------ */ 9106 .balign 64 9107.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 9108/* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */ 9109 /* 9110 * Handle a static method call. 9111 */ 9112 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 9113 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 9114 FETCH(r0, 1) @ r1<- aaaa (lo) 9115 FETCH(r1, 2) @ r1<- AAAA (hi) 9116 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 9117 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 9118 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 9119 cmp r0, #0 @ already resolved? 9120 EXPORT_PC() @ must export for invoke 9121 bne common_invokeMethodJumbo @ yes, continue on 91220: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 9123 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 9124 mov r2, #METHOD_STATIC @ resolver method type 9125 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 9126 cmp r0, #0 @ got null? 9127 bne common_invokeMethodJumbo @ no, continue 9128 b common_exceptionThrown @ yes, handle exception 9129 9130/* ------------------------------ */ 9131 .balign 64 9132.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 9133/* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */ 9134 /* 9135 * Handle an interface method call. 9136 */ 9137 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 9138 FETCH(r2, 4) @ r2<- CCCC 9139 FETCH(r0, 1) @ r0<- aaaa (lo) 9140 FETCH(r1, 2) @ r1<- AAAA (hi) 9141 EXPORT_PC() @ must export for invoke 9142 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 9143 GET_VREG(r0, r2) @ r0<- first arg ("this") 9144 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 9145 cmp r0, #0 @ null obj? 9146 ldr r2, [rSELF, #offThread_method] @ r2<- method 9147 beq common_errNullObject @ yes, fail 9148 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 9149 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 9150 cmp r0, #0 @ failed? 9151 beq common_exceptionThrown @ yes, handle exception 9152 b common_invokeMethodJumbo @ jump to common handler 9153 9154/* ------------------------------ */ 9155 .balign 64 9156.L_OP_UNUSED_27FF: /* 0x127 */ 9157/* File: armv5te/OP_UNUSED_27FF.S */ 9158/* File: armv5te/unused.S */ 9159 bl common_abort 9160 9161 9162/* ------------------------------ */ 9163 .balign 64 9164.L_OP_UNUSED_28FF: /* 0x128 */ 9165/* File: armv5te/OP_UNUSED_28FF.S */ 9166/* File: armv5te/unused.S */ 9167 bl common_abort 9168 9169 9170/* ------------------------------ */ 9171 .balign 64 9172.L_OP_UNUSED_29FF: /* 0x129 */ 9173/* File: armv5te/OP_UNUSED_29FF.S */ 9174/* File: armv5te/unused.S */ 9175 bl common_abort 9176 9177 9178/* ------------------------------ */ 9179 .balign 64 9180.L_OP_UNUSED_2AFF: /* 0x12a */ 9181/* File: armv5te/OP_UNUSED_2AFF.S */ 9182/* File: armv5te/unused.S */ 9183 bl common_abort 9184 9185 9186/* ------------------------------ */ 9187 .balign 64 9188.L_OP_UNUSED_2BFF: /* 0x12b */ 9189/* File: armv5te/OP_UNUSED_2BFF.S */ 9190/* File: armv5te/unused.S */ 9191 bl common_abort 9192 9193 9194/* ------------------------------ */ 9195 .balign 64 9196.L_OP_UNUSED_2CFF: /* 0x12c */ 9197/* File: armv5te/OP_UNUSED_2CFF.S */ 9198/* File: armv5te/unused.S */ 9199 bl common_abort 9200 9201 9202/* ------------------------------ */ 9203 .balign 64 9204.L_OP_UNUSED_2DFF: /* 0x12d */ 9205/* File: armv5te/OP_UNUSED_2DFF.S */ 9206/* File: armv5te/unused.S */ 9207 bl common_abort 9208 9209 9210/* ------------------------------ */ 9211 .balign 64 9212.L_OP_UNUSED_2EFF: /* 0x12e */ 9213/* File: armv5te/OP_UNUSED_2EFF.S */ 9214/* File: armv5te/unused.S */ 9215 bl common_abort 9216 9217 9218/* ------------------------------ */ 9219 .balign 64 9220.L_OP_UNUSED_2FFF: /* 0x12f */ 9221/* File: armv5te/OP_UNUSED_2FFF.S */ 9222/* File: armv5te/unused.S */ 9223 bl common_abort 9224 9225 9226/* ------------------------------ */ 9227 .balign 64 9228.L_OP_UNUSED_30FF: /* 0x130 */ 9229/* File: armv5te/OP_UNUSED_30FF.S */ 9230/* File: armv5te/unused.S */ 9231 bl common_abort 9232 9233 9234/* ------------------------------ */ 9235 .balign 64 9236.L_OP_UNUSED_31FF: /* 0x131 */ 9237/* File: armv5te/OP_UNUSED_31FF.S */ 9238/* File: armv5te/unused.S */ 9239 bl common_abort 9240 9241 9242/* ------------------------------ */ 9243 .balign 64 9244.L_OP_UNUSED_32FF: /* 0x132 */ 9245/* File: armv5te/OP_UNUSED_32FF.S */ 9246/* File: armv5te/unused.S */ 9247 bl common_abort 9248 9249 9250/* ------------------------------ */ 9251 .balign 64 9252.L_OP_UNUSED_33FF: /* 0x133 */ 9253/* File: armv5te/OP_UNUSED_33FF.S */ 9254/* File: armv5te/unused.S */ 9255 bl common_abort 9256 9257 9258/* ------------------------------ */ 9259 .balign 64 9260.L_OP_UNUSED_34FF: /* 0x134 */ 9261/* File: armv5te/OP_UNUSED_34FF.S */ 9262/* File: armv5te/unused.S */ 9263 bl common_abort 9264 9265 9266/* ------------------------------ */ 9267 .balign 64 9268.L_OP_UNUSED_35FF: /* 0x135 */ 9269/* File: armv5te/OP_UNUSED_35FF.S */ 9270/* File: armv5te/unused.S */ 9271 bl common_abort 9272 9273 9274/* ------------------------------ */ 9275 .balign 64 9276.L_OP_UNUSED_36FF: /* 0x136 */ 9277/* File: armv5te/OP_UNUSED_36FF.S */ 9278/* File: armv5te/unused.S */ 9279 bl common_abort 9280 9281 9282/* ------------------------------ */ 9283 .balign 64 9284.L_OP_UNUSED_37FF: /* 0x137 */ 9285/* File: armv5te/OP_UNUSED_37FF.S */ 9286/* File: armv5te/unused.S */ 9287 bl common_abort 9288 9289 9290/* ------------------------------ */ 9291 .balign 64 9292.L_OP_UNUSED_38FF: /* 0x138 */ 9293/* File: armv5te/OP_UNUSED_38FF.S */ 9294/* File: armv5te/unused.S */ 9295 bl common_abort 9296 9297 9298/* ------------------------------ */ 9299 .balign 64 9300.L_OP_UNUSED_39FF: /* 0x139 */ 9301/* File: armv5te/OP_UNUSED_39FF.S */ 9302/* File: armv5te/unused.S */ 9303 bl common_abort 9304 9305 9306/* ------------------------------ */ 9307 .balign 64 9308.L_OP_UNUSED_3AFF: /* 0x13a */ 9309/* File: armv5te/OP_UNUSED_3AFF.S */ 9310/* File: armv5te/unused.S */ 9311 bl common_abort 9312 9313 9314/* ------------------------------ */ 9315 .balign 64 9316.L_OP_UNUSED_3BFF: /* 0x13b */ 9317/* File: armv5te/OP_UNUSED_3BFF.S */ 9318/* File: armv5te/unused.S */ 9319 bl common_abort 9320 9321 9322/* ------------------------------ */ 9323 .balign 64 9324.L_OP_UNUSED_3CFF: /* 0x13c */ 9325/* File: armv5te/OP_UNUSED_3CFF.S */ 9326/* File: armv5te/unused.S */ 9327 bl common_abort 9328 9329 9330/* ------------------------------ */ 9331 .balign 64 9332.L_OP_UNUSED_3DFF: /* 0x13d */ 9333/* File: armv5te/OP_UNUSED_3DFF.S */ 9334/* File: armv5te/unused.S */ 9335 bl common_abort 9336 9337 9338/* ------------------------------ */ 9339 .balign 64 9340.L_OP_UNUSED_3EFF: /* 0x13e */ 9341/* File: armv5te/OP_UNUSED_3EFF.S */ 9342/* File: armv5te/unused.S */ 9343 bl common_abort 9344 9345 9346/* ------------------------------ */ 9347 .balign 64 9348.L_OP_UNUSED_3FFF: /* 0x13f */ 9349/* File: armv5te/OP_UNUSED_3FFF.S */ 9350/* File: armv5te/unused.S */ 9351 bl common_abort 9352 9353 9354/* ------------------------------ */ 9355 .balign 64 9356.L_OP_UNUSED_40FF: /* 0x140 */ 9357/* File: armv5te/OP_UNUSED_40FF.S */ 9358/* File: armv5te/unused.S */ 9359 bl common_abort 9360 9361 9362/* ------------------------------ */ 9363 .balign 64 9364.L_OP_UNUSED_41FF: /* 0x141 */ 9365/* File: armv5te/OP_UNUSED_41FF.S */ 9366/* File: armv5te/unused.S */ 9367 bl common_abort 9368 9369 9370/* ------------------------------ */ 9371 .balign 64 9372.L_OP_UNUSED_42FF: /* 0x142 */ 9373/* File: armv5te/OP_UNUSED_42FF.S */ 9374/* File: armv5te/unused.S */ 9375 bl common_abort 9376 9377 9378/* ------------------------------ */ 9379 .balign 64 9380.L_OP_UNUSED_43FF: /* 0x143 */ 9381/* File: armv5te/OP_UNUSED_43FF.S */ 9382/* File: armv5te/unused.S */ 9383 bl common_abort 9384 9385 9386/* ------------------------------ */ 9387 .balign 64 9388.L_OP_UNUSED_44FF: /* 0x144 */ 9389/* File: armv5te/OP_UNUSED_44FF.S */ 9390/* File: armv5te/unused.S */ 9391 bl common_abort 9392 9393 9394/* ------------------------------ */ 9395 .balign 64 9396.L_OP_UNUSED_45FF: /* 0x145 */ 9397/* File: armv5te/OP_UNUSED_45FF.S */ 9398/* File: armv5te/unused.S */ 9399 bl common_abort 9400 9401 9402/* ------------------------------ */ 9403 .balign 64 9404.L_OP_UNUSED_46FF: /* 0x146 */ 9405/* File: armv5te/OP_UNUSED_46FF.S */ 9406/* File: armv5te/unused.S */ 9407 bl common_abort 9408 9409 9410/* ------------------------------ */ 9411 .balign 64 9412.L_OP_UNUSED_47FF: /* 0x147 */ 9413/* File: armv5te/OP_UNUSED_47FF.S */ 9414/* File: armv5te/unused.S */ 9415 bl common_abort 9416 9417 9418/* ------------------------------ */ 9419 .balign 64 9420.L_OP_UNUSED_48FF: /* 0x148 */ 9421/* File: armv5te/OP_UNUSED_48FF.S */ 9422/* File: armv5te/unused.S */ 9423 bl common_abort 9424 9425 9426/* ------------------------------ */ 9427 .balign 64 9428.L_OP_UNUSED_49FF: /* 0x149 */ 9429/* File: armv5te/OP_UNUSED_49FF.S */ 9430/* File: armv5te/unused.S */ 9431 bl common_abort 9432 9433 9434/* ------------------------------ */ 9435 .balign 64 9436.L_OP_UNUSED_4AFF: /* 0x14a */ 9437/* File: armv5te/OP_UNUSED_4AFF.S */ 9438/* File: armv5te/unused.S */ 9439 bl common_abort 9440 9441 9442/* ------------------------------ */ 9443 .balign 64 9444.L_OP_UNUSED_4BFF: /* 0x14b */ 9445/* File: armv5te/OP_UNUSED_4BFF.S */ 9446/* File: armv5te/unused.S */ 9447 bl common_abort 9448 9449 9450/* ------------------------------ */ 9451 .balign 64 9452.L_OP_UNUSED_4CFF: /* 0x14c */ 9453/* File: armv5te/OP_UNUSED_4CFF.S */ 9454/* File: armv5te/unused.S */ 9455 bl common_abort 9456 9457 9458/* ------------------------------ */ 9459 .balign 64 9460.L_OP_UNUSED_4DFF: /* 0x14d */ 9461/* File: armv5te/OP_UNUSED_4DFF.S */ 9462/* File: armv5te/unused.S */ 9463 bl common_abort 9464 9465 9466/* ------------------------------ */ 9467 .balign 64 9468.L_OP_UNUSED_4EFF: /* 0x14e */ 9469/* File: armv5te/OP_UNUSED_4EFF.S */ 9470/* File: armv5te/unused.S */ 9471 bl common_abort 9472 9473 9474/* ------------------------------ */ 9475 .balign 64 9476.L_OP_UNUSED_4FFF: /* 0x14f */ 9477/* File: armv5te/OP_UNUSED_4FFF.S */ 9478/* File: armv5te/unused.S */ 9479 bl common_abort 9480 9481 9482/* ------------------------------ */ 9483 .balign 64 9484.L_OP_UNUSED_50FF: /* 0x150 */ 9485/* File: armv5te/OP_UNUSED_50FF.S */ 9486/* File: armv5te/unused.S */ 9487 bl common_abort 9488 9489 9490/* ------------------------------ */ 9491 .balign 64 9492.L_OP_UNUSED_51FF: /* 0x151 */ 9493/* File: armv5te/OP_UNUSED_51FF.S */ 9494/* File: armv5te/unused.S */ 9495 bl common_abort 9496 9497 9498/* ------------------------------ */ 9499 .balign 64 9500.L_OP_UNUSED_52FF: /* 0x152 */ 9501/* File: armv5te/OP_UNUSED_52FF.S */ 9502/* File: armv5te/unused.S */ 9503 bl common_abort 9504 9505 9506/* ------------------------------ */ 9507 .balign 64 9508.L_OP_UNUSED_53FF: /* 0x153 */ 9509/* File: armv5te/OP_UNUSED_53FF.S */ 9510/* File: armv5te/unused.S */ 9511 bl common_abort 9512 9513 9514/* ------------------------------ */ 9515 .balign 64 9516.L_OP_UNUSED_54FF: /* 0x154 */ 9517/* File: armv5te/OP_UNUSED_54FF.S */ 9518/* File: armv5te/unused.S */ 9519 bl common_abort 9520 9521 9522/* ------------------------------ */ 9523 .balign 64 9524.L_OP_UNUSED_55FF: /* 0x155 */ 9525/* File: armv5te/OP_UNUSED_55FF.S */ 9526/* File: armv5te/unused.S */ 9527 bl common_abort 9528 9529 9530/* ------------------------------ */ 9531 .balign 64 9532.L_OP_UNUSED_56FF: /* 0x156 */ 9533/* File: armv5te/OP_UNUSED_56FF.S */ 9534/* File: armv5te/unused.S */ 9535 bl common_abort 9536 9537 9538/* ------------------------------ */ 9539 .balign 64 9540.L_OP_UNUSED_57FF: /* 0x157 */ 9541/* File: armv5te/OP_UNUSED_57FF.S */ 9542/* File: armv5te/unused.S */ 9543 bl common_abort 9544 9545 9546/* ------------------------------ */ 9547 .balign 64 9548.L_OP_UNUSED_58FF: /* 0x158 */ 9549/* File: armv5te/OP_UNUSED_58FF.S */ 9550/* File: armv5te/unused.S */ 9551 bl common_abort 9552 9553 9554/* ------------------------------ */ 9555 .balign 64 9556.L_OP_UNUSED_59FF: /* 0x159 */ 9557/* File: armv5te/OP_UNUSED_59FF.S */ 9558/* File: armv5te/unused.S */ 9559 bl common_abort 9560 9561 9562/* ------------------------------ */ 9563 .balign 64 9564.L_OP_UNUSED_5AFF: /* 0x15a */ 9565/* File: armv5te/OP_UNUSED_5AFF.S */ 9566/* File: armv5te/unused.S */ 9567 bl common_abort 9568 9569 9570/* ------------------------------ */ 9571 .balign 64 9572.L_OP_UNUSED_5BFF: /* 0x15b */ 9573/* File: armv5te/OP_UNUSED_5BFF.S */ 9574/* File: armv5te/unused.S */ 9575 bl common_abort 9576 9577 9578/* ------------------------------ */ 9579 .balign 64 9580.L_OP_UNUSED_5CFF: /* 0x15c */ 9581/* File: armv5te/OP_UNUSED_5CFF.S */ 9582/* File: armv5te/unused.S */ 9583 bl common_abort 9584 9585 9586/* ------------------------------ */ 9587 .balign 64 9588.L_OP_UNUSED_5DFF: /* 0x15d */ 9589/* File: armv5te/OP_UNUSED_5DFF.S */ 9590/* File: armv5te/unused.S */ 9591 bl common_abort 9592 9593 9594/* ------------------------------ */ 9595 .balign 64 9596.L_OP_UNUSED_5EFF: /* 0x15e */ 9597/* File: armv5te/OP_UNUSED_5EFF.S */ 9598/* File: armv5te/unused.S */ 9599 bl common_abort 9600 9601 9602/* ------------------------------ */ 9603 .balign 64 9604.L_OP_UNUSED_5FFF: /* 0x15f */ 9605/* File: armv5te/OP_UNUSED_5FFF.S */ 9606/* File: armv5te/unused.S */ 9607 bl common_abort 9608 9609 9610/* ------------------------------ */ 9611 .balign 64 9612.L_OP_UNUSED_60FF: /* 0x160 */ 9613/* File: armv5te/OP_UNUSED_60FF.S */ 9614/* File: armv5te/unused.S */ 9615 bl common_abort 9616 9617 9618/* ------------------------------ */ 9619 .balign 64 9620.L_OP_UNUSED_61FF: /* 0x161 */ 9621/* File: armv5te/OP_UNUSED_61FF.S */ 9622/* File: armv5te/unused.S */ 9623 bl common_abort 9624 9625 9626/* ------------------------------ */ 9627 .balign 64 9628.L_OP_UNUSED_62FF: /* 0x162 */ 9629/* File: armv5te/OP_UNUSED_62FF.S */ 9630/* File: armv5te/unused.S */ 9631 bl common_abort 9632 9633 9634/* ------------------------------ */ 9635 .balign 64 9636.L_OP_UNUSED_63FF: /* 0x163 */ 9637/* File: armv5te/OP_UNUSED_63FF.S */ 9638/* File: armv5te/unused.S */ 9639 bl common_abort 9640 9641 9642/* ------------------------------ */ 9643 .balign 64 9644.L_OP_UNUSED_64FF: /* 0x164 */ 9645/* File: armv5te/OP_UNUSED_64FF.S */ 9646/* File: armv5te/unused.S */ 9647 bl common_abort 9648 9649 9650/* ------------------------------ */ 9651 .balign 64 9652.L_OP_UNUSED_65FF: /* 0x165 */ 9653/* File: armv5te/OP_UNUSED_65FF.S */ 9654/* File: armv5te/unused.S */ 9655 bl common_abort 9656 9657 9658/* ------------------------------ */ 9659 .balign 64 9660.L_OP_UNUSED_66FF: /* 0x166 */ 9661/* File: armv5te/OP_UNUSED_66FF.S */ 9662/* File: armv5te/unused.S */ 9663 bl common_abort 9664 9665 9666/* ------------------------------ */ 9667 .balign 64 9668.L_OP_UNUSED_67FF: /* 0x167 */ 9669/* File: armv5te/OP_UNUSED_67FF.S */ 9670/* File: armv5te/unused.S */ 9671 bl common_abort 9672 9673 9674/* ------------------------------ */ 9675 .balign 64 9676.L_OP_UNUSED_68FF: /* 0x168 */ 9677/* File: armv5te/OP_UNUSED_68FF.S */ 9678/* File: armv5te/unused.S */ 9679 bl common_abort 9680 9681 9682/* ------------------------------ */ 9683 .balign 64 9684.L_OP_UNUSED_69FF: /* 0x169 */ 9685/* File: armv5te/OP_UNUSED_69FF.S */ 9686/* File: armv5te/unused.S */ 9687 bl common_abort 9688 9689 9690/* ------------------------------ */ 9691 .balign 64 9692.L_OP_UNUSED_6AFF: /* 0x16a */ 9693/* File: armv5te/OP_UNUSED_6AFF.S */ 9694/* File: armv5te/unused.S */ 9695 bl common_abort 9696 9697 9698/* ------------------------------ */ 9699 .balign 64 9700.L_OP_UNUSED_6BFF: /* 0x16b */ 9701/* File: armv5te/OP_UNUSED_6BFF.S */ 9702/* File: armv5te/unused.S */ 9703 bl common_abort 9704 9705 9706/* ------------------------------ */ 9707 .balign 64 9708.L_OP_UNUSED_6CFF: /* 0x16c */ 9709/* File: armv5te/OP_UNUSED_6CFF.S */ 9710/* File: armv5te/unused.S */ 9711 bl common_abort 9712 9713 9714/* ------------------------------ */ 9715 .balign 64 9716.L_OP_UNUSED_6DFF: /* 0x16d */ 9717/* File: armv5te/OP_UNUSED_6DFF.S */ 9718/* File: armv5te/unused.S */ 9719 bl common_abort 9720 9721 9722/* ------------------------------ */ 9723 .balign 64 9724.L_OP_UNUSED_6EFF: /* 0x16e */ 9725/* File: armv5te/OP_UNUSED_6EFF.S */ 9726/* File: armv5te/unused.S */ 9727 bl common_abort 9728 9729 9730/* ------------------------------ */ 9731 .balign 64 9732.L_OP_UNUSED_6FFF: /* 0x16f */ 9733/* File: armv5te/OP_UNUSED_6FFF.S */ 9734/* File: armv5te/unused.S */ 9735 bl common_abort 9736 9737 9738/* ------------------------------ */ 9739 .balign 64 9740.L_OP_UNUSED_70FF: /* 0x170 */ 9741/* File: armv5te/OP_UNUSED_70FF.S */ 9742/* File: armv5te/unused.S */ 9743 bl common_abort 9744 9745 9746/* ------------------------------ */ 9747 .balign 64 9748.L_OP_UNUSED_71FF: /* 0x171 */ 9749/* File: armv5te/OP_UNUSED_71FF.S */ 9750/* File: armv5te/unused.S */ 9751 bl common_abort 9752 9753 9754/* ------------------------------ */ 9755 .balign 64 9756.L_OP_UNUSED_72FF: /* 0x172 */ 9757/* File: armv5te/OP_UNUSED_72FF.S */ 9758/* File: armv5te/unused.S */ 9759 bl common_abort 9760 9761 9762/* ------------------------------ */ 9763 .balign 64 9764.L_OP_UNUSED_73FF: /* 0x173 */ 9765/* File: armv5te/OP_UNUSED_73FF.S */ 9766/* File: armv5te/unused.S */ 9767 bl common_abort 9768 9769 9770/* ------------------------------ */ 9771 .balign 64 9772.L_OP_UNUSED_74FF: /* 0x174 */ 9773/* File: armv5te/OP_UNUSED_74FF.S */ 9774/* File: armv5te/unused.S */ 9775 bl common_abort 9776 9777 9778/* ------------------------------ */ 9779 .balign 64 9780.L_OP_UNUSED_75FF: /* 0x175 */ 9781/* File: armv5te/OP_UNUSED_75FF.S */ 9782/* File: armv5te/unused.S */ 9783 bl common_abort 9784 9785 9786/* ------------------------------ */ 9787 .balign 64 9788.L_OP_UNUSED_76FF: /* 0x176 */ 9789/* File: armv5te/OP_UNUSED_76FF.S */ 9790/* File: armv5te/unused.S */ 9791 bl common_abort 9792 9793 9794/* ------------------------------ */ 9795 .balign 64 9796.L_OP_UNUSED_77FF: /* 0x177 */ 9797/* File: armv5te/OP_UNUSED_77FF.S */ 9798/* File: armv5te/unused.S */ 9799 bl common_abort 9800 9801 9802/* ------------------------------ */ 9803 .balign 64 9804.L_OP_UNUSED_78FF: /* 0x178 */ 9805/* File: armv5te/OP_UNUSED_78FF.S */ 9806/* File: armv5te/unused.S */ 9807 bl common_abort 9808 9809 9810/* ------------------------------ */ 9811 .balign 64 9812.L_OP_UNUSED_79FF: /* 0x179 */ 9813/* File: armv5te/OP_UNUSED_79FF.S */ 9814/* File: armv5te/unused.S */ 9815 bl common_abort 9816 9817 9818/* ------------------------------ */ 9819 .balign 64 9820.L_OP_UNUSED_7AFF: /* 0x17a */ 9821/* File: armv5te/OP_UNUSED_7AFF.S */ 9822/* File: armv5te/unused.S */ 9823 bl common_abort 9824 9825 9826/* ------------------------------ */ 9827 .balign 64 9828.L_OP_UNUSED_7BFF: /* 0x17b */ 9829/* File: armv5te/OP_UNUSED_7BFF.S */ 9830/* File: armv5te/unused.S */ 9831 bl common_abort 9832 9833 9834/* ------------------------------ */ 9835 .balign 64 9836.L_OP_UNUSED_7CFF: /* 0x17c */ 9837/* File: armv5te/OP_UNUSED_7CFF.S */ 9838/* File: armv5te/unused.S */ 9839 bl common_abort 9840 9841 9842/* ------------------------------ */ 9843 .balign 64 9844.L_OP_UNUSED_7DFF: /* 0x17d */ 9845/* File: armv5te/OP_UNUSED_7DFF.S */ 9846/* File: armv5te/unused.S */ 9847 bl common_abort 9848 9849 9850/* ------------------------------ */ 9851 .balign 64 9852.L_OP_UNUSED_7EFF: /* 0x17e */ 9853/* File: armv5te/OP_UNUSED_7EFF.S */ 9854/* File: armv5te/unused.S */ 9855 bl common_abort 9856 9857 9858/* ------------------------------ */ 9859 .balign 64 9860.L_OP_UNUSED_7FFF: /* 0x17f */ 9861/* File: armv5te/OP_UNUSED_7FFF.S */ 9862/* File: armv5te/unused.S */ 9863 bl common_abort 9864 9865 9866/* ------------------------------ */ 9867 .balign 64 9868.L_OP_UNUSED_80FF: /* 0x180 */ 9869/* File: armv5te/OP_UNUSED_80FF.S */ 9870/* File: armv5te/unused.S */ 9871 bl common_abort 9872 9873 9874/* ------------------------------ */ 9875 .balign 64 9876.L_OP_UNUSED_81FF: /* 0x181 */ 9877/* File: armv5te/OP_UNUSED_81FF.S */ 9878/* File: armv5te/unused.S */ 9879 bl common_abort 9880 9881 9882/* ------------------------------ */ 9883 .balign 64 9884.L_OP_UNUSED_82FF: /* 0x182 */ 9885/* File: armv5te/OP_UNUSED_82FF.S */ 9886/* File: armv5te/unused.S */ 9887 bl common_abort 9888 9889 9890/* ------------------------------ */ 9891 .balign 64 9892.L_OP_UNUSED_83FF: /* 0x183 */ 9893/* File: armv5te/OP_UNUSED_83FF.S */ 9894/* File: armv5te/unused.S */ 9895 bl common_abort 9896 9897 9898/* ------------------------------ */ 9899 .balign 64 9900.L_OP_UNUSED_84FF: /* 0x184 */ 9901/* File: armv5te/OP_UNUSED_84FF.S */ 9902/* File: armv5te/unused.S */ 9903 bl common_abort 9904 9905 9906/* ------------------------------ */ 9907 .balign 64 9908.L_OP_UNUSED_85FF: /* 0x185 */ 9909/* File: armv5te/OP_UNUSED_85FF.S */ 9910/* File: armv5te/unused.S */ 9911 bl common_abort 9912 9913 9914/* ------------------------------ */ 9915 .balign 64 9916.L_OP_UNUSED_86FF: /* 0x186 */ 9917/* File: armv5te/OP_UNUSED_86FF.S */ 9918/* File: armv5te/unused.S */ 9919 bl common_abort 9920 9921 9922/* ------------------------------ */ 9923 .balign 64 9924.L_OP_UNUSED_87FF: /* 0x187 */ 9925/* File: armv5te/OP_UNUSED_87FF.S */ 9926/* File: armv5te/unused.S */ 9927 bl common_abort 9928 9929 9930/* ------------------------------ */ 9931 .balign 64 9932.L_OP_UNUSED_88FF: /* 0x188 */ 9933/* File: armv5te/OP_UNUSED_88FF.S */ 9934/* File: armv5te/unused.S */ 9935 bl common_abort 9936 9937 9938/* ------------------------------ */ 9939 .balign 64 9940.L_OP_UNUSED_89FF: /* 0x189 */ 9941/* File: armv5te/OP_UNUSED_89FF.S */ 9942/* File: armv5te/unused.S */ 9943 bl common_abort 9944 9945 9946/* ------------------------------ */ 9947 .balign 64 9948.L_OP_UNUSED_8AFF: /* 0x18a */ 9949/* File: armv5te/OP_UNUSED_8AFF.S */ 9950/* File: armv5te/unused.S */ 9951 bl common_abort 9952 9953 9954/* ------------------------------ */ 9955 .balign 64 9956.L_OP_UNUSED_8BFF: /* 0x18b */ 9957/* File: armv5te/OP_UNUSED_8BFF.S */ 9958/* File: armv5te/unused.S */ 9959 bl common_abort 9960 9961 9962/* ------------------------------ */ 9963 .balign 64 9964.L_OP_UNUSED_8CFF: /* 0x18c */ 9965/* File: armv5te/OP_UNUSED_8CFF.S */ 9966/* File: armv5te/unused.S */ 9967 bl common_abort 9968 9969 9970/* ------------------------------ */ 9971 .balign 64 9972.L_OP_UNUSED_8DFF: /* 0x18d */ 9973/* File: armv5te/OP_UNUSED_8DFF.S */ 9974/* File: armv5te/unused.S */ 9975 bl common_abort 9976 9977 9978/* ------------------------------ */ 9979 .balign 64 9980.L_OP_UNUSED_8EFF: /* 0x18e */ 9981/* File: armv5te/OP_UNUSED_8EFF.S */ 9982/* File: armv5te/unused.S */ 9983 bl common_abort 9984 9985 9986/* ------------------------------ */ 9987 .balign 64 9988.L_OP_UNUSED_8FFF: /* 0x18f */ 9989/* File: armv5te/OP_UNUSED_8FFF.S */ 9990/* File: armv5te/unused.S */ 9991 bl common_abort 9992 9993 9994/* ------------------------------ */ 9995 .balign 64 9996.L_OP_UNUSED_90FF: /* 0x190 */ 9997/* File: armv5te/OP_UNUSED_90FF.S */ 9998/* File: armv5te/unused.S */ 9999 bl common_abort 10000 10001 10002/* ------------------------------ */ 10003 .balign 64 10004.L_OP_UNUSED_91FF: /* 0x191 */ 10005/* File: armv5te/OP_UNUSED_91FF.S */ 10006/* File: armv5te/unused.S */ 10007 bl common_abort 10008 10009 10010/* ------------------------------ */ 10011 .balign 64 10012.L_OP_UNUSED_92FF: /* 0x192 */ 10013/* File: armv5te/OP_UNUSED_92FF.S */ 10014/* File: armv5te/unused.S */ 10015 bl common_abort 10016 10017 10018/* ------------------------------ */ 10019 .balign 64 10020.L_OP_UNUSED_93FF: /* 0x193 */ 10021/* File: armv5te/OP_UNUSED_93FF.S */ 10022/* File: armv5te/unused.S */ 10023 bl common_abort 10024 10025 10026/* ------------------------------ */ 10027 .balign 64 10028.L_OP_UNUSED_94FF: /* 0x194 */ 10029/* File: armv5te/OP_UNUSED_94FF.S */ 10030/* File: armv5te/unused.S */ 10031 bl common_abort 10032 10033 10034/* ------------------------------ */ 10035 .balign 64 10036.L_OP_UNUSED_95FF: /* 0x195 */ 10037/* File: armv5te/OP_UNUSED_95FF.S */ 10038/* File: armv5te/unused.S */ 10039 bl common_abort 10040 10041 10042/* ------------------------------ */ 10043 .balign 64 10044.L_OP_UNUSED_96FF: /* 0x196 */ 10045/* File: armv5te/OP_UNUSED_96FF.S */ 10046/* File: armv5te/unused.S */ 10047 bl common_abort 10048 10049 10050/* ------------------------------ */ 10051 .balign 64 10052.L_OP_UNUSED_97FF: /* 0x197 */ 10053/* File: armv5te/OP_UNUSED_97FF.S */ 10054/* File: armv5te/unused.S */ 10055 bl common_abort 10056 10057 10058/* ------------------------------ */ 10059 .balign 64 10060.L_OP_UNUSED_98FF: /* 0x198 */ 10061/* File: armv5te/OP_UNUSED_98FF.S */ 10062/* File: armv5te/unused.S */ 10063 bl common_abort 10064 10065 10066/* ------------------------------ */ 10067 .balign 64 10068.L_OP_UNUSED_99FF: /* 0x199 */ 10069/* File: armv5te/OP_UNUSED_99FF.S */ 10070/* File: armv5te/unused.S */ 10071 bl common_abort 10072 10073 10074/* ------------------------------ */ 10075 .balign 64 10076.L_OP_UNUSED_9AFF: /* 0x19a */ 10077/* File: armv5te/OP_UNUSED_9AFF.S */ 10078/* File: armv5te/unused.S */ 10079 bl common_abort 10080 10081 10082/* ------------------------------ */ 10083 .balign 64 10084.L_OP_UNUSED_9BFF: /* 0x19b */ 10085/* File: armv5te/OP_UNUSED_9BFF.S */ 10086/* File: armv5te/unused.S */ 10087 bl common_abort 10088 10089 10090/* ------------------------------ */ 10091 .balign 64 10092.L_OP_UNUSED_9CFF: /* 0x19c */ 10093/* File: armv5te/OP_UNUSED_9CFF.S */ 10094/* File: armv5te/unused.S */ 10095 bl common_abort 10096 10097 10098/* ------------------------------ */ 10099 .balign 64 10100.L_OP_UNUSED_9DFF: /* 0x19d */ 10101/* File: armv5te/OP_UNUSED_9DFF.S */ 10102/* File: armv5te/unused.S */ 10103 bl common_abort 10104 10105 10106/* ------------------------------ */ 10107 .balign 64 10108.L_OP_UNUSED_9EFF: /* 0x19e */ 10109/* File: armv5te/OP_UNUSED_9EFF.S */ 10110/* File: armv5te/unused.S */ 10111 bl common_abort 10112 10113 10114/* ------------------------------ */ 10115 .balign 64 10116.L_OP_UNUSED_9FFF: /* 0x19f */ 10117/* File: armv5te/OP_UNUSED_9FFF.S */ 10118/* File: armv5te/unused.S */ 10119 bl common_abort 10120 10121 10122/* ------------------------------ */ 10123 .balign 64 10124.L_OP_UNUSED_A0FF: /* 0x1a0 */ 10125/* File: armv5te/OP_UNUSED_A0FF.S */ 10126/* File: armv5te/unused.S */ 10127 bl common_abort 10128 10129 10130/* ------------------------------ */ 10131 .balign 64 10132.L_OP_UNUSED_A1FF: /* 0x1a1 */ 10133/* File: armv5te/OP_UNUSED_A1FF.S */ 10134/* File: armv5te/unused.S */ 10135 bl common_abort 10136 10137 10138/* ------------------------------ */ 10139 .balign 64 10140.L_OP_UNUSED_A2FF: /* 0x1a2 */ 10141/* File: armv5te/OP_UNUSED_A2FF.S */ 10142/* File: armv5te/unused.S */ 10143 bl common_abort 10144 10145 10146/* ------------------------------ */ 10147 .balign 64 10148.L_OP_UNUSED_A3FF: /* 0x1a3 */ 10149/* File: armv5te/OP_UNUSED_A3FF.S */ 10150/* File: armv5te/unused.S */ 10151 bl common_abort 10152 10153 10154/* ------------------------------ */ 10155 .balign 64 10156.L_OP_UNUSED_A4FF: /* 0x1a4 */ 10157/* File: armv5te/OP_UNUSED_A4FF.S */ 10158/* File: armv5te/unused.S */ 10159 bl common_abort 10160 10161 10162/* ------------------------------ */ 10163 .balign 64 10164.L_OP_UNUSED_A5FF: /* 0x1a5 */ 10165/* File: armv5te/OP_UNUSED_A5FF.S */ 10166/* File: armv5te/unused.S */ 10167 bl common_abort 10168 10169 10170/* ------------------------------ */ 10171 .balign 64 10172.L_OP_UNUSED_A6FF: /* 0x1a6 */ 10173/* File: armv5te/OP_UNUSED_A6FF.S */ 10174/* File: armv5te/unused.S */ 10175 bl common_abort 10176 10177 10178/* ------------------------------ */ 10179 .balign 64 10180.L_OP_UNUSED_A7FF: /* 0x1a7 */ 10181/* File: armv5te/OP_UNUSED_A7FF.S */ 10182/* File: armv5te/unused.S */ 10183 bl common_abort 10184 10185 10186/* ------------------------------ */ 10187 .balign 64 10188.L_OP_UNUSED_A8FF: /* 0x1a8 */ 10189/* File: armv5te/OP_UNUSED_A8FF.S */ 10190/* File: armv5te/unused.S */ 10191 bl common_abort 10192 10193 10194/* ------------------------------ */ 10195 .balign 64 10196.L_OP_UNUSED_A9FF: /* 0x1a9 */ 10197/* File: armv5te/OP_UNUSED_A9FF.S */ 10198/* File: armv5te/unused.S */ 10199 bl common_abort 10200 10201 10202/* ------------------------------ */ 10203 .balign 64 10204.L_OP_UNUSED_AAFF: /* 0x1aa */ 10205/* File: armv5te/OP_UNUSED_AAFF.S */ 10206/* File: armv5te/unused.S */ 10207 bl common_abort 10208 10209 10210/* ------------------------------ */ 10211 .balign 64 10212.L_OP_UNUSED_ABFF: /* 0x1ab */ 10213/* File: armv5te/OP_UNUSED_ABFF.S */ 10214/* File: armv5te/unused.S */ 10215 bl common_abort 10216 10217 10218/* ------------------------------ */ 10219 .balign 64 10220.L_OP_UNUSED_ACFF: /* 0x1ac */ 10221/* File: armv5te/OP_UNUSED_ACFF.S */ 10222/* File: armv5te/unused.S */ 10223 bl common_abort 10224 10225 10226/* ------------------------------ */ 10227 .balign 64 10228.L_OP_UNUSED_ADFF: /* 0x1ad */ 10229/* File: armv5te/OP_UNUSED_ADFF.S */ 10230/* File: armv5te/unused.S */ 10231 bl common_abort 10232 10233 10234/* ------------------------------ */ 10235 .balign 64 10236.L_OP_UNUSED_AEFF: /* 0x1ae */ 10237/* File: armv5te/OP_UNUSED_AEFF.S */ 10238/* File: armv5te/unused.S */ 10239 bl common_abort 10240 10241 10242/* ------------------------------ */ 10243 .balign 64 10244.L_OP_UNUSED_AFFF: /* 0x1af */ 10245/* File: armv5te/OP_UNUSED_AFFF.S */ 10246/* File: armv5te/unused.S */ 10247 bl common_abort 10248 10249 10250/* ------------------------------ */ 10251 .balign 64 10252.L_OP_UNUSED_B0FF: /* 0x1b0 */ 10253/* File: armv5te/OP_UNUSED_B0FF.S */ 10254/* File: armv5te/unused.S */ 10255 bl common_abort 10256 10257 10258/* ------------------------------ */ 10259 .balign 64 10260.L_OP_UNUSED_B1FF: /* 0x1b1 */ 10261/* File: armv5te/OP_UNUSED_B1FF.S */ 10262/* File: armv5te/unused.S */ 10263 bl common_abort 10264 10265 10266/* ------------------------------ */ 10267 .balign 64 10268.L_OP_UNUSED_B2FF: /* 0x1b2 */ 10269/* File: armv5te/OP_UNUSED_B2FF.S */ 10270/* File: armv5te/unused.S */ 10271 bl common_abort 10272 10273 10274/* ------------------------------ */ 10275 .balign 64 10276.L_OP_UNUSED_B3FF: /* 0x1b3 */ 10277/* File: armv5te/OP_UNUSED_B3FF.S */ 10278/* File: armv5te/unused.S */ 10279 bl common_abort 10280 10281 10282/* ------------------------------ */ 10283 .balign 64 10284.L_OP_UNUSED_B4FF: /* 0x1b4 */ 10285/* File: armv5te/OP_UNUSED_B4FF.S */ 10286/* File: armv5te/unused.S */ 10287 bl common_abort 10288 10289 10290/* ------------------------------ */ 10291 .balign 64 10292.L_OP_UNUSED_B5FF: /* 0x1b5 */ 10293/* File: armv5te/OP_UNUSED_B5FF.S */ 10294/* File: armv5te/unused.S */ 10295 bl common_abort 10296 10297 10298/* ------------------------------ */ 10299 .balign 64 10300.L_OP_UNUSED_B6FF: /* 0x1b6 */ 10301/* File: armv5te/OP_UNUSED_B6FF.S */ 10302/* File: armv5te/unused.S */ 10303 bl common_abort 10304 10305 10306/* ------------------------------ */ 10307 .balign 64 10308.L_OP_UNUSED_B7FF: /* 0x1b7 */ 10309/* File: armv5te/OP_UNUSED_B7FF.S */ 10310/* File: armv5te/unused.S */ 10311 bl common_abort 10312 10313 10314/* ------------------------------ */ 10315 .balign 64 10316.L_OP_UNUSED_B8FF: /* 0x1b8 */ 10317/* File: armv5te/OP_UNUSED_B8FF.S */ 10318/* File: armv5te/unused.S */ 10319 bl common_abort 10320 10321 10322/* ------------------------------ */ 10323 .balign 64 10324.L_OP_UNUSED_B9FF: /* 0x1b9 */ 10325/* File: armv5te/OP_UNUSED_B9FF.S */ 10326/* File: armv5te/unused.S */ 10327 bl common_abort 10328 10329 10330/* ------------------------------ */ 10331 .balign 64 10332.L_OP_UNUSED_BAFF: /* 0x1ba */ 10333/* File: armv5te/OP_UNUSED_BAFF.S */ 10334/* File: armv5te/unused.S */ 10335 bl common_abort 10336 10337 10338/* ------------------------------ */ 10339 .balign 64 10340.L_OP_UNUSED_BBFF: /* 0x1bb */ 10341/* File: armv5te/OP_UNUSED_BBFF.S */ 10342/* File: armv5te/unused.S */ 10343 bl common_abort 10344 10345 10346/* ------------------------------ */ 10347 .balign 64 10348.L_OP_UNUSED_BCFF: /* 0x1bc */ 10349/* File: armv5te/OP_UNUSED_BCFF.S */ 10350/* File: armv5te/unused.S */ 10351 bl common_abort 10352 10353 10354/* ------------------------------ */ 10355 .balign 64 10356.L_OP_UNUSED_BDFF: /* 0x1bd */ 10357/* File: armv5te/OP_UNUSED_BDFF.S */ 10358/* File: armv5te/unused.S */ 10359 bl common_abort 10360 10361 10362/* ------------------------------ */ 10363 .balign 64 10364.L_OP_UNUSED_BEFF: /* 0x1be */ 10365/* File: armv5te/OP_UNUSED_BEFF.S */ 10366/* File: armv5te/unused.S */ 10367 bl common_abort 10368 10369 10370/* ------------------------------ */ 10371 .balign 64 10372.L_OP_UNUSED_BFFF: /* 0x1bf */ 10373/* File: armv5te/OP_UNUSED_BFFF.S */ 10374/* File: armv5te/unused.S */ 10375 bl common_abort 10376 10377 10378/* ------------------------------ */ 10379 .balign 64 10380.L_OP_UNUSED_C0FF: /* 0x1c0 */ 10381/* File: armv5te/OP_UNUSED_C0FF.S */ 10382/* File: armv5te/unused.S */ 10383 bl common_abort 10384 10385 10386/* ------------------------------ */ 10387 .balign 64 10388.L_OP_UNUSED_C1FF: /* 0x1c1 */ 10389/* File: armv5te/OP_UNUSED_C1FF.S */ 10390/* File: armv5te/unused.S */ 10391 bl common_abort 10392 10393 10394/* ------------------------------ */ 10395 .balign 64 10396.L_OP_UNUSED_C2FF: /* 0x1c2 */ 10397/* File: armv5te/OP_UNUSED_C2FF.S */ 10398/* File: armv5te/unused.S */ 10399 bl common_abort 10400 10401 10402/* ------------------------------ */ 10403 .balign 64 10404.L_OP_UNUSED_C3FF: /* 0x1c3 */ 10405/* File: armv5te/OP_UNUSED_C3FF.S */ 10406/* File: armv5te/unused.S */ 10407 bl common_abort 10408 10409 10410/* ------------------------------ */ 10411 .balign 64 10412.L_OP_UNUSED_C4FF: /* 0x1c4 */ 10413/* File: armv5te/OP_UNUSED_C4FF.S */ 10414/* File: armv5te/unused.S */ 10415 bl common_abort 10416 10417 10418/* ------------------------------ */ 10419 .balign 64 10420.L_OP_UNUSED_C5FF: /* 0x1c5 */ 10421/* File: armv5te/OP_UNUSED_C5FF.S */ 10422/* File: armv5te/unused.S */ 10423 bl common_abort 10424 10425 10426/* ------------------------------ */ 10427 .balign 64 10428.L_OP_UNUSED_C6FF: /* 0x1c6 */ 10429/* File: armv5te/OP_UNUSED_C6FF.S */ 10430/* File: armv5te/unused.S */ 10431 bl common_abort 10432 10433 10434/* ------------------------------ */ 10435 .balign 64 10436.L_OP_UNUSED_C7FF: /* 0x1c7 */ 10437/* File: armv5te/OP_UNUSED_C7FF.S */ 10438/* File: armv5te/unused.S */ 10439 bl common_abort 10440 10441 10442/* ------------------------------ */ 10443 .balign 64 10444.L_OP_UNUSED_C8FF: /* 0x1c8 */ 10445/* File: armv5te/OP_UNUSED_C8FF.S */ 10446/* File: armv5te/unused.S */ 10447 bl common_abort 10448 10449 10450/* ------------------------------ */ 10451 .balign 64 10452.L_OP_UNUSED_C9FF: /* 0x1c9 */ 10453/* File: armv5te/OP_UNUSED_C9FF.S */ 10454/* File: armv5te/unused.S */ 10455 bl common_abort 10456 10457 10458/* ------------------------------ */ 10459 .balign 64 10460.L_OP_UNUSED_CAFF: /* 0x1ca */ 10461/* File: armv5te/OP_UNUSED_CAFF.S */ 10462/* File: armv5te/unused.S */ 10463 bl common_abort 10464 10465 10466/* ------------------------------ */ 10467 .balign 64 10468.L_OP_UNUSED_CBFF: /* 0x1cb */ 10469/* File: armv5te/OP_UNUSED_CBFF.S */ 10470/* File: armv5te/unused.S */ 10471 bl common_abort 10472 10473 10474/* ------------------------------ */ 10475 .balign 64 10476.L_OP_UNUSED_CCFF: /* 0x1cc */ 10477/* File: armv5te/OP_UNUSED_CCFF.S */ 10478/* File: armv5te/unused.S */ 10479 bl common_abort 10480 10481 10482/* ------------------------------ */ 10483 .balign 64 10484.L_OP_UNUSED_CDFF: /* 0x1cd */ 10485/* File: armv5te/OP_UNUSED_CDFF.S */ 10486/* File: armv5te/unused.S */ 10487 bl common_abort 10488 10489 10490/* ------------------------------ */ 10491 .balign 64 10492.L_OP_UNUSED_CEFF: /* 0x1ce */ 10493/* File: armv5te/OP_UNUSED_CEFF.S */ 10494/* File: armv5te/unused.S */ 10495 bl common_abort 10496 10497 10498/* ------------------------------ */ 10499 .balign 64 10500.L_OP_UNUSED_CFFF: /* 0x1cf */ 10501/* File: armv5te/OP_UNUSED_CFFF.S */ 10502/* File: armv5te/unused.S */ 10503 bl common_abort 10504 10505 10506/* ------------------------------ */ 10507 .balign 64 10508.L_OP_UNUSED_D0FF: /* 0x1d0 */ 10509/* File: armv5te/OP_UNUSED_D0FF.S */ 10510/* File: armv5te/unused.S */ 10511 bl common_abort 10512 10513 10514/* ------------------------------ */ 10515 .balign 64 10516.L_OP_UNUSED_D1FF: /* 0x1d1 */ 10517/* File: armv5te/OP_UNUSED_D1FF.S */ 10518/* File: armv5te/unused.S */ 10519 bl common_abort 10520 10521 10522/* ------------------------------ */ 10523 .balign 64 10524.L_OP_UNUSED_D2FF: /* 0x1d2 */ 10525/* File: armv5te/OP_UNUSED_D2FF.S */ 10526/* File: armv5te/unused.S */ 10527 bl common_abort 10528 10529 10530/* ------------------------------ */ 10531 .balign 64 10532.L_OP_UNUSED_D3FF: /* 0x1d3 */ 10533/* File: armv5te/OP_UNUSED_D3FF.S */ 10534/* File: armv5te/unused.S */ 10535 bl common_abort 10536 10537 10538/* ------------------------------ */ 10539 .balign 64 10540.L_OP_UNUSED_D4FF: /* 0x1d4 */ 10541/* File: armv5te/OP_UNUSED_D4FF.S */ 10542/* File: armv5te/unused.S */ 10543 bl common_abort 10544 10545 10546/* ------------------------------ */ 10547 .balign 64 10548.L_OP_UNUSED_D5FF: /* 0x1d5 */ 10549/* File: armv5te/OP_UNUSED_D5FF.S */ 10550/* File: armv5te/unused.S */ 10551 bl common_abort 10552 10553 10554/* ------------------------------ */ 10555 .balign 64 10556.L_OP_UNUSED_D6FF: /* 0x1d6 */ 10557/* File: armv5te/OP_UNUSED_D6FF.S */ 10558/* File: armv5te/unused.S */ 10559 bl common_abort 10560 10561 10562/* ------------------------------ */ 10563 .balign 64 10564.L_OP_UNUSED_D7FF: /* 0x1d7 */ 10565/* File: armv5te/OP_UNUSED_D7FF.S */ 10566/* File: armv5te/unused.S */ 10567 bl common_abort 10568 10569 10570/* ------------------------------ */ 10571 .balign 64 10572.L_OP_UNUSED_D8FF: /* 0x1d8 */ 10573/* File: armv5te/OP_UNUSED_D8FF.S */ 10574/* File: armv5te/unused.S */ 10575 bl common_abort 10576 10577 10578/* ------------------------------ */ 10579 .balign 64 10580.L_OP_UNUSED_D9FF: /* 0x1d9 */ 10581/* File: armv5te/OP_UNUSED_D9FF.S */ 10582/* File: armv5te/unused.S */ 10583 bl common_abort 10584 10585 10586/* ------------------------------ */ 10587 .balign 64 10588.L_OP_UNUSED_DAFF: /* 0x1da */ 10589/* File: armv5te/OP_UNUSED_DAFF.S */ 10590/* File: armv5te/unused.S */ 10591 bl common_abort 10592 10593 10594/* ------------------------------ */ 10595 .balign 64 10596.L_OP_UNUSED_DBFF: /* 0x1db */ 10597/* File: armv5te/OP_UNUSED_DBFF.S */ 10598/* File: armv5te/unused.S */ 10599 bl common_abort 10600 10601 10602/* ------------------------------ */ 10603 .balign 64 10604.L_OP_UNUSED_DCFF: /* 0x1dc */ 10605/* File: armv5te/OP_UNUSED_DCFF.S */ 10606/* File: armv5te/unused.S */ 10607 bl common_abort 10608 10609 10610/* ------------------------------ */ 10611 .balign 64 10612.L_OP_UNUSED_DDFF: /* 0x1dd */ 10613/* File: armv5te/OP_UNUSED_DDFF.S */ 10614/* File: armv5te/unused.S */ 10615 bl common_abort 10616 10617 10618/* ------------------------------ */ 10619 .balign 64 10620.L_OP_UNUSED_DEFF: /* 0x1de */ 10621/* File: armv5te/OP_UNUSED_DEFF.S */ 10622/* File: armv5te/unused.S */ 10623 bl common_abort 10624 10625 10626/* ------------------------------ */ 10627 .balign 64 10628.L_OP_UNUSED_DFFF: /* 0x1df */ 10629/* File: armv5te/OP_UNUSED_DFFF.S */ 10630/* File: armv5te/unused.S */ 10631 bl common_abort 10632 10633 10634/* ------------------------------ */ 10635 .balign 64 10636.L_OP_UNUSED_E0FF: /* 0x1e0 */ 10637/* File: armv5te/OP_UNUSED_E0FF.S */ 10638/* File: armv5te/unused.S */ 10639 bl common_abort 10640 10641 10642/* ------------------------------ */ 10643 .balign 64 10644.L_OP_UNUSED_E1FF: /* 0x1e1 */ 10645/* File: armv5te/OP_UNUSED_E1FF.S */ 10646/* File: armv5te/unused.S */ 10647 bl common_abort 10648 10649 10650/* ------------------------------ */ 10651 .balign 64 10652.L_OP_UNUSED_E2FF: /* 0x1e2 */ 10653/* File: armv5te/OP_UNUSED_E2FF.S */ 10654/* File: armv5te/unused.S */ 10655 bl common_abort 10656 10657 10658/* ------------------------------ */ 10659 .balign 64 10660.L_OP_UNUSED_E3FF: /* 0x1e3 */ 10661/* File: armv5te/OP_UNUSED_E3FF.S */ 10662/* File: armv5te/unused.S */ 10663 bl common_abort 10664 10665 10666/* ------------------------------ */ 10667 .balign 64 10668.L_OP_UNUSED_E4FF: /* 0x1e4 */ 10669/* File: armv5te/OP_UNUSED_E4FF.S */ 10670/* File: armv5te/unused.S */ 10671 bl common_abort 10672 10673 10674/* ------------------------------ */ 10675 .balign 64 10676.L_OP_UNUSED_E5FF: /* 0x1e5 */ 10677/* File: armv5te/OP_UNUSED_E5FF.S */ 10678/* File: armv5te/unused.S */ 10679 bl common_abort 10680 10681 10682/* ------------------------------ */ 10683 .balign 64 10684.L_OP_UNUSED_E6FF: /* 0x1e6 */ 10685/* File: armv5te/OP_UNUSED_E6FF.S */ 10686/* File: armv5te/unused.S */ 10687 bl common_abort 10688 10689 10690/* ------------------------------ */ 10691 .balign 64 10692.L_OP_UNUSED_E7FF: /* 0x1e7 */ 10693/* File: armv5te/OP_UNUSED_E7FF.S */ 10694/* File: armv5te/unused.S */ 10695 bl common_abort 10696 10697 10698/* ------------------------------ */ 10699 .balign 64 10700.L_OP_UNUSED_E8FF: /* 0x1e8 */ 10701/* File: armv5te/OP_UNUSED_E8FF.S */ 10702/* File: armv5te/unused.S */ 10703 bl common_abort 10704 10705 10706/* ------------------------------ */ 10707 .balign 64 10708.L_OP_UNUSED_E9FF: /* 0x1e9 */ 10709/* File: armv5te/OP_UNUSED_E9FF.S */ 10710/* File: armv5te/unused.S */ 10711 bl common_abort 10712 10713 10714/* ------------------------------ */ 10715 .balign 64 10716.L_OP_UNUSED_EAFF: /* 0x1ea */ 10717/* File: armv5te/OP_UNUSED_EAFF.S */ 10718/* File: armv5te/unused.S */ 10719 bl common_abort 10720 10721 10722/* ------------------------------ */ 10723 .balign 64 10724.L_OP_UNUSED_EBFF: /* 0x1eb */ 10725/* File: armv5te/OP_UNUSED_EBFF.S */ 10726/* File: armv5te/unused.S */ 10727 bl common_abort 10728 10729 10730/* ------------------------------ */ 10731 .balign 64 10732.L_OP_UNUSED_ECFF: /* 0x1ec */ 10733/* File: armv5te/OP_UNUSED_ECFF.S */ 10734/* File: armv5te/unused.S */ 10735 bl common_abort 10736 10737 10738/* ------------------------------ */ 10739 .balign 64 10740.L_OP_UNUSED_EDFF: /* 0x1ed */ 10741/* File: armv5te/OP_UNUSED_EDFF.S */ 10742/* File: armv5te/unused.S */ 10743 bl common_abort 10744 10745 10746/* ------------------------------ */ 10747 .balign 64 10748.L_OP_UNUSED_EEFF: /* 0x1ee */ 10749/* File: armv5te/OP_UNUSED_EEFF.S */ 10750/* File: armv5te/unused.S */ 10751 bl common_abort 10752 10753 10754/* ------------------------------ */ 10755 .balign 64 10756.L_OP_UNUSED_EFFF: /* 0x1ef */ 10757/* File: armv5te/OP_UNUSED_EFFF.S */ 10758/* File: armv5te/unused.S */ 10759 bl common_abort 10760 10761 10762/* ------------------------------ */ 10763 .balign 64 10764.L_OP_UNUSED_F0FF: /* 0x1f0 */ 10765/* File: armv5te/OP_UNUSED_F0FF.S */ 10766/* File: armv5te/unused.S */ 10767 bl common_abort 10768 10769 10770/* ------------------------------ */ 10771 .balign 64 10772.L_OP_UNUSED_F1FF: /* 0x1f1 */ 10773/* File: armv5te/OP_UNUSED_F1FF.S */ 10774/* File: armv5te/unused.S */ 10775 bl common_abort 10776 10777 10778/* ------------------------------ */ 10779 .balign 64 10780.L_OP_UNUSED_F2FF: /* 0x1f2 */ 10781/* File: armv5te/OP_UNUSED_F2FF.S */ 10782/* File: armv5te/unused.S */ 10783 bl common_abort 10784 10785 10786/* ------------------------------ */ 10787 .balign 64 10788.L_OP_UNUSED_F3FF: /* 0x1f3 */ 10789/* File: armv5te/OP_UNUSED_F3FF.S */ 10790/* File: armv5te/unused.S */ 10791 bl common_abort 10792 10793 10794/* ------------------------------ */ 10795 .balign 64 10796.L_OP_UNUSED_F4FF: /* 0x1f4 */ 10797/* File: armv5te/OP_UNUSED_F4FF.S */ 10798/* File: armv5te/unused.S */ 10799 bl common_abort 10800 10801 10802/* ------------------------------ */ 10803 .balign 64 10804.L_OP_UNUSED_F5FF: /* 0x1f5 */ 10805/* File: armv5te/OP_UNUSED_F5FF.S */ 10806/* File: armv5te/unused.S */ 10807 bl common_abort 10808 10809 10810/* ------------------------------ */ 10811 .balign 64 10812.L_OP_UNUSED_F6FF: /* 0x1f6 */ 10813/* File: armv5te/OP_UNUSED_F6FF.S */ 10814/* File: armv5te/unused.S */ 10815 bl common_abort 10816 10817 10818/* ------------------------------ */ 10819 .balign 64 10820.L_OP_UNUSED_F7FF: /* 0x1f7 */ 10821/* File: armv5te/OP_UNUSED_F7FF.S */ 10822/* File: armv5te/unused.S */ 10823 bl common_abort 10824 10825 10826/* ------------------------------ */ 10827 .balign 64 10828.L_OP_UNUSED_F8FF: /* 0x1f8 */ 10829/* File: armv5te/OP_UNUSED_F8FF.S */ 10830/* File: armv5te/unused.S */ 10831 bl common_abort 10832 10833 10834/* ------------------------------ */ 10835 .balign 64 10836.L_OP_UNUSED_F9FF: /* 0x1f9 */ 10837/* File: armv5te/OP_UNUSED_F9FF.S */ 10838/* File: armv5te/unused.S */ 10839 bl common_abort 10840 10841 10842/* ------------------------------ */ 10843 .balign 64 10844.L_OP_UNUSED_FAFF: /* 0x1fa */ 10845/* File: armv5te/OP_UNUSED_FAFF.S */ 10846/* File: armv5te/unused.S */ 10847 bl common_abort 10848 10849 10850/* ------------------------------ */ 10851 .balign 64 10852.L_OP_UNUSED_FBFF: /* 0x1fb */ 10853/* File: armv5te/OP_UNUSED_FBFF.S */ 10854/* File: armv5te/unused.S */ 10855 bl common_abort 10856 10857 10858/* ------------------------------ */ 10859 .balign 64 10860.L_OP_UNUSED_FCFF: /* 0x1fc */ 10861/* File: armv5te/OP_UNUSED_FCFF.S */ 10862/* File: armv5te/unused.S */ 10863 bl common_abort 10864 10865 10866/* ------------------------------ */ 10867 .balign 64 10868.L_OP_UNUSED_FDFF: /* 0x1fd */ 10869/* File: armv5te/OP_UNUSED_FDFF.S */ 10870/* File: armv5te/unused.S */ 10871 bl common_abort 10872 10873 10874/* ------------------------------ */ 10875 .balign 64 10876.L_OP_UNUSED_FEFF: /* 0x1fe */ 10877/* File: armv5te/OP_UNUSED_FEFF.S */ 10878/* File: armv5te/unused.S */ 10879 bl common_abort 10880 10881 10882/* ------------------------------ */ 10883 .balign 64 10884.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 10885/* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */ 10886 /* 10887 * Handle a jumbo throw-verification-error instruction. This throws an 10888 * exception for an error discovered during verification. The 10889 * exception is indicated by BBBB, with some detail provided by AAAAAAAA. 10890 */ 10891 /* exop BBBB, Class@AAAAAAAA */ 10892 FETCH(r1, 1) @ r1<- aaaa (lo) 10893 FETCH(r2, 2) @ r2<- AAAA (hi) 10894 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10895 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa 10896 EXPORT_PC() @ export the PC 10897 FETCH(r1, 3) @ r1<- BBBB 10898 bl dvmThrowVerificationError @ always throws 10899 b common_exceptionThrown @ handle exception 10900 10901 .balign 64 10902 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 10903 .global dvmAsmInstructionEnd 10904dvmAsmInstructionEnd: 10905 10906/* 10907 * =========================================================================== 10908 * Sister implementations 10909 * =========================================================================== 10910 */ 10911 .global dvmAsmSisterStart 10912 .type dvmAsmSisterStart, %function 10913 .text 10914 .balign 4 10915dvmAsmSisterStart: 10916 10917/* continuation for OP_CONST_STRING */ 10918 10919 /* 10920 * Continuation if the String has not yet been resolved. 10921 * r1: BBBB (String ref) 10922 * r9: target register 10923 */ 10924.LOP_CONST_STRING_resolve: 10925 EXPORT_PC() 10926 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10927 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10928 bl dvmResolveString @ r0<- String reference 10929 cmp r0, #0 @ failed? 10930 beq common_exceptionThrown @ yup, handle the exception 10931 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10932 GET_INST_OPCODE(ip) @ extract opcode from rINST 10933 SET_VREG(r0, r9) @ vAA<- r0 10934 GOTO_OPCODE(ip) @ jump to next instruction 10935 10936/* continuation for OP_CONST_STRING_JUMBO */ 10937 10938 /* 10939 * Continuation if the String has not yet been resolved. 10940 * r1: BBBBBBBB (String ref) 10941 * r9: target register 10942 */ 10943.LOP_CONST_STRING_JUMBO_resolve: 10944 EXPORT_PC() 10945 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10946 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10947 bl dvmResolveString @ r0<- String reference 10948 cmp r0, #0 @ failed? 10949 beq common_exceptionThrown @ yup, handle the exception 10950 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10951 GET_INST_OPCODE(ip) @ extract opcode from rINST 10952 SET_VREG(r0, r9) @ vAA<- r0 10953 GOTO_OPCODE(ip) @ jump to next instruction 10954 10955/* continuation for OP_CONST_CLASS */ 10956 10957 /* 10958 * Continuation if the Class has not yet been resolved. 10959 * r1: BBBB (Class ref) 10960 * r9: target register 10961 */ 10962.LOP_CONST_CLASS_resolve: 10963 EXPORT_PC() 10964 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10965 mov r2, #1 @ r2<- true 10966 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10967 bl dvmResolveClass @ r0<- Class reference 10968 cmp r0, #0 @ failed? 10969 beq common_exceptionThrown @ yup, handle the exception 10970 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10971 GET_INST_OPCODE(ip) @ extract opcode from rINST 10972 SET_VREG(r0, r9) @ vAA<- r0 10973 GOTO_OPCODE(ip) @ jump to next instruction 10974 10975/* continuation for OP_CHECK_CAST */ 10976 10977 /* 10978 * Trivial test failed, need to perform full check. This is common. 10979 * r0 holds obj->clazz 10980 * r1 holds desired class resolved from BBBB 10981 * r9 holds object 10982 */ 10983.LOP_CHECK_CAST_fullcheck: 10984 mov r10, r1 @ avoid ClassObject getting clobbered 10985 bl dvmInstanceofNonTrivial @ r0<- boolean result 10986 cmp r0, #0 @ failed? 10987 bne .LOP_CHECK_CAST_okay @ no, success 10988 10989 @ A cast has failed. We need to throw a ClassCastException. 10990 EXPORT_PC() @ about to throw 10991 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 10992 mov r1, r10 @ r1<- desired class 10993 bl dvmThrowClassCastException 10994 b common_exceptionThrown 10995 10996 /* 10997 * Resolution required. This is the least-likely path. 10998 * 10999 * r2 holds BBBB 11000 * r9 holds object 11001 */ 11002.LOP_CHECK_CAST_resolve: 11003 EXPORT_PC() @ resolve() could throw 11004 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11005 mov r1, r2 @ r1<- BBBB 11006 mov r2, #0 @ r2<- false 11007 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11008 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11009 cmp r0, #0 @ got null? 11010 beq common_exceptionThrown @ yes, handle exception 11011 mov r1, r0 @ r1<- class resolved from BBB 11012 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11013 b .LOP_CHECK_CAST_resolved @ pick up where we left off 11014 11015/* continuation for OP_INSTANCE_OF */ 11016 11017 /* 11018 * Trivial test failed, need to perform full check. This is common. 11019 * r0 holds obj->clazz 11020 * r1 holds class resolved from BBBB 11021 * r9 holds A 11022 */ 11023.LOP_INSTANCE_OF_fullcheck: 11024 bl dvmInstanceofNonTrivial @ r0<- boolean result 11025 @ fall through to OP_INSTANCE_OF_store 11026 11027 /* 11028 * r0 holds boolean result 11029 * r9 holds A 11030 */ 11031.LOP_INSTANCE_OF_store: 11032 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11033 SET_VREG(r0, r9) @ vA<- r0 11034 GET_INST_OPCODE(ip) @ extract opcode from rINST 11035 GOTO_OPCODE(ip) @ jump to next instruction 11036 11037 /* 11038 * Trivial test succeeded, save and bail. 11039 * r9 holds A 11040 */ 11041.LOP_INSTANCE_OF_trivial: 11042 mov r0, #1 @ indicate success 11043 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 11044 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11045 SET_VREG(r0, r9) @ vA<- r0 11046 GET_INST_OPCODE(ip) @ extract opcode from rINST 11047 GOTO_OPCODE(ip) @ jump to next instruction 11048 11049 /* 11050 * Resolution required. This is the least-likely path. 11051 * 11052 * r3 holds BBBB 11053 * r9 holds A 11054 */ 11055.LOP_INSTANCE_OF_resolve: 11056 EXPORT_PC() @ resolve() could throw 11057 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 11058 mov r1, r3 @ r1<- BBBB 11059 mov r2, #1 @ r2<- true 11060 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 11061 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11062 cmp r0, #0 @ got null? 11063 beq common_exceptionThrown @ yes, handle exception 11064 mov r1, r0 @ r1<- class resolved from BBB 11065 mov r3, rINST, lsr #12 @ r3<- B 11066 GET_VREG(r0, r3) @ r0<- vB (object) 11067 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 11068 b .LOP_INSTANCE_OF_resolved @ pick up where we left off 11069 11070/* continuation for OP_NEW_INSTANCE */ 11071 11072 .balign 32 @ minimize cache lines 11073.LOP_NEW_INSTANCE_finish: @ r0=new object 11074 mov r3, rINST, lsr #8 @ r3<- AA 11075 cmp r0, #0 @ failed? 11076 beq common_exceptionThrown @ yes, handle the exception 11077 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11078 GET_INST_OPCODE(ip) @ extract opcode from rINST 11079 SET_VREG(r0, r3) @ vAA<- r0 11080 GOTO_OPCODE(ip) @ jump to next instruction 11081 11082 /* 11083 * Class initialization required. 11084 * 11085 * r0 holds class object 11086 */ 11087.LOP_NEW_INSTANCE_needinit: 11088 mov r9, r0 @ save r0 11089 bl dvmInitClass @ initialize class 11090 cmp r0, #0 @ check boolean result 11091 mov r0, r9 @ restore r0 11092 bne .LOP_NEW_INSTANCE_initialized @ success, continue 11093 b common_exceptionThrown @ failed, deal with init exception 11094 11095 /* 11096 * Resolution required. This is the least-likely path. 11097 * 11098 * r1 holds BBBB 11099 */ 11100.LOP_NEW_INSTANCE_resolve: 11101 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11102 mov r2, #0 @ r2<- false 11103 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11104 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11105 cmp r0, #0 @ got null? 11106 bne .LOP_NEW_INSTANCE_resolved @ no, continue 11107 b common_exceptionThrown @ yes, handle exception 11108 11109/* continuation for OP_NEW_ARRAY */ 11110 11111 11112 /* 11113 * Resolve class. (This is an uncommon case.) 11114 * 11115 * r1 holds array length 11116 * r2 holds class ref CCCC 11117 */ 11118.LOP_NEW_ARRAY_resolve: 11119 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11120 mov r9, r1 @ r9<- length (save) 11121 mov r1, r2 @ r1<- CCCC 11122 mov r2, #0 @ r2<- false 11123 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11124 bl dvmResolveClass @ r0<- call(clazz, ref) 11125 cmp r0, #0 @ got null? 11126 mov r1, r9 @ r1<- length (restore) 11127 beq common_exceptionThrown @ yes, handle exception 11128 @ fall through to OP_NEW_ARRAY_finish 11129 11130 /* 11131 * Finish allocation. 11132 * 11133 * r0 holds class 11134 * r1 holds array length 11135 */ 11136.LOP_NEW_ARRAY_finish: 11137 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 11138 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 11139 cmp r0, #0 @ failed? 11140 mov r2, rINST, lsr #8 @ r2<- A+ 11141 beq common_exceptionThrown @ yes, handle the exception 11142 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11143 and r2, r2, #15 @ r2<- A 11144 GET_INST_OPCODE(ip) @ extract opcode from rINST 11145 SET_VREG(r0, r2) @ vA<- r0 11146 GOTO_OPCODE(ip) @ jump to next instruction 11147 11148/* continuation for OP_FILLED_NEW_ARRAY */ 11149 11150 /* 11151 * On entry: 11152 * r0 holds array class 11153 * r10 holds AA or BA 11154 */ 11155.LOP_FILLED_NEW_ARRAY_continue: 11156 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11157 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11158 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11159 .if 0 11160 mov r1, r10 @ r1<- AA (length) 11161 .else 11162 mov r1, r10, lsr #4 @ r1<- B (length) 11163 .endif 11164 cmp rINST, #'I' @ array of ints? 11165 cmpne rINST, #'L' @ array of objects? 11166 cmpne rINST, #'[' @ array of arrays? 11167 mov r9, r1 @ save length in r9 11168 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 11169 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11170 cmp r0, #0 @ null return? 11171 beq common_exceptionThrown @ alloc failed, handle exception 11172 11173 FETCH(r1, 2) @ r1<- FEDC or CCCC 11174 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11175 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11176 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11177 subs r9, r9, #1 @ length--, check for neg 11178 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11179 bmi 2f @ was zero, bail 11180 11181 @ copy values from registers into the array 11182 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11183 .if 0 11184 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 111851: ldr r3, [r2], #4 @ r3<- *r2++ 11186 subs r9, r9, #1 @ count-- 11187 str r3, [r0], #4 @ *contents++ = vX 11188 bpl 1b 11189 @ continue at 2 11190 .else 11191 cmp r9, #4 @ length was initially 5? 11192 and r2, r10, #15 @ r2<- A 11193 bne 1f @ <= 4 args, branch 11194 GET_VREG(r3, r2) @ r3<- vA 11195 sub r9, r9, #1 @ count-- 11196 str r3, [r0, #16] @ contents[4] = vA 111971: and r2, r1, #15 @ r2<- F/E/D/C 11198 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11199 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11200 subs r9, r9, #1 @ count-- 11201 str r3, [r0], #4 @ *contents++ = vX 11202 bpl 1b 11203 @ continue at 2 11204 .endif 11205 112062: 11207 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11208 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11209 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11210 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11211 cmp r1, #'I' @ Is int array? 11212 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11213 GOTO_OPCODE(ip) @ execute it 11214 11215 /* 11216 * Throw an exception indicating that we have not implemented this 11217 * mode of filled-new-array. 11218 */ 11219.LOP_FILLED_NEW_ARRAY_notimpl: 11220 ldr r0, .L_strFilledNewArrayNotImpl 11221 bl dvmThrowInternalError 11222 b common_exceptionThrown 11223 11224 .if (!0) @ define in one or the other, not both 11225.L_strFilledNewArrayNotImpl: 11226 .word .LstrFilledNewArrayNotImpl 11227 .endif 11228 11229/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 11230 11231 /* 11232 * On entry: 11233 * r0 holds array class 11234 * r10 holds AA or BA 11235 */ 11236.LOP_FILLED_NEW_ARRAY_RANGE_continue: 11237 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11238 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11239 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11240 .if 1 11241 mov r1, r10 @ r1<- AA (length) 11242 .else 11243 mov r1, r10, lsr #4 @ r1<- B (length) 11244 .endif 11245 cmp rINST, #'I' @ array of ints? 11246 cmpne rINST, #'L' @ array of objects? 11247 cmpne rINST, #'[' @ array of arrays? 11248 mov r9, r1 @ save length in r9 11249 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 11250 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11251 cmp r0, #0 @ null return? 11252 beq common_exceptionThrown @ alloc failed, handle exception 11253 11254 FETCH(r1, 2) @ r1<- FEDC or CCCC 11255 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11256 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11257 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11258 subs r9, r9, #1 @ length--, check for neg 11259 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11260 bmi 2f @ was zero, bail 11261 11262 @ copy values from registers into the array 11263 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11264 .if 1 11265 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 112661: ldr r3, [r2], #4 @ r3<- *r2++ 11267 subs r9, r9, #1 @ count-- 11268 str r3, [r0], #4 @ *contents++ = vX 11269 bpl 1b 11270 @ continue at 2 11271 .else 11272 cmp r9, #4 @ length was initially 5? 11273 and r2, r10, #15 @ r2<- A 11274 bne 1f @ <= 4 args, branch 11275 GET_VREG(r3, r2) @ r3<- vA 11276 sub r9, r9, #1 @ count-- 11277 str r3, [r0, #16] @ contents[4] = vA 112781: and r2, r1, #15 @ r2<- F/E/D/C 11279 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11280 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11281 subs r9, r9, #1 @ count-- 11282 str r3, [r0], #4 @ *contents++ = vX 11283 bpl 1b 11284 @ continue at 2 11285 .endif 11286 112872: 11288 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11289 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11290 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11291 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11292 cmp r1, #'I' @ Is int array? 11293 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11294 GOTO_OPCODE(ip) @ execute it 11295 11296 /* 11297 * Throw an exception indicating that we have not implemented this 11298 * mode of filled-new-array. 11299 */ 11300.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 11301 ldr r0, .L_strFilledNewArrayNotImpl 11302 bl dvmThrowInternalError 11303 b common_exceptionThrown 11304 11305 .if (!1) @ define in one or the other, not both 11306.L_strFilledNewArrayNotImpl: 11307 .word .LstrFilledNewArrayNotImpl 11308 .endif 11309 11310/* continuation for OP_CMPL_FLOAT */ 11311 11312 @ Test for NaN with a second comparison. EABI forbids testing bit 11313 @ patterns, and we can't represent 0x7fc00000 in immediate form, so 11314 @ make the library call. 11315.LOP_CMPL_FLOAT_gt_or_nan: 11316 mov r1, r9 @ reverse order 11317 mov r0, r10 11318 bl __aeabi_cfcmple @ r0<- Z set if eq, C clear if < 11319 @bleq common_abort 11320 movcc r1, #1 @ (greater than) r1<- 1 11321 bcc .LOP_CMPL_FLOAT_finish 11322 mvn r1, #0 @ r1<- 1 or -1 for NaN 11323 b .LOP_CMPL_FLOAT_finish 11324 11325 11326#if 0 /* "clasic" form */ 11327 FETCH(r0, 1) @ r0<- CCBB 11328 and r2, r0, #255 @ r2<- BB 11329 mov r3, r0, lsr #8 @ r3<- CC 11330 GET_VREG(r9, r2) @ r9<- vBB 11331 GET_VREG(r10, r3) @ r10<- vCC 11332 mov r0, r9 @ r0<- vBB 11333 mov r1, r10 @ r1<- vCC 11334 bl __aeabi_fcmpeq @ r0<- (vBB == vCC) 11335 cmp r0, #0 @ equal? 11336 movne r1, #0 @ yes, result is 0 11337 bne OP_CMPL_FLOAT_finish 11338 mov r0, r9 @ r0<- vBB 11339 mov r1, r10 @ r1<- vCC 11340 bl __aeabi_fcmplt @ r0<- (vBB < vCC) 11341 cmp r0, #0 @ less than? 11342 b OP_CMPL_FLOAT_continue 11343@%break 11344 11345OP_CMPL_FLOAT_continue: 11346 mvnne r1, #0 @ yes, result is -1 11347 bne OP_CMPL_FLOAT_finish 11348 mov r0, r9 @ r0<- vBB 11349 mov r1, r10 @ r1<- vCC 11350 bl __aeabi_fcmpgt @ r0<- (vBB > vCC) 11351 cmp r0, #0 @ greater than? 11352 beq OP_CMPL_FLOAT_nan @ no, must be NaN 11353 mov r1, #1 @ yes, result is 1 11354 @ fall through to _finish 11355 11356OP_CMPL_FLOAT_finish: 11357 mov r3, rINST, lsr #8 @ r3<- AA 11358 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11359 SET_VREG(r1, r3) @ vAA<- r1 11360 GET_INST_OPCODE(ip) @ extract opcode from rINST 11361 GOTO_OPCODE(ip) @ jump to next instruction 11362 11363 /* 11364 * This is expected to be uncommon, so we double-branch (once to here, 11365 * again back to _finish). 11366 */ 11367OP_CMPL_FLOAT_nan: 11368 mvn r1, #0 @ r1<- 1 or -1 for NaN 11369 b OP_CMPL_FLOAT_finish 11370 11371#endif 11372 11373/* continuation for OP_CMPG_FLOAT */ 11374 11375 @ Test for NaN with a second comparison. EABI forbids testing bit 11376 @ patterns, and we can't represent 0x7fc00000 in immediate form, so 11377 @ make the library call. 11378.LOP_CMPG_FLOAT_gt_or_nan: 11379 mov r1, r9 @ reverse order 11380 mov r0, r10 11381 bl __aeabi_cfcmple @ r0<- Z set if eq, C clear if < 11382 @bleq common_abort 11383 movcc r1, #1 @ (greater than) r1<- 1 11384 bcc .LOP_CMPG_FLOAT_finish 11385 mov r1, #1 @ r1<- 1 or -1 for NaN 11386 b .LOP_CMPG_FLOAT_finish 11387 11388 11389#if 0 /* "clasic" form */ 11390 FETCH(r0, 1) @ r0<- CCBB 11391 and r2, r0, #255 @ r2<- BB 11392 mov r3, r0, lsr #8 @ r3<- CC 11393 GET_VREG(r9, r2) @ r9<- vBB 11394 GET_VREG(r10, r3) @ r10<- vCC 11395 mov r0, r9 @ r0<- vBB 11396 mov r1, r10 @ r1<- vCC 11397 bl __aeabi_fcmpeq @ r0<- (vBB == vCC) 11398 cmp r0, #0 @ equal? 11399 movne r1, #0 @ yes, result is 0 11400 bne OP_CMPG_FLOAT_finish 11401 mov r0, r9 @ r0<- vBB 11402 mov r1, r10 @ r1<- vCC 11403 bl __aeabi_fcmplt @ r0<- (vBB < vCC) 11404 cmp r0, #0 @ less than? 11405 b OP_CMPG_FLOAT_continue 11406@%break 11407 11408OP_CMPG_FLOAT_continue: 11409 mvnne r1, #0 @ yes, result is -1 11410 bne OP_CMPG_FLOAT_finish 11411 mov r0, r9 @ r0<- vBB 11412 mov r1, r10 @ r1<- vCC 11413 bl __aeabi_fcmpgt @ r0<- (vBB > vCC) 11414 cmp r0, #0 @ greater than? 11415 beq OP_CMPG_FLOAT_nan @ no, must be NaN 11416 mov r1, #1 @ yes, result is 1 11417 @ fall through to _finish 11418 11419OP_CMPG_FLOAT_finish: 11420 mov r3, rINST, lsr #8 @ r3<- AA 11421 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11422 SET_VREG(r1, r3) @ vAA<- r1 11423 GET_INST_OPCODE(ip) @ extract opcode from rINST 11424 GOTO_OPCODE(ip) @ jump to next instruction 11425 11426 /* 11427 * This is expected to be uncommon, so we double-branch (once to here, 11428 * again back to _finish). 11429 */ 11430OP_CMPG_FLOAT_nan: 11431 mov r1, #1 @ r1<- 1 or -1 for NaN 11432 b OP_CMPG_FLOAT_finish 11433 11434#endif 11435 11436/* continuation for OP_CMPL_DOUBLE */ 11437 11438 @ Test for NaN with a second comparison. EABI forbids testing bit 11439 @ patterns, and we can't represent 0x7fc00000 in immediate form, so 11440 @ make the library call. 11441.LOP_CMPL_DOUBLE_gt_or_nan: 11442 ldmia r10, {r0-r1} @ reverse order 11443 ldmia r9, {r2-r3} 11444 bl __aeabi_cdcmple @ r0<- Z set if eq, C clear if < 11445 @bleq common_abort 11446 movcc r1, #1 @ (greater than) r1<- 1 11447 bcc .LOP_CMPL_DOUBLE_finish 11448 mvn r1, #0 @ r1<- 1 or -1 for NaN 11449 b .LOP_CMPL_DOUBLE_finish 11450 11451/* continuation for OP_CMPG_DOUBLE */ 11452 11453 @ Test for NaN with a second comparison. EABI forbids testing bit 11454 @ patterns, and we can't represent 0x7fc00000 in immediate form, so 11455 @ make the library call. 11456.LOP_CMPG_DOUBLE_gt_or_nan: 11457 ldmia r10, {r0-r1} @ reverse order 11458 ldmia r9, {r2-r3} 11459 bl __aeabi_cdcmple @ r0<- Z set if eq, C clear if < 11460 @bleq common_abort 11461 movcc r1, #1 @ (greater than) r1<- 1 11462 bcc .LOP_CMPG_DOUBLE_finish 11463 mov r1, #1 @ r1<- 1 or -1 for NaN 11464 b .LOP_CMPG_DOUBLE_finish 11465 11466/* continuation for OP_CMP_LONG */ 11467 11468.LOP_CMP_LONG_less: 11469 mvn r1, #0 @ r1<- -1 11470 @ Want to cond code the next mov so we can avoid branch, but don't see it; 11471 @ instead, we just replicate the tail end. 11472 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11473 SET_VREG(r1, r9) @ vAA<- r1 11474 GET_INST_OPCODE(ip) @ extract opcode from rINST 11475 GOTO_OPCODE(ip) @ jump to next instruction 11476 11477.LOP_CMP_LONG_greater: 11478 mov r1, #1 @ r1<- 1 11479 @ fall through to _finish 11480 11481.LOP_CMP_LONG_finish: 11482 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11483 SET_VREG(r1, r9) @ vAA<- r1 11484 GET_INST_OPCODE(ip) @ extract opcode from rINST 11485 GOTO_OPCODE(ip) @ jump to next instruction 11486 11487/* continuation for OP_AGET_WIDE */ 11488 11489.LOP_AGET_WIDE_finish: 11490 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11491 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11492 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 11493 GET_INST_OPCODE(ip) @ extract opcode from rINST 11494 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 11495 GOTO_OPCODE(ip) @ jump to next instruction 11496 11497/* continuation for OP_APUT_WIDE */ 11498 11499.LOP_APUT_WIDE_finish: 11500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11501 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 11502 GET_INST_OPCODE(ip) @ extract opcode from rINST 11503 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11504 GOTO_OPCODE(ip) @ jump to next instruction 11505 11506/* continuation for OP_APUT_OBJECT */ 11507 /* 11508 * On entry: 11509 * rINST = vBB (arrayObj) 11510 * r9 = vAA (obj) 11511 * r10 = offset into array (vBB + vCC * width) 11512 */ 11513.LOP_APUT_OBJECT_finish: 11514 cmp r9, #0 @ storing null reference? 11515 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 11516 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11517 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 11518 bl dvmCanPutArrayElement @ test object type vs. array type 11519 cmp r0, #0 @ okay? 11520 beq .LOP_APUT_OBJECT_throw @ no 11521 mov r1, rINST @ r1<- arrayObj 11522 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11523 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base 11524 add r10, #offArrayObject_contents @ r0<- pointer to slot 11525 GET_INST_OPCODE(ip) @ extract opcode from rINST 11526 str r9, [r10] @ vBB[vCC]<- vAA 11527 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 11528 GOTO_OPCODE(ip) @ jump to next instruction 11529.LOP_APUT_OBJECT_skip_check: 11530 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11531 GET_INST_OPCODE(ip) @ extract opcode from rINST 11532 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 11533 GOTO_OPCODE(ip) @ jump to next instruction 11534.LOP_APUT_OBJECT_throw: 11535 @ The types don't match. We need to throw an ArrayStoreException. 11536 ldr r0, [r9, #offObject_clazz] 11537 ldr r1, [rINST, #offObject_clazz] 11538 EXPORT_PC() 11539 bl dvmThrowArrayStoreException 11540 b common_exceptionThrown 11541 11542/* continuation for OP_IGET */ 11543 11544 /* 11545 * Currently: 11546 * r0 holds resolved field 11547 * r9 holds object 11548 */ 11549.LOP_IGET_finish: 11550 @bl common_squeak0 11551 cmp r9, #0 @ check object for null 11552 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11553 beq common_errNullObject @ object was null 11554 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11555 @ no-op @ acquiring load 11556 mov r2, rINST, lsr #8 @ r2<- A+ 11557 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11558 and r2, r2, #15 @ r2<- A 11559 GET_INST_OPCODE(ip) @ extract opcode from rINST 11560 SET_VREG(r0, r2) @ fp[A]<- r0 11561 GOTO_OPCODE(ip) @ jump to next instruction 11562 11563/* continuation for OP_IGET_WIDE */ 11564 11565 /* 11566 * Currently: 11567 * r0 holds resolved field 11568 * r9 holds object 11569 */ 11570.LOP_IGET_WIDE_finish: 11571 cmp r9, #0 @ check object for null 11572 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11573 beq common_errNullObject @ object was null 11574 .if 0 11575 add r0, r9, r3 @ r0<- address of field 11576 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11577 .else 11578 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11579 .endif 11580 mov r2, rINST, lsr #8 @ r2<- A+ 11581 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11582 and r2, r2, #15 @ r2<- A 11583 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11584 GET_INST_OPCODE(ip) @ extract opcode from rINST 11585 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11586 GOTO_OPCODE(ip) @ jump to next instruction 11587 11588/* continuation for OP_IGET_OBJECT */ 11589 11590 /* 11591 * Currently: 11592 * r0 holds resolved field 11593 * r9 holds object 11594 */ 11595.LOP_IGET_OBJECT_finish: 11596 @bl common_squeak0 11597 cmp r9, #0 @ check object for null 11598 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11599 beq common_errNullObject @ object was null 11600 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11601 @ no-op @ acquiring load 11602 mov r2, rINST, lsr #8 @ r2<- A+ 11603 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11604 and r2, r2, #15 @ r2<- A 11605 GET_INST_OPCODE(ip) @ extract opcode from rINST 11606 SET_VREG(r0, r2) @ fp[A]<- r0 11607 GOTO_OPCODE(ip) @ jump to next instruction 11608 11609/* continuation for OP_IGET_BOOLEAN */ 11610 11611 /* 11612 * Currently: 11613 * r0 holds resolved field 11614 * r9 holds object 11615 */ 11616.LOP_IGET_BOOLEAN_finish: 11617 @bl common_squeak1 11618 cmp r9, #0 @ check object for null 11619 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11620 beq common_errNullObject @ object was null 11621 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11622 @ no-op @ acquiring load 11623 mov r2, rINST, lsr #8 @ r2<- A+ 11624 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11625 and r2, r2, #15 @ r2<- A 11626 GET_INST_OPCODE(ip) @ extract opcode from rINST 11627 SET_VREG(r0, r2) @ fp[A]<- r0 11628 GOTO_OPCODE(ip) @ jump to next instruction 11629 11630/* continuation for OP_IGET_BYTE */ 11631 11632 /* 11633 * Currently: 11634 * r0 holds resolved field 11635 * r9 holds object 11636 */ 11637.LOP_IGET_BYTE_finish: 11638 @bl common_squeak2 11639 cmp r9, #0 @ check object for null 11640 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11641 beq common_errNullObject @ object was null 11642 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11643 @ no-op @ acquiring load 11644 mov r2, rINST, lsr #8 @ r2<- A+ 11645 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11646 and r2, r2, #15 @ r2<- A 11647 GET_INST_OPCODE(ip) @ extract opcode from rINST 11648 SET_VREG(r0, r2) @ fp[A]<- r0 11649 GOTO_OPCODE(ip) @ jump to next instruction 11650 11651/* continuation for OP_IGET_CHAR */ 11652 11653 /* 11654 * Currently: 11655 * r0 holds resolved field 11656 * r9 holds object 11657 */ 11658.LOP_IGET_CHAR_finish: 11659 @bl common_squeak3 11660 cmp r9, #0 @ check object for null 11661 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11662 beq common_errNullObject @ object was null 11663 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11664 @ no-op @ acquiring load 11665 mov r2, rINST, lsr #8 @ r2<- A+ 11666 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11667 and r2, r2, #15 @ r2<- A 11668 GET_INST_OPCODE(ip) @ extract opcode from rINST 11669 SET_VREG(r0, r2) @ fp[A]<- r0 11670 GOTO_OPCODE(ip) @ jump to next instruction 11671 11672/* continuation for OP_IGET_SHORT */ 11673 11674 /* 11675 * Currently: 11676 * r0 holds resolved field 11677 * r9 holds object 11678 */ 11679.LOP_IGET_SHORT_finish: 11680 @bl common_squeak4 11681 cmp r9, #0 @ check object for null 11682 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11683 beq common_errNullObject @ object was null 11684 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11685 @ no-op @ acquiring load 11686 mov r2, rINST, lsr #8 @ r2<- A+ 11687 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11688 and r2, r2, #15 @ r2<- A 11689 GET_INST_OPCODE(ip) @ extract opcode from rINST 11690 SET_VREG(r0, r2) @ fp[A]<- r0 11691 GOTO_OPCODE(ip) @ jump to next instruction 11692 11693/* continuation for OP_IPUT */ 11694 11695 /* 11696 * Currently: 11697 * r0 holds resolved field 11698 * r9 holds object 11699 */ 11700.LOP_IPUT_finish: 11701 @bl common_squeak0 11702 mov r1, rINST, lsr #8 @ r1<- A+ 11703 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11704 and r1, r1, #15 @ r1<- A 11705 cmp r9, #0 @ check object for null 11706 GET_VREG(r0, r1) @ r0<- fp[A] 11707 beq common_errNullObject @ object was null 11708 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11709 GET_INST_OPCODE(ip) @ extract opcode from rINST 11710 @ no-op @ releasing store 11711 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11712 GOTO_OPCODE(ip) @ jump to next instruction 11713 11714/* continuation for OP_IPUT_WIDE */ 11715 11716 /* 11717 * Currently: 11718 * r0 holds resolved field 11719 * r9 holds object 11720 */ 11721.LOP_IPUT_WIDE_finish: 11722 mov r2, rINST, lsr #8 @ r2<- A+ 11723 cmp r9, #0 @ check object for null 11724 and r2, r2, #15 @ r2<- A 11725 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11726 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11727 beq common_errNullObject @ object was null 11728 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11729 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11730 GET_INST_OPCODE(r10) @ extract opcode from rINST 11731 .if 0 11732 add r2, r9, r3 @ r2<- target address 11733 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 11734 .else 11735 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 11736 .endif 11737 GOTO_OPCODE(r10) @ jump to next instruction 11738 11739/* continuation for OP_IPUT_OBJECT */ 11740 11741 /* 11742 * Currently: 11743 * r0 holds resolved field 11744 * r9 holds object 11745 */ 11746.LOP_IPUT_OBJECT_finish: 11747 @bl common_squeak0 11748 mov r1, rINST, lsr #8 @ r1<- A+ 11749 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11750 and r1, r1, #15 @ r1<- A 11751 cmp r9, #0 @ check object for null 11752 GET_VREG(r0, r1) @ r0<- fp[A] 11753 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11754 beq common_errNullObject @ object was null 11755 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11756 GET_INST_OPCODE(ip) @ extract opcode from rINST 11757 @ no-op @ releasing store 11758 str r0, [r9, r3] @ obj.field (32 bits)<- r0 11759 cmp r0, #0 @ stored a null reference? 11760 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 11761 GOTO_OPCODE(ip) @ jump to next instruction 11762 11763/* continuation for OP_IPUT_BOOLEAN */ 11764 11765 /* 11766 * Currently: 11767 * r0 holds resolved field 11768 * r9 holds object 11769 */ 11770.LOP_IPUT_BOOLEAN_finish: 11771 @bl common_squeak1 11772 mov r1, rINST, lsr #8 @ r1<- A+ 11773 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11774 and r1, r1, #15 @ r1<- A 11775 cmp r9, #0 @ check object for null 11776 GET_VREG(r0, r1) @ r0<- fp[A] 11777 beq common_errNullObject @ object was null 11778 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11779 GET_INST_OPCODE(ip) @ extract opcode from rINST 11780 @ no-op @ releasing store 11781 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11782 GOTO_OPCODE(ip) @ jump to next instruction 11783 11784/* continuation for OP_IPUT_BYTE */ 11785 11786 /* 11787 * Currently: 11788 * r0 holds resolved field 11789 * r9 holds object 11790 */ 11791.LOP_IPUT_BYTE_finish: 11792 @bl common_squeak2 11793 mov r1, rINST, lsr #8 @ r1<- A+ 11794 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11795 and r1, r1, #15 @ r1<- A 11796 cmp r9, #0 @ check object for null 11797 GET_VREG(r0, r1) @ r0<- fp[A] 11798 beq common_errNullObject @ object was null 11799 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11800 GET_INST_OPCODE(ip) @ extract opcode from rINST 11801 @ no-op @ releasing store 11802 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11803 GOTO_OPCODE(ip) @ jump to next instruction 11804 11805/* continuation for OP_IPUT_CHAR */ 11806 11807 /* 11808 * Currently: 11809 * r0 holds resolved field 11810 * r9 holds object 11811 */ 11812.LOP_IPUT_CHAR_finish: 11813 @bl common_squeak3 11814 mov r1, rINST, lsr #8 @ r1<- A+ 11815 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11816 and r1, r1, #15 @ r1<- A 11817 cmp r9, #0 @ check object for null 11818 GET_VREG(r0, r1) @ r0<- fp[A] 11819 beq common_errNullObject @ object was null 11820 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11821 GET_INST_OPCODE(ip) @ extract opcode from rINST 11822 @ no-op @ releasing store 11823 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11824 GOTO_OPCODE(ip) @ jump to next instruction 11825 11826/* continuation for OP_IPUT_SHORT */ 11827 11828 /* 11829 * Currently: 11830 * r0 holds resolved field 11831 * r9 holds object 11832 */ 11833.LOP_IPUT_SHORT_finish: 11834 @bl common_squeak4 11835 mov r1, rINST, lsr #8 @ r1<- A+ 11836 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11837 and r1, r1, #15 @ r1<- A 11838 cmp r9, #0 @ check object for null 11839 GET_VREG(r0, r1) @ r0<- fp[A] 11840 beq common_errNullObject @ object was null 11841 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11842 GET_INST_OPCODE(ip) @ extract opcode from rINST 11843 @ no-op @ releasing store 11844 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11845 GOTO_OPCODE(ip) @ jump to next instruction 11846 11847/* continuation for OP_SGET */ 11848 11849 /* 11850 * Continuation if the field has not yet been resolved. 11851 * r1: BBBB field ref 11852 */ 11853.LOP_SGET_resolve: 11854 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11855 EXPORT_PC() @ resolve() could throw, so export now 11856 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11857 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11858 cmp r0, #0 @ success? 11859 bne .LOP_SGET_finish @ yes, finish 11860 b common_exceptionThrown @ no, handle exception 11861 11862/* continuation for OP_SGET_WIDE */ 11863 11864 /* 11865 * Continuation if the field has not yet been resolved. 11866 * r1: BBBB field ref 11867 * 11868 * Returns StaticField pointer in r0. 11869 */ 11870.LOP_SGET_WIDE_resolve: 11871 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11872 EXPORT_PC() @ resolve() could throw, so export now 11873 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11874 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11875 cmp r0, #0 @ success? 11876 bne .LOP_SGET_WIDE_finish @ yes, finish 11877 b common_exceptionThrown @ no, handle exception 11878 11879/* continuation for OP_SGET_OBJECT */ 11880 11881 /* 11882 * Continuation if the field has not yet been resolved. 11883 * r1: BBBB field ref 11884 */ 11885.LOP_SGET_OBJECT_resolve: 11886 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11887 EXPORT_PC() @ resolve() could throw, so export now 11888 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11889 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11890 cmp r0, #0 @ success? 11891 bne .LOP_SGET_OBJECT_finish @ yes, finish 11892 b common_exceptionThrown @ no, handle exception 11893 11894/* continuation for OP_SGET_BOOLEAN */ 11895 11896 /* 11897 * Continuation if the field has not yet been resolved. 11898 * r1: BBBB field ref 11899 */ 11900.LOP_SGET_BOOLEAN_resolve: 11901 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11902 EXPORT_PC() @ resolve() could throw, so export now 11903 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11904 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11905 cmp r0, #0 @ success? 11906 bne .LOP_SGET_BOOLEAN_finish @ yes, finish 11907 b common_exceptionThrown @ no, handle exception 11908 11909/* continuation for OP_SGET_BYTE */ 11910 11911 /* 11912 * Continuation if the field has not yet been resolved. 11913 * r1: BBBB field ref 11914 */ 11915.LOP_SGET_BYTE_resolve: 11916 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11917 EXPORT_PC() @ resolve() could throw, so export now 11918 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11919 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11920 cmp r0, #0 @ success? 11921 bne .LOP_SGET_BYTE_finish @ yes, finish 11922 b common_exceptionThrown @ no, handle exception 11923 11924/* continuation for OP_SGET_CHAR */ 11925 11926 /* 11927 * Continuation if the field has not yet been resolved. 11928 * r1: BBBB field ref 11929 */ 11930.LOP_SGET_CHAR_resolve: 11931 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11932 EXPORT_PC() @ resolve() could throw, so export now 11933 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11934 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11935 cmp r0, #0 @ success? 11936 bne .LOP_SGET_CHAR_finish @ yes, finish 11937 b common_exceptionThrown @ no, handle exception 11938 11939/* continuation for OP_SGET_SHORT */ 11940 11941 /* 11942 * Continuation if the field has not yet been resolved. 11943 * r1: BBBB field ref 11944 */ 11945.LOP_SGET_SHORT_resolve: 11946 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11947 EXPORT_PC() @ resolve() could throw, so export now 11948 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11949 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11950 cmp r0, #0 @ success? 11951 bne .LOP_SGET_SHORT_finish @ yes, finish 11952 b common_exceptionThrown @ no, handle exception 11953 11954/* continuation for OP_SPUT */ 11955 11956 /* 11957 * Continuation if the field has not yet been resolved. 11958 * r1: BBBB field ref 11959 */ 11960.LOP_SPUT_resolve: 11961 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11962 EXPORT_PC() @ resolve() could throw, so export now 11963 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11964 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11965 cmp r0, #0 @ success? 11966 bne .LOP_SPUT_finish @ yes, finish 11967 b common_exceptionThrown @ no, handle exception 11968 11969/* continuation for OP_SPUT_WIDE */ 11970 11971 /* 11972 * Continuation if the field has not yet been resolved. 11973 * r1: BBBB field ref 11974 * r9: &fp[AA] 11975 * 11976 * Returns StaticField pointer in r2. 11977 */ 11978.LOP_SPUT_WIDE_resolve: 11979 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11980 EXPORT_PC() @ resolve() could throw, so export now 11981 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11982 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11983 cmp r0, #0 @ success? 11984 mov r2, r0 @ copy to r2 11985 bne .LOP_SPUT_WIDE_finish @ yes, finish 11986 b common_exceptionThrown @ no, handle exception 11987 11988/* continuation for OP_SPUT_OBJECT */ 11989.LOP_SPUT_OBJECT_finish: @ field ptr in r0 11990 mov r2, rINST, lsr #8 @ r2<- AA 11991 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11992 GET_VREG(r1, r2) @ r1<- fp[AA] 11993 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11994 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 11995 GET_INST_OPCODE(ip) @ extract opcode from rINST 11996 @ no-op @ releasing store 11997 str r1, [r0, #offStaticField_value] @ field<- vAA 11998 cmp r1, #0 @ stored a null object? 11999 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12000 GOTO_OPCODE(ip) @ jump to next instruction 12001 12002/* continuation for OP_SPUT_BOOLEAN */ 12003 12004 /* 12005 * Continuation if the field has not yet been resolved. 12006 * r1: BBBB field ref 12007 */ 12008.LOP_SPUT_BOOLEAN_resolve: 12009 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12010 EXPORT_PC() @ resolve() could throw, so export now 12011 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12012 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12013 cmp r0, #0 @ success? 12014 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 12015 b common_exceptionThrown @ no, handle exception 12016 12017/* continuation for OP_SPUT_BYTE */ 12018 12019 /* 12020 * Continuation if the field has not yet been resolved. 12021 * r1: BBBB field ref 12022 */ 12023.LOP_SPUT_BYTE_resolve: 12024 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12025 EXPORT_PC() @ resolve() could throw, so export now 12026 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12027 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12028 cmp r0, #0 @ success? 12029 bne .LOP_SPUT_BYTE_finish @ yes, finish 12030 b common_exceptionThrown @ no, handle exception 12031 12032/* continuation for OP_SPUT_CHAR */ 12033 12034 /* 12035 * Continuation if the field has not yet been resolved. 12036 * r1: BBBB field ref 12037 */ 12038.LOP_SPUT_CHAR_resolve: 12039 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12040 EXPORT_PC() @ resolve() could throw, so export now 12041 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12042 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12043 cmp r0, #0 @ success? 12044 bne .LOP_SPUT_CHAR_finish @ yes, finish 12045 b common_exceptionThrown @ no, handle exception 12046 12047/* continuation for OP_SPUT_SHORT */ 12048 12049 /* 12050 * Continuation if the field has not yet been resolved. 12051 * r1: BBBB field ref 12052 */ 12053.LOP_SPUT_SHORT_resolve: 12054 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12055 EXPORT_PC() @ resolve() could throw, so export now 12056 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12057 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12058 cmp r0, #0 @ success? 12059 bne .LOP_SPUT_SHORT_finish @ yes, finish 12060 b common_exceptionThrown @ no, handle exception 12061 12062/* continuation for OP_INVOKE_VIRTUAL */ 12063 12064 /* 12065 * At this point: 12066 * r0 = resolved base method 12067 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 12068 */ 12069.LOP_INVOKE_VIRTUAL_continue: 12070 GET_VREG(r1, r10) @ r1<- "this" ptr 12071 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12072 cmp r1, #0 @ is "this" null? 12073 beq common_errNullObject @ null "this", throw exception 12074 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 12075 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 12076 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 12077 bl common_invokeMethodNoRange @ continue on 12078 12079/* continuation for OP_INVOKE_SUPER */ 12080 12081 /* 12082 * At this point: 12083 * r0 = resolved base method 12084 * r9 = method->clazz 12085 */ 12086.LOP_INVOKE_SUPER_continue: 12087 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 12088 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12089 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 12090 EXPORT_PC() @ must export for invoke 12091 cmp r2, r3 @ compare (methodIndex, vtableCount) 12092 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 12093 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 12094 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 12095 bl common_invokeMethodNoRange @ continue on 12096 12097.LOP_INVOKE_SUPER_resolve: 12098 mov r0, r9 @ r0<- method->clazz 12099 mov r2, #METHOD_VIRTUAL @ resolver method type 12100 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12101 cmp r0, #0 @ got null? 12102 bne .LOP_INVOKE_SUPER_continue @ no, continue 12103 b common_exceptionThrown @ yes, handle exception 12104 12105 /* 12106 * Throw a NoSuchMethodError with the method name as the message. 12107 * r0 = resolved base method 12108 */ 12109.LOP_INVOKE_SUPER_nsm: 12110 ldr r1, [r0, #offMethod_name] @ r1<- method name 12111 b common_errNoSuchMethod 12112 12113/* continuation for OP_INVOKE_DIRECT */ 12114 12115 /* 12116 * On entry: 12117 * r1 = reference (BBBB or CCCC) 12118 * r10 = "this" register 12119 */ 12120.LOP_INVOKE_DIRECT_resolve: 12121 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12122 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12123 mov r2, #METHOD_DIRECT @ resolver method type 12124 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12125 cmp r0, #0 @ got null? 12126 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 12127 bne .LOP_INVOKE_DIRECT_finish @ no, continue 12128 b common_exceptionThrown @ yes, handle exception 12129 12130/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 12131 12132 /* 12133 * At this point: 12134 * r0 = resolved base method 12135 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 12136 */ 12137.LOP_INVOKE_VIRTUAL_RANGE_continue: 12138 GET_VREG(r1, r10) @ r1<- "this" ptr 12139 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12140 cmp r1, #0 @ is "this" null? 12141 beq common_errNullObject @ null "this", throw exception 12142 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 12143 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 12144 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 12145 bl common_invokeMethodRange @ continue on 12146 12147/* continuation for OP_INVOKE_SUPER_RANGE */ 12148 12149 /* 12150 * At this point: 12151 * r0 = resolved base method 12152 * r9 = method->clazz 12153 */ 12154.LOP_INVOKE_SUPER_RANGE_continue: 12155 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 12156 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12157 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 12158 EXPORT_PC() @ must export for invoke 12159 cmp r2, r3 @ compare (methodIndex, vtableCount) 12160 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 12161 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 12162 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 12163 bl common_invokeMethodRange @ continue on 12164 12165.LOP_INVOKE_SUPER_RANGE_resolve: 12166 mov r0, r9 @ r0<- method->clazz 12167 mov r2, #METHOD_VIRTUAL @ resolver method type 12168 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12169 cmp r0, #0 @ got null? 12170 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 12171 b common_exceptionThrown @ yes, handle exception 12172 12173 /* 12174 * Throw a NoSuchMethodError with the method name as the message. 12175 * r0 = resolved base method 12176 */ 12177.LOP_INVOKE_SUPER_RANGE_nsm: 12178 ldr r1, [r0, #offMethod_name] @ r1<- method name 12179 b common_errNoSuchMethod 12180 12181/* continuation for OP_INVOKE_DIRECT_RANGE */ 12182 12183 /* 12184 * On entry: 12185 * r1 = reference (BBBB or CCCC) 12186 * r10 = "this" register 12187 */ 12188.LOP_INVOKE_DIRECT_RANGE_resolve: 12189 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12190 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12191 mov r2, #METHOD_DIRECT @ resolver method type 12192 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12193 cmp r0, #0 @ got null? 12194 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 12195 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 12196 b common_exceptionThrown @ yes, handle exception 12197 12198/* continuation for OP_FLOAT_TO_LONG */ 12199/* 12200 * Convert the float in r0 to a long in r0/r1. 12201 * 12202 * We have to clip values to long min/max per the specification. The 12203 * expected common case is a "reasonable" value that converts directly 12204 * to modest integer. The EABI convert function isn't doing this for us. 12205 */ 12206f2l_doconv: 12207 stmfd sp!, {r4, lr} 12208 mov r1, #0x5f000000 @ (float)maxlong 12209 mov r4, r0 12210 bl __aeabi_fcmpge @ is arg >= maxlong? 12211 cmp r0, #0 @ nonzero == yes 12212 mvnne r0, #0 @ return maxlong (7fffffff) 12213 mvnne r1, #0x80000000 12214 ldmnefd sp!, {r4, pc} 12215 12216 mov r0, r4 @ recover arg 12217 mov r1, #0xdf000000 @ (float)minlong 12218 bl __aeabi_fcmple @ is arg <= minlong? 12219 cmp r0, #0 @ nonzero == yes 12220 movne r0, #0 @ return minlong (80000000) 12221 movne r1, #0x80000000 12222 ldmnefd sp!, {r4, pc} 12223 12224 mov r0, r4 @ recover arg 12225 mov r1, r4 12226 bl __aeabi_fcmpeq @ is arg == self? 12227 cmp r0, #0 @ zero == no 12228 moveq r1, #0 @ return zero for NaN 12229 ldmeqfd sp!, {r4, pc} 12230 12231 mov r0, r4 @ recover arg 12232 bl __aeabi_f2lz @ convert float to long 12233 ldmfd sp!, {r4, pc} 12234 12235/* continuation for OP_DOUBLE_TO_LONG */ 12236/* 12237 * Convert the double in r0/r1 to a long in r0/r1. 12238 * 12239 * We have to clip values to long min/max per the specification. The 12240 * expected common case is a "reasonable" value that converts directly 12241 * to modest integer. The EABI convert function isn't doing this for us. 12242 */ 12243d2l_doconv: 12244 stmfd sp!, {r4, r5, lr} @ save regs 12245 mov r3, #0x43000000 @ maxlong, as a double (high word) 12246 add r3, #0x00e00000 @ 0x43e00000 12247 mov r2, #0 @ maxlong, as a double (low word) 12248 sub sp, sp, #4 @ align for EABI 12249 mov r4, r0 @ save a copy of r0 12250 mov r5, r1 @ and r1 12251 bl __aeabi_dcmpge @ is arg >= maxlong? 12252 cmp r0, #0 @ nonzero == yes 12253 mvnne r0, #0 @ return maxlong (7fffffffffffffff) 12254 mvnne r1, #0x80000000 12255 bne 1f 12256 12257 mov r0, r4 @ recover arg 12258 mov r1, r5 12259 mov r3, #0xc3000000 @ minlong, as a double (high word) 12260 add r3, #0x00e00000 @ 0xc3e00000 12261 mov r2, #0 @ minlong, as a double (low word) 12262 bl __aeabi_dcmple @ is arg <= minlong? 12263 cmp r0, #0 @ nonzero == yes 12264 movne r0, #0 @ return minlong (8000000000000000) 12265 movne r1, #0x80000000 12266 bne 1f 12267 12268 mov r0, r4 @ recover arg 12269 mov r1, r5 12270 mov r2, r4 @ compare against self 12271 mov r3, r5 12272 bl __aeabi_dcmpeq @ is arg == self? 12273 cmp r0, #0 @ zero == no 12274 moveq r1, #0 @ return zero for NaN 12275 beq 1f 12276 12277 mov r0, r4 @ recover arg 12278 mov r1, r5 12279 bl __aeabi_d2lz @ convert double to long 12280 122811: 12282 add sp, sp, #4 12283 ldmfd sp!, {r4, r5, pc} 12284 12285/* continuation for OP_MUL_LONG */ 12286 12287.LOP_MUL_LONG_finish: 12288 GET_INST_OPCODE(ip) @ extract opcode from rINST 12289 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 12290 GOTO_OPCODE(ip) @ jump to next instruction 12291 12292/* continuation for OP_SHL_LONG */ 12293 12294.LOP_SHL_LONG_finish: 12295 mov r0, r0, asl r2 @ r0<- r0 << r2 12296 GET_INST_OPCODE(ip) @ extract opcode from rINST 12297 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12298 GOTO_OPCODE(ip) @ jump to next instruction 12299 12300/* continuation for OP_SHR_LONG */ 12301 12302.LOP_SHR_LONG_finish: 12303 mov r1, r1, asr r2 @ r1<- r1 >> r2 12304 GET_INST_OPCODE(ip) @ extract opcode from rINST 12305 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12306 GOTO_OPCODE(ip) @ jump to next instruction 12307 12308/* continuation for OP_USHR_LONG */ 12309 12310.LOP_USHR_LONG_finish: 12311 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 12312 GET_INST_OPCODE(ip) @ extract opcode from rINST 12313 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12314 GOTO_OPCODE(ip) @ jump to next instruction 12315 12316/* continuation for OP_SHL_LONG_2ADDR */ 12317 12318.LOP_SHL_LONG_2ADDR_finish: 12319 GET_INST_OPCODE(ip) @ extract opcode from rINST 12320 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12321 GOTO_OPCODE(ip) @ jump to next instruction 12322 12323/* continuation for OP_SHR_LONG_2ADDR */ 12324 12325.LOP_SHR_LONG_2ADDR_finish: 12326 GET_INST_OPCODE(ip) @ extract opcode from rINST 12327 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12328 GOTO_OPCODE(ip) @ jump to next instruction 12329 12330/* continuation for OP_USHR_LONG_2ADDR */ 12331 12332.LOP_USHR_LONG_2ADDR_finish: 12333 GET_INST_OPCODE(ip) @ extract opcode from rINST 12334 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12335 GOTO_OPCODE(ip) @ jump to next instruction 12336 12337/* continuation for OP_IGET_VOLATILE */ 12338 12339 /* 12340 * Currently: 12341 * r0 holds resolved field 12342 * r9 holds object 12343 */ 12344.LOP_IGET_VOLATILE_finish: 12345 @bl common_squeak0 12346 cmp r9, #0 @ check object for null 12347 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12348 beq common_errNullObject @ object was null 12349 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12350 SMP_DMB @ acquiring load 12351 mov r2, rINST, lsr #8 @ r2<- A+ 12352 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12353 and r2, r2, #15 @ r2<- A 12354 GET_INST_OPCODE(ip) @ extract opcode from rINST 12355 SET_VREG(r0, r2) @ fp[A]<- r0 12356 GOTO_OPCODE(ip) @ jump to next instruction 12357 12358/* continuation for OP_IPUT_VOLATILE */ 12359 12360 /* 12361 * Currently: 12362 * r0 holds resolved field 12363 * r9 holds object 12364 */ 12365.LOP_IPUT_VOLATILE_finish: 12366 @bl common_squeak0 12367 mov r1, rINST, lsr #8 @ r1<- A+ 12368 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12369 and r1, r1, #15 @ r1<- A 12370 cmp r9, #0 @ check object for null 12371 GET_VREG(r0, r1) @ r0<- fp[A] 12372 beq common_errNullObject @ object was null 12373 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12374 GET_INST_OPCODE(ip) @ extract opcode from rINST 12375 SMP_DMB @ releasing store 12376 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12377 GOTO_OPCODE(ip) @ jump to next instruction 12378 12379/* continuation for OP_SGET_VOLATILE */ 12380 12381 /* 12382 * Continuation if the field has not yet been resolved. 12383 * r1: BBBB field ref 12384 */ 12385.LOP_SGET_VOLATILE_resolve: 12386 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12387 EXPORT_PC() @ resolve() could throw, so export now 12388 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12389 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12390 cmp r0, #0 @ success? 12391 bne .LOP_SGET_VOLATILE_finish @ yes, finish 12392 b common_exceptionThrown @ no, handle exception 12393 12394/* continuation for OP_SPUT_VOLATILE */ 12395 12396 /* 12397 * Continuation if the field has not yet been resolved. 12398 * r1: BBBB field ref 12399 */ 12400.LOP_SPUT_VOLATILE_resolve: 12401 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12402 EXPORT_PC() @ resolve() could throw, so export now 12403 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12404 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12405 cmp r0, #0 @ success? 12406 bne .LOP_SPUT_VOLATILE_finish @ yes, finish 12407 b common_exceptionThrown @ no, handle exception 12408 12409/* continuation for OP_IGET_OBJECT_VOLATILE */ 12410 12411 /* 12412 * Currently: 12413 * r0 holds resolved field 12414 * r9 holds object 12415 */ 12416.LOP_IGET_OBJECT_VOLATILE_finish: 12417 @bl common_squeak0 12418 cmp r9, #0 @ check object for null 12419 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12420 beq common_errNullObject @ object was null 12421 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12422 SMP_DMB @ acquiring load 12423 mov r2, rINST, lsr #8 @ r2<- A+ 12424 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12425 and r2, r2, #15 @ r2<- A 12426 GET_INST_OPCODE(ip) @ extract opcode from rINST 12427 SET_VREG(r0, r2) @ fp[A]<- r0 12428 GOTO_OPCODE(ip) @ jump to next instruction 12429 12430/* continuation for OP_IGET_WIDE_VOLATILE */ 12431 12432 /* 12433 * Currently: 12434 * r0 holds resolved field 12435 * r9 holds object 12436 */ 12437.LOP_IGET_WIDE_VOLATILE_finish: 12438 cmp r9, #0 @ check object for null 12439 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12440 beq common_errNullObject @ object was null 12441 .if 1 12442 add r0, r9, r3 @ r0<- address of field 12443 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 12444 .else 12445 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12446 .endif 12447 mov r2, rINST, lsr #8 @ r2<- A+ 12448 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12449 and r2, r2, #15 @ r2<- A 12450 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 12451 GET_INST_OPCODE(ip) @ extract opcode from rINST 12452 stmia r3, {r0-r1} @ fp[A]<- r0/r1 12453 GOTO_OPCODE(ip) @ jump to next instruction 12454 12455/* continuation for OP_IPUT_WIDE_VOLATILE */ 12456 12457 /* 12458 * Currently: 12459 * r0 holds resolved field 12460 * r9 holds object 12461 */ 12462.LOP_IPUT_WIDE_VOLATILE_finish: 12463 mov r2, rINST, lsr #8 @ r2<- A+ 12464 cmp r9, #0 @ check object for null 12465 and r2, r2, #15 @ r2<- A 12466 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12467 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 12468 beq common_errNullObject @ object was null 12469 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12470 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 12471 GET_INST_OPCODE(r10) @ extract opcode from rINST 12472 .if 1 12473 add r2, r9, r3 @ r2<- target address 12474 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 12475 .else 12476 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12477 .endif 12478 GOTO_OPCODE(r10) @ jump to next instruction 12479 12480/* continuation for OP_SGET_WIDE_VOLATILE */ 12481 12482 /* 12483 * Continuation if the field has not yet been resolved. 12484 * r1: BBBB field ref 12485 * 12486 * Returns StaticField pointer in r0. 12487 */ 12488.LOP_SGET_WIDE_VOLATILE_resolve: 12489 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12490 EXPORT_PC() @ resolve() could throw, so export now 12491 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12492 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12493 cmp r0, #0 @ success? 12494 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 12495 b common_exceptionThrown @ no, handle exception 12496 12497/* continuation for OP_SPUT_WIDE_VOLATILE */ 12498 12499 /* 12500 * Continuation if the field has not yet been resolved. 12501 * r1: BBBB field ref 12502 * r9: &fp[AA] 12503 * 12504 * Returns StaticField pointer in r2. 12505 */ 12506.LOP_SPUT_WIDE_VOLATILE_resolve: 12507 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12508 EXPORT_PC() @ resolve() could throw, so export now 12509 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12510 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12511 cmp r0, #0 @ success? 12512 mov r2, r0 @ copy to r2 12513 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 12514 b common_exceptionThrown @ no, handle exception 12515 12516/* continuation for OP_EXECUTE_INLINE */ 12517 12518 /* 12519 * Extract args, call function. 12520 * r0 = #of args (0-4) 12521 * r10 = call index 12522 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12523 * 12524 * Other ideas: 12525 * - Use a jump table from the main piece to jump directly into the 12526 * AND/LDR pairs. Costs a data load, saves a branch. 12527 * - Have five separate pieces that do the loading, so we can work the 12528 * interleave a little better. Increases code size. 12529 */ 12530.LOP_EXECUTE_INLINE_continue: 12531 rsb r0, r0, #4 @ r0<- 4-r0 12532 FETCH(r9, 2) @ r9<- FEDC 12533 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12534 bl common_abort @ (skipped due to ARM prefetch) 125354: and ip, r9, #0xf000 @ isolate F 12536 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 125373: and ip, r9, #0x0f00 @ isolate E 12538 ldr r2, [rFP, ip, lsr #6] @ r2<- vE 125392: and ip, r9, #0x00f0 @ isolate D 12540 ldr r1, [rFP, ip, lsr #2] @ r1<- vD 125411: and ip, r9, #0x000f @ isolate C 12542 ldr r0, [rFP, ip, lsl #2] @ r0<- vC 125430: 12544 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 12545 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12546 @ (not reached) 12547 12548.LOP_EXECUTE_INLINE_table: 12549 .word gDvmInlineOpsTable 12550 12551/* continuation for OP_EXECUTE_INLINE_RANGE */ 12552 12553 /* 12554 * Extract args, call function. 12555 * r0 = #of args (0-4) 12556 * r10 = call index 12557 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12558 */ 12559.LOP_EXECUTE_INLINE_RANGE_continue: 12560 rsb r0, r0, #4 @ r0<- 4-r0 12561 FETCH(r9, 2) @ r9<- CCCC 12562 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12563 bl common_abort @ (skipped due to ARM prefetch) 125644: add ip, r9, #3 @ base+3 12565 GET_VREG(r3, ip) @ r3<- vBase[3] 125663: add ip, r9, #2 @ base+2 12567 GET_VREG(r2, ip) @ r2<- vBase[2] 125682: add ip, r9, #1 @ base+1 12569 GET_VREG(r1, ip) @ r1<- vBase[1] 125701: add ip, r9, #0 @ (nop) 12571 GET_VREG(r0, ip) @ r0<- vBase[0] 125720: 12573 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 12574 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12575 @ (not reached) 12576 12577.LOP_EXECUTE_INLINE_RANGE_table: 12578 .word gDvmInlineOpsTable 12579 12580/* continuation for OP_IPUT_OBJECT_VOLATILE */ 12581 12582 /* 12583 * Currently: 12584 * r0 holds resolved field 12585 * r9 holds object 12586 */ 12587.LOP_IPUT_OBJECT_VOLATILE_finish: 12588 @bl common_squeak0 12589 mov r1, rINST, lsr #8 @ r1<- A+ 12590 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12591 and r1, r1, #15 @ r1<- A 12592 cmp r9, #0 @ check object for null 12593 GET_VREG(r0, r1) @ r0<- fp[A] 12594 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12595 beq common_errNullObject @ object was null 12596 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12597 GET_INST_OPCODE(ip) @ extract opcode from rINST 12598 SMP_DMB @ releasing store 12599 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12600 cmp r0, #0 @ stored a null reference? 12601 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12602 GOTO_OPCODE(ip) @ jump to next instruction 12603 12604/* continuation for OP_SGET_OBJECT_VOLATILE */ 12605 12606 /* 12607 * Continuation if the field has not yet been resolved. 12608 * r1: BBBB field ref 12609 */ 12610.LOP_SGET_OBJECT_VOLATILE_resolve: 12611 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12612 EXPORT_PC() @ resolve() could throw, so export now 12613 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12614 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12615 cmp r0, #0 @ success? 12616 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 12617 b common_exceptionThrown @ no, handle exception 12618 12619/* continuation for OP_SPUT_OBJECT_VOLATILE */ 12620.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 12621 mov r2, rINST, lsr #8 @ r2<- AA 12622 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12623 GET_VREG(r1, r2) @ r1<- fp[AA] 12624 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12625 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 12626 GET_INST_OPCODE(ip) @ extract opcode from rINST 12627 SMP_DMB @ releasing store 12628 str r1, [r0, #offStaticField_value] @ field<- vAA 12629 cmp r1, #0 @ stored a null object? 12630 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12631 GOTO_OPCODE(ip) @ jump to next instruction 12632 12633/* continuation for OP_CONST_CLASS_JUMBO */ 12634 12635 /* 12636 * Continuation if the Class has not yet been resolved. 12637 * r1: AAAAAAAA (Class ref) 12638 * r9: target register 12639 */ 12640.LOP_CONST_CLASS_JUMBO_resolve: 12641 EXPORT_PC() 12642 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12643 mov r2, #1 @ r2<- true 12644 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12645 bl dvmResolveClass @ r0<- Class reference 12646 cmp r0, #0 @ failed? 12647 beq common_exceptionThrown @ yup, handle the exception 12648 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12649 GET_INST_OPCODE(ip) @ extract opcode from rINST 12650 SET_VREG(r0, r9) @ vBBBB<- r0 12651 GOTO_OPCODE(ip) @ jump to next instruction 12652 12653/* continuation for OP_CHECK_CAST_JUMBO */ 12654 12655 /* 12656 * Trivial test failed, need to perform full check. This is common. 12657 * r0 holds obj->clazz 12658 * r1 holds desired class resolved from AAAAAAAA 12659 * r9 holds object 12660 */ 12661.LOP_CHECK_CAST_JUMBO_fullcheck: 12662 mov r10, r1 @ avoid ClassObject getting clobbered 12663 bl dvmInstanceofNonTrivial @ r0<- boolean result 12664 cmp r0, #0 @ failed? 12665 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success 12666 12667 @ A cast has failed. We need to throw a ClassCastException. 12668 EXPORT_PC() @ about to throw 12669 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 12670 mov r1, r10 @ r1<- desired class 12671 bl dvmThrowClassCastException 12672 b common_exceptionThrown 12673 12674 /* 12675 * Advance PC and get the next opcode. 12676 */ 12677.LOP_CHECK_CAST_JUMBO_okay: 12678 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12679 GET_INST_OPCODE(ip) @ extract opcode from rINST 12680 GOTO_OPCODE(ip) @ jump to next instruction 12681 12682 /* 12683 * Resolution required. This is the least-likely path. 12684 * 12685 * r2 holds AAAAAAAA 12686 * r9 holds object 12687 */ 12688.LOP_CHECK_CAST_JUMBO_resolve: 12689 EXPORT_PC() @ resolve() could throw 12690 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12691 mov r1, r2 @ r1<- AAAAAAAA 12692 mov r2, #0 @ r2<- false 12693 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12694 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12695 cmp r0, #0 @ got null? 12696 beq common_exceptionThrown @ yes, handle exception 12697 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12698 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 12699 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off 12700 12701/* continuation for OP_INSTANCE_OF_JUMBO */ 12702 12703 /* 12704 * Class resolved, determine type of check necessary. This is common. 12705 * r0 holds obj->clazz 12706 * r1 holds class resolved from AAAAAAAA 12707 * r9 holds BBBB 12708 */ 12709.LOP_INSTANCE_OF_JUMBO_resolved: 12710 cmp r0, r1 @ same class (trivial success)? 12711 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish 12712 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck 12713 12714 /* 12715 * Trivial test failed, need to perform full check. This is common. 12716 * r0 holds obj->clazz 12717 * r1 holds class resolved from AAAAAAAA 12718 * r9 holds BBBB 12719 */ 12720.LOP_INSTANCE_OF_JUMBO_fullcheck: 12721 bl dvmInstanceofNonTrivial @ r0<- boolean result 12722 @ fall through to OP_INSTANCE_OF_JUMBO_store 12723 12724 /* 12725 * r0 holds boolean result 12726 * r9 holds BBBB 12727 */ 12728.LOP_INSTANCE_OF_JUMBO_store: 12729 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12730 SET_VREG(r0, r9) @ vBBBB<- r0 12731 GET_INST_OPCODE(ip) @ extract opcode from rINST 12732 GOTO_OPCODE(ip) @ jump to next instruction 12733 12734 /* 12735 * Trivial test succeeded, save and bail. 12736 * r9 holds BBBB 12737 */ 12738.LOP_INSTANCE_OF_JUMBO_trivial: 12739 mov r0, #1 @ indicate success 12740 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper 12741 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12742 SET_VREG(r0, r9) @ vBBBB<- r0 12743 GET_INST_OPCODE(ip) @ extract opcode from rINST 12744 GOTO_OPCODE(ip) @ jump to next instruction 12745 12746 /* 12747 * Resolution required. This is the least-likely path. 12748 * 12749 * r3 holds AAAAAAAA 12750 * r9 holds BBBB 12751 */ 12752 12753.LOP_INSTANCE_OF_JUMBO_resolve: 12754 EXPORT_PC() @ resolve() could throw 12755 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12756 mov r1, r3 @ r1<- AAAAAAAA 12757 mov r2, #1 @ r2<- true 12758 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12759 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12760 cmp r0, #0 @ got null? 12761 beq common_exceptionThrown @ yes, handle exception 12762 FETCH(r3, 4) @ r3<- vCCCC 12763 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12764 GET_VREG(r0, r3) @ r0<- vCCCC (object) 12765 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 12766 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off 12767 12768/* continuation for OP_NEW_INSTANCE_JUMBO */ 12769 12770 .balign 32 @ minimize cache lines 12771.LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object 12772 FETCH(r3, 3) @ r3<- BBBB 12773 cmp r0, #0 @ failed? 12774 beq common_exceptionThrown @ yes, handle the exception 12775 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12776 GET_INST_OPCODE(ip) @ extract opcode from rINST 12777 SET_VREG(r0, r3) @ vBBBB<- r0 12778 GOTO_OPCODE(ip) @ jump to next instruction 12779 12780 /* 12781 * Class initialization required. 12782 * 12783 * r0 holds class object 12784 */ 12785.LOP_NEW_INSTANCE_JUMBO_needinit: 12786 mov r9, r0 @ save r0 12787 bl dvmInitClass @ initialize class 12788 cmp r0, #0 @ check boolean result 12789 mov r0, r9 @ restore r0 12790 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue 12791 b common_exceptionThrown @ failed, deal with init exception 12792 12793 /* 12794 * Resolution required. This is the least-likely path. 12795 * 12796 * r1 holds AAAAAAAA 12797 */ 12798.LOP_NEW_INSTANCE_JUMBO_resolve: 12799 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12800 mov r2, #0 @ r2<- false 12801 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12802 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12803 cmp r0, #0 @ got null? 12804 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue 12805 b common_exceptionThrown @ yes, handle exception 12806 12807/* continuation for OP_NEW_ARRAY_JUMBO */ 12808 12809 12810 /* 12811 * Resolve class. (This is an uncommon case.) 12812 * 12813 * r1 holds array length 12814 * r2 holds class ref AAAAAAAA 12815 */ 12816.LOP_NEW_ARRAY_JUMBO_resolve: 12817 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12818 mov r9, r1 @ r9<- length (save) 12819 mov r1, r2 @ r1<- AAAAAAAA 12820 mov r2, #0 @ r2<- false 12821 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12822 bl dvmResolveClass @ r0<- call(clazz, ref) 12823 cmp r0, #0 @ got null? 12824 mov r1, r9 @ r1<- length (restore) 12825 beq common_exceptionThrown @ yes, handle exception 12826 @ fall through to OP_NEW_ARRAY_JUMBO_finish 12827 12828 /* 12829 * Finish allocation. 12830 * 12831 * r0 holds class 12832 * r1 holds array length 12833 */ 12834.LOP_NEW_ARRAY_JUMBO_finish: 12835 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 12836 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 12837 cmp r0, #0 @ failed? 12838 FETCH(r2, 3) @ r2<- vBBBB 12839 beq common_exceptionThrown @ yes, handle the exception 12840 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12841 GET_INST_OPCODE(ip) @ extract opcode from rINST 12842 SET_VREG(r0, r2) @ vBBBB<- r0 12843 GOTO_OPCODE(ip) @ jump to next instruction 12844 12845/* continuation for OP_FILLED_NEW_ARRAY_JUMBO */ 12846 12847 /* 12848 * On entry: 12849 * r0 holds array class 12850 */ 12851.LOP_FILLED_NEW_ARRAY_JUMBO_continue: 12852 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 12853 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 12854 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 12855 FETCH(r1, 3) @ r1<- BBBB (length) 12856 cmp rINST, #'I' @ array of ints? 12857 cmpne rINST, #'L' @ array of objects? 12858 cmpne rINST, #'[' @ array of arrays? 12859 mov r9, r1 @ save length in r9 12860 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet 12861 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 12862 cmp r0, #0 @ null return? 12863 beq common_exceptionThrown @ alloc failed, handle exception 12864 12865 FETCH(r1, 4) @ r1<- CCCC 12866 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 12867 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 12868 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 12869 subs r9, r9, #1 @ length--, check for neg 12870 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST 12871 bmi 2f @ was zero, bail 12872 12873 @ copy values from registers into the array 12874 @ r0=array, r1=CCCC, r9=BBBB (length) 12875 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 128761: ldr r3, [r2], #4 @ r3<- *r2++ 12877 subs r9, r9, #1 @ count-- 12878 str r3, [r0], #4 @ *contents++ = vX 12879 bpl 1b 12880 128812: ldr r0, [rSELF, #offThread_retval] @ r0<- object 12882 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 12883 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12884 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 12885 cmp r1, #'I' @ Is int array? 12886 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 12887 GOTO_OPCODE(ip) @ execute it 12888 12889 /* 12890 * Throw an exception indicating that we have not implemented this 12891 * mode of filled-new-array. 12892 */ 12893.LOP_FILLED_NEW_ARRAY_JUMBO_notimpl: 12894 ldr r0, .L_strFilledNewArrayNotImpl 12895 bl dvmThrowInternalError 12896 b common_exceptionThrown 12897 12898/* continuation for OP_IGET_JUMBO */ 12899 12900 /* 12901 * Currently: 12902 * r0 holds resolved field 12903 * r9 holds object 12904 */ 12905.LOP_IGET_JUMBO_resolved: 12906 cmp r0, #0 @ resolution unsuccessful? 12907 beq common_exceptionThrown @ yes, throw exception 12908 @ fall through to OP_IGET_JUMBO_finish 12909 12910 /* 12911 * Currently: 12912 * r0 holds resolved field 12913 * r9 holds object 12914 */ 12915.LOP_IGET_JUMBO_finish: 12916 @bl common_squeak0 12917 cmp r9, #0 @ check object for null 12918 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12919 beq common_errNullObject @ object was null 12920 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12921 @ no-op @ acquiring load 12922 FETCH(r2, 3) @ r2<- BBBB 12923 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12924 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12925 GET_INST_OPCODE(ip) @ extract opcode from rINST 12926 GOTO_OPCODE(ip) @ jump to next instruction 12927 12928/* continuation for OP_IGET_WIDE_JUMBO */ 12929 12930 /* 12931 * Currently: 12932 * r0 holds resolved field 12933 * r9 holds object 12934 */ 12935.LOP_IGET_WIDE_JUMBO_resolved: 12936 cmp r0, #0 @ resolution unsuccessful? 12937 beq common_exceptionThrown @ yes, throw exception 12938 @ fall through to OP_IGET_WIDE_JUMBO_finish 12939 12940 /* 12941 * Currently: 12942 * r0 holds resolved field 12943 * r9 holds object 12944 */ 12945.LOP_IGET_WIDE_JUMBO_finish: 12946 cmp r9, #0 @ check object for null 12947 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12948 beq common_errNullObject @ object was null 12949 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12950 FETCH(r2, 3) @ r2<- BBBB 12951 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12952 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 12953 GET_INST_OPCODE(ip) @ extract opcode from rINST 12954 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 12955 GOTO_OPCODE(ip) @ jump to next instruction 12956 12957/* continuation for OP_IGET_OBJECT_JUMBO */ 12958 12959 /* 12960 * Currently: 12961 * r0 holds resolved field 12962 * r9 holds object 12963 */ 12964.LOP_IGET_OBJECT_JUMBO_resolved: 12965 cmp r0, #0 @ resolution unsuccessful? 12966 beq common_exceptionThrown @ yes, throw exception 12967 @ fall through to OP_IGET_OBJECT_JUMBO_finish 12968 12969 /* 12970 * Currently: 12971 * r0 holds resolved field 12972 * r9 holds object 12973 */ 12974.LOP_IGET_OBJECT_JUMBO_finish: 12975 @bl common_squeak0 12976 cmp r9, #0 @ check object for null 12977 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12978 beq common_errNullObject @ object was null 12979 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12980 @ no-op @ acquiring load 12981 FETCH(r2, 3) @ r2<- BBBB 12982 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12983 SET_VREG(r0, r2) @ fp[BBBB]<- r0 12984 GET_INST_OPCODE(ip) @ extract opcode from rINST 12985 GOTO_OPCODE(ip) @ jump to next instruction 12986 12987/* continuation for OP_IGET_BOOLEAN_JUMBO */ 12988 12989 /* 12990 * Currently: 12991 * r0 holds resolved field 12992 * r9 holds object 12993 */ 12994.LOP_IGET_BOOLEAN_JUMBO_resolved: 12995 cmp r0, #0 @ resolution unsuccessful? 12996 beq common_exceptionThrown @ yes, throw exception 12997 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish 12998 12999 /* 13000 * Currently: 13001 * r0 holds resolved field 13002 * r9 holds object 13003 */ 13004.LOP_IGET_BOOLEAN_JUMBO_finish: 13005 @bl common_squeak1 13006 cmp r9, #0 @ check object for null 13007 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13008 beq common_errNullObject @ object was null 13009 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13010 @ no-op @ acquiring load 13011 FETCH(r2, 3) @ r2<- BBBB 13012 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13013 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13014 GET_INST_OPCODE(ip) @ extract opcode from rINST 13015 GOTO_OPCODE(ip) @ jump to next instruction 13016 13017/* continuation for OP_IGET_BYTE_JUMBO */ 13018 13019 /* 13020 * Currently: 13021 * r0 holds resolved field 13022 * r9 holds object 13023 */ 13024.LOP_IGET_BYTE_JUMBO_resolved: 13025 cmp r0, #0 @ resolution unsuccessful? 13026 beq common_exceptionThrown @ yes, throw exception 13027 @ fall through to OP_IGET_BYTE_JUMBO_finish 13028 13029 /* 13030 * Currently: 13031 * r0 holds resolved field 13032 * r9 holds object 13033 */ 13034.LOP_IGET_BYTE_JUMBO_finish: 13035 @bl common_squeak2 13036 cmp r9, #0 @ check object for null 13037 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13038 beq common_errNullObject @ object was null 13039 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13040 @ no-op @ acquiring load 13041 FETCH(r2, 3) @ r2<- BBBB 13042 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13043 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13044 GET_INST_OPCODE(ip) @ extract opcode from rINST 13045 GOTO_OPCODE(ip) @ jump to next instruction 13046 13047/* continuation for OP_IGET_CHAR_JUMBO */ 13048 13049 /* 13050 * Currently: 13051 * r0 holds resolved field 13052 * r9 holds object 13053 */ 13054.LOP_IGET_CHAR_JUMBO_resolved: 13055 cmp r0, #0 @ resolution unsuccessful? 13056 beq common_exceptionThrown @ yes, throw exception 13057 @ fall through to OP_IGET_CHAR_JUMBO_finish 13058 13059 /* 13060 * Currently: 13061 * r0 holds resolved field 13062 * r9 holds object 13063 */ 13064.LOP_IGET_CHAR_JUMBO_finish: 13065 @bl common_squeak3 13066 cmp r9, #0 @ check object for null 13067 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13068 beq common_errNullObject @ object was null 13069 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13070 @ no-op @ acquiring load 13071 FETCH(r2, 3) @ r2<- BBBB 13072 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13073 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13074 GET_INST_OPCODE(ip) @ extract opcode from rINST 13075 GOTO_OPCODE(ip) @ jump to next instruction 13076 13077/* continuation for OP_IGET_SHORT_JUMBO */ 13078 13079 /* 13080 * Currently: 13081 * r0 holds resolved field 13082 * r9 holds object 13083 */ 13084.LOP_IGET_SHORT_JUMBO_resolved: 13085 cmp r0, #0 @ resolution unsuccessful? 13086 beq common_exceptionThrown @ yes, throw exception 13087 @ fall through to OP_IGET_SHORT_JUMBO_finish 13088 13089 /* 13090 * Currently: 13091 * r0 holds resolved field 13092 * r9 holds object 13093 */ 13094.LOP_IGET_SHORT_JUMBO_finish: 13095 @bl common_squeak4 13096 cmp r9, #0 @ check object for null 13097 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13098 beq common_errNullObject @ object was null 13099 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13100 @ no-op @ acquiring load 13101 FETCH(r2, 3) @ r2<- BBBB 13102 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13103 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13104 GET_INST_OPCODE(ip) @ extract opcode from rINST 13105 GOTO_OPCODE(ip) @ jump to next instruction 13106 13107/* continuation for OP_IPUT_JUMBO */ 13108 13109 /* 13110 * Currently: 13111 * r0 holds resolved field 13112 * r9 holds object 13113 */ 13114.LOP_IPUT_JUMBO_resolved: 13115 cmp r0, #0 @ resolution unsuccessful? 13116 beq common_exceptionThrown @ yes, throw exception 13117 @ fall through to OP_IPUT_JUMBO_finish 13118 13119 /* 13120 * Currently: 13121 * r0 holds resolved field 13122 * r9 holds object 13123 */ 13124.LOP_IPUT_JUMBO_finish: 13125 @bl common_squeak0 13126 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13127 FETCH(r1, 3) @ r1<- BBBB 13128 cmp r9, #0 @ check object for null 13129 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13130 beq common_errNullObject @ object was null 13131 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13132 GET_INST_OPCODE(ip) @ extract opcode from rINST 13133 @ no-op @ releasing store 13134 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13135 GOTO_OPCODE(ip) @ jump to next instruction 13136 13137/* continuation for OP_IPUT_WIDE_JUMBO */ 13138 13139 /* 13140 * Currently: 13141 * r0 holds resolved field 13142 * r9 holds object 13143 */ 13144.LOP_IPUT_WIDE_JUMBO_resolved: 13145 cmp r0, #0 @ resolution unsuccessful? 13146 beq common_exceptionThrown @ yes, throw exception 13147 @ fall through to OP_IPUT_WIDE_JUMBO_finish 13148 13149 /* 13150 * Currently: 13151 * r0 holds resolved field 13152 * r9 holds object 13153 */ 13154.LOP_IPUT_WIDE_JUMBO_finish: 13155 cmp r9, #0 @ check object for null 13156 FETCH(r2, 3) @ r1<- BBBB 13157 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13158 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 13159 beq common_errNullObject @ object was null 13160 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13161 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 13162 GET_INST_OPCODE(r10) @ extract opcode from rINST 13163 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 13164 GOTO_OPCODE(r10) @ jump to next instruction 13165 13166/* continuation for OP_IPUT_OBJECT_JUMBO */ 13167 13168 /* 13169 * Currently: 13170 * r0 holds resolved field 13171 * r9 holds object 13172 */ 13173.LOP_IPUT_OBJECT_JUMBO_resolved: 13174 cmp r0, #0 @ resolution unsuccessful? 13175 beq common_exceptionThrown @ yes, throw exception 13176 @ fall through to OP_IPUT_OBJECT_JUMBO_finish 13177 13178 /* 13179 * Currently: 13180 * r0 holds resolved field 13181 * r9 holds object 13182 */ 13183.LOP_IPUT_OBJECT_JUMBO_finish: 13184 @bl common_squeak0 13185 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13186 FETCH(r1, 3) @ r1<- BBBB 13187 cmp r9, #0 @ check object for null 13188 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13189 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13190 beq common_errNullObject @ object was null 13191 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13192 GET_INST_OPCODE(ip) @ extract opcode from rINST 13193 @ no-op @ releasing store 13194 str r0, [r9, r3] @ obj.field (32 bits)<- r0 13195 cmp r0, #0 @ stored a null reference? 13196 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 13197 GOTO_OPCODE(ip) @ jump to next instruction 13198 13199/* continuation for OP_IPUT_BOOLEAN_JUMBO */ 13200 13201 /* 13202 * Currently: 13203 * r0 holds resolved field 13204 * r9 holds object 13205 */ 13206.LOP_IPUT_BOOLEAN_JUMBO_resolved: 13207 cmp r0, #0 @ resolution unsuccessful? 13208 beq common_exceptionThrown @ yes, throw exception 13209 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish 13210 13211 /* 13212 * Currently: 13213 * r0 holds resolved field 13214 * r9 holds object 13215 */ 13216.LOP_IPUT_BOOLEAN_JUMBO_finish: 13217 @bl common_squeak1 13218 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13219 FETCH(r1, 3) @ r1<- BBBB 13220 cmp r9, #0 @ check object for null 13221 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13222 beq common_errNullObject @ object was null 13223 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13224 GET_INST_OPCODE(ip) @ extract opcode from rINST 13225 @ no-op @ releasing store 13226 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13227 GOTO_OPCODE(ip) @ jump to next instruction 13228 13229/* continuation for OP_IPUT_BYTE_JUMBO */ 13230 13231 /* 13232 * Currently: 13233 * r0 holds resolved field 13234 * r9 holds object 13235 */ 13236.LOP_IPUT_BYTE_JUMBO_resolved: 13237 cmp r0, #0 @ resolution unsuccessful? 13238 beq common_exceptionThrown @ yes, throw exception 13239 @ fall through to OP_IPUT_BYTE_JUMBO_finish 13240 13241 /* 13242 * Currently: 13243 * r0 holds resolved field 13244 * r9 holds object 13245 */ 13246.LOP_IPUT_BYTE_JUMBO_finish: 13247 @bl common_squeak2 13248 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13249 FETCH(r1, 3) @ r1<- BBBB 13250 cmp r9, #0 @ check object for null 13251 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13252 beq common_errNullObject @ object was null 13253 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13254 GET_INST_OPCODE(ip) @ extract opcode from rINST 13255 @ no-op @ releasing store 13256 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13257 GOTO_OPCODE(ip) @ jump to next instruction 13258 13259/* continuation for OP_IPUT_CHAR_JUMBO */ 13260 13261 /* 13262 * Currently: 13263 * r0 holds resolved field 13264 * r9 holds object 13265 */ 13266.LOP_IPUT_CHAR_JUMBO_resolved: 13267 cmp r0, #0 @ resolution unsuccessful? 13268 beq common_exceptionThrown @ yes, throw exception 13269 @ fall through to OP_IPUT_CHAR_JUMBO_finish 13270 13271 /* 13272 * Currently: 13273 * r0 holds resolved field 13274 * r9 holds object 13275 */ 13276.LOP_IPUT_CHAR_JUMBO_finish: 13277 @bl common_squeak3 13278 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13279 FETCH(r1, 3) @ r1<- BBBB 13280 cmp r9, #0 @ check object for null 13281 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13282 beq common_errNullObject @ object was null 13283 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13284 GET_INST_OPCODE(ip) @ extract opcode from rINST 13285 @ no-op @ releasing store 13286 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13287 GOTO_OPCODE(ip) @ jump to next instruction 13288 13289/* continuation for OP_IPUT_SHORT_JUMBO */ 13290 13291 /* 13292 * Currently: 13293 * r0 holds resolved field 13294 * r9 holds object 13295 */ 13296.LOP_IPUT_SHORT_JUMBO_resolved: 13297 cmp r0, #0 @ resolution unsuccessful? 13298 beq common_exceptionThrown @ yes, throw exception 13299 @ fall through to OP_IPUT_SHORT_JUMBO_finish 13300 13301 /* 13302 * Currently: 13303 * r0 holds resolved field 13304 * r9 holds object 13305 */ 13306.LOP_IPUT_SHORT_JUMBO_finish: 13307 @bl common_squeak4 13308 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13309 FETCH(r1, 3) @ r1<- BBBB 13310 cmp r9, #0 @ check object for null 13311 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13312 beq common_errNullObject @ object was null 13313 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13314 GET_INST_OPCODE(ip) @ extract opcode from rINST 13315 @ no-op @ releasing store 13316 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13317 GOTO_OPCODE(ip) @ jump to next instruction 13318 13319/* continuation for OP_SGET_JUMBO */ 13320 13321 /* 13322 * Continuation if the field has not yet been resolved. 13323 * r1: AAAAAAAA field ref 13324 */ 13325.LOP_SGET_JUMBO_resolve: 13326 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13327 EXPORT_PC() @ resolve() could throw, so export now 13328 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13329 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13330 cmp r0, #0 @ success? 13331 bne .LOP_SGET_JUMBO_finish @ yes, finish 13332 b common_exceptionThrown @ no, handle exception 13333 13334/* continuation for OP_SGET_WIDE_JUMBO */ 13335 13336 /* 13337 * Continuation if the field has not yet been resolved. 13338 * r1: BBBB field ref 13339 * 13340 * Returns StaticField pointer in r0. 13341 */ 13342.LOP_SGET_WIDE_JUMBO_resolve: 13343 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13344 EXPORT_PC() @ resolve() could throw, so export now 13345 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13346 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13347 cmp r0, #0 @ success? 13348 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish 13349 b common_exceptionThrown @ no, handle exception 13350 13351/* continuation for OP_SGET_OBJECT_JUMBO */ 13352 13353 /* 13354 * Continuation if the field has not yet been resolved. 13355 * r1: AAAAAAAA field ref 13356 */ 13357.LOP_SGET_OBJECT_JUMBO_resolve: 13358 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13359 EXPORT_PC() @ resolve() could throw, so export now 13360 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13361 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13362 cmp r0, #0 @ success? 13363 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish 13364 b common_exceptionThrown @ no, handle exception 13365 13366/* continuation for OP_SGET_BOOLEAN_JUMBO */ 13367 13368 /* 13369 * Continuation if the field has not yet been resolved. 13370 * r1: AAAAAAAA field ref 13371 */ 13372.LOP_SGET_BOOLEAN_JUMBO_resolve: 13373 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13374 EXPORT_PC() @ resolve() could throw, so export now 13375 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13376 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13377 cmp r0, #0 @ success? 13378 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish 13379 b common_exceptionThrown @ no, handle exception 13380 13381/* continuation for OP_SGET_BYTE_JUMBO */ 13382 13383 /* 13384 * Continuation if the field has not yet been resolved. 13385 * r1: AAAAAAAA field ref 13386 */ 13387.LOP_SGET_BYTE_JUMBO_resolve: 13388 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13389 EXPORT_PC() @ resolve() could throw, so export now 13390 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13391 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13392 cmp r0, #0 @ success? 13393 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish 13394 b common_exceptionThrown @ no, handle exception 13395 13396/* continuation for OP_SGET_CHAR_JUMBO */ 13397 13398 /* 13399 * Continuation if the field has not yet been resolved. 13400 * r1: AAAAAAAA field ref 13401 */ 13402.LOP_SGET_CHAR_JUMBO_resolve: 13403 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13404 EXPORT_PC() @ resolve() could throw, so export now 13405 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13406 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13407 cmp r0, #0 @ success? 13408 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish 13409 b common_exceptionThrown @ no, handle exception 13410 13411/* continuation for OP_SGET_SHORT_JUMBO */ 13412 13413 /* 13414 * Continuation if the field has not yet been resolved. 13415 * r1: AAAAAAAA field ref 13416 */ 13417.LOP_SGET_SHORT_JUMBO_resolve: 13418 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13419 EXPORT_PC() @ resolve() could throw, so export now 13420 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13421 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13422 cmp r0, #0 @ success? 13423 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish 13424 b common_exceptionThrown @ no, handle exception 13425 13426/* continuation for OP_SPUT_JUMBO */ 13427 13428 /* 13429 * Continuation if the field has not yet been resolved. 13430 * r1: AAAAAAAA field ref 13431 */ 13432.LOP_SPUT_JUMBO_resolve: 13433 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13434 EXPORT_PC() @ resolve() could throw, so export now 13435 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13436 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13437 cmp r0, #0 @ success? 13438 bne .LOP_SPUT_JUMBO_finish @ yes, finish 13439 b common_exceptionThrown @ no, handle exception 13440 13441/* continuation for OP_SPUT_WIDE_JUMBO */ 13442 13443 /* 13444 * Continuation if the field has not yet been resolved. 13445 * r1: BBBB field ref 13446 * r9: &fp[AA] 13447 * 13448 * Returns StaticField pointer in r2. 13449 */ 13450.LOP_SPUT_WIDE_JUMBO_resolve: 13451 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13452 EXPORT_PC() @ resolve() could throw, so export now 13453 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13454 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13455 cmp r0, #0 @ success? 13456 mov r2, r0 @ copy to r2 13457 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish 13458 b common_exceptionThrown @ no, handle exception 13459 13460/* continuation for OP_SPUT_OBJECT_JUMBO */ 13461 13462.LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0 13463 FETCH(r2, 3) @ r2<- BBBB 13464 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 13465 GET_VREG(r1, r2) @ r1<- fp[BBBB] 13466 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13467 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 13468 GET_INST_OPCODE(ip) @ extract opcode from rINST 13469 @ no-op @ releasing store 13470 str r1, [r0, #offStaticField_value] @ field<- vBBBB 13471 cmp r1, #0 @ stored a null object? 13472 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 13473 GOTO_OPCODE(ip) @ jump to next instruction 13474 13475/* continuation for OP_SPUT_BOOLEAN_JUMBO */ 13476 13477 /* 13478 * Continuation if the field has not yet been resolved. 13479 * r1: AAAAAAAA field ref 13480 */ 13481.LOP_SPUT_BOOLEAN_JUMBO_resolve: 13482 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13483 EXPORT_PC() @ resolve() could throw, so export now 13484 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13485 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13486 cmp r0, #0 @ success? 13487 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish 13488 b common_exceptionThrown @ no, handle exception 13489 13490/* continuation for OP_SPUT_BYTE_JUMBO */ 13491 13492 /* 13493 * Continuation if the field has not yet been resolved. 13494 * r1: AAAAAAAA field ref 13495 */ 13496.LOP_SPUT_BYTE_JUMBO_resolve: 13497 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13498 EXPORT_PC() @ resolve() could throw, so export now 13499 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13500 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13501 cmp r0, #0 @ success? 13502 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish 13503 b common_exceptionThrown @ no, handle exception 13504 13505/* continuation for OP_SPUT_CHAR_JUMBO */ 13506 13507 /* 13508 * Continuation if the field has not yet been resolved. 13509 * r1: AAAAAAAA field ref 13510 */ 13511.LOP_SPUT_CHAR_JUMBO_resolve: 13512 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13513 EXPORT_PC() @ resolve() could throw, so export now 13514 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13515 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13516 cmp r0, #0 @ success? 13517 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish 13518 b common_exceptionThrown @ no, handle exception 13519 13520/* continuation for OP_SPUT_SHORT_JUMBO */ 13521 13522 /* 13523 * Continuation if the field has not yet been resolved. 13524 * r1: AAAAAAAA field ref 13525 */ 13526.LOP_SPUT_SHORT_JUMBO_resolve: 13527 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13528 EXPORT_PC() @ resolve() could throw, so export now 13529 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13530 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13531 cmp r0, #0 @ success? 13532 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish 13533 b common_exceptionThrown @ no, handle exception 13534 13535/* continuation for OP_INVOKE_VIRTUAL_JUMBO */ 13536 13537 /* 13538 * At this point: 13539 * r0 = resolved base method 13540 */ 13541.LOP_INVOKE_VIRTUAL_JUMBO_continue: 13542 FETCH(r10, 4) @ r10<- CCCC 13543 GET_VREG(r1, r10) @ r1<- "this" ptr 13544 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13545 cmp r1, #0 @ is "this" null? 13546 beq common_errNullObject @ null "this", throw exception 13547 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 13548 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 13549 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 13550 bl common_invokeMethodJumbo @ continue on 13551 13552/* continuation for OP_INVOKE_SUPER_JUMBO */ 13553 13554 /* 13555 * At this point: 13556 * r0 = resolved base method 13557 * r9 = method->clazz 13558 */ 13559.LOP_INVOKE_SUPER_JUMBO_continue: 13560 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 13561 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13562 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 13563 EXPORT_PC() @ must export for invoke 13564 cmp r2, r3 @ compare (methodIndex, vtableCount) 13565 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass 13566 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 13567 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 13568 bl common_invokeMethodJumbo @ continue on 13569 13570.LOP_INVOKE_SUPER_JUMBO_resolve: 13571 mov r0, r9 @ r0<- method->clazz 13572 mov r2, #METHOD_VIRTUAL @ resolver method type 13573 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13574 cmp r0, #0 @ got null? 13575 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue 13576 b common_exceptionThrown @ yes, handle exception 13577 13578 /* 13579 * Throw a NoSuchMethodError with the method name as the message. 13580 * r0 = resolved base method 13581 */ 13582.LOP_INVOKE_SUPER_JUMBO_nsm: 13583 ldr r1, [r0, #offMethod_name] @ r1<- method name 13584 b common_errNoSuchMethod 13585 13586/* continuation for OP_INVOKE_DIRECT_JUMBO */ 13587 13588 /* 13589 * On entry: 13590 * r1 = reference (CCCC) 13591 * r10 = "this" register 13592 */ 13593.LOP_INVOKE_DIRECT_JUMBO_resolve: 13594 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13595 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13596 mov r2, #METHOD_DIRECT @ resolver method type 13597 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 13598 cmp r0, #0 @ got null? 13599 GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 13600 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue 13601 b common_exceptionThrown @ yes, handle exception 13602 13603 .size dvmAsmSisterStart, .-dvmAsmSisterStart 13604 .global dvmAsmSisterEnd 13605dvmAsmSisterEnd: 13606 13607 13608 .global dvmAsmAltInstructionStart 13609 .type dvmAsmAltInstructionStart, %function 13610dvmAsmAltInstructionStart: 13611 .text 13612 13613/* ------------------------------ */ 13614 .balign 64 13615.L_ALT_OP_NOP: /* 0x00 */ 13616/* File: armv5te/ALT_STUB.S */ 13617/* 13618 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13619 * any interesting requests and then jump to the real instruction 13620 * handler. Note that the call to dvmCheckInst is done as a tail call. 13621 */ 13622 adrl lr, dvmAsmInstructionStart + (0 * 64) 13623 mov r0, rPC @ arg0 13624 mov r1, rSELF @ arg1 13625 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13626 13627/* ------------------------------ */ 13628 .balign 64 13629.L_ALT_OP_MOVE: /* 0x01 */ 13630/* File: armv5te/ALT_STUB.S */ 13631/* 13632 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13633 * any interesting requests and then jump to the real instruction 13634 * handler. Note that the call to dvmCheckInst is done as a tail call. 13635 */ 13636 adrl lr, dvmAsmInstructionStart + (1 * 64) 13637 mov r0, rPC @ arg0 13638 mov r1, rSELF @ arg1 13639 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13640 13641/* ------------------------------ */ 13642 .balign 64 13643.L_ALT_OP_MOVE_FROM16: /* 0x02 */ 13644/* File: armv5te/ALT_STUB.S */ 13645/* 13646 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13647 * any interesting requests and then jump to the real instruction 13648 * handler. Note that the call to dvmCheckInst is done as a tail call. 13649 */ 13650 adrl lr, dvmAsmInstructionStart + (2 * 64) 13651 mov r0, rPC @ arg0 13652 mov r1, rSELF @ arg1 13653 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13654 13655/* ------------------------------ */ 13656 .balign 64 13657.L_ALT_OP_MOVE_16: /* 0x03 */ 13658/* File: armv5te/ALT_STUB.S */ 13659/* 13660 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13661 * any interesting requests and then jump to the real instruction 13662 * handler. Note that the call to dvmCheckInst is done as a tail call. 13663 */ 13664 adrl lr, dvmAsmInstructionStart + (3 * 64) 13665 mov r0, rPC @ arg0 13666 mov r1, rSELF @ arg1 13667 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13668 13669/* ------------------------------ */ 13670 .balign 64 13671.L_ALT_OP_MOVE_WIDE: /* 0x04 */ 13672/* File: armv5te/ALT_STUB.S */ 13673/* 13674 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13675 * any interesting requests and then jump to the real instruction 13676 * handler. Note that the call to dvmCheckInst is done as a tail call. 13677 */ 13678 adrl lr, dvmAsmInstructionStart + (4 * 64) 13679 mov r0, rPC @ arg0 13680 mov r1, rSELF @ arg1 13681 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13682 13683/* ------------------------------ */ 13684 .balign 64 13685.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 13686/* File: armv5te/ALT_STUB.S */ 13687/* 13688 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13689 * any interesting requests and then jump to the real instruction 13690 * handler. Note that the call to dvmCheckInst is done as a tail call. 13691 */ 13692 adrl lr, dvmAsmInstructionStart + (5 * 64) 13693 mov r0, rPC @ arg0 13694 mov r1, rSELF @ arg1 13695 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13696 13697/* ------------------------------ */ 13698 .balign 64 13699.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 13700/* File: armv5te/ALT_STUB.S */ 13701/* 13702 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13703 * any interesting requests and then jump to the real instruction 13704 * handler. Note that the call to dvmCheckInst is done as a tail call. 13705 */ 13706 adrl lr, dvmAsmInstructionStart + (6 * 64) 13707 mov r0, rPC @ arg0 13708 mov r1, rSELF @ arg1 13709 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13710 13711/* ------------------------------ */ 13712 .balign 64 13713.L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 13714/* File: armv5te/ALT_STUB.S */ 13715/* 13716 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13717 * any interesting requests and then jump to the real instruction 13718 * handler. Note that the call to dvmCheckInst is done as a tail call. 13719 */ 13720 adrl lr, dvmAsmInstructionStart + (7 * 64) 13721 mov r0, rPC @ arg0 13722 mov r1, rSELF @ arg1 13723 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13724 13725/* ------------------------------ */ 13726 .balign 64 13727.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 13728/* File: armv5te/ALT_STUB.S */ 13729/* 13730 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13731 * any interesting requests and then jump to the real instruction 13732 * handler. Note that the call to dvmCheckInst is done as a tail call. 13733 */ 13734 adrl lr, dvmAsmInstructionStart + (8 * 64) 13735 mov r0, rPC @ arg0 13736 mov r1, rSELF @ arg1 13737 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13738 13739/* ------------------------------ */ 13740 .balign 64 13741.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 13742/* File: armv5te/ALT_STUB.S */ 13743/* 13744 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13745 * any interesting requests and then jump to the real instruction 13746 * handler. Note that the call to dvmCheckInst is done as a tail call. 13747 */ 13748 adrl lr, dvmAsmInstructionStart + (9 * 64) 13749 mov r0, rPC @ arg0 13750 mov r1, rSELF @ arg1 13751 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13752 13753/* ------------------------------ */ 13754 .balign 64 13755.L_ALT_OP_MOVE_RESULT: /* 0x0a */ 13756/* File: armv5te/ALT_STUB.S */ 13757/* 13758 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13759 * any interesting requests and then jump to the real instruction 13760 * handler. Note that the call to dvmCheckInst is done as a tail call. 13761 */ 13762 adrl lr, dvmAsmInstructionStart + (10 * 64) 13763 mov r0, rPC @ arg0 13764 mov r1, rSELF @ arg1 13765 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13766 13767/* ------------------------------ */ 13768 .balign 64 13769.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 13770/* File: armv5te/ALT_STUB.S */ 13771/* 13772 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13773 * any interesting requests and then jump to the real instruction 13774 * handler. Note that the call to dvmCheckInst is done as a tail call. 13775 */ 13776 adrl lr, dvmAsmInstructionStart + (11 * 64) 13777 mov r0, rPC @ arg0 13778 mov r1, rSELF @ arg1 13779 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13780 13781/* ------------------------------ */ 13782 .balign 64 13783.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 13784/* File: armv5te/ALT_STUB.S */ 13785/* 13786 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13787 * any interesting requests and then jump to the real instruction 13788 * handler. Note that the call to dvmCheckInst is done as a tail call. 13789 */ 13790 adrl lr, dvmAsmInstructionStart + (12 * 64) 13791 mov r0, rPC @ arg0 13792 mov r1, rSELF @ arg1 13793 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13794 13795/* ------------------------------ */ 13796 .balign 64 13797.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 13798/* File: armv5te/ALT_STUB.S */ 13799/* 13800 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13801 * any interesting requests and then jump to the real instruction 13802 * handler. Note that the call to dvmCheckInst is done as a tail call. 13803 */ 13804 adrl lr, dvmAsmInstructionStart + (13 * 64) 13805 mov r0, rPC @ arg0 13806 mov r1, rSELF @ arg1 13807 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13808 13809/* ------------------------------ */ 13810 .balign 64 13811.L_ALT_OP_RETURN_VOID: /* 0x0e */ 13812/* File: armv5te/ALT_STUB.S */ 13813/* 13814 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13815 * any interesting requests and then jump to the real instruction 13816 * handler. Note that the call to dvmCheckInst is done as a tail call. 13817 */ 13818 adrl lr, dvmAsmInstructionStart + (14 * 64) 13819 mov r0, rPC @ arg0 13820 mov r1, rSELF @ arg1 13821 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13822 13823/* ------------------------------ */ 13824 .balign 64 13825.L_ALT_OP_RETURN: /* 0x0f */ 13826/* File: armv5te/ALT_STUB.S */ 13827/* 13828 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13829 * any interesting requests and then jump to the real instruction 13830 * handler. Note that the call to dvmCheckInst is done as a tail call. 13831 */ 13832 adrl lr, dvmAsmInstructionStart + (15 * 64) 13833 mov r0, rPC @ arg0 13834 mov r1, rSELF @ arg1 13835 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13836 13837/* ------------------------------ */ 13838 .balign 64 13839.L_ALT_OP_RETURN_WIDE: /* 0x10 */ 13840/* File: armv5te/ALT_STUB.S */ 13841/* 13842 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13843 * any interesting requests and then jump to the real instruction 13844 * handler. Note that the call to dvmCheckInst is done as a tail call. 13845 */ 13846 adrl lr, dvmAsmInstructionStart + (16 * 64) 13847 mov r0, rPC @ arg0 13848 mov r1, rSELF @ arg1 13849 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13850 13851/* ------------------------------ */ 13852 .balign 64 13853.L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 13854/* File: armv5te/ALT_STUB.S */ 13855/* 13856 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13857 * any interesting requests and then jump to the real instruction 13858 * handler. Note that the call to dvmCheckInst is done as a tail call. 13859 */ 13860 adrl lr, dvmAsmInstructionStart + (17 * 64) 13861 mov r0, rPC @ arg0 13862 mov r1, rSELF @ arg1 13863 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13864 13865/* ------------------------------ */ 13866 .balign 64 13867.L_ALT_OP_CONST_4: /* 0x12 */ 13868/* File: armv5te/ALT_STUB.S */ 13869/* 13870 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13871 * any interesting requests and then jump to the real instruction 13872 * handler. Note that the call to dvmCheckInst is done as a tail call. 13873 */ 13874 adrl lr, dvmAsmInstructionStart + (18 * 64) 13875 mov r0, rPC @ arg0 13876 mov r1, rSELF @ arg1 13877 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13878 13879/* ------------------------------ */ 13880 .balign 64 13881.L_ALT_OP_CONST_16: /* 0x13 */ 13882/* File: armv5te/ALT_STUB.S */ 13883/* 13884 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13885 * any interesting requests and then jump to the real instruction 13886 * handler. Note that the call to dvmCheckInst is done as a tail call. 13887 */ 13888 adrl lr, dvmAsmInstructionStart + (19 * 64) 13889 mov r0, rPC @ arg0 13890 mov r1, rSELF @ arg1 13891 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13892 13893/* ------------------------------ */ 13894 .balign 64 13895.L_ALT_OP_CONST: /* 0x14 */ 13896/* File: armv5te/ALT_STUB.S */ 13897/* 13898 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13899 * any interesting requests and then jump to the real instruction 13900 * handler. Note that the call to dvmCheckInst is done as a tail call. 13901 */ 13902 adrl lr, dvmAsmInstructionStart + (20 * 64) 13903 mov r0, rPC @ arg0 13904 mov r1, rSELF @ arg1 13905 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13906 13907/* ------------------------------ */ 13908 .balign 64 13909.L_ALT_OP_CONST_HIGH16: /* 0x15 */ 13910/* File: armv5te/ALT_STUB.S */ 13911/* 13912 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13913 * any interesting requests and then jump to the real instruction 13914 * handler. Note that the call to dvmCheckInst is done as a tail call. 13915 */ 13916 adrl lr, dvmAsmInstructionStart + (21 * 64) 13917 mov r0, rPC @ arg0 13918 mov r1, rSELF @ arg1 13919 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13920 13921/* ------------------------------ */ 13922 .balign 64 13923.L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 13924/* File: armv5te/ALT_STUB.S */ 13925/* 13926 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13927 * any interesting requests and then jump to the real instruction 13928 * handler. Note that the call to dvmCheckInst is done as a tail call. 13929 */ 13930 adrl lr, dvmAsmInstructionStart + (22 * 64) 13931 mov r0, rPC @ arg0 13932 mov r1, rSELF @ arg1 13933 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13934 13935/* ------------------------------ */ 13936 .balign 64 13937.L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 13938/* File: armv5te/ALT_STUB.S */ 13939/* 13940 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13941 * any interesting requests and then jump to the real instruction 13942 * handler. Note that the call to dvmCheckInst is done as a tail call. 13943 */ 13944 adrl lr, dvmAsmInstructionStart + (23 * 64) 13945 mov r0, rPC @ arg0 13946 mov r1, rSELF @ arg1 13947 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13948 13949/* ------------------------------ */ 13950 .balign 64 13951.L_ALT_OP_CONST_WIDE: /* 0x18 */ 13952/* File: armv5te/ALT_STUB.S */ 13953/* 13954 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13955 * any interesting requests and then jump to the real instruction 13956 * handler. Note that the call to dvmCheckInst is done as a tail call. 13957 */ 13958 adrl lr, dvmAsmInstructionStart + (24 * 64) 13959 mov r0, rPC @ arg0 13960 mov r1, rSELF @ arg1 13961 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13962 13963/* ------------------------------ */ 13964 .balign 64 13965.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 13966/* File: armv5te/ALT_STUB.S */ 13967/* 13968 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13969 * any interesting requests and then jump to the real instruction 13970 * handler. Note that the call to dvmCheckInst is done as a tail call. 13971 */ 13972 adrl lr, dvmAsmInstructionStart + (25 * 64) 13973 mov r0, rPC @ arg0 13974 mov r1, rSELF @ arg1 13975 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13976 13977/* ------------------------------ */ 13978 .balign 64 13979.L_ALT_OP_CONST_STRING: /* 0x1a */ 13980/* File: armv5te/ALT_STUB.S */ 13981/* 13982 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13983 * any interesting requests and then jump to the real instruction 13984 * handler. Note that the call to dvmCheckInst is done as a tail call. 13985 */ 13986 adrl lr, dvmAsmInstructionStart + (26 * 64) 13987 mov r0, rPC @ arg0 13988 mov r1, rSELF @ arg1 13989 b dvmCheckInst @ (dPC,self) tail call to instruction checker 13990 13991/* ------------------------------ */ 13992 .balign 64 13993.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 13994/* File: armv5te/ALT_STUB.S */ 13995/* 13996 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 13997 * any interesting requests and then jump to the real instruction 13998 * handler. Note that the call to dvmCheckInst is done as a tail call. 13999 */ 14000 adrl lr, dvmAsmInstructionStart + (27 * 64) 14001 mov r0, rPC @ arg0 14002 mov r1, rSELF @ arg1 14003 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14004 14005/* ------------------------------ */ 14006 .balign 64 14007.L_ALT_OP_CONST_CLASS: /* 0x1c */ 14008/* File: armv5te/ALT_STUB.S */ 14009/* 14010 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14011 * any interesting requests and then jump to the real instruction 14012 * handler. Note that the call to dvmCheckInst is done as a tail call. 14013 */ 14014 adrl lr, dvmAsmInstructionStart + (28 * 64) 14015 mov r0, rPC @ arg0 14016 mov r1, rSELF @ arg1 14017 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14018 14019/* ------------------------------ */ 14020 .balign 64 14021.L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 14022/* File: armv5te/ALT_STUB.S */ 14023/* 14024 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14025 * any interesting requests and then jump to the real instruction 14026 * handler. Note that the call to dvmCheckInst is done as a tail call. 14027 */ 14028 adrl lr, dvmAsmInstructionStart + (29 * 64) 14029 mov r0, rPC @ arg0 14030 mov r1, rSELF @ arg1 14031 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14032 14033/* ------------------------------ */ 14034 .balign 64 14035.L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 14036/* File: armv5te/ALT_STUB.S */ 14037/* 14038 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14039 * any interesting requests and then jump to the real instruction 14040 * handler. Note that the call to dvmCheckInst is done as a tail call. 14041 */ 14042 adrl lr, dvmAsmInstructionStart + (30 * 64) 14043 mov r0, rPC @ arg0 14044 mov r1, rSELF @ arg1 14045 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14046 14047/* ------------------------------ */ 14048 .balign 64 14049.L_ALT_OP_CHECK_CAST: /* 0x1f */ 14050/* File: armv5te/ALT_STUB.S */ 14051/* 14052 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14053 * any interesting requests and then jump to the real instruction 14054 * handler. Note that the call to dvmCheckInst is done as a tail call. 14055 */ 14056 adrl lr, dvmAsmInstructionStart + (31 * 64) 14057 mov r0, rPC @ arg0 14058 mov r1, rSELF @ arg1 14059 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14060 14061/* ------------------------------ */ 14062 .balign 64 14063.L_ALT_OP_INSTANCE_OF: /* 0x20 */ 14064/* File: armv5te/ALT_STUB.S */ 14065/* 14066 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14067 * any interesting requests and then jump to the real instruction 14068 * handler. Note that the call to dvmCheckInst is done as a tail call. 14069 */ 14070 adrl lr, dvmAsmInstructionStart + (32 * 64) 14071 mov r0, rPC @ arg0 14072 mov r1, rSELF @ arg1 14073 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14074 14075/* ------------------------------ */ 14076 .balign 64 14077.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 14078/* File: armv5te/ALT_STUB.S */ 14079/* 14080 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14081 * any interesting requests and then jump to the real instruction 14082 * handler. Note that the call to dvmCheckInst is done as a tail call. 14083 */ 14084 adrl lr, dvmAsmInstructionStart + (33 * 64) 14085 mov r0, rPC @ arg0 14086 mov r1, rSELF @ arg1 14087 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14088 14089/* ------------------------------ */ 14090 .balign 64 14091.L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 14092/* File: armv5te/ALT_STUB.S */ 14093/* 14094 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14095 * any interesting requests and then jump to the real instruction 14096 * handler. Note that the call to dvmCheckInst is done as a tail call. 14097 */ 14098 adrl lr, dvmAsmInstructionStart + (34 * 64) 14099 mov r0, rPC @ arg0 14100 mov r1, rSELF @ arg1 14101 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14102 14103/* ------------------------------ */ 14104 .balign 64 14105.L_ALT_OP_NEW_ARRAY: /* 0x23 */ 14106/* File: armv5te/ALT_STUB.S */ 14107/* 14108 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14109 * any interesting requests and then jump to the real instruction 14110 * handler. Note that the call to dvmCheckInst is done as a tail call. 14111 */ 14112 adrl lr, dvmAsmInstructionStart + (35 * 64) 14113 mov r0, rPC @ arg0 14114 mov r1, rSELF @ arg1 14115 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14116 14117/* ------------------------------ */ 14118 .balign 64 14119.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 14120/* File: armv5te/ALT_STUB.S */ 14121/* 14122 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14123 * any interesting requests and then jump to the real instruction 14124 * handler. Note that the call to dvmCheckInst is done as a tail call. 14125 */ 14126 adrl lr, dvmAsmInstructionStart + (36 * 64) 14127 mov r0, rPC @ arg0 14128 mov r1, rSELF @ arg1 14129 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14130 14131/* ------------------------------ */ 14132 .balign 64 14133.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 14134/* File: armv5te/ALT_STUB.S */ 14135/* 14136 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14137 * any interesting requests and then jump to the real instruction 14138 * handler. Note that the call to dvmCheckInst is done as a tail call. 14139 */ 14140 adrl lr, dvmAsmInstructionStart + (37 * 64) 14141 mov r0, rPC @ arg0 14142 mov r1, rSELF @ arg1 14143 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14144 14145/* ------------------------------ */ 14146 .balign 64 14147.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 14148/* File: armv5te/ALT_STUB.S */ 14149/* 14150 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14151 * any interesting requests and then jump to the real instruction 14152 * handler. Note that the call to dvmCheckInst is done as a tail call. 14153 */ 14154 adrl lr, dvmAsmInstructionStart + (38 * 64) 14155 mov r0, rPC @ arg0 14156 mov r1, rSELF @ arg1 14157 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14158 14159/* ------------------------------ */ 14160 .balign 64 14161.L_ALT_OP_THROW: /* 0x27 */ 14162/* File: armv5te/ALT_STUB.S */ 14163/* 14164 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14165 * any interesting requests and then jump to the real instruction 14166 * handler. Note that the call to dvmCheckInst is done as a tail call. 14167 */ 14168 adrl lr, dvmAsmInstructionStart + (39 * 64) 14169 mov r0, rPC @ arg0 14170 mov r1, rSELF @ arg1 14171 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14172 14173/* ------------------------------ */ 14174 .balign 64 14175.L_ALT_OP_GOTO: /* 0x28 */ 14176/* File: armv5te/ALT_STUB.S */ 14177/* 14178 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14179 * any interesting requests and then jump to the real instruction 14180 * handler. Note that the call to dvmCheckInst is done as a tail call. 14181 */ 14182 adrl lr, dvmAsmInstructionStart + (40 * 64) 14183 mov r0, rPC @ arg0 14184 mov r1, rSELF @ arg1 14185 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14186 14187/* ------------------------------ */ 14188 .balign 64 14189.L_ALT_OP_GOTO_16: /* 0x29 */ 14190/* File: armv5te/ALT_STUB.S */ 14191/* 14192 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14193 * any interesting requests and then jump to the real instruction 14194 * handler. Note that the call to dvmCheckInst is done as a tail call. 14195 */ 14196 adrl lr, dvmAsmInstructionStart + (41 * 64) 14197 mov r0, rPC @ arg0 14198 mov r1, rSELF @ arg1 14199 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14200 14201/* ------------------------------ */ 14202 .balign 64 14203.L_ALT_OP_GOTO_32: /* 0x2a */ 14204/* File: armv5te/ALT_STUB.S */ 14205/* 14206 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14207 * any interesting requests and then jump to the real instruction 14208 * handler. Note that the call to dvmCheckInst is done as a tail call. 14209 */ 14210 adrl lr, dvmAsmInstructionStart + (42 * 64) 14211 mov r0, rPC @ arg0 14212 mov r1, rSELF @ arg1 14213 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14214 14215/* ------------------------------ */ 14216 .balign 64 14217.L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 14218/* File: armv5te/ALT_STUB.S */ 14219/* 14220 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14221 * any interesting requests and then jump to the real instruction 14222 * handler. Note that the call to dvmCheckInst is done as a tail call. 14223 */ 14224 adrl lr, dvmAsmInstructionStart + (43 * 64) 14225 mov r0, rPC @ arg0 14226 mov r1, rSELF @ arg1 14227 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14228 14229/* ------------------------------ */ 14230 .balign 64 14231.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 14232/* File: armv5te/ALT_STUB.S */ 14233/* 14234 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14235 * any interesting requests and then jump to the real instruction 14236 * handler. Note that the call to dvmCheckInst is done as a tail call. 14237 */ 14238 adrl lr, dvmAsmInstructionStart + (44 * 64) 14239 mov r0, rPC @ arg0 14240 mov r1, rSELF @ arg1 14241 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14242 14243/* ------------------------------ */ 14244 .balign 64 14245.L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 14246/* File: armv5te/ALT_STUB.S */ 14247/* 14248 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14249 * any interesting requests and then jump to the real instruction 14250 * handler. Note that the call to dvmCheckInst is done as a tail call. 14251 */ 14252 adrl lr, dvmAsmInstructionStart + (45 * 64) 14253 mov r0, rPC @ arg0 14254 mov r1, rSELF @ arg1 14255 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14256 14257/* ------------------------------ */ 14258 .balign 64 14259.L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 14260/* File: armv5te/ALT_STUB.S */ 14261/* 14262 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14263 * any interesting requests and then jump to the real instruction 14264 * handler. Note that the call to dvmCheckInst is done as a tail call. 14265 */ 14266 adrl lr, dvmAsmInstructionStart + (46 * 64) 14267 mov r0, rPC @ arg0 14268 mov r1, rSELF @ arg1 14269 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14270 14271/* ------------------------------ */ 14272 .balign 64 14273.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 14274/* File: armv5te/ALT_STUB.S */ 14275/* 14276 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14277 * any interesting requests and then jump to the real instruction 14278 * handler. Note that the call to dvmCheckInst is done as a tail call. 14279 */ 14280 adrl lr, dvmAsmInstructionStart + (47 * 64) 14281 mov r0, rPC @ arg0 14282 mov r1, rSELF @ arg1 14283 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14284 14285/* ------------------------------ */ 14286 .balign 64 14287.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 14288/* File: armv5te/ALT_STUB.S */ 14289/* 14290 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14291 * any interesting requests and then jump to the real instruction 14292 * handler. Note that the call to dvmCheckInst is done as a tail call. 14293 */ 14294 adrl lr, dvmAsmInstructionStart + (48 * 64) 14295 mov r0, rPC @ arg0 14296 mov r1, rSELF @ arg1 14297 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14298 14299/* ------------------------------ */ 14300 .balign 64 14301.L_ALT_OP_CMP_LONG: /* 0x31 */ 14302/* File: armv5te/ALT_STUB.S */ 14303/* 14304 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14305 * any interesting requests and then jump to the real instruction 14306 * handler. Note that the call to dvmCheckInst is done as a tail call. 14307 */ 14308 adrl lr, dvmAsmInstructionStart + (49 * 64) 14309 mov r0, rPC @ arg0 14310 mov r1, rSELF @ arg1 14311 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14312 14313/* ------------------------------ */ 14314 .balign 64 14315.L_ALT_OP_IF_EQ: /* 0x32 */ 14316/* File: armv5te/ALT_STUB.S */ 14317/* 14318 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14319 * any interesting requests and then jump to the real instruction 14320 * handler. Note that the call to dvmCheckInst is done as a tail call. 14321 */ 14322 adrl lr, dvmAsmInstructionStart + (50 * 64) 14323 mov r0, rPC @ arg0 14324 mov r1, rSELF @ arg1 14325 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14326 14327/* ------------------------------ */ 14328 .balign 64 14329.L_ALT_OP_IF_NE: /* 0x33 */ 14330/* File: armv5te/ALT_STUB.S */ 14331/* 14332 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14333 * any interesting requests and then jump to the real instruction 14334 * handler. Note that the call to dvmCheckInst is done as a tail call. 14335 */ 14336 adrl lr, dvmAsmInstructionStart + (51 * 64) 14337 mov r0, rPC @ arg0 14338 mov r1, rSELF @ arg1 14339 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14340 14341/* ------------------------------ */ 14342 .balign 64 14343.L_ALT_OP_IF_LT: /* 0x34 */ 14344/* File: armv5te/ALT_STUB.S */ 14345/* 14346 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14347 * any interesting requests and then jump to the real instruction 14348 * handler. Note that the call to dvmCheckInst is done as a tail call. 14349 */ 14350 adrl lr, dvmAsmInstructionStart + (52 * 64) 14351 mov r0, rPC @ arg0 14352 mov r1, rSELF @ arg1 14353 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14354 14355/* ------------------------------ */ 14356 .balign 64 14357.L_ALT_OP_IF_GE: /* 0x35 */ 14358/* File: armv5te/ALT_STUB.S */ 14359/* 14360 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14361 * any interesting requests and then jump to the real instruction 14362 * handler. Note that the call to dvmCheckInst is done as a tail call. 14363 */ 14364 adrl lr, dvmAsmInstructionStart + (53 * 64) 14365 mov r0, rPC @ arg0 14366 mov r1, rSELF @ arg1 14367 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14368 14369/* ------------------------------ */ 14370 .balign 64 14371.L_ALT_OP_IF_GT: /* 0x36 */ 14372/* File: armv5te/ALT_STUB.S */ 14373/* 14374 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14375 * any interesting requests and then jump to the real instruction 14376 * handler. Note that the call to dvmCheckInst is done as a tail call. 14377 */ 14378 adrl lr, dvmAsmInstructionStart + (54 * 64) 14379 mov r0, rPC @ arg0 14380 mov r1, rSELF @ arg1 14381 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14382 14383/* ------------------------------ */ 14384 .balign 64 14385.L_ALT_OP_IF_LE: /* 0x37 */ 14386/* File: armv5te/ALT_STUB.S */ 14387/* 14388 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14389 * any interesting requests and then jump to the real instruction 14390 * handler. Note that the call to dvmCheckInst is done as a tail call. 14391 */ 14392 adrl lr, dvmAsmInstructionStart + (55 * 64) 14393 mov r0, rPC @ arg0 14394 mov r1, rSELF @ arg1 14395 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14396 14397/* ------------------------------ */ 14398 .balign 64 14399.L_ALT_OP_IF_EQZ: /* 0x38 */ 14400/* File: armv5te/ALT_STUB.S */ 14401/* 14402 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14403 * any interesting requests and then jump to the real instruction 14404 * handler. Note that the call to dvmCheckInst is done as a tail call. 14405 */ 14406 adrl lr, dvmAsmInstructionStart + (56 * 64) 14407 mov r0, rPC @ arg0 14408 mov r1, rSELF @ arg1 14409 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14410 14411/* ------------------------------ */ 14412 .balign 64 14413.L_ALT_OP_IF_NEZ: /* 0x39 */ 14414/* File: armv5te/ALT_STUB.S */ 14415/* 14416 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14417 * any interesting requests and then jump to the real instruction 14418 * handler. Note that the call to dvmCheckInst is done as a tail call. 14419 */ 14420 adrl lr, dvmAsmInstructionStart + (57 * 64) 14421 mov r0, rPC @ arg0 14422 mov r1, rSELF @ arg1 14423 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14424 14425/* ------------------------------ */ 14426 .balign 64 14427.L_ALT_OP_IF_LTZ: /* 0x3a */ 14428/* File: armv5te/ALT_STUB.S */ 14429/* 14430 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14431 * any interesting requests and then jump to the real instruction 14432 * handler. Note that the call to dvmCheckInst is done as a tail call. 14433 */ 14434 adrl lr, dvmAsmInstructionStart + (58 * 64) 14435 mov r0, rPC @ arg0 14436 mov r1, rSELF @ arg1 14437 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14438 14439/* ------------------------------ */ 14440 .balign 64 14441.L_ALT_OP_IF_GEZ: /* 0x3b */ 14442/* File: armv5te/ALT_STUB.S */ 14443/* 14444 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14445 * any interesting requests and then jump to the real instruction 14446 * handler. Note that the call to dvmCheckInst is done as a tail call. 14447 */ 14448 adrl lr, dvmAsmInstructionStart + (59 * 64) 14449 mov r0, rPC @ arg0 14450 mov r1, rSELF @ arg1 14451 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14452 14453/* ------------------------------ */ 14454 .balign 64 14455.L_ALT_OP_IF_GTZ: /* 0x3c */ 14456/* File: armv5te/ALT_STUB.S */ 14457/* 14458 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14459 * any interesting requests and then jump to the real instruction 14460 * handler. Note that the call to dvmCheckInst is done as a tail call. 14461 */ 14462 adrl lr, dvmAsmInstructionStart + (60 * 64) 14463 mov r0, rPC @ arg0 14464 mov r1, rSELF @ arg1 14465 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14466 14467/* ------------------------------ */ 14468 .balign 64 14469.L_ALT_OP_IF_LEZ: /* 0x3d */ 14470/* File: armv5te/ALT_STUB.S */ 14471/* 14472 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14473 * any interesting requests and then jump to the real instruction 14474 * handler. Note that the call to dvmCheckInst is done as a tail call. 14475 */ 14476 adrl lr, dvmAsmInstructionStart + (61 * 64) 14477 mov r0, rPC @ arg0 14478 mov r1, rSELF @ arg1 14479 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14480 14481/* ------------------------------ */ 14482 .balign 64 14483.L_ALT_OP_UNUSED_3E: /* 0x3e */ 14484/* File: armv5te/ALT_STUB.S */ 14485/* 14486 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14487 * any interesting requests and then jump to the real instruction 14488 * handler. Note that the call to dvmCheckInst is done as a tail call. 14489 */ 14490 adrl lr, dvmAsmInstructionStart + (62 * 64) 14491 mov r0, rPC @ arg0 14492 mov r1, rSELF @ arg1 14493 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14494 14495/* ------------------------------ */ 14496 .balign 64 14497.L_ALT_OP_UNUSED_3F: /* 0x3f */ 14498/* File: armv5te/ALT_STUB.S */ 14499/* 14500 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14501 * any interesting requests and then jump to the real instruction 14502 * handler. Note that the call to dvmCheckInst is done as a tail call. 14503 */ 14504 adrl lr, dvmAsmInstructionStart + (63 * 64) 14505 mov r0, rPC @ arg0 14506 mov r1, rSELF @ arg1 14507 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14508 14509/* ------------------------------ */ 14510 .balign 64 14511.L_ALT_OP_UNUSED_40: /* 0x40 */ 14512/* File: armv5te/ALT_STUB.S */ 14513/* 14514 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14515 * any interesting requests and then jump to the real instruction 14516 * handler. Note that the call to dvmCheckInst is done as a tail call. 14517 */ 14518 adrl lr, dvmAsmInstructionStart + (64 * 64) 14519 mov r0, rPC @ arg0 14520 mov r1, rSELF @ arg1 14521 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14522 14523/* ------------------------------ */ 14524 .balign 64 14525.L_ALT_OP_UNUSED_41: /* 0x41 */ 14526/* File: armv5te/ALT_STUB.S */ 14527/* 14528 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14529 * any interesting requests and then jump to the real instruction 14530 * handler. Note that the call to dvmCheckInst is done as a tail call. 14531 */ 14532 adrl lr, dvmAsmInstructionStart + (65 * 64) 14533 mov r0, rPC @ arg0 14534 mov r1, rSELF @ arg1 14535 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14536 14537/* ------------------------------ */ 14538 .balign 64 14539.L_ALT_OP_UNUSED_42: /* 0x42 */ 14540/* File: armv5te/ALT_STUB.S */ 14541/* 14542 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14543 * any interesting requests and then jump to the real instruction 14544 * handler. Note that the call to dvmCheckInst is done as a tail call. 14545 */ 14546 adrl lr, dvmAsmInstructionStart + (66 * 64) 14547 mov r0, rPC @ arg0 14548 mov r1, rSELF @ arg1 14549 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14550 14551/* ------------------------------ */ 14552 .balign 64 14553.L_ALT_OP_UNUSED_43: /* 0x43 */ 14554/* File: armv5te/ALT_STUB.S */ 14555/* 14556 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14557 * any interesting requests and then jump to the real instruction 14558 * handler. Note that the call to dvmCheckInst is done as a tail call. 14559 */ 14560 adrl lr, dvmAsmInstructionStart + (67 * 64) 14561 mov r0, rPC @ arg0 14562 mov r1, rSELF @ arg1 14563 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14564 14565/* ------------------------------ */ 14566 .balign 64 14567.L_ALT_OP_AGET: /* 0x44 */ 14568/* File: armv5te/ALT_STUB.S */ 14569/* 14570 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14571 * any interesting requests and then jump to the real instruction 14572 * handler. Note that the call to dvmCheckInst is done as a tail call. 14573 */ 14574 adrl lr, dvmAsmInstructionStart + (68 * 64) 14575 mov r0, rPC @ arg0 14576 mov r1, rSELF @ arg1 14577 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14578 14579/* ------------------------------ */ 14580 .balign 64 14581.L_ALT_OP_AGET_WIDE: /* 0x45 */ 14582/* File: armv5te/ALT_STUB.S */ 14583/* 14584 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14585 * any interesting requests and then jump to the real instruction 14586 * handler. Note that the call to dvmCheckInst is done as a tail call. 14587 */ 14588 adrl lr, dvmAsmInstructionStart + (69 * 64) 14589 mov r0, rPC @ arg0 14590 mov r1, rSELF @ arg1 14591 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14592 14593/* ------------------------------ */ 14594 .balign 64 14595.L_ALT_OP_AGET_OBJECT: /* 0x46 */ 14596/* File: armv5te/ALT_STUB.S */ 14597/* 14598 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14599 * any interesting requests and then jump to the real instruction 14600 * handler. Note that the call to dvmCheckInst is done as a tail call. 14601 */ 14602 adrl lr, dvmAsmInstructionStart + (70 * 64) 14603 mov r0, rPC @ arg0 14604 mov r1, rSELF @ arg1 14605 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14606 14607/* ------------------------------ */ 14608 .balign 64 14609.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 14610/* File: armv5te/ALT_STUB.S */ 14611/* 14612 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14613 * any interesting requests and then jump to the real instruction 14614 * handler. Note that the call to dvmCheckInst is done as a tail call. 14615 */ 14616 adrl lr, dvmAsmInstructionStart + (71 * 64) 14617 mov r0, rPC @ arg0 14618 mov r1, rSELF @ arg1 14619 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14620 14621/* ------------------------------ */ 14622 .balign 64 14623.L_ALT_OP_AGET_BYTE: /* 0x48 */ 14624/* File: armv5te/ALT_STUB.S */ 14625/* 14626 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14627 * any interesting requests and then jump to the real instruction 14628 * handler. Note that the call to dvmCheckInst is done as a tail call. 14629 */ 14630 adrl lr, dvmAsmInstructionStart + (72 * 64) 14631 mov r0, rPC @ arg0 14632 mov r1, rSELF @ arg1 14633 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14634 14635/* ------------------------------ */ 14636 .balign 64 14637.L_ALT_OP_AGET_CHAR: /* 0x49 */ 14638/* File: armv5te/ALT_STUB.S */ 14639/* 14640 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14641 * any interesting requests and then jump to the real instruction 14642 * handler. Note that the call to dvmCheckInst is done as a tail call. 14643 */ 14644 adrl lr, dvmAsmInstructionStart + (73 * 64) 14645 mov r0, rPC @ arg0 14646 mov r1, rSELF @ arg1 14647 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14648 14649/* ------------------------------ */ 14650 .balign 64 14651.L_ALT_OP_AGET_SHORT: /* 0x4a */ 14652/* File: armv5te/ALT_STUB.S */ 14653/* 14654 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14655 * any interesting requests and then jump to the real instruction 14656 * handler. Note that the call to dvmCheckInst is done as a tail call. 14657 */ 14658 adrl lr, dvmAsmInstructionStart + (74 * 64) 14659 mov r0, rPC @ arg0 14660 mov r1, rSELF @ arg1 14661 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14662 14663/* ------------------------------ */ 14664 .balign 64 14665.L_ALT_OP_APUT: /* 0x4b */ 14666/* File: armv5te/ALT_STUB.S */ 14667/* 14668 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14669 * any interesting requests and then jump to the real instruction 14670 * handler. Note that the call to dvmCheckInst is done as a tail call. 14671 */ 14672 adrl lr, dvmAsmInstructionStart + (75 * 64) 14673 mov r0, rPC @ arg0 14674 mov r1, rSELF @ arg1 14675 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14676 14677/* ------------------------------ */ 14678 .balign 64 14679.L_ALT_OP_APUT_WIDE: /* 0x4c */ 14680/* File: armv5te/ALT_STUB.S */ 14681/* 14682 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14683 * any interesting requests and then jump to the real instruction 14684 * handler. Note that the call to dvmCheckInst is done as a tail call. 14685 */ 14686 adrl lr, dvmAsmInstructionStart + (76 * 64) 14687 mov r0, rPC @ arg0 14688 mov r1, rSELF @ arg1 14689 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14690 14691/* ------------------------------ */ 14692 .balign 64 14693.L_ALT_OP_APUT_OBJECT: /* 0x4d */ 14694/* File: armv5te/ALT_STUB.S */ 14695/* 14696 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14697 * any interesting requests and then jump to the real instruction 14698 * handler. Note that the call to dvmCheckInst is done as a tail call. 14699 */ 14700 adrl lr, dvmAsmInstructionStart + (77 * 64) 14701 mov r0, rPC @ arg0 14702 mov r1, rSELF @ arg1 14703 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14704 14705/* ------------------------------ */ 14706 .balign 64 14707.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 14708/* File: armv5te/ALT_STUB.S */ 14709/* 14710 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14711 * any interesting requests and then jump to the real instruction 14712 * handler. Note that the call to dvmCheckInst is done as a tail call. 14713 */ 14714 adrl lr, dvmAsmInstructionStart + (78 * 64) 14715 mov r0, rPC @ arg0 14716 mov r1, rSELF @ arg1 14717 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14718 14719/* ------------------------------ */ 14720 .balign 64 14721.L_ALT_OP_APUT_BYTE: /* 0x4f */ 14722/* File: armv5te/ALT_STUB.S */ 14723/* 14724 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14725 * any interesting requests and then jump to the real instruction 14726 * handler. Note that the call to dvmCheckInst is done as a tail call. 14727 */ 14728 adrl lr, dvmAsmInstructionStart + (79 * 64) 14729 mov r0, rPC @ arg0 14730 mov r1, rSELF @ arg1 14731 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14732 14733/* ------------------------------ */ 14734 .balign 64 14735.L_ALT_OP_APUT_CHAR: /* 0x50 */ 14736/* File: armv5te/ALT_STUB.S */ 14737/* 14738 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14739 * any interesting requests and then jump to the real instruction 14740 * handler. Note that the call to dvmCheckInst is done as a tail call. 14741 */ 14742 adrl lr, dvmAsmInstructionStart + (80 * 64) 14743 mov r0, rPC @ arg0 14744 mov r1, rSELF @ arg1 14745 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14746 14747/* ------------------------------ */ 14748 .balign 64 14749.L_ALT_OP_APUT_SHORT: /* 0x51 */ 14750/* File: armv5te/ALT_STUB.S */ 14751/* 14752 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14753 * any interesting requests and then jump to the real instruction 14754 * handler. Note that the call to dvmCheckInst is done as a tail call. 14755 */ 14756 adrl lr, dvmAsmInstructionStart + (81 * 64) 14757 mov r0, rPC @ arg0 14758 mov r1, rSELF @ arg1 14759 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14760 14761/* ------------------------------ */ 14762 .balign 64 14763.L_ALT_OP_IGET: /* 0x52 */ 14764/* File: armv5te/ALT_STUB.S */ 14765/* 14766 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14767 * any interesting requests and then jump to the real instruction 14768 * handler. Note that the call to dvmCheckInst is done as a tail call. 14769 */ 14770 adrl lr, dvmAsmInstructionStart + (82 * 64) 14771 mov r0, rPC @ arg0 14772 mov r1, rSELF @ arg1 14773 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14774 14775/* ------------------------------ */ 14776 .balign 64 14777.L_ALT_OP_IGET_WIDE: /* 0x53 */ 14778/* File: armv5te/ALT_STUB.S */ 14779/* 14780 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14781 * any interesting requests and then jump to the real instruction 14782 * handler. Note that the call to dvmCheckInst is done as a tail call. 14783 */ 14784 adrl lr, dvmAsmInstructionStart + (83 * 64) 14785 mov r0, rPC @ arg0 14786 mov r1, rSELF @ arg1 14787 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14788 14789/* ------------------------------ */ 14790 .balign 64 14791.L_ALT_OP_IGET_OBJECT: /* 0x54 */ 14792/* File: armv5te/ALT_STUB.S */ 14793/* 14794 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14795 * any interesting requests and then jump to the real instruction 14796 * handler. Note that the call to dvmCheckInst is done as a tail call. 14797 */ 14798 adrl lr, dvmAsmInstructionStart + (84 * 64) 14799 mov r0, rPC @ arg0 14800 mov r1, rSELF @ arg1 14801 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14802 14803/* ------------------------------ */ 14804 .balign 64 14805.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 14806/* File: armv5te/ALT_STUB.S */ 14807/* 14808 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14809 * any interesting requests and then jump to the real instruction 14810 * handler. Note that the call to dvmCheckInst is done as a tail call. 14811 */ 14812 adrl lr, dvmAsmInstructionStart + (85 * 64) 14813 mov r0, rPC @ arg0 14814 mov r1, rSELF @ arg1 14815 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14816 14817/* ------------------------------ */ 14818 .balign 64 14819.L_ALT_OP_IGET_BYTE: /* 0x56 */ 14820/* File: armv5te/ALT_STUB.S */ 14821/* 14822 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14823 * any interesting requests and then jump to the real instruction 14824 * handler. Note that the call to dvmCheckInst is done as a tail call. 14825 */ 14826 adrl lr, dvmAsmInstructionStart + (86 * 64) 14827 mov r0, rPC @ arg0 14828 mov r1, rSELF @ arg1 14829 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14830 14831/* ------------------------------ */ 14832 .balign 64 14833.L_ALT_OP_IGET_CHAR: /* 0x57 */ 14834/* File: armv5te/ALT_STUB.S */ 14835/* 14836 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14837 * any interesting requests and then jump to the real instruction 14838 * handler. Note that the call to dvmCheckInst is done as a tail call. 14839 */ 14840 adrl lr, dvmAsmInstructionStart + (87 * 64) 14841 mov r0, rPC @ arg0 14842 mov r1, rSELF @ arg1 14843 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14844 14845/* ------------------------------ */ 14846 .balign 64 14847.L_ALT_OP_IGET_SHORT: /* 0x58 */ 14848/* File: armv5te/ALT_STUB.S */ 14849/* 14850 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14851 * any interesting requests and then jump to the real instruction 14852 * handler. Note that the call to dvmCheckInst is done as a tail call. 14853 */ 14854 adrl lr, dvmAsmInstructionStart + (88 * 64) 14855 mov r0, rPC @ arg0 14856 mov r1, rSELF @ arg1 14857 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14858 14859/* ------------------------------ */ 14860 .balign 64 14861.L_ALT_OP_IPUT: /* 0x59 */ 14862/* File: armv5te/ALT_STUB.S */ 14863/* 14864 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14865 * any interesting requests and then jump to the real instruction 14866 * handler. Note that the call to dvmCheckInst is done as a tail call. 14867 */ 14868 adrl lr, dvmAsmInstructionStart + (89 * 64) 14869 mov r0, rPC @ arg0 14870 mov r1, rSELF @ arg1 14871 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14872 14873/* ------------------------------ */ 14874 .balign 64 14875.L_ALT_OP_IPUT_WIDE: /* 0x5a */ 14876/* File: armv5te/ALT_STUB.S */ 14877/* 14878 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14879 * any interesting requests and then jump to the real instruction 14880 * handler. Note that the call to dvmCheckInst is done as a tail call. 14881 */ 14882 adrl lr, dvmAsmInstructionStart + (90 * 64) 14883 mov r0, rPC @ arg0 14884 mov r1, rSELF @ arg1 14885 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14886 14887/* ------------------------------ */ 14888 .balign 64 14889.L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 14890/* File: armv5te/ALT_STUB.S */ 14891/* 14892 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14893 * any interesting requests and then jump to the real instruction 14894 * handler. Note that the call to dvmCheckInst is done as a tail call. 14895 */ 14896 adrl lr, dvmAsmInstructionStart + (91 * 64) 14897 mov r0, rPC @ arg0 14898 mov r1, rSELF @ arg1 14899 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14900 14901/* ------------------------------ */ 14902 .balign 64 14903.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 14904/* File: armv5te/ALT_STUB.S */ 14905/* 14906 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14907 * any interesting requests and then jump to the real instruction 14908 * handler. Note that the call to dvmCheckInst is done as a tail call. 14909 */ 14910 adrl lr, dvmAsmInstructionStart + (92 * 64) 14911 mov r0, rPC @ arg0 14912 mov r1, rSELF @ arg1 14913 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14914 14915/* ------------------------------ */ 14916 .balign 64 14917.L_ALT_OP_IPUT_BYTE: /* 0x5d */ 14918/* File: armv5te/ALT_STUB.S */ 14919/* 14920 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14921 * any interesting requests and then jump to the real instruction 14922 * handler. Note that the call to dvmCheckInst is done as a tail call. 14923 */ 14924 adrl lr, dvmAsmInstructionStart + (93 * 64) 14925 mov r0, rPC @ arg0 14926 mov r1, rSELF @ arg1 14927 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14928 14929/* ------------------------------ */ 14930 .balign 64 14931.L_ALT_OP_IPUT_CHAR: /* 0x5e */ 14932/* File: armv5te/ALT_STUB.S */ 14933/* 14934 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14935 * any interesting requests and then jump to the real instruction 14936 * handler. Note that the call to dvmCheckInst is done as a tail call. 14937 */ 14938 adrl lr, dvmAsmInstructionStart + (94 * 64) 14939 mov r0, rPC @ arg0 14940 mov r1, rSELF @ arg1 14941 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14942 14943/* ------------------------------ */ 14944 .balign 64 14945.L_ALT_OP_IPUT_SHORT: /* 0x5f */ 14946/* File: armv5te/ALT_STUB.S */ 14947/* 14948 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14949 * any interesting requests and then jump to the real instruction 14950 * handler. Note that the call to dvmCheckInst is done as a tail call. 14951 */ 14952 adrl lr, dvmAsmInstructionStart + (95 * 64) 14953 mov r0, rPC @ arg0 14954 mov r1, rSELF @ arg1 14955 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14956 14957/* ------------------------------ */ 14958 .balign 64 14959.L_ALT_OP_SGET: /* 0x60 */ 14960/* File: armv5te/ALT_STUB.S */ 14961/* 14962 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14963 * any interesting requests and then jump to the real instruction 14964 * handler. Note that the call to dvmCheckInst is done as a tail call. 14965 */ 14966 adrl lr, dvmAsmInstructionStart + (96 * 64) 14967 mov r0, rPC @ arg0 14968 mov r1, rSELF @ arg1 14969 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14970 14971/* ------------------------------ */ 14972 .balign 64 14973.L_ALT_OP_SGET_WIDE: /* 0x61 */ 14974/* File: armv5te/ALT_STUB.S */ 14975/* 14976 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14977 * any interesting requests and then jump to the real instruction 14978 * handler. Note that the call to dvmCheckInst is done as a tail call. 14979 */ 14980 adrl lr, dvmAsmInstructionStart + (97 * 64) 14981 mov r0, rPC @ arg0 14982 mov r1, rSELF @ arg1 14983 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14984 14985/* ------------------------------ */ 14986 .balign 64 14987.L_ALT_OP_SGET_OBJECT: /* 0x62 */ 14988/* File: armv5te/ALT_STUB.S */ 14989/* 14990 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 14991 * any interesting requests and then jump to the real instruction 14992 * handler. Note that the call to dvmCheckInst is done as a tail call. 14993 */ 14994 adrl lr, dvmAsmInstructionStart + (98 * 64) 14995 mov r0, rPC @ arg0 14996 mov r1, rSELF @ arg1 14997 b dvmCheckInst @ (dPC,self) tail call to instruction checker 14998 14999/* ------------------------------ */ 15000 .balign 64 15001.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 15002/* File: armv5te/ALT_STUB.S */ 15003/* 15004 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15005 * any interesting requests and then jump to the real instruction 15006 * handler. Note that the call to dvmCheckInst is done as a tail call. 15007 */ 15008 adrl lr, dvmAsmInstructionStart + (99 * 64) 15009 mov r0, rPC @ arg0 15010 mov r1, rSELF @ arg1 15011 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15012 15013/* ------------------------------ */ 15014 .balign 64 15015.L_ALT_OP_SGET_BYTE: /* 0x64 */ 15016/* File: armv5te/ALT_STUB.S */ 15017/* 15018 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15019 * any interesting requests and then jump to the real instruction 15020 * handler. Note that the call to dvmCheckInst is done as a tail call. 15021 */ 15022 adrl lr, dvmAsmInstructionStart + (100 * 64) 15023 mov r0, rPC @ arg0 15024 mov r1, rSELF @ arg1 15025 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15026 15027/* ------------------------------ */ 15028 .balign 64 15029.L_ALT_OP_SGET_CHAR: /* 0x65 */ 15030/* File: armv5te/ALT_STUB.S */ 15031/* 15032 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15033 * any interesting requests and then jump to the real instruction 15034 * handler. Note that the call to dvmCheckInst is done as a tail call. 15035 */ 15036 adrl lr, dvmAsmInstructionStart + (101 * 64) 15037 mov r0, rPC @ arg0 15038 mov r1, rSELF @ arg1 15039 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15040 15041/* ------------------------------ */ 15042 .balign 64 15043.L_ALT_OP_SGET_SHORT: /* 0x66 */ 15044/* File: armv5te/ALT_STUB.S */ 15045/* 15046 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15047 * any interesting requests and then jump to the real instruction 15048 * handler. Note that the call to dvmCheckInst is done as a tail call. 15049 */ 15050 adrl lr, dvmAsmInstructionStart + (102 * 64) 15051 mov r0, rPC @ arg0 15052 mov r1, rSELF @ arg1 15053 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15054 15055/* ------------------------------ */ 15056 .balign 64 15057.L_ALT_OP_SPUT: /* 0x67 */ 15058/* File: armv5te/ALT_STUB.S */ 15059/* 15060 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15061 * any interesting requests and then jump to the real instruction 15062 * handler. Note that the call to dvmCheckInst is done as a tail call. 15063 */ 15064 adrl lr, dvmAsmInstructionStart + (103 * 64) 15065 mov r0, rPC @ arg0 15066 mov r1, rSELF @ arg1 15067 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15068 15069/* ------------------------------ */ 15070 .balign 64 15071.L_ALT_OP_SPUT_WIDE: /* 0x68 */ 15072/* File: armv5te/ALT_STUB.S */ 15073/* 15074 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15075 * any interesting requests and then jump to the real instruction 15076 * handler. Note that the call to dvmCheckInst is done as a tail call. 15077 */ 15078 adrl lr, dvmAsmInstructionStart + (104 * 64) 15079 mov r0, rPC @ arg0 15080 mov r1, rSELF @ arg1 15081 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15082 15083/* ------------------------------ */ 15084 .balign 64 15085.L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 15086/* File: armv5te/ALT_STUB.S */ 15087/* 15088 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15089 * any interesting requests and then jump to the real instruction 15090 * handler. Note that the call to dvmCheckInst is done as a tail call. 15091 */ 15092 adrl lr, dvmAsmInstructionStart + (105 * 64) 15093 mov r0, rPC @ arg0 15094 mov r1, rSELF @ arg1 15095 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15096 15097/* ------------------------------ */ 15098 .balign 64 15099.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 15100/* File: armv5te/ALT_STUB.S */ 15101/* 15102 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15103 * any interesting requests and then jump to the real instruction 15104 * handler. Note that the call to dvmCheckInst is done as a tail call. 15105 */ 15106 adrl lr, dvmAsmInstructionStart + (106 * 64) 15107 mov r0, rPC @ arg0 15108 mov r1, rSELF @ arg1 15109 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15110 15111/* ------------------------------ */ 15112 .balign 64 15113.L_ALT_OP_SPUT_BYTE: /* 0x6b */ 15114/* File: armv5te/ALT_STUB.S */ 15115/* 15116 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15117 * any interesting requests and then jump to the real instruction 15118 * handler. Note that the call to dvmCheckInst is done as a tail call. 15119 */ 15120 adrl lr, dvmAsmInstructionStart + (107 * 64) 15121 mov r0, rPC @ arg0 15122 mov r1, rSELF @ arg1 15123 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15124 15125/* ------------------------------ */ 15126 .balign 64 15127.L_ALT_OP_SPUT_CHAR: /* 0x6c */ 15128/* File: armv5te/ALT_STUB.S */ 15129/* 15130 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15131 * any interesting requests and then jump to the real instruction 15132 * handler. Note that the call to dvmCheckInst is done as a tail call. 15133 */ 15134 adrl lr, dvmAsmInstructionStart + (108 * 64) 15135 mov r0, rPC @ arg0 15136 mov r1, rSELF @ arg1 15137 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15138 15139/* ------------------------------ */ 15140 .balign 64 15141.L_ALT_OP_SPUT_SHORT: /* 0x6d */ 15142/* File: armv5te/ALT_STUB.S */ 15143/* 15144 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15145 * any interesting requests and then jump to the real instruction 15146 * handler. Note that the call to dvmCheckInst is done as a tail call. 15147 */ 15148 adrl lr, dvmAsmInstructionStart + (109 * 64) 15149 mov r0, rPC @ arg0 15150 mov r1, rSELF @ arg1 15151 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15152 15153/* ------------------------------ */ 15154 .balign 64 15155.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 15156/* File: armv5te/ALT_STUB.S */ 15157/* 15158 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15159 * any interesting requests and then jump to the real instruction 15160 * handler. Note that the call to dvmCheckInst is done as a tail call. 15161 */ 15162 adrl lr, dvmAsmInstructionStart + (110 * 64) 15163 mov r0, rPC @ arg0 15164 mov r1, rSELF @ arg1 15165 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15166 15167/* ------------------------------ */ 15168 .balign 64 15169.L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 15170/* File: armv5te/ALT_STUB.S */ 15171/* 15172 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15173 * any interesting requests and then jump to the real instruction 15174 * handler. Note that the call to dvmCheckInst is done as a tail call. 15175 */ 15176 adrl lr, dvmAsmInstructionStart + (111 * 64) 15177 mov r0, rPC @ arg0 15178 mov r1, rSELF @ arg1 15179 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15180 15181/* ------------------------------ */ 15182 .balign 64 15183.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 15184/* File: armv5te/ALT_STUB.S */ 15185/* 15186 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15187 * any interesting requests and then jump to the real instruction 15188 * handler. Note that the call to dvmCheckInst is done as a tail call. 15189 */ 15190 adrl lr, dvmAsmInstructionStart + (112 * 64) 15191 mov r0, rPC @ arg0 15192 mov r1, rSELF @ arg1 15193 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15194 15195/* ------------------------------ */ 15196 .balign 64 15197.L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 15198/* File: armv5te/ALT_STUB.S */ 15199/* 15200 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15201 * any interesting requests and then jump to the real instruction 15202 * handler. Note that the call to dvmCheckInst is done as a tail call. 15203 */ 15204 adrl lr, dvmAsmInstructionStart + (113 * 64) 15205 mov r0, rPC @ arg0 15206 mov r1, rSELF @ arg1 15207 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15208 15209/* ------------------------------ */ 15210 .balign 64 15211.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 15212/* File: armv5te/ALT_STUB.S */ 15213/* 15214 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15215 * any interesting requests and then jump to the real instruction 15216 * handler. Note that the call to dvmCheckInst is done as a tail call. 15217 */ 15218 adrl lr, dvmAsmInstructionStart + (114 * 64) 15219 mov r0, rPC @ arg0 15220 mov r1, rSELF @ arg1 15221 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15222 15223/* ------------------------------ */ 15224 .balign 64 15225.L_ALT_OP_UNUSED_73: /* 0x73 */ 15226/* File: armv5te/ALT_STUB.S */ 15227/* 15228 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15229 * any interesting requests and then jump to the real instruction 15230 * handler. Note that the call to dvmCheckInst is done as a tail call. 15231 */ 15232 adrl lr, dvmAsmInstructionStart + (115 * 64) 15233 mov r0, rPC @ arg0 15234 mov r1, rSELF @ arg1 15235 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15236 15237/* ------------------------------ */ 15238 .balign 64 15239.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 15240/* File: armv5te/ALT_STUB.S */ 15241/* 15242 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15243 * any interesting requests and then jump to the real instruction 15244 * handler. Note that the call to dvmCheckInst is done as a tail call. 15245 */ 15246 adrl lr, dvmAsmInstructionStart + (116 * 64) 15247 mov r0, rPC @ arg0 15248 mov r1, rSELF @ arg1 15249 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15250 15251/* ------------------------------ */ 15252 .balign 64 15253.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 15254/* File: armv5te/ALT_STUB.S */ 15255/* 15256 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15257 * any interesting requests and then jump to the real instruction 15258 * handler. Note that the call to dvmCheckInst is done as a tail call. 15259 */ 15260 adrl lr, dvmAsmInstructionStart + (117 * 64) 15261 mov r0, rPC @ arg0 15262 mov r1, rSELF @ arg1 15263 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15264 15265/* ------------------------------ */ 15266 .balign 64 15267.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 15268/* File: armv5te/ALT_STUB.S */ 15269/* 15270 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15271 * any interesting requests and then jump to the real instruction 15272 * handler. Note that the call to dvmCheckInst is done as a tail call. 15273 */ 15274 adrl lr, dvmAsmInstructionStart + (118 * 64) 15275 mov r0, rPC @ arg0 15276 mov r1, rSELF @ arg1 15277 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15278 15279/* ------------------------------ */ 15280 .balign 64 15281.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 15282/* File: armv5te/ALT_STUB.S */ 15283/* 15284 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15285 * any interesting requests and then jump to the real instruction 15286 * handler. Note that the call to dvmCheckInst is done as a tail call. 15287 */ 15288 adrl lr, dvmAsmInstructionStart + (119 * 64) 15289 mov r0, rPC @ arg0 15290 mov r1, rSELF @ arg1 15291 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15292 15293/* ------------------------------ */ 15294 .balign 64 15295.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 15296/* File: armv5te/ALT_STUB.S */ 15297/* 15298 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15299 * any interesting requests and then jump to the real instruction 15300 * handler. Note that the call to dvmCheckInst is done as a tail call. 15301 */ 15302 adrl lr, dvmAsmInstructionStart + (120 * 64) 15303 mov r0, rPC @ arg0 15304 mov r1, rSELF @ arg1 15305 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15306 15307/* ------------------------------ */ 15308 .balign 64 15309.L_ALT_OP_UNUSED_79: /* 0x79 */ 15310/* File: armv5te/ALT_STUB.S */ 15311/* 15312 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15313 * any interesting requests and then jump to the real instruction 15314 * handler. Note that the call to dvmCheckInst is done as a tail call. 15315 */ 15316 adrl lr, dvmAsmInstructionStart + (121 * 64) 15317 mov r0, rPC @ arg0 15318 mov r1, rSELF @ arg1 15319 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15320 15321/* ------------------------------ */ 15322 .balign 64 15323.L_ALT_OP_UNUSED_7A: /* 0x7a */ 15324/* File: armv5te/ALT_STUB.S */ 15325/* 15326 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15327 * any interesting requests and then jump to the real instruction 15328 * handler. Note that the call to dvmCheckInst is done as a tail call. 15329 */ 15330 adrl lr, dvmAsmInstructionStart + (122 * 64) 15331 mov r0, rPC @ arg0 15332 mov r1, rSELF @ arg1 15333 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15334 15335/* ------------------------------ */ 15336 .balign 64 15337.L_ALT_OP_NEG_INT: /* 0x7b */ 15338/* File: armv5te/ALT_STUB.S */ 15339/* 15340 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15341 * any interesting requests and then jump to the real instruction 15342 * handler. Note that the call to dvmCheckInst is done as a tail call. 15343 */ 15344 adrl lr, dvmAsmInstructionStart + (123 * 64) 15345 mov r0, rPC @ arg0 15346 mov r1, rSELF @ arg1 15347 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15348 15349/* ------------------------------ */ 15350 .balign 64 15351.L_ALT_OP_NOT_INT: /* 0x7c */ 15352/* File: armv5te/ALT_STUB.S */ 15353/* 15354 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15355 * any interesting requests and then jump to the real instruction 15356 * handler. Note that the call to dvmCheckInst is done as a tail call. 15357 */ 15358 adrl lr, dvmAsmInstructionStart + (124 * 64) 15359 mov r0, rPC @ arg0 15360 mov r1, rSELF @ arg1 15361 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15362 15363/* ------------------------------ */ 15364 .balign 64 15365.L_ALT_OP_NEG_LONG: /* 0x7d */ 15366/* File: armv5te/ALT_STUB.S */ 15367/* 15368 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15369 * any interesting requests and then jump to the real instruction 15370 * handler. Note that the call to dvmCheckInst is done as a tail call. 15371 */ 15372 adrl lr, dvmAsmInstructionStart + (125 * 64) 15373 mov r0, rPC @ arg0 15374 mov r1, rSELF @ arg1 15375 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15376 15377/* ------------------------------ */ 15378 .balign 64 15379.L_ALT_OP_NOT_LONG: /* 0x7e */ 15380/* File: armv5te/ALT_STUB.S */ 15381/* 15382 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15383 * any interesting requests and then jump to the real instruction 15384 * handler. Note that the call to dvmCheckInst is done as a tail call. 15385 */ 15386 adrl lr, dvmAsmInstructionStart + (126 * 64) 15387 mov r0, rPC @ arg0 15388 mov r1, rSELF @ arg1 15389 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15390 15391/* ------------------------------ */ 15392 .balign 64 15393.L_ALT_OP_NEG_FLOAT: /* 0x7f */ 15394/* File: armv5te/ALT_STUB.S */ 15395/* 15396 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15397 * any interesting requests and then jump to the real instruction 15398 * handler. Note that the call to dvmCheckInst is done as a tail call. 15399 */ 15400 adrl lr, dvmAsmInstructionStart + (127 * 64) 15401 mov r0, rPC @ arg0 15402 mov r1, rSELF @ arg1 15403 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15404 15405/* ------------------------------ */ 15406 .balign 64 15407.L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 15408/* File: armv5te/ALT_STUB.S */ 15409/* 15410 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15411 * any interesting requests and then jump to the real instruction 15412 * handler. Note that the call to dvmCheckInst is done as a tail call. 15413 */ 15414 adrl lr, dvmAsmInstructionStart + (128 * 64) 15415 mov r0, rPC @ arg0 15416 mov r1, rSELF @ arg1 15417 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15418 15419/* ------------------------------ */ 15420 .balign 64 15421.L_ALT_OP_INT_TO_LONG: /* 0x81 */ 15422/* File: armv5te/ALT_STUB.S */ 15423/* 15424 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15425 * any interesting requests and then jump to the real instruction 15426 * handler. Note that the call to dvmCheckInst is done as a tail call. 15427 */ 15428 adrl lr, dvmAsmInstructionStart + (129 * 64) 15429 mov r0, rPC @ arg0 15430 mov r1, rSELF @ arg1 15431 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15432 15433/* ------------------------------ */ 15434 .balign 64 15435.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 15436/* File: armv5te/ALT_STUB.S */ 15437/* 15438 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15439 * any interesting requests and then jump to the real instruction 15440 * handler. Note that the call to dvmCheckInst is done as a tail call. 15441 */ 15442 adrl lr, dvmAsmInstructionStart + (130 * 64) 15443 mov r0, rPC @ arg0 15444 mov r1, rSELF @ arg1 15445 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15446 15447/* ------------------------------ */ 15448 .balign 64 15449.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 15450/* File: armv5te/ALT_STUB.S */ 15451/* 15452 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15453 * any interesting requests and then jump to the real instruction 15454 * handler. Note that the call to dvmCheckInst is done as a tail call. 15455 */ 15456 adrl lr, dvmAsmInstructionStart + (131 * 64) 15457 mov r0, rPC @ arg0 15458 mov r1, rSELF @ arg1 15459 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15460 15461/* ------------------------------ */ 15462 .balign 64 15463.L_ALT_OP_LONG_TO_INT: /* 0x84 */ 15464/* File: armv5te/ALT_STUB.S */ 15465/* 15466 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15467 * any interesting requests and then jump to the real instruction 15468 * handler. Note that the call to dvmCheckInst is done as a tail call. 15469 */ 15470 adrl lr, dvmAsmInstructionStart + (132 * 64) 15471 mov r0, rPC @ arg0 15472 mov r1, rSELF @ arg1 15473 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15474 15475/* ------------------------------ */ 15476 .balign 64 15477.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 15478/* File: armv5te/ALT_STUB.S */ 15479/* 15480 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15481 * any interesting requests and then jump to the real instruction 15482 * handler. Note that the call to dvmCheckInst is done as a tail call. 15483 */ 15484 adrl lr, dvmAsmInstructionStart + (133 * 64) 15485 mov r0, rPC @ arg0 15486 mov r1, rSELF @ arg1 15487 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15488 15489/* ------------------------------ */ 15490 .balign 64 15491.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 15492/* File: armv5te/ALT_STUB.S */ 15493/* 15494 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15495 * any interesting requests and then jump to the real instruction 15496 * handler. Note that the call to dvmCheckInst is done as a tail call. 15497 */ 15498 adrl lr, dvmAsmInstructionStart + (134 * 64) 15499 mov r0, rPC @ arg0 15500 mov r1, rSELF @ arg1 15501 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15502 15503/* ------------------------------ */ 15504 .balign 64 15505.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 15506/* File: armv5te/ALT_STUB.S */ 15507/* 15508 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15509 * any interesting requests and then jump to the real instruction 15510 * handler. Note that the call to dvmCheckInst is done as a tail call. 15511 */ 15512 adrl lr, dvmAsmInstructionStart + (135 * 64) 15513 mov r0, rPC @ arg0 15514 mov r1, rSELF @ arg1 15515 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15516 15517/* ------------------------------ */ 15518 .balign 64 15519.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 15520/* File: armv5te/ALT_STUB.S */ 15521/* 15522 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15523 * any interesting requests and then jump to the real instruction 15524 * handler. Note that the call to dvmCheckInst is done as a tail call. 15525 */ 15526 adrl lr, dvmAsmInstructionStart + (136 * 64) 15527 mov r0, rPC @ arg0 15528 mov r1, rSELF @ arg1 15529 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15530 15531/* ------------------------------ */ 15532 .balign 64 15533.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 15534/* File: armv5te/ALT_STUB.S */ 15535/* 15536 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15537 * any interesting requests and then jump to the real instruction 15538 * handler. Note that the call to dvmCheckInst is done as a tail call. 15539 */ 15540 adrl lr, dvmAsmInstructionStart + (137 * 64) 15541 mov r0, rPC @ arg0 15542 mov r1, rSELF @ arg1 15543 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15544 15545/* ------------------------------ */ 15546 .balign 64 15547.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 15548/* File: armv5te/ALT_STUB.S */ 15549/* 15550 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15551 * any interesting requests and then jump to the real instruction 15552 * handler. Note that the call to dvmCheckInst is done as a tail call. 15553 */ 15554 adrl lr, dvmAsmInstructionStart + (138 * 64) 15555 mov r0, rPC @ arg0 15556 mov r1, rSELF @ arg1 15557 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15558 15559/* ------------------------------ */ 15560 .balign 64 15561.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 15562/* File: armv5te/ALT_STUB.S */ 15563/* 15564 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15565 * any interesting requests and then jump to the real instruction 15566 * handler. Note that the call to dvmCheckInst is done as a tail call. 15567 */ 15568 adrl lr, dvmAsmInstructionStart + (139 * 64) 15569 mov r0, rPC @ arg0 15570 mov r1, rSELF @ arg1 15571 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15572 15573/* ------------------------------ */ 15574 .balign 64 15575.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 15576/* File: armv5te/ALT_STUB.S */ 15577/* 15578 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15579 * any interesting requests and then jump to the real instruction 15580 * handler. Note that the call to dvmCheckInst is done as a tail call. 15581 */ 15582 adrl lr, dvmAsmInstructionStart + (140 * 64) 15583 mov r0, rPC @ arg0 15584 mov r1, rSELF @ arg1 15585 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15586 15587/* ------------------------------ */ 15588 .balign 64 15589.L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 15590/* File: armv5te/ALT_STUB.S */ 15591/* 15592 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15593 * any interesting requests and then jump to the real instruction 15594 * handler. Note that the call to dvmCheckInst is done as a tail call. 15595 */ 15596 adrl lr, dvmAsmInstructionStart + (141 * 64) 15597 mov r0, rPC @ arg0 15598 mov r1, rSELF @ arg1 15599 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15600 15601/* ------------------------------ */ 15602 .balign 64 15603.L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 15604/* File: armv5te/ALT_STUB.S */ 15605/* 15606 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15607 * any interesting requests and then jump to the real instruction 15608 * handler. Note that the call to dvmCheckInst is done as a tail call. 15609 */ 15610 adrl lr, dvmAsmInstructionStart + (142 * 64) 15611 mov r0, rPC @ arg0 15612 mov r1, rSELF @ arg1 15613 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15614 15615/* ------------------------------ */ 15616 .balign 64 15617.L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 15618/* File: armv5te/ALT_STUB.S */ 15619/* 15620 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15621 * any interesting requests and then jump to the real instruction 15622 * handler. Note that the call to dvmCheckInst is done as a tail call. 15623 */ 15624 adrl lr, dvmAsmInstructionStart + (143 * 64) 15625 mov r0, rPC @ arg0 15626 mov r1, rSELF @ arg1 15627 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15628 15629/* ------------------------------ */ 15630 .balign 64 15631.L_ALT_OP_ADD_INT: /* 0x90 */ 15632/* File: armv5te/ALT_STUB.S */ 15633/* 15634 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15635 * any interesting requests and then jump to the real instruction 15636 * handler. Note that the call to dvmCheckInst is done as a tail call. 15637 */ 15638 adrl lr, dvmAsmInstructionStart + (144 * 64) 15639 mov r0, rPC @ arg0 15640 mov r1, rSELF @ arg1 15641 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15642 15643/* ------------------------------ */ 15644 .balign 64 15645.L_ALT_OP_SUB_INT: /* 0x91 */ 15646/* File: armv5te/ALT_STUB.S */ 15647/* 15648 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15649 * any interesting requests and then jump to the real instruction 15650 * handler. Note that the call to dvmCheckInst is done as a tail call. 15651 */ 15652 adrl lr, dvmAsmInstructionStart + (145 * 64) 15653 mov r0, rPC @ arg0 15654 mov r1, rSELF @ arg1 15655 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15656 15657/* ------------------------------ */ 15658 .balign 64 15659.L_ALT_OP_MUL_INT: /* 0x92 */ 15660/* File: armv5te/ALT_STUB.S */ 15661/* 15662 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15663 * any interesting requests and then jump to the real instruction 15664 * handler. Note that the call to dvmCheckInst is done as a tail call. 15665 */ 15666 adrl lr, dvmAsmInstructionStart + (146 * 64) 15667 mov r0, rPC @ arg0 15668 mov r1, rSELF @ arg1 15669 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15670 15671/* ------------------------------ */ 15672 .balign 64 15673.L_ALT_OP_DIV_INT: /* 0x93 */ 15674/* File: armv5te/ALT_STUB.S */ 15675/* 15676 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15677 * any interesting requests and then jump to the real instruction 15678 * handler. Note that the call to dvmCheckInst is done as a tail call. 15679 */ 15680 adrl lr, dvmAsmInstructionStart + (147 * 64) 15681 mov r0, rPC @ arg0 15682 mov r1, rSELF @ arg1 15683 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15684 15685/* ------------------------------ */ 15686 .balign 64 15687.L_ALT_OP_REM_INT: /* 0x94 */ 15688/* File: armv5te/ALT_STUB.S */ 15689/* 15690 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15691 * any interesting requests and then jump to the real instruction 15692 * handler. Note that the call to dvmCheckInst is done as a tail call. 15693 */ 15694 adrl lr, dvmAsmInstructionStart + (148 * 64) 15695 mov r0, rPC @ arg0 15696 mov r1, rSELF @ arg1 15697 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15698 15699/* ------------------------------ */ 15700 .balign 64 15701.L_ALT_OP_AND_INT: /* 0x95 */ 15702/* File: armv5te/ALT_STUB.S */ 15703/* 15704 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15705 * any interesting requests and then jump to the real instruction 15706 * handler. Note that the call to dvmCheckInst is done as a tail call. 15707 */ 15708 adrl lr, dvmAsmInstructionStart + (149 * 64) 15709 mov r0, rPC @ arg0 15710 mov r1, rSELF @ arg1 15711 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15712 15713/* ------------------------------ */ 15714 .balign 64 15715.L_ALT_OP_OR_INT: /* 0x96 */ 15716/* File: armv5te/ALT_STUB.S */ 15717/* 15718 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15719 * any interesting requests and then jump to the real instruction 15720 * handler. Note that the call to dvmCheckInst is done as a tail call. 15721 */ 15722 adrl lr, dvmAsmInstructionStart + (150 * 64) 15723 mov r0, rPC @ arg0 15724 mov r1, rSELF @ arg1 15725 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15726 15727/* ------------------------------ */ 15728 .balign 64 15729.L_ALT_OP_XOR_INT: /* 0x97 */ 15730/* File: armv5te/ALT_STUB.S */ 15731/* 15732 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15733 * any interesting requests and then jump to the real instruction 15734 * handler. Note that the call to dvmCheckInst is done as a tail call. 15735 */ 15736 adrl lr, dvmAsmInstructionStart + (151 * 64) 15737 mov r0, rPC @ arg0 15738 mov r1, rSELF @ arg1 15739 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15740 15741/* ------------------------------ */ 15742 .balign 64 15743.L_ALT_OP_SHL_INT: /* 0x98 */ 15744/* File: armv5te/ALT_STUB.S */ 15745/* 15746 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15747 * any interesting requests and then jump to the real instruction 15748 * handler. Note that the call to dvmCheckInst is done as a tail call. 15749 */ 15750 adrl lr, dvmAsmInstructionStart + (152 * 64) 15751 mov r0, rPC @ arg0 15752 mov r1, rSELF @ arg1 15753 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15754 15755/* ------------------------------ */ 15756 .balign 64 15757.L_ALT_OP_SHR_INT: /* 0x99 */ 15758/* File: armv5te/ALT_STUB.S */ 15759/* 15760 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15761 * any interesting requests and then jump to the real instruction 15762 * handler. Note that the call to dvmCheckInst is done as a tail call. 15763 */ 15764 adrl lr, dvmAsmInstructionStart + (153 * 64) 15765 mov r0, rPC @ arg0 15766 mov r1, rSELF @ arg1 15767 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15768 15769/* ------------------------------ */ 15770 .balign 64 15771.L_ALT_OP_USHR_INT: /* 0x9a */ 15772/* File: armv5te/ALT_STUB.S */ 15773/* 15774 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15775 * any interesting requests and then jump to the real instruction 15776 * handler. Note that the call to dvmCheckInst is done as a tail call. 15777 */ 15778 adrl lr, dvmAsmInstructionStart + (154 * 64) 15779 mov r0, rPC @ arg0 15780 mov r1, rSELF @ arg1 15781 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15782 15783/* ------------------------------ */ 15784 .balign 64 15785.L_ALT_OP_ADD_LONG: /* 0x9b */ 15786/* File: armv5te/ALT_STUB.S */ 15787/* 15788 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15789 * any interesting requests and then jump to the real instruction 15790 * handler. Note that the call to dvmCheckInst is done as a tail call. 15791 */ 15792 adrl lr, dvmAsmInstructionStart + (155 * 64) 15793 mov r0, rPC @ arg0 15794 mov r1, rSELF @ arg1 15795 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15796 15797/* ------------------------------ */ 15798 .balign 64 15799.L_ALT_OP_SUB_LONG: /* 0x9c */ 15800/* File: armv5te/ALT_STUB.S */ 15801/* 15802 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15803 * any interesting requests and then jump to the real instruction 15804 * handler. Note that the call to dvmCheckInst is done as a tail call. 15805 */ 15806 adrl lr, dvmAsmInstructionStart + (156 * 64) 15807 mov r0, rPC @ arg0 15808 mov r1, rSELF @ arg1 15809 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15810 15811/* ------------------------------ */ 15812 .balign 64 15813.L_ALT_OP_MUL_LONG: /* 0x9d */ 15814/* File: armv5te/ALT_STUB.S */ 15815/* 15816 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15817 * any interesting requests and then jump to the real instruction 15818 * handler. Note that the call to dvmCheckInst is done as a tail call. 15819 */ 15820 adrl lr, dvmAsmInstructionStart + (157 * 64) 15821 mov r0, rPC @ arg0 15822 mov r1, rSELF @ arg1 15823 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15824 15825/* ------------------------------ */ 15826 .balign 64 15827.L_ALT_OP_DIV_LONG: /* 0x9e */ 15828/* File: armv5te/ALT_STUB.S */ 15829/* 15830 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15831 * any interesting requests and then jump to the real instruction 15832 * handler. Note that the call to dvmCheckInst is done as a tail call. 15833 */ 15834 adrl lr, dvmAsmInstructionStart + (158 * 64) 15835 mov r0, rPC @ arg0 15836 mov r1, rSELF @ arg1 15837 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15838 15839/* ------------------------------ */ 15840 .balign 64 15841.L_ALT_OP_REM_LONG: /* 0x9f */ 15842/* File: armv5te/ALT_STUB.S */ 15843/* 15844 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15845 * any interesting requests and then jump to the real instruction 15846 * handler. Note that the call to dvmCheckInst is done as a tail call. 15847 */ 15848 adrl lr, dvmAsmInstructionStart + (159 * 64) 15849 mov r0, rPC @ arg0 15850 mov r1, rSELF @ arg1 15851 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15852 15853/* ------------------------------ */ 15854 .balign 64 15855.L_ALT_OP_AND_LONG: /* 0xa0 */ 15856/* File: armv5te/ALT_STUB.S */ 15857/* 15858 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15859 * any interesting requests and then jump to the real instruction 15860 * handler. Note that the call to dvmCheckInst is done as a tail call. 15861 */ 15862 adrl lr, dvmAsmInstructionStart + (160 * 64) 15863 mov r0, rPC @ arg0 15864 mov r1, rSELF @ arg1 15865 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15866 15867/* ------------------------------ */ 15868 .balign 64 15869.L_ALT_OP_OR_LONG: /* 0xa1 */ 15870/* File: armv5te/ALT_STUB.S */ 15871/* 15872 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15873 * any interesting requests and then jump to the real instruction 15874 * handler. Note that the call to dvmCheckInst is done as a tail call. 15875 */ 15876 adrl lr, dvmAsmInstructionStart + (161 * 64) 15877 mov r0, rPC @ arg0 15878 mov r1, rSELF @ arg1 15879 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15880 15881/* ------------------------------ */ 15882 .balign 64 15883.L_ALT_OP_XOR_LONG: /* 0xa2 */ 15884/* File: armv5te/ALT_STUB.S */ 15885/* 15886 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15887 * any interesting requests and then jump to the real instruction 15888 * handler. Note that the call to dvmCheckInst is done as a tail call. 15889 */ 15890 adrl lr, dvmAsmInstructionStart + (162 * 64) 15891 mov r0, rPC @ arg0 15892 mov r1, rSELF @ arg1 15893 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15894 15895/* ------------------------------ */ 15896 .balign 64 15897.L_ALT_OP_SHL_LONG: /* 0xa3 */ 15898/* File: armv5te/ALT_STUB.S */ 15899/* 15900 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15901 * any interesting requests and then jump to the real instruction 15902 * handler. Note that the call to dvmCheckInst is done as a tail call. 15903 */ 15904 adrl lr, dvmAsmInstructionStart + (163 * 64) 15905 mov r0, rPC @ arg0 15906 mov r1, rSELF @ arg1 15907 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15908 15909/* ------------------------------ */ 15910 .balign 64 15911.L_ALT_OP_SHR_LONG: /* 0xa4 */ 15912/* File: armv5te/ALT_STUB.S */ 15913/* 15914 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15915 * any interesting requests and then jump to the real instruction 15916 * handler. Note that the call to dvmCheckInst is done as a tail call. 15917 */ 15918 adrl lr, dvmAsmInstructionStart + (164 * 64) 15919 mov r0, rPC @ arg0 15920 mov r1, rSELF @ arg1 15921 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15922 15923/* ------------------------------ */ 15924 .balign 64 15925.L_ALT_OP_USHR_LONG: /* 0xa5 */ 15926/* File: armv5te/ALT_STUB.S */ 15927/* 15928 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15929 * any interesting requests and then jump to the real instruction 15930 * handler. Note that the call to dvmCheckInst is done as a tail call. 15931 */ 15932 adrl lr, dvmAsmInstructionStart + (165 * 64) 15933 mov r0, rPC @ arg0 15934 mov r1, rSELF @ arg1 15935 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15936 15937/* ------------------------------ */ 15938 .balign 64 15939.L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 15940/* File: armv5te/ALT_STUB.S */ 15941/* 15942 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15943 * any interesting requests and then jump to the real instruction 15944 * handler. Note that the call to dvmCheckInst is done as a tail call. 15945 */ 15946 adrl lr, dvmAsmInstructionStart + (166 * 64) 15947 mov r0, rPC @ arg0 15948 mov r1, rSELF @ arg1 15949 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15950 15951/* ------------------------------ */ 15952 .balign 64 15953.L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 15954/* File: armv5te/ALT_STUB.S */ 15955/* 15956 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15957 * any interesting requests and then jump to the real instruction 15958 * handler. Note that the call to dvmCheckInst is done as a tail call. 15959 */ 15960 adrl lr, dvmAsmInstructionStart + (167 * 64) 15961 mov r0, rPC @ arg0 15962 mov r1, rSELF @ arg1 15963 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15964 15965/* ------------------------------ */ 15966 .balign 64 15967.L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 15968/* File: armv5te/ALT_STUB.S */ 15969/* 15970 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15971 * any interesting requests and then jump to the real instruction 15972 * handler. Note that the call to dvmCheckInst is done as a tail call. 15973 */ 15974 adrl lr, dvmAsmInstructionStart + (168 * 64) 15975 mov r0, rPC @ arg0 15976 mov r1, rSELF @ arg1 15977 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15978 15979/* ------------------------------ */ 15980 .balign 64 15981.L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 15982/* File: armv5te/ALT_STUB.S */ 15983/* 15984 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15985 * any interesting requests and then jump to the real instruction 15986 * handler. Note that the call to dvmCheckInst is done as a tail call. 15987 */ 15988 adrl lr, dvmAsmInstructionStart + (169 * 64) 15989 mov r0, rPC @ arg0 15990 mov r1, rSELF @ arg1 15991 b dvmCheckInst @ (dPC,self) tail call to instruction checker 15992 15993/* ------------------------------ */ 15994 .balign 64 15995.L_ALT_OP_REM_FLOAT: /* 0xaa */ 15996/* File: armv5te/ALT_STUB.S */ 15997/* 15998 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 15999 * any interesting requests and then jump to the real instruction 16000 * handler. Note that the call to dvmCheckInst is done as a tail call. 16001 */ 16002 adrl lr, dvmAsmInstructionStart + (170 * 64) 16003 mov r0, rPC @ arg0 16004 mov r1, rSELF @ arg1 16005 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16006 16007/* ------------------------------ */ 16008 .balign 64 16009.L_ALT_OP_ADD_DOUBLE: /* 0xab */ 16010/* File: armv5te/ALT_STUB.S */ 16011/* 16012 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16013 * any interesting requests and then jump to the real instruction 16014 * handler. Note that the call to dvmCheckInst is done as a tail call. 16015 */ 16016 adrl lr, dvmAsmInstructionStart + (171 * 64) 16017 mov r0, rPC @ arg0 16018 mov r1, rSELF @ arg1 16019 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16020 16021/* ------------------------------ */ 16022 .balign 64 16023.L_ALT_OP_SUB_DOUBLE: /* 0xac */ 16024/* File: armv5te/ALT_STUB.S */ 16025/* 16026 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16027 * any interesting requests and then jump to the real instruction 16028 * handler. Note that the call to dvmCheckInst is done as a tail call. 16029 */ 16030 adrl lr, dvmAsmInstructionStart + (172 * 64) 16031 mov r0, rPC @ arg0 16032 mov r1, rSELF @ arg1 16033 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16034 16035/* ------------------------------ */ 16036 .balign 64 16037.L_ALT_OP_MUL_DOUBLE: /* 0xad */ 16038/* File: armv5te/ALT_STUB.S */ 16039/* 16040 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16041 * any interesting requests and then jump to the real instruction 16042 * handler. Note that the call to dvmCheckInst is done as a tail call. 16043 */ 16044 adrl lr, dvmAsmInstructionStart + (173 * 64) 16045 mov r0, rPC @ arg0 16046 mov r1, rSELF @ arg1 16047 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16048 16049/* ------------------------------ */ 16050 .balign 64 16051.L_ALT_OP_DIV_DOUBLE: /* 0xae */ 16052/* File: armv5te/ALT_STUB.S */ 16053/* 16054 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16055 * any interesting requests and then jump to the real instruction 16056 * handler. Note that the call to dvmCheckInst is done as a tail call. 16057 */ 16058 adrl lr, dvmAsmInstructionStart + (174 * 64) 16059 mov r0, rPC @ arg0 16060 mov r1, rSELF @ arg1 16061 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16062 16063/* ------------------------------ */ 16064 .balign 64 16065.L_ALT_OP_REM_DOUBLE: /* 0xaf */ 16066/* File: armv5te/ALT_STUB.S */ 16067/* 16068 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16069 * any interesting requests and then jump to the real instruction 16070 * handler. Note that the call to dvmCheckInst is done as a tail call. 16071 */ 16072 adrl lr, dvmAsmInstructionStart + (175 * 64) 16073 mov r0, rPC @ arg0 16074 mov r1, rSELF @ arg1 16075 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16076 16077/* ------------------------------ */ 16078 .balign 64 16079.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 16080/* File: armv5te/ALT_STUB.S */ 16081/* 16082 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16083 * any interesting requests and then jump to the real instruction 16084 * handler. Note that the call to dvmCheckInst is done as a tail call. 16085 */ 16086 adrl lr, dvmAsmInstructionStart + (176 * 64) 16087 mov r0, rPC @ arg0 16088 mov r1, rSELF @ arg1 16089 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16090 16091/* ------------------------------ */ 16092 .balign 64 16093.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 16094/* File: armv5te/ALT_STUB.S */ 16095/* 16096 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16097 * any interesting requests and then jump to the real instruction 16098 * handler. Note that the call to dvmCheckInst is done as a tail call. 16099 */ 16100 adrl lr, dvmAsmInstructionStart + (177 * 64) 16101 mov r0, rPC @ arg0 16102 mov r1, rSELF @ arg1 16103 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16104 16105/* ------------------------------ */ 16106 .balign 64 16107.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 16108/* File: armv5te/ALT_STUB.S */ 16109/* 16110 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16111 * any interesting requests and then jump to the real instruction 16112 * handler. Note that the call to dvmCheckInst is done as a tail call. 16113 */ 16114 adrl lr, dvmAsmInstructionStart + (178 * 64) 16115 mov r0, rPC @ arg0 16116 mov r1, rSELF @ arg1 16117 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16118 16119/* ------------------------------ */ 16120 .balign 64 16121.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 16122/* File: armv5te/ALT_STUB.S */ 16123/* 16124 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16125 * any interesting requests and then jump to the real instruction 16126 * handler. Note that the call to dvmCheckInst is done as a tail call. 16127 */ 16128 adrl lr, dvmAsmInstructionStart + (179 * 64) 16129 mov r0, rPC @ arg0 16130 mov r1, rSELF @ arg1 16131 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16132 16133/* ------------------------------ */ 16134 .balign 64 16135.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 16136/* File: armv5te/ALT_STUB.S */ 16137/* 16138 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16139 * any interesting requests and then jump to the real instruction 16140 * handler. Note that the call to dvmCheckInst is done as a tail call. 16141 */ 16142 adrl lr, dvmAsmInstructionStart + (180 * 64) 16143 mov r0, rPC @ arg0 16144 mov r1, rSELF @ arg1 16145 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16146 16147/* ------------------------------ */ 16148 .balign 64 16149.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 16150/* File: armv5te/ALT_STUB.S */ 16151/* 16152 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16153 * any interesting requests and then jump to the real instruction 16154 * handler. Note that the call to dvmCheckInst is done as a tail call. 16155 */ 16156 adrl lr, dvmAsmInstructionStart + (181 * 64) 16157 mov r0, rPC @ arg0 16158 mov r1, rSELF @ arg1 16159 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16160 16161/* ------------------------------ */ 16162 .balign 64 16163.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 16164/* File: armv5te/ALT_STUB.S */ 16165/* 16166 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16167 * any interesting requests and then jump to the real instruction 16168 * handler. Note that the call to dvmCheckInst is done as a tail call. 16169 */ 16170 adrl lr, dvmAsmInstructionStart + (182 * 64) 16171 mov r0, rPC @ arg0 16172 mov r1, rSELF @ arg1 16173 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16174 16175/* ------------------------------ */ 16176 .balign 64 16177.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 16178/* File: armv5te/ALT_STUB.S */ 16179/* 16180 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16181 * any interesting requests and then jump to the real instruction 16182 * handler. Note that the call to dvmCheckInst is done as a tail call. 16183 */ 16184 adrl lr, dvmAsmInstructionStart + (183 * 64) 16185 mov r0, rPC @ arg0 16186 mov r1, rSELF @ arg1 16187 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16188 16189/* ------------------------------ */ 16190 .balign 64 16191.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 16192/* File: armv5te/ALT_STUB.S */ 16193/* 16194 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16195 * any interesting requests and then jump to the real instruction 16196 * handler. Note that the call to dvmCheckInst is done as a tail call. 16197 */ 16198 adrl lr, dvmAsmInstructionStart + (184 * 64) 16199 mov r0, rPC @ arg0 16200 mov r1, rSELF @ arg1 16201 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16202 16203/* ------------------------------ */ 16204 .balign 64 16205.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 16206/* File: armv5te/ALT_STUB.S */ 16207/* 16208 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16209 * any interesting requests and then jump to the real instruction 16210 * handler. Note that the call to dvmCheckInst is done as a tail call. 16211 */ 16212 adrl lr, dvmAsmInstructionStart + (185 * 64) 16213 mov r0, rPC @ arg0 16214 mov r1, rSELF @ arg1 16215 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16216 16217/* ------------------------------ */ 16218 .balign 64 16219.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 16220/* File: armv5te/ALT_STUB.S */ 16221/* 16222 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16223 * any interesting requests and then jump to the real instruction 16224 * handler. Note that the call to dvmCheckInst is done as a tail call. 16225 */ 16226 adrl lr, dvmAsmInstructionStart + (186 * 64) 16227 mov r0, rPC @ arg0 16228 mov r1, rSELF @ arg1 16229 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16230 16231/* ------------------------------ */ 16232 .balign 64 16233.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 16234/* File: armv5te/ALT_STUB.S */ 16235/* 16236 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16237 * any interesting requests and then jump to the real instruction 16238 * handler. Note that the call to dvmCheckInst is done as a tail call. 16239 */ 16240 adrl lr, dvmAsmInstructionStart + (187 * 64) 16241 mov r0, rPC @ arg0 16242 mov r1, rSELF @ arg1 16243 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16244 16245/* ------------------------------ */ 16246 .balign 64 16247.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 16248/* File: armv5te/ALT_STUB.S */ 16249/* 16250 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16251 * any interesting requests and then jump to the real instruction 16252 * handler. Note that the call to dvmCheckInst is done as a tail call. 16253 */ 16254 adrl lr, dvmAsmInstructionStart + (188 * 64) 16255 mov r0, rPC @ arg0 16256 mov r1, rSELF @ arg1 16257 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16258 16259/* ------------------------------ */ 16260 .balign 64 16261.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 16262/* File: armv5te/ALT_STUB.S */ 16263/* 16264 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16265 * any interesting requests and then jump to the real instruction 16266 * handler. Note that the call to dvmCheckInst is done as a tail call. 16267 */ 16268 adrl lr, dvmAsmInstructionStart + (189 * 64) 16269 mov r0, rPC @ arg0 16270 mov r1, rSELF @ arg1 16271 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16272 16273/* ------------------------------ */ 16274 .balign 64 16275.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 16276/* File: armv5te/ALT_STUB.S */ 16277/* 16278 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16279 * any interesting requests and then jump to the real instruction 16280 * handler. Note that the call to dvmCheckInst is done as a tail call. 16281 */ 16282 adrl lr, dvmAsmInstructionStart + (190 * 64) 16283 mov r0, rPC @ arg0 16284 mov r1, rSELF @ arg1 16285 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16286 16287/* ------------------------------ */ 16288 .balign 64 16289.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 16290/* File: armv5te/ALT_STUB.S */ 16291/* 16292 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16293 * any interesting requests and then jump to the real instruction 16294 * handler. Note that the call to dvmCheckInst is done as a tail call. 16295 */ 16296 adrl lr, dvmAsmInstructionStart + (191 * 64) 16297 mov r0, rPC @ arg0 16298 mov r1, rSELF @ arg1 16299 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16300 16301/* ------------------------------ */ 16302 .balign 64 16303.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 16304/* File: armv5te/ALT_STUB.S */ 16305/* 16306 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16307 * any interesting requests and then jump to the real instruction 16308 * handler. Note that the call to dvmCheckInst is done as a tail call. 16309 */ 16310 adrl lr, dvmAsmInstructionStart + (192 * 64) 16311 mov r0, rPC @ arg0 16312 mov r1, rSELF @ arg1 16313 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16314 16315/* ------------------------------ */ 16316 .balign 64 16317.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 16318/* File: armv5te/ALT_STUB.S */ 16319/* 16320 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16321 * any interesting requests and then jump to the real instruction 16322 * handler. Note that the call to dvmCheckInst is done as a tail call. 16323 */ 16324 adrl lr, dvmAsmInstructionStart + (193 * 64) 16325 mov r0, rPC @ arg0 16326 mov r1, rSELF @ arg1 16327 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16328 16329/* ------------------------------ */ 16330 .balign 64 16331.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 16332/* File: armv5te/ALT_STUB.S */ 16333/* 16334 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16335 * any interesting requests and then jump to the real instruction 16336 * handler. Note that the call to dvmCheckInst is done as a tail call. 16337 */ 16338 adrl lr, dvmAsmInstructionStart + (194 * 64) 16339 mov r0, rPC @ arg0 16340 mov r1, rSELF @ arg1 16341 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16342 16343/* ------------------------------ */ 16344 .balign 64 16345.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 16346/* File: armv5te/ALT_STUB.S */ 16347/* 16348 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16349 * any interesting requests and then jump to the real instruction 16350 * handler. Note that the call to dvmCheckInst is done as a tail call. 16351 */ 16352 adrl lr, dvmAsmInstructionStart + (195 * 64) 16353 mov r0, rPC @ arg0 16354 mov r1, rSELF @ arg1 16355 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16356 16357/* ------------------------------ */ 16358 .balign 64 16359.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 16360/* File: armv5te/ALT_STUB.S */ 16361/* 16362 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16363 * any interesting requests and then jump to the real instruction 16364 * handler. Note that the call to dvmCheckInst is done as a tail call. 16365 */ 16366 adrl lr, dvmAsmInstructionStart + (196 * 64) 16367 mov r0, rPC @ arg0 16368 mov r1, rSELF @ arg1 16369 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16370 16371/* ------------------------------ */ 16372 .balign 64 16373.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 16374/* File: armv5te/ALT_STUB.S */ 16375/* 16376 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16377 * any interesting requests and then jump to the real instruction 16378 * handler. Note that the call to dvmCheckInst is done as a tail call. 16379 */ 16380 adrl lr, dvmAsmInstructionStart + (197 * 64) 16381 mov r0, rPC @ arg0 16382 mov r1, rSELF @ arg1 16383 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16384 16385/* ------------------------------ */ 16386 .balign 64 16387.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 16388/* File: armv5te/ALT_STUB.S */ 16389/* 16390 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16391 * any interesting requests and then jump to the real instruction 16392 * handler. Note that the call to dvmCheckInst is done as a tail call. 16393 */ 16394 adrl lr, dvmAsmInstructionStart + (198 * 64) 16395 mov r0, rPC @ arg0 16396 mov r1, rSELF @ arg1 16397 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16398 16399/* ------------------------------ */ 16400 .balign 64 16401.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 16402/* File: armv5te/ALT_STUB.S */ 16403/* 16404 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16405 * any interesting requests and then jump to the real instruction 16406 * handler. Note that the call to dvmCheckInst is done as a tail call. 16407 */ 16408 adrl lr, dvmAsmInstructionStart + (199 * 64) 16409 mov r0, rPC @ arg0 16410 mov r1, rSELF @ arg1 16411 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16412 16413/* ------------------------------ */ 16414 .balign 64 16415.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 16416/* File: armv5te/ALT_STUB.S */ 16417/* 16418 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16419 * any interesting requests and then jump to the real instruction 16420 * handler. Note that the call to dvmCheckInst is done as a tail call. 16421 */ 16422 adrl lr, dvmAsmInstructionStart + (200 * 64) 16423 mov r0, rPC @ arg0 16424 mov r1, rSELF @ arg1 16425 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16426 16427/* ------------------------------ */ 16428 .balign 64 16429.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 16430/* File: armv5te/ALT_STUB.S */ 16431/* 16432 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16433 * any interesting requests and then jump to the real instruction 16434 * handler. Note that the call to dvmCheckInst is done as a tail call. 16435 */ 16436 adrl lr, dvmAsmInstructionStart + (201 * 64) 16437 mov r0, rPC @ arg0 16438 mov r1, rSELF @ arg1 16439 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16440 16441/* ------------------------------ */ 16442 .balign 64 16443.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 16444/* File: armv5te/ALT_STUB.S */ 16445/* 16446 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16447 * any interesting requests and then jump to the real instruction 16448 * handler. Note that the call to dvmCheckInst is done as a tail call. 16449 */ 16450 adrl lr, dvmAsmInstructionStart + (202 * 64) 16451 mov r0, rPC @ arg0 16452 mov r1, rSELF @ arg1 16453 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16454 16455/* ------------------------------ */ 16456 .balign 64 16457.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 16458/* File: armv5te/ALT_STUB.S */ 16459/* 16460 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16461 * any interesting requests and then jump to the real instruction 16462 * handler. Note that the call to dvmCheckInst is done as a tail call. 16463 */ 16464 adrl lr, dvmAsmInstructionStart + (203 * 64) 16465 mov r0, rPC @ arg0 16466 mov r1, rSELF @ arg1 16467 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16468 16469/* ------------------------------ */ 16470 .balign 64 16471.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 16472/* File: armv5te/ALT_STUB.S */ 16473/* 16474 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16475 * any interesting requests and then jump to the real instruction 16476 * handler. Note that the call to dvmCheckInst is done as a tail call. 16477 */ 16478 adrl lr, dvmAsmInstructionStart + (204 * 64) 16479 mov r0, rPC @ arg0 16480 mov r1, rSELF @ arg1 16481 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16482 16483/* ------------------------------ */ 16484 .balign 64 16485.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 16486/* File: armv5te/ALT_STUB.S */ 16487/* 16488 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16489 * any interesting requests and then jump to the real instruction 16490 * handler. Note that the call to dvmCheckInst is done as a tail call. 16491 */ 16492 adrl lr, dvmAsmInstructionStart + (205 * 64) 16493 mov r0, rPC @ arg0 16494 mov r1, rSELF @ arg1 16495 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16496 16497/* ------------------------------ */ 16498 .balign 64 16499.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 16500/* File: armv5te/ALT_STUB.S */ 16501/* 16502 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16503 * any interesting requests and then jump to the real instruction 16504 * handler. Note that the call to dvmCheckInst is done as a tail call. 16505 */ 16506 adrl lr, dvmAsmInstructionStart + (206 * 64) 16507 mov r0, rPC @ arg0 16508 mov r1, rSELF @ arg1 16509 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16510 16511/* ------------------------------ */ 16512 .balign 64 16513.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 16514/* File: armv5te/ALT_STUB.S */ 16515/* 16516 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16517 * any interesting requests and then jump to the real instruction 16518 * handler. Note that the call to dvmCheckInst is done as a tail call. 16519 */ 16520 adrl lr, dvmAsmInstructionStart + (207 * 64) 16521 mov r0, rPC @ arg0 16522 mov r1, rSELF @ arg1 16523 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16524 16525/* ------------------------------ */ 16526 .balign 64 16527.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 16528/* File: armv5te/ALT_STUB.S */ 16529/* 16530 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16531 * any interesting requests and then jump to the real instruction 16532 * handler. Note that the call to dvmCheckInst is done as a tail call. 16533 */ 16534 adrl lr, dvmAsmInstructionStart + (208 * 64) 16535 mov r0, rPC @ arg0 16536 mov r1, rSELF @ arg1 16537 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16538 16539/* ------------------------------ */ 16540 .balign 64 16541.L_ALT_OP_RSUB_INT: /* 0xd1 */ 16542/* File: armv5te/ALT_STUB.S */ 16543/* 16544 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16545 * any interesting requests and then jump to the real instruction 16546 * handler. Note that the call to dvmCheckInst is done as a tail call. 16547 */ 16548 adrl lr, dvmAsmInstructionStart + (209 * 64) 16549 mov r0, rPC @ arg0 16550 mov r1, rSELF @ arg1 16551 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16552 16553/* ------------------------------ */ 16554 .balign 64 16555.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 16556/* File: armv5te/ALT_STUB.S */ 16557/* 16558 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16559 * any interesting requests and then jump to the real instruction 16560 * handler. Note that the call to dvmCheckInst is done as a tail call. 16561 */ 16562 adrl lr, dvmAsmInstructionStart + (210 * 64) 16563 mov r0, rPC @ arg0 16564 mov r1, rSELF @ arg1 16565 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16566 16567/* ------------------------------ */ 16568 .balign 64 16569.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 16570/* File: armv5te/ALT_STUB.S */ 16571/* 16572 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16573 * any interesting requests and then jump to the real instruction 16574 * handler. Note that the call to dvmCheckInst is done as a tail call. 16575 */ 16576 adrl lr, dvmAsmInstructionStart + (211 * 64) 16577 mov r0, rPC @ arg0 16578 mov r1, rSELF @ arg1 16579 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16580 16581/* ------------------------------ */ 16582 .balign 64 16583.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 16584/* File: armv5te/ALT_STUB.S */ 16585/* 16586 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16587 * any interesting requests and then jump to the real instruction 16588 * handler. Note that the call to dvmCheckInst is done as a tail call. 16589 */ 16590 adrl lr, dvmAsmInstructionStart + (212 * 64) 16591 mov r0, rPC @ arg0 16592 mov r1, rSELF @ arg1 16593 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16594 16595/* ------------------------------ */ 16596 .balign 64 16597.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 16598/* File: armv5te/ALT_STUB.S */ 16599/* 16600 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16601 * any interesting requests and then jump to the real instruction 16602 * handler. Note that the call to dvmCheckInst is done as a tail call. 16603 */ 16604 adrl lr, dvmAsmInstructionStart + (213 * 64) 16605 mov r0, rPC @ arg0 16606 mov r1, rSELF @ arg1 16607 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16608 16609/* ------------------------------ */ 16610 .balign 64 16611.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 16612/* File: armv5te/ALT_STUB.S */ 16613/* 16614 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16615 * any interesting requests and then jump to the real instruction 16616 * handler. Note that the call to dvmCheckInst is done as a tail call. 16617 */ 16618 adrl lr, dvmAsmInstructionStart + (214 * 64) 16619 mov r0, rPC @ arg0 16620 mov r1, rSELF @ arg1 16621 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16622 16623/* ------------------------------ */ 16624 .balign 64 16625.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 16626/* File: armv5te/ALT_STUB.S */ 16627/* 16628 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16629 * any interesting requests and then jump to the real instruction 16630 * handler. Note that the call to dvmCheckInst is done as a tail call. 16631 */ 16632 adrl lr, dvmAsmInstructionStart + (215 * 64) 16633 mov r0, rPC @ arg0 16634 mov r1, rSELF @ arg1 16635 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16636 16637/* ------------------------------ */ 16638 .balign 64 16639.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 16640/* File: armv5te/ALT_STUB.S */ 16641/* 16642 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16643 * any interesting requests and then jump to the real instruction 16644 * handler. Note that the call to dvmCheckInst is done as a tail call. 16645 */ 16646 adrl lr, dvmAsmInstructionStart + (216 * 64) 16647 mov r0, rPC @ arg0 16648 mov r1, rSELF @ arg1 16649 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16650 16651/* ------------------------------ */ 16652 .balign 64 16653.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 16654/* File: armv5te/ALT_STUB.S */ 16655/* 16656 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16657 * any interesting requests and then jump to the real instruction 16658 * handler. Note that the call to dvmCheckInst is done as a tail call. 16659 */ 16660 adrl lr, dvmAsmInstructionStart + (217 * 64) 16661 mov r0, rPC @ arg0 16662 mov r1, rSELF @ arg1 16663 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16664 16665/* ------------------------------ */ 16666 .balign 64 16667.L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 16668/* File: armv5te/ALT_STUB.S */ 16669/* 16670 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16671 * any interesting requests and then jump to the real instruction 16672 * handler. Note that the call to dvmCheckInst is done as a tail call. 16673 */ 16674 adrl lr, dvmAsmInstructionStart + (218 * 64) 16675 mov r0, rPC @ arg0 16676 mov r1, rSELF @ arg1 16677 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16678 16679/* ------------------------------ */ 16680 .balign 64 16681.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 16682/* File: armv5te/ALT_STUB.S */ 16683/* 16684 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16685 * any interesting requests and then jump to the real instruction 16686 * handler. Note that the call to dvmCheckInst is done as a tail call. 16687 */ 16688 adrl lr, dvmAsmInstructionStart + (219 * 64) 16689 mov r0, rPC @ arg0 16690 mov r1, rSELF @ arg1 16691 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16692 16693/* ------------------------------ */ 16694 .balign 64 16695.L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 16696/* File: armv5te/ALT_STUB.S */ 16697/* 16698 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16699 * any interesting requests and then jump to the real instruction 16700 * handler. Note that the call to dvmCheckInst is done as a tail call. 16701 */ 16702 adrl lr, dvmAsmInstructionStart + (220 * 64) 16703 mov r0, rPC @ arg0 16704 mov r1, rSELF @ arg1 16705 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16706 16707/* ------------------------------ */ 16708 .balign 64 16709.L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 16710/* File: armv5te/ALT_STUB.S */ 16711/* 16712 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16713 * any interesting requests and then jump to the real instruction 16714 * handler. Note that the call to dvmCheckInst is done as a tail call. 16715 */ 16716 adrl lr, dvmAsmInstructionStart + (221 * 64) 16717 mov r0, rPC @ arg0 16718 mov r1, rSELF @ arg1 16719 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16720 16721/* ------------------------------ */ 16722 .balign 64 16723.L_ALT_OP_OR_INT_LIT8: /* 0xde */ 16724/* File: armv5te/ALT_STUB.S */ 16725/* 16726 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16727 * any interesting requests and then jump to the real instruction 16728 * handler. Note that the call to dvmCheckInst is done as a tail call. 16729 */ 16730 adrl lr, dvmAsmInstructionStart + (222 * 64) 16731 mov r0, rPC @ arg0 16732 mov r1, rSELF @ arg1 16733 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16734 16735/* ------------------------------ */ 16736 .balign 64 16737.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 16738/* File: armv5te/ALT_STUB.S */ 16739/* 16740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16741 * any interesting requests and then jump to the real instruction 16742 * handler. Note that the call to dvmCheckInst is done as a tail call. 16743 */ 16744 adrl lr, dvmAsmInstructionStart + (223 * 64) 16745 mov r0, rPC @ arg0 16746 mov r1, rSELF @ arg1 16747 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16748 16749/* ------------------------------ */ 16750 .balign 64 16751.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 16752/* File: armv5te/ALT_STUB.S */ 16753/* 16754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16755 * any interesting requests and then jump to the real instruction 16756 * handler. Note that the call to dvmCheckInst is done as a tail call. 16757 */ 16758 adrl lr, dvmAsmInstructionStart + (224 * 64) 16759 mov r0, rPC @ arg0 16760 mov r1, rSELF @ arg1 16761 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16762 16763/* ------------------------------ */ 16764 .balign 64 16765.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 16766/* File: armv5te/ALT_STUB.S */ 16767/* 16768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16769 * any interesting requests and then jump to the real instruction 16770 * handler. Note that the call to dvmCheckInst is done as a tail call. 16771 */ 16772 adrl lr, dvmAsmInstructionStart + (225 * 64) 16773 mov r0, rPC @ arg0 16774 mov r1, rSELF @ arg1 16775 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16776 16777/* ------------------------------ */ 16778 .balign 64 16779.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 16780/* File: armv5te/ALT_STUB.S */ 16781/* 16782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16783 * any interesting requests and then jump to the real instruction 16784 * handler. Note that the call to dvmCheckInst is done as a tail call. 16785 */ 16786 adrl lr, dvmAsmInstructionStart + (226 * 64) 16787 mov r0, rPC @ arg0 16788 mov r1, rSELF @ arg1 16789 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16790 16791/* ------------------------------ */ 16792 .balign 64 16793.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 16794/* File: armv5te/ALT_STUB.S */ 16795/* 16796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16797 * any interesting requests and then jump to the real instruction 16798 * handler. Note that the call to dvmCheckInst is done as a tail call. 16799 */ 16800 adrl lr, dvmAsmInstructionStart + (227 * 64) 16801 mov r0, rPC @ arg0 16802 mov r1, rSELF @ arg1 16803 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16804 16805/* ------------------------------ */ 16806 .balign 64 16807.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 16808/* File: armv5te/ALT_STUB.S */ 16809/* 16810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16811 * any interesting requests and then jump to the real instruction 16812 * handler. Note that the call to dvmCheckInst is done as a tail call. 16813 */ 16814 adrl lr, dvmAsmInstructionStart + (228 * 64) 16815 mov r0, rPC @ arg0 16816 mov r1, rSELF @ arg1 16817 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16818 16819/* ------------------------------ */ 16820 .balign 64 16821.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 16822/* File: armv5te/ALT_STUB.S */ 16823/* 16824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16825 * any interesting requests and then jump to the real instruction 16826 * handler. Note that the call to dvmCheckInst is done as a tail call. 16827 */ 16828 adrl lr, dvmAsmInstructionStart + (229 * 64) 16829 mov r0, rPC @ arg0 16830 mov r1, rSELF @ arg1 16831 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16832 16833/* ------------------------------ */ 16834 .balign 64 16835.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 16836/* File: armv5te/ALT_STUB.S */ 16837/* 16838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16839 * any interesting requests and then jump to the real instruction 16840 * handler. Note that the call to dvmCheckInst is done as a tail call. 16841 */ 16842 adrl lr, dvmAsmInstructionStart + (230 * 64) 16843 mov r0, rPC @ arg0 16844 mov r1, rSELF @ arg1 16845 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16846 16847/* ------------------------------ */ 16848 .balign 64 16849.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 16850/* File: armv5te/ALT_STUB.S */ 16851/* 16852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16853 * any interesting requests and then jump to the real instruction 16854 * handler. Note that the call to dvmCheckInst is done as a tail call. 16855 */ 16856 adrl lr, dvmAsmInstructionStart + (231 * 64) 16857 mov r0, rPC @ arg0 16858 mov r1, rSELF @ arg1 16859 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16860 16861/* ------------------------------ */ 16862 .balign 64 16863.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 16864/* File: armv5te/ALT_STUB.S */ 16865/* 16866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16867 * any interesting requests and then jump to the real instruction 16868 * handler. Note that the call to dvmCheckInst is done as a tail call. 16869 */ 16870 adrl lr, dvmAsmInstructionStart + (232 * 64) 16871 mov r0, rPC @ arg0 16872 mov r1, rSELF @ arg1 16873 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16874 16875/* ------------------------------ */ 16876 .balign 64 16877.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 16878/* File: armv5te/ALT_STUB.S */ 16879/* 16880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16881 * any interesting requests and then jump to the real instruction 16882 * handler. Note that the call to dvmCheckInst is done as a tail call. 16883 */ 16884 adrl lr, dvmAsmInstructionStart + (233 * 64) 16885 mov r0, rPC @ arg0 16886 mov r1, rSELF @ arg1 16887 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16888 16889/* ------------------------------ */ 16890 .balign 64 16891.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 16892/* File: armv5te/ALT_STUB.S */ 16893/* 16894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16895 * any interesting requests and then jump to the real instruction 16896 * handler. Note that the call to dvmCheckInst is done as a tail call. 16897 */ 16898 adrl lr, dvmAsmInstructionStart + (234 * 64) 16899 mov r0, rPC @ arg0 16900 mov r1, rSELF @ arg1 16901 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16902 16903/* ------------------------------ */ 16904 .balign 64 16905.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 16906/* File: armv5te/ALT_STUB.S */ 16907/* 16908 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16909 * any interesting requests and then jump to the real instruction 16910 * handler. Note that the call to dvmCheckInst is done as a tail call. 16911 */ 16912 adrl lr, dvmAsmInstructionStart + (235 * 64) 16913 mov r0, rPC @ arg0 16914 mov r1, rSELF @ arg1 16915 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16916 16917/* ------------------------------ */ 16918 .balign 64 16919.L_ALT_OP_BREAKPOINT: /* 0xec */ 16920/* File: armv5te/ALT_STUB.S */ 16921/* 16922 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16923 * any interesting requests and then jump to the real instruction 16924 * handler. Note that the call to dvmCheckInst is done as a tail call. 16925 */ 16926 adrl lr, dvmAsmInstructionStart + (236 * 64) 16927 mov r0, rPC @ arg0 16928 mov r1, rSELF @ arg1 16929 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16930 16931/* ------------------------------ */ 16932 .balign 64 16933.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 16934/* File: armv5te/ALT_STUB.S */ 16935/* 16936 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16937 * any interesting requests and then jump to the real instruction 16938 * handler. Note that the call to dvmCheckInst is done as a tail call. 16939 */ 16940 adrl lr, dvmAsmInstructionStart + (237 * 64) 16941 mov r0, rPC @ arg0 16942 mov r1, rSELF @ arg1 16943 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16944 16945/* ------------------------------ */ 16946 .balign 64 16947.L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 16948/* File: armv5te/ALT_STUB.S */ 16949/* 16950 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16951 * any interesting requests and then jump to the real instruction 16952 * handler. Note that the call to dvmCheckInst is done as a tail call. 16953 */ 16954 adrl lr, dvmAsmInstructionStart + (238 * 64) 16955 mov r0, rPC @ arg0 16956 mov r1, rSELF @ arg1 16957 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16958 16959/* ------------------------------ */ 16960 .balign 64 16961.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 16962/* File: armv5te/ALT_STUB.S */ 16963/* 16964 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16965 * any interesting requests and then jump to the real instruction 16966 * handler. Note that the call to dvmCheckInst is done as a tail call. 16967 */ 16968 adrl lr, dvmAsmInstructionStart + (239 * 64) 16969 mov r0, rPC @ arg0 16970 mov r1, rSELF @ arg1 16971 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16972 16973/* ------------------------------ */ 16974 .balign 64 16975.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */ 16976/* File: armv5te/ALT_STUB.S */ 16977/* 16978 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16979 * any interesting requests and then jump to the real instruction 16980 * handler. Note that the call to dvmCheckInst is done as a tail call. 16981 */ 16982 adrl lr, dvmAsmInstructionStart + (240 * 64) 16983 mov r0, rPC @ arg0 16984 mov r1, rSELF @ arg1 16985 b dvmCheckInst @ (dPC,self) tail call to instruction checker 16986 16987/* ------------------------------ */ 16988 .balign 64 16989.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 16990/* File: armv5te/ALT_STUB.S */ 16991/* 16992 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 16993 * any interesting requests and then jump to the real instruction 16994 * handler. Note that the call to dvmCheckInst is done as a tail call. 16995 */ 16996 adrl lr, dvmAsmInstructionStart + (241 * 64) 16997 mov r0, rPC @ arg0 16998 mov r1, rSELF @ arg1 16999 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17000 17001/* ------------------------------ */ 17002 .balign 64 17003.L_ALT_OP_IGET_QUICK: /* 0xf2 */ 17004/* File: armv5te/ALT_STUB.S */ 17005/* 17006 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17007 * any interesting requests and then jump to the real instruction 17008 * handler. Note that the call to dvmCheckInst is done as a tail call. 17009 */ 17010 adrl lr, dvmAsmInstructionStart + (242 * 64) 17011 mov r0, rPC @ arg0 17012 mov r1, rSELF @ arg1 17013 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17014 17015/* ------------------------------ */ 17016 .balign 64 17017.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 17018/* File: armv5te/ALT_STUB.S */ 17019/* 17020 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17021 * any interesting requests and then jump to the real instruction 17022 * handler. Note that the call to dvmCheckInst is done as a tail call. 17023 */ 17024 adrl lr, dvmAsmInstructionStart + (243 * 64) 17025 mov r0, rPC @ arg0 17026 mov r1, rSELF @ arg1 17027 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17028 17029/* ------------------------------ */ 17030 .balign 64 17031.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 17032/* File: armv5te/ALT_STUB.S */ 17033/* 17034 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17035 * any interesting requests and then jump to the real instruction 17036 * handler. Note that the call to dvmCheckInst is done as a tail call. 17037 */ 17038 adrl lr, dvmAsmInstructionStart + (244 * 64) 17039 mov r0, rPC @ arg0 17040 mov r1, rSELF @ arg1 17041 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17042 17043/* ------------------------------ */ 17044 .balign 64 17045.L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 17046/* File: armv5te/ALT_STUB.S */ 17047/* 17048 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17049 * any interesting requests and then jump to the real instruction 17050 * handler. Note that the call to dvmCheckInst is done as a tail call. 17051 */ 17052 adrl lr, dvmAsmInstructionStart + (245 * 64) 17053 mov r0, rPC @ arg0 17054 mov r1, rSELF @ arg1 17055 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17056 17057/* ------------------------------ */ 17058 .balign 64 17059.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 17060/* File: armv5te/ALT_STUB.S */ 17061/* 17062 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17063 * any interesting requests and then jump to the real instruction 17064 * handler. Note that the call to dvmCheckInst is done as a tail call. 17065 */ 17066 adrl lr, dvmAsmInstructionStart + (246 * 64) 17067 mov r0, rPC @ arg0 17068 mov r1, rSELF @ arg1 17069 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17070 17071/* ------------------------------ */ 17072 .balign 64 17073.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 17074/* File: armv5te/ALT_STUB.S */ 17075/* 17076 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17077 * any interesting requests and then jump to the real instruction 17078 * handler. Note that the call to dvmCheckInst is done as a tail call. 17079 */ 17080 adrl lr, dvmAsmInstructionStart + (247 * 64) 17081 mov r0, rPC @ arg0 17082 mov r1, rSELF @ arg1 17083 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17084 17085/* ------------------------------ */ 17086 .balign 64 17087.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 17088/* File: armv5te/ALT_STUB.S */ 17089/* 17090 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17091 * any interesting requests and then jump to the real instruction 17092 * handler. Note that the call to dvmCheckInst is done as a tail call. 17093 */ 17094 adrl lr, dvmAsmInstructionStart + (248 * 64) 17095 mov r0, rPC @ arg0 17096 mov r1, rSELF @ arg1 17097 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17098 17099/* ------------------------------ */ 17100 .balign 64 17101.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 17102/* File: armv5te/ALT_STUB.S */ 17103/* 17104 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17105 * any interesting requests and then jump to the real instruction 17106 * handler. Note that the call to dvmCheckInst is done as a tail call. 17107 */ 17108 adrl lr, dvmAsmInstructionStart + (249 * 64) 17109 mov r0, rPC @ arg0 17110 mov r1, rSELF @ arg1 17111 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17112 17113/* ------------------------------ */ 17114 .balign 64 17115.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 17116/* File: armv5te/ALT_STUB.S */ 17117/* 17118 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17119 * any interesting requests and then jump to the real instruction 17120 * handler. Note that the call to dvmCheckInst is done as a tail call. 17121 */ 17122 adrl lr, dvmAsmInstructionStart + (250 * 64) 17123 mov r0, rPC @ arg0 17124 mov r1, rSELF @ arg1 17125 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17126 17127/* ------------------------------ */ 17128 .balign 64 17129.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 17130/* File: armv5te/ALT_STUB.S */ 17131/* 17132 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17133 * any interesting requests and then jump to the real instruction 17134 * handler. Note that the call to dvmCheckInst is done as a tail call. 17135 */ 17136 adrl lr, dvmAsmInstructionStart + (251 * 64) 17137 mov r0, rPC @ arg0 17138 mov r1, rSELF @ arg1 17139 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17140 17141/* ------------------------------ */ 17142 .balign 64 17143.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 17144/* File: armv5te/ALT_STUB.S */ 17145/* 17146 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17147 * any interesting requests and then jump to the real instruction 17148 * handler. Note that the call to dvmCheckInst is done as a tail call. 17149 */ 17150 adrl lr, dvmAsmInstructionStart + (252 * 64) 17151 mov r0, rPC @ arg0 17152 mov r1, rSELF @ arg1 17153 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17154 17155/* ------------------------------ */ 17156 .balign 64 17157.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 17158/* File: armv5te/ALT_STUB.S */ 17159/* 17160 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17161 * any interesting requests and then jump to the real instruction 17162 * handler. Note that the call to dvmCheckInst is done as a tail call. 17163 */ 17164 adrl lr, dvmAsmInstructionStart + (253 * 64) 17165 mov r0, rPC @ arg0 17166 mov r1, rSELF @ arg1 17167 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17168 17169/* ------------------------------ */ 17170 .balign 64 17171.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 17172/* File: armv5te/ALT_STUB.S */ 17173/* 17174 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17175 * any interesting requests and then jump to the real instruction 17176 * handler. Note that the call to dvmCheckInst is done as a tail call. 17177 */ 17178 adrl lr, dvmAsmInstructionStart + (254 * 64) 17179 mov r0, rPC @ arg0 17180 mov r1, rSELF @ arg1 17181 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17182 17183/* ------------------------------ */ 17184 .balign 64 17185.L_ALT_OP_DISPATCH_FF: /* 0xff */ 17186/* File: armv5te/ALT_OP_DISPATCH_FF.S */ 17187 mov ip, rINST, lsr #8 @ ip<- extended opcode 17188 add ip, ip, #256 @ add offset for extended opcodes 17189 GOTO_OPCODE(ip) @ go to proper extended handler 17190 17191 17192/* ------------------------------ */ 17193 .balign 64 17194.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */ 17195/* File: armv5te/ALT_STUB.S */ 17196/* 17197 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17198 * any interesting requests and then jump to the real instruction 17199 * handler. Note that the call to dvmCheckInst is done as a tail call. 17200 */ 17201 adrl lr, dvmAsmInstructionStart + (256 * 64) 17202 mov r0, rPC @ arg0 17203 mov r1, rSELF @ arg1 17204 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17205 17206/* ------------------------------ */ 17207 .balign 64 17208.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */ 17209/* File: armv5te/ALT_STUB.S */ 17210/* 17211 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17212 * any interesting requests and then jump to the real instruction 17213 * handler. Note that the call to dvmCheckInst is done as a tail call. 17214 */ 17215 adrl lr, dvmAsmInstructionStart + (257 * 64) 17216 mov r0, rPC @ arg0 17217 mov r1, rSELF @ arg1 17218 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17219 17220/* ------------------------------ */ 17221 .balign 64 17222.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 17223/* File: armv5te/ALT_STUB.S */ 17224/* 17225 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17226 * any interesting requests and then jump to the real instruction 17227 * handler. Note that the call to dvmCheckInst is done as a tail call. 17228 */ 17229 adrl lr, dvmAsmInstructionStart + (258 * 64) 17230 mov r0, rPC @ arg0 17231 mov r1, rSELF @ arg1 17232 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17233 17234/* ------------------------------ */ 17235 .balign 64 17236.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 17237/* File: armv5te/ALT_STUB.S */ 17238/* 17239 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17240 * any interesting requests and then jump to the real instruction 17241 * handler. Note that the call to dvmCheckInst is done as a tail call. 17242 */ 17243 adrl lr, dvmAsmInstructionStart + (259 * 64) 17244 mov r0, rPC @ arg0 17245 mov r1, rSELF @ arg1 17246 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17247 17248/* ------------------------------ */ 17249 .balign 64 17250.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 17251/* File: armv5te/ALT_STUB.S */ 17252/* 17253 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17254 * any interesting requests and then jump to the real instruction 17255 * handler. Note that the call to dvmCheckInst is done as a tail call. 17256 */ 17257 adrl lr, dvmAsmInstructionStart + (260 * 64) 17258 mov r0, rPC @ arg0 17259 mov r1, rSELF @ arg1 17260 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17261 17262/* ------------------------------ */ 17263 .balign 64 17264.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 17265/* File: armv5te/ALT_STUB.S */ 17266/* 17267 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17268 * any interesting requests and then jump to the real instruction 17269 * handler. Note that the call to dvmCheckInst is done as a tail call. 17270 */ 17271 adrl lr, dvmAsmInstructionStart + (261 * 64) 17272 mov r0, rPC @ arg0 17273 mov r1, rSELF @ arg1 17274 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17275 17276/* ------------------------------ */ 17277 .balign 64 17278.L_ALT_OP_IGET_JUMBO: /* 0x106 */ 17279/* File: armv5te/ALT_STUB.S */ 17280/* 17281 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17282 * any interesting requests and then jump to the real instruction 17283 * handler. Note that the call to dvmCheckInst is done as a tail call. 17284 */ 17285 adrl lr, dvmAsmInstructionStart + (262 * 64) 17286 mov r0, rPC @ arg0 17287 mov r1, rSELF @ arg1 17288 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17289 17290/* ------------------------------ */ 17291 .balign 64 17292.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */ 17293/* File: armv5te/ALT_STUB.S */ 17294/* 17295 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17296 * any interesting requests and then jump to the real instruction 17297 * handler. Note that the call to dvmCheckInst is done as a tail call. 17298 */ 17299 adrl lr, dvmAsmInstructionStart + (263 * 64) 17300 mov r0, rPC @ arg0 17301 mov r1, rSELF @ arg1 17302 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17303 17304/* ------------------------------ */ 17305 .balign 64 17306.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 17307/* File: armv5te/ALT_STUB.S */ 17308/* 17309 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17310 * any interesting requests and then jump to the real instruction 17311 * handler. Note that the call to dvmCheckInst is done as a tail call. 17312 */ 17313 adrl lr, dvmAsmInstructionStart + (264 * 64) 17314 mov r0, rPC @ arg0 17315 mov r1, rSELF @ arg1 17316 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17317 17318/* ------------------------------ */ 17319 .balign 64 17320.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 17321/* File: armv5te/ALT_STUB.S */ 17322/* 17323 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17324 * any interesting requests and then jump to the real instruction 17325 * handler. Note that the call to dvmCheckInst is done as a tail call. 17326 */ 17327 adrl lr, dvmAsmInstructionStart + (265 * 64) 17328 mov r0, rPC @ arg0 17329 mov r1, rSELF @ arg1 17330 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17331 17332/* ------------------------------ */ 17333 .balign 64 17334.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */ 17335/* File: armv5te/ALT_STUB.S */ 17336/* 17337 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17338 * any interesting requests and then jump to the real instruction 17339 * handler. Note that the call to dvmCheckInst is done as a tail call. 17340 */ 17341 adrl lr, dvmAsmInstructionStart + (266 * 64) 17342 mov r0, rPC @ arg0 17343 mov r1, rSELF @ arg1 17344 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17345 17346/* ------------------------------ */ 17347 .balign 64 17348.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */ 17349/* File: armv5te/ALT_STUB.S */ 17350/* 17351 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17352 * any interesting requests and then jump to the real instruction 17353 * handler. Note that the call to dvmCheckInst is done as a tail call. 17354 */ 17355 adrl lr, dvmAsmInstructionStart + (267 * 64) 17356 mov r0, rPC @ arg0 17357 mov r1, rSELF @ arg1 17358 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17359 17360/* ------------------------------ */ 17361 .balign 64 17362.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */ 17363/* File: armv5te/ALT_STUB.S */ 17364/* 17365 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17366 * any interesting requests and then jump to the real instruction 17367 * handler. Note that the call to dvmCheckInst is done as a tail call. 17368 */ 17369 adrl lr, dvmAsmInstructionStart + (268 * 64) 17370 mov r0, rPC @ arg0 17371 mov r1, rSELF @ arg1 17372 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17373 17374/* ------------------------------ */ 17375 .balign 64 17376.L_ALT_OP_IPUT_JUMBO: /* 0x10d */ 17377/* File: armv5te/ALT_STUB.S */ 17378/* 17379 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17380 * any interesting requests and then jump to the real instruction 17381 * handler. Note that the call to dvmCheckInst is done as a tail call. 17382 */ 17383 adrl lr, dvmAsmInstructionStart + (269 * 64) 17384 mov r0, rPC @ arg0 17385 mov r1, rSELF @ arg1 17386 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17387 17388/* ------------------------------ */ 17389 .balign 64 17390.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 17391/* File: armv5te/ALT_STUB.S */ 17392/* 17393 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17394 * any interesting requests and then jump to the real instruction 17395 * handler. Note that the call to dvmCheckInst is done as a tail call. 17396 */ 17397 adrl lr, dvmAsmInstructionStart + (270 * 64) 17398 mov r0, rPC @ arg0 17399 mov r1, rSELF @ arg1 17400 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17401 17402/* ------------------------------ */ 17403 .balign 64 17404.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 17405/* File: armv5te/ALT_STUB.S */ 17406/* 17407 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17408 * any interesting requests and then jump to the real instruction 17409 * handler. Note that the call to dvmCheckInst is done as a tail call. 17410 */ 17411 adrl lr, dvmAsmInstructionStart + (271 * 64) 17412 mov r0, rPC @ arg0 17413 mov r1, rSELF @ arg1 17414 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17415 17416/* ------------------------------ */ 17417 .balign 64 17418.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 17419/* File: armv5te/ALT_STUB.S */ 17420/* 17421 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17422 * any interesting requests and then jump to the real instruction 17423 * handler. Note that the call to dvmCheckInst is done as a tail call. 17424 */ 17425 adrl lr, dvmAsmInstructionStart + (272 * 64) 17426 mov r0, rPC @ arg0 17427 mov r1, rSELF @ arg1 17428 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17429 17430/* ------------------------------ */ 17431 .balign 64 17432.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 17433/* File: armv5te/ALT_STUB.S */ 17434/* 17435 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17436 * any interesting requests and then jump to the real instruction 17437 * handler. Note that the call to dvmCheckInst is done as a tail call. 17438 */ 17439 adrl lr, dvmAsmInstructionStart + (273 * 64) 17440 mov r0, rPC @ arg0 17441 mov r1, rSELF @ arg1 17442 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17443 17444/* ------------------------------ */ 17445 .balign 64 17446.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 17447/* File: armv5te/ALT_STUB.S */ 17448/* 17449 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17450 * any interesting requests and then jump to the real instruction 17451 * handler. Note that the call to dvmCheckInst is done as a tail call. 17452 */ 17453 adrl lr, dvmAsmInstructionStart + (274 * 64) 17454 mov r0, rPC @ arg0 17455 mov r1, rSELF @ arg1 17456 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17457 17458/* ------------------------------ */ 17459 .balign 64 17460.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 17461/* File: armv5te/ALT_STUB.S */ 17462/* 17463 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17464 * any interesting requests and then jump to the real instruction 17465 * handler. Note that the call to dvmCheckInst is done as a tail call. 17466 */ 17467 adrl lr, dvmAsmInstructionStart + (275 * 64) 17468 mov r0, rPC @ arg0 17469 mov r1, rSELF @ arg1 17470 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17471 17472/* ------------------------------ */ 17473 .balign 64 17474.L_ALT_OP_SGET_JUMBO: /* 0x114 */ 17475/* File: armv5te/ALT_STUB.S */ 17476/* 17477 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17478 * any interesting requests and then jump to the real instruction 17479 * handler. Note that the call to dvmCheckInst is done as a tail call. 17480 */ 17481 adrl lr, dvmAsmInstructionStart + (276 * 64) 17482 mov r0, rPC @ arg0 17483 mov r1, rSELF @ arg1 17484 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17485 17486/* ------------------------------ */ 17487 .balign 64 17488.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */ 17489/* File: armv5te/ALT_STUB.S */ 17490/* 17491 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17492 * any interesting requests and then jump to the real instruction 17493 * handler. Note that the call to dvmCheckInst is done as a tail call. 17494 */ 17495 adrl lr, dvmAsmInstructionStart + (277 * 64) 17496 mov r0, rPC @ arg0 17497 mov r1, rSELF @ arg1 17498 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17499 17500/* ------------------------------ */ 17501 .balign 64 17502.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 17503/* File: armv5te/ALT_STUB.S */ 17504/* 17505 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17506 * any interesting requests and then jump to the real instruction 17507 * handler. Note that the call to dvmCheckInst is done as a tail call. 17508 */ 17509 adrl lr, dvmAsmInstructionStart + (278 * 64) 17510 mov r0, rPC @ arg0 17511 mov r1, rSELF @ arg1 17512 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17513 17514/* ------------------------------ */ 17515 .balign 64 17516.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 17517/* File: armv5te/ALT_STUB.S */ 17518/* 17519 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17520 * any interesting requests and then jump to the real instruction 17521 * handler. Note that the call to dvmCheckInst is done as a tail call. 17522 */ 17523 adrl lr, dvmAsmInstructionStart + (279 * 64) 17524 mov r0, rPC @ arg0 17525 mov r1, rSELF @ arg1 17526 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17527 17528/* ------------------------------ */ 17529 .balign 64 17530.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */ 17531/* File: armv5te/ALT_STUB.S */ 17532/* 17533 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17534 * any interesting requests and then jump to the real instruction 17535 * handler. Note that the call to dvmCheckInst is done as a tail call. 17536 */ 17537 adrl lr, dvmAsmInstructionStart + (280 * 64) 17538 mov r0, rPC @ arg0 17539 mov r1, rSELF @ arg1 17540 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17541 17542/* ------------------------------ */ 17543 .balign 64 17544.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */ 17545/* File: armv5te/ALT_STUB.S */ 17546/* 17547 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17548 * any interesting requests and then jump to the real instruction 17549 * handler. Note that the call to dvmCheckInst is done as a tail call. 17550 */ 17551 adrl lr, dvmAsmInstructionStart + (281 * 64) 17552 mov r0, rPC @ arg0 17553 mov r1, rSELF @ arg1 17554 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17555 17556/* ------------------------------ */ 17557 .balign 64 17558.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */ 17559/* File: armv5te/ALT_STUB.S */ 17560/* 17561 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17562 * any interesting requests and then jump to the real instruction 17563 * handler. Note that the call to dvmCheckInst is done as a tail call. 17564 */ 17565 adrl lr, dvmAsmInstructionStart + (282 * 64) 17566 mov r0, rPC @ arg0 17567 mov r1, rSELF @ arg1 17568 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17569 17570/* ------------------------------ */ 17571 .balign 64 17572.L_ALT_OP_SPUT_JUMBO: /* 0x11b */ 17573/* File: armv5te/ALT_STUB.S */ 17574/* 17575 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17576 * any interesting requests and then jump to the real instruction 17577 * handler. Note that the call to dvmCheckInst is done as a tail call. 17578 */ 17579 adrl lr, dvmAsmInstructionStart + (283 * 64) 17580 mov r0, rPC @ arg0 17581 mov r1, rSELF @ arg1 17582 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17583 17584/* ------------------------------ */ 17585 .balign 64 17586.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 17587/* File: armv5te/ALT_STUB.S */ 17588/* 17589 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17590 * any interesting requests and then jump to the real instruction 17591 * handler. Note that the call to dvmCheckInst is done as a tail call. 17592 */ 17593 adrl lr, dvmAsmInstructionStart + (284 * 64) 17594 mov r0, rPC @ arg0 17595 mov r1, rSELF @ arg1 17596 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17597 17598/* ------------------------------ */ 17599 .balign 64 17600.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 17601/* File: armv5te/ALT_STUB.S */ 17602/* 17603 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17604 * any interesting requests and then jump to the real instruction 17605 * handler. Note that the call to dvmCheckInst is done as a tail call. 17606 */ 17607 adrl lr, dvmAsmInstructionStart + (285 * 64) 17608 mov r0, rPC @ arg0 17609 mov r1, rSELF @ arg1 17610 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17611 17612/* ------------------------------ */ 17613 .balign 64 17614.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 17615/* File: armv5te/ALT_STUB.S */ 17616/* 17617 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17618 * any interesting requests and then jump to the real instruction 17619 * handler. Note that the call to dvmCheckInst is done as a tail call. 17620 */ 17621 adrl lr, dvmAsmInstructionStart + (286 * 64) 17622 mov r0, rPC @ arg0 17623 mov r1, rSELF @ arg1 17624 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17625 17626/* ------------------------------ */ 17627 .balign 64 17628.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 17629/* File: armv5te/ALT_STUB.S */ 17630/* 17631 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17632 * any interesting requests and then jump to the real instruction 17633 * handler. Note that the call to dvmCheckInst is done as a tail call. 17634 */ 17635 adrl lr, dvmAsmInstructionStart + (287 * 64) 17636 mov r0, rPC @ arg0 17637 mov r1, rSELF @ arg1 17638 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17639 17640/* ------------------------------ */ 17641 .balign 64 17642.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 17643/* File: armv5te/ALT_STUB.S */ 17644/* 17645 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17646 * any interesting requests and then jump to the real instruction 17647 * handler. Note that the call to dvmCheckInst is done as a tail call. 17648 */ 17649 adrl lr, dvmAsmInstructionStart + (288 * 64) 17650 mov r0, rPC @ arg0 17651 mov r1, rSELF @ arg1 17652 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17653 17654/* ------------------------------ */ 17655 .balign 64 17656.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 17657/* File: armv5te/ALT_STUB.S */ 17658/* 17659 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17660 * any interesting requests and then jump to the real instruction 17661 * handler. Note that the call to dvmCheckInst is done as a tail call. 17662 */ 17663 adrl lr, dvmAsmInstructionStart + (289 * 64) 17664 mov r0, rPC @ arg0 17665 mov r1, rSELF @ arg1 17666 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17667 17668/* ------------------------------ */ 17669 .balign 64 17670.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 17671/* File: armv5te/ALT_STUB.S */ 17672/* 17673 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17674 * any interesting requests and then jump to the real instruction 17675 * handler. Note that the call to dvmCheckInst is done as a tail call. 17676 */ 17677 adrl lr, dvmAsmInstructionStart + (290 * 64) 17678 mov r0, rPC @ arg0 17679 mov r1, rSELF @ arg1 17680 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17681 17682/* ------------------------------ */ 17683 .balign 64 17684.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 17685/* File: armv5te/ALT_STUB.S */ 17686/* 17687 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17688 * any interesting requests and then jump to the real instruction 17689 * handler. Note that the call to dvmCheckInst is done as a tail call. 17690 */ 17691 adrl lr, dvmAsmInstructionStart + (291 * 64) 17692 mov r0, rPC @ arg0 17693 mov r1, rSELF @ arg1 17694 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17695 17696/* ------------------------------ */ 17697 .balign 64 17698.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 17699/* File: armv5te/ALT_STUB.S */ 17700/* 17701 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17702 * any interesting requests and then jump to the real instruction 17703 * handler. Note that the call to dvmCheckInst is done as a tail call. 17704 */ 17705 adrl lr, dvmAsmInstructionStart + (292 * 64) 17706 mov r0, rPC @ arg0 17707 mov r1, rSELF @ arg1 17708 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17709 17710/* ------------------------------ */ 17711 .balign 64 17712.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 17713/* File: armv5te/ALT_STUB.S */ 17714/* 17715 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17716 * any interesting requests and then jump to the real instruction 17717 * handler. Note that the call to dvmCheckInst is done as a tail call. 17718 */ 17719 adrl lr, dvmAsmInstructionStart + (293 * 64) 17720 mov r0, rPC @ arg0 17721 mov r1, rSELF @ arg1 17722 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17723 17724/* ------------------------------ */ 17725 .balign 64 17726.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 17727/* File: armv5te/ALT_STUB.S */ 17728/* 17729 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17730 * any interesting requests and then jump to the real instruction 17731 * handler. Note that the call to dvmCheckInst is done as a tail call. 17732 */ 17733 adrl lr, dvmAsmInstructionStart + (294 * 64) 17734 mov r0, rPC @ arg0 17735 mov r1, rSELF @ arg1 17736 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17737 17738/* ------------------------------ */ 17739 .balign 64 17740.L_ALT_OP_UNUSED_27FF: /* 0x127 */ 17741/* File: armv5te/ALT_STUB.S */ 17742/* 17743 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17744 * any interesting requests and then jump to the real instruction 17745 * handler. Note that the call to dvmCheckInst is done as a tail call. 17746 */ 17747 adrl lr, dvmAsmInstructionStart + (295 * 64) 17748 mov r0, rPC @ arg0 17749 mov r1, rSELF @ arg1 17750 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17751 17752/* ------------------------------ */ 17753 .balign 64 17754.L_ALT_OP_UNUSED_28FF: /* 0x128 */ 17755/* File: armv5te/ALT_STUB.S */ 17756/* 17757 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17758 * any interesting requests and then jump to the real instruction 17759 * handler. Note that the call to dvmCheckInst is done as a tail call. 17760 */ 17761 adrl lr, dvmAsmInstructionStart + (296 * 64) 17762 mov r0, rPC @ arg0 17763 mov r1, rSELF @ arg1 17764 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17765 17766/* ------------------------------ */ 17767 .balign 64 17768.L_ALT_OP_UNUSED_29FF: /* 0x129 */ 17769/* File: armv5te/ALT_STUB.S */ 17770/* 17771 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17772 * any interesting requests and then jump to the real instruction 17773 * handler. Note that the call to dvmCheckInst is done as a tail call. 17774 */ 17775 adrl lr, dvmAsmInstructionStart + (297 * 64) 17776 mov r0, rPC @ arg0 17777 mov r1, rSELF @ arg1 17778 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17779 17780/* ------------------------------ */ 17781 .balign 64 17782.L_ALT_OP_UNUSED_2AFF: /* 0x12a */ 17783/* File: armv5te/ALT_STUB.S */ 17784/* 17785 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17786 * any interesting requests and then jump to the real instruction 17787 * handler. Note that the call to dvmCheckInst is done as a tail call. 17788 */ 17789 adrl lr, dvmAsmInstructionStart + (298 * 64) 17790 mov r0, rPC @ arg0 17791 mov r1, rSELF @ arg1 17792 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17793 17794/* ------------------------------ */ 17795 .balign 64 17796.L_ALT_OP_UNUSED_2BFF: /* 0x12b */ 17797/* File: armv5te/ALT_STUB.S */ 17798/* 17799 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17800 * any interesting requests and then jump to the real instruction 17801 * handler. Note that the call to dvmCheckInst is done as a tail call. 17802 */ 17803 adrl lr, dvmAsmInstructionStart + (299 * 64) 17804 mov r0, rPC @ arg0 17805 mov r1, rSELF @ arg1 17806 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17807 17808/* ------------------------------ */ 17809 .balign 64 17810.L_ALT_OP_UNUSED_2CFF: /* 0x12c */ 17811/* File: armv5te/ALT_STUB.S */ 17812/* 17813 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17814 * any interesting requests and then jump to the real instruction 17815 * handler. Note that the call to dvmCheckInst is done as a tail call. 17816 */ 17817 adrl lr, dvmAsmInstructionStart + (300 * 64) 17818 mov r0, rPC @ arg0 17819 mov r1, rSELF @ arg1 17820 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17821 17822/* ------------------------------ */ 17823 .balign 64 17824.L_ALT_OP_UNUSED_2DFF: /* 0x12d */ 17825/* File: armv5te/ALT_STUB.S */ 17826/* 17827 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17828 * any interesting requests and then jump to the real instruction 17829 * handler. Note that the call to dvmCheckInst is done as a tail call. 17830 */ 17831 adrl lr, dvmAsmInstructionStart + (301 * 64) 17832 mov r0, rPC @ arg0 17833 mov r1, rSELF @ arg1 17834 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17835 17836/* ------------------------------ */ 17837 .balign 64 17838.L_ALT_OP_UNUSED_2EFF: /* 0x12e */ 17839/* File: armv5te/ALT_STUB.S */ 17840/* 17841 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17842 * any interesting requests and then jump to the real instruction 17843 * handler. Note that the call to dvmCheckInst is done as a tail call. 17844 */ 17845 adrl lr, dvmAsmInstructionStart + (302 * 64) 17846 mov r0, rPC @ arg0 17847 mov r1, rSELF @ arg1 17848 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17849 17850/* ------------------------------ */ 17851 .balign 64 17852.L_ALT_OP_UNUSED_2FFF: /* 0x12f */ 17853/* File: armv5te/ALT_STUB.S */ 17854/* 17855 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17856 * any interesting requests and then jump to the real instruction 17857 * handler. Note that the call to dvmCheckInst is done as a tail call. 17858 */ 17859 adrl lr, dvmAsmInstructionStart + (303 * 64) 17860 mov r0, rPC @ arg0 17861 mov r1, rSELF @ arg1 17862 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17863 17864/* ------------------------------ */ 17865 .balign 64 17866.L_ALT_OP_UNUSED_30FF: /* 0x130 */ 17867/* File: armv5te/ALT_STUB.S */ 17868/* 17869 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17870 * any interesting requests and then jump to the real instruction 17871 * handler. Note that the call to dvmCheckInst is done as a tail call. 17872 */ 17873 adrl lr, dvmAsmInstructionStart + (304 * 64) 17874 mov r0, rPC @ arg0 17875 mov r1, rSELF @ arg1 17876 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17877 17878/* ------------------------------ */ 17879 .balign 64 17880.L_ALT_OP_UNUSED_31FF: /* 0x131 */ 17881/* File: armv5te/ALT_STUB.S */ 17882/* 17883 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17884 * any interesting requests and then jump to the real instruction 17885 * handler. Note that the call to dvmCheckInst is done as a tail call. 17886 */ 17887 adrl lr, dvmAsmInstructionStart + (305 * 64) 17888 mov r0, rPC @ arg0 17889 mov r1, rSELF @ arg1 17890 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17891 17892/* ------------------------------ */ 17893 .balign 64 17894.L_ALT_OP_UNUSED_32FF: /* 0x132 */ 17895/* File: armv5te/ALT_STUB.S */ 17896/* 17897 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17898 * any interesting requests and then jump to the real instruction 17899 * handler. Note that the call to dvmCheckInst is done as a tail call. 17900 */ 17901 adrl lr, dvmAsmInstructionStart + (306 * 64) 17902 mov r0, rPC @ arg0 17903 mov r1, rSELF @ arg1 17904 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17905 17906/* ------------------------------ */ 17907 .balign 64 17908.L_ALT_OP_UNUSED_33FF: /* 0x133 */ 17909/* File: armv5te/ALT_STUB.S */ 17910/* 17911 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17912 * any interesting requests and then jump to the real instruction 17913 * handler. Note that the call to dvmCheckInst is done as a tail call. 17914 */ 17915 adrl lr, dvmAsmInstructionStart + (307 * 64) 17916 mov r0, rPC @ arg0 17917 mov r1, rSELF @ arg1 17918 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17919 17920/* ------------------------------ */ 17921 .balign 64 17922.L_ALT_OP_UNUSED_34FF: /* 0x134 */ 17923/* File: armv5te/ALT_STUB.S */ 17924/* 17925 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17926 * any interesting requests and then jump to the real instruction 17927 * handler. Note that the call to dvmCheckInst is done as a tail call. 17928 */ 17929 adrl lr, dvmAsmInstructionStart + (308 * 64) 17930 mov r0, rPC @ arg0 17931 mov r1, rSELF @ arg1 17932 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17933 17934/* ------------------------------ */ 17935 .balign 64 17936.L_ALT_OP_UNUSED_35FF: /* 0x135 */ 17937/* File: armv5te/ALT_STUB.S */ 17938/* 17939 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17940 * any interesting requests and then jump to the real instruction 17941 * handler. Note that the call to dvmCheckInst is done as a tail call. 17942 */ 17943 adrl lr, dvmAsmInstructionStart + (309 * 64) 17944 mov r0, rPC @ arg0 17945 mov r1, rSELF @ arg1 17946 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17947 17948/* ------------------------------ */ 17949 .balign 64 17950.L_ALT_OP_UNUSED_36FF: /* 0x136 */ 17951/* File: armv5te/ALT_STUB.S */ 17952/* 17953 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17954 * any interesting requests and then jump to the real instruction 17955 * handler. Note that the call to dvmCheckInst is done as a tail call. 17956 */ 17957 adrl lr, dvmAsmInstructionStart + (310 * 64) 17958 mov r0, rPC @ arg0 17959 mov r1, rSELF @ arg1 17960 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17961 17962/* ------------------------------ */ 17963 .balign 64 17964.L_ALT_OP_UNUSED_37FF: /* 0x137 */ 17965/* File: armv5te/ALT_STUB.S */ 17966/* 17967 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17968 * any interesting requests and then jump to the real instruction 17969 * handler. Note that the call to dvmCheckInst is done as a tail call. 17970 */ 17971 adrl lr, dvmAsmInstructionStart + (311 * 64) 17972 mov r0, rPC @ arg0 17973 mov r1, rSELF @ arg1 17974 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17975 17976/* ------------------------------ */ 17977 .balign 64 17978.L_ALT_OP_UNUSED_38FF: /* 0x138 */ 17979/* File: armv5te/ALT_STUB.S */ 17980/* 17981 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17982 * any interesting requests and then jump to the real instruction 17983 * handler. Note that the call to dvmCheckInst is done as a tail call. 17984 */ 17985 adrl lr, dvmAsmInstructionStart + (312 * 64) 17986 mov r0, rPC @ arg0 17987 mov r1, rSELF @ arg1 17988 b dvmCheckInst @ (dPC,self) tail call to instruction checker 17989 17990/* ------------------------------ */ 17991 .balign 64 17992.L_ALT_OP_UNUSED_39FF: /* 0x139 */ 17993/* File: armv5te/ALT_STUB.S */ 17994/* 17995 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 17996 * any interesting requests and then jump to the real instruction 17997 * handler. Note that the call to dvmCheckInst is done as a tail call. 17998 */ 17999 adrl lr, dvmAsmInstructionStart + (313 * 64) 18000 mov r0, rPC @ arg0 18001 mov r1, rSELF @ arg1 18002 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18003 18004/* ------------------------------ */ 18005 .balign 64 18006.L_ALT_OP_UNUSED_3AFF: /* 0x13a */ 18007/* File: armv5te/ALT_STUB.S */ 18008/* 18009 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18010 * any interesting requests and then jump to the real instruction 18011 * handler. Note that the call to dvmCheckInst is done as a tail call. 18012 */ 18013 adrl lr, dvmAsmInstructionStart + (314 * 64) 18014 mov r0, rPC @ arg0 18015 mov r1, rSELF @ arg1 18016 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18017 18018/* ------------------------------ */ 18019 .balign 64 18020.L_ALT_OP_UNUSED_3BFF: /* 0x13b */ 18021/* File: armv5te/ALT_STUB.S */ 18022/* 18023 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18024 * any interesting requests and then jump to the real instruction 18025 * handler. Note that the call to dvmCheckInst is done as a tail call. 18026 */ 18027 adrl lr, dvmAsmInstructionStart + (315 * 64) 18028 mov r0, rPC @ arg0 18029 mov r1, rSELF @ arg1 18030 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18031 18032/* ------------------------------ */ 18033 .balign 64 18034.L_ALT_OP_UNUSED_3CFF: /* 0x13c */ 18035/* File: armv5te/ALT_STUB.S */ 18036/* 18037 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18038 * any interesting requests and then jump to the real instruction 18039 * handler. Note that the call to dvmCheckInst is done as a tail call. 18040 */ 18041 adrl lr, dvmAsmInstructionStart + (316 * 64) 18042 mov r0, rPC @ arg0 18043 mov r1, rSELF @ arg1 18044 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18045 18046/* ------------------------------ */ 18047 .balign 64 18048.L_ALT_OP_UNUSED_3DFF: /* 0x13d */ 18049/* File: armv5te/ALT_STUB.S */ 18050/* 18051 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18052 * any interesting requests and then jump to the real instruction 18053 * handler. Note that the call to dvmCheckInst is done as a tail call. 18054 */ 18055 adrl lr, dvmAsmInstructionStart + (317 * 64) 18056 mov r0, rPC @ arg0 18057 mov r1, rSELF @ arg1 18058 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18059 18060/* ------------------------------ */ 18061 .balign 64 18062.L_ALT_OP_UNUSED_3EFF: /* 0x13e */ 18063/* File: armv5te/ALT_STUB.S */ 18064/* 18065 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18066 * any interesting requests and then jump to the real instruction 18067 * handler. Note that the call to dvmCheckInst is done as a tail call. 18068 */ 18069 adrl lr, dvmAsmInstructionStart + (318 * 64) 18070 mov r0, rPC @ arg0 18071 mov r1, rSELF @ arg1 18072 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18073 18074/* ------------------------------ */ 18075 .balign 64 18076.L_ALT_OP_UNUSED_3FFF: /* 0x13f */ 18077/* File: armv5te/ALT_STUB.S */ 18078/* 18079 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18080 * any interesting requests and then jump to the real instruction 18081 * handler. Note that the call to dvmCheckInst is done as a tail call. 18082 */ 18083 adrl lr, dvmAsmInstructionStart + (319 * 64) 18084 mov r0, rPC @ arg0 18085 mov r1, rSELF @ arg1 18086 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18087 18088/* ------------------------------ */ 18089 .balign 64 18090.L_ALT_OP_UNUSED_40FF: /* 0x140 */ 18091/* File: armv5te/ALT_STUB.S */ 18092/* 18093 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18094 * any interesting requests and then jump to the real instruction 18095 * handler. Note that the call to dvmCheckInst is done as a tail call. 18096 */ 18097 adrl lr, dvmAsmInstructionStart + (320 * 64) 18098 mov r0, rPC @ arg0 18099 mov r1, rSELF @ arg1 18100 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18101 18102/* ------------------------------ */ 18103 .balign 64 18104.L_ALT_OP_UNUSED_41FF: /* 0x141 */ 18105/* File: armv5te/ALT_STUB.S */ 18106/* 18107 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18108 * any interesting requests and then jump to the real instruction 18109 * handler. Note that the call to dvmCheckInst is done as a tail call. 18110 */ 18111 adrl lr, dvmAsmInstructionStart + (321 * 64) 18112 mov r0, rPC @ arg0 18113 mov r1, rSELF @ arg1 18114 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18115 18116/* ------------------------------ */ 18117 .balign 64 18118.L_ALT_OP_UNUSED_42FF: /* 0x142 */ 18119/* File: armv5te/ALT_STUB.S */ 18120/* 18121 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18122 * any interesting requests and then jump to the real instruction 18123 * handler. Note that the call to dvmCheckInst is done as a tail call. 18124 */ 18125 adrl lr, dvmAsmInstructionStart + (322 * 64) 18126 mov r0, rPC @ arg0 18127 mov r1, rSELF @ arg1 18128 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18129 18130/* ------------------------------ */ 18131 .balign 64 18132.L_ALT_OP_UNUSED_43FF: /* 0x143 */ 18133/* File: armv5te/ALT_STUB.S */ 18134/* 18135 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18136 * any interesting requests and then jump to the real instruction 18137 * handler. Note that the call to dvmCheckInst is done as a tail call. 18138 */ 18139 adrl lr, dvmAsmInstructionStart + (323 * 64) 18140 mov r0, rPC @ arg0 18141 mov r1, rSELF @ arg1 18142 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18143 18144/* ------------------------------ */ 18145 .balign 64 18146.L_ALT_OP_UNUSED_44FF: /* 0x144 */ 18147/* File: armv5te/ALT_STUB.S */ 18148/* 18149 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18150 * any interesting requests and then jump to the real instruction 18151 * handler. Note that the call to dvmCheckInst is done as a tail call. 18152 */ 18153 adrl lr, dvmAsmInstructionStart + (324 * 64) 18154 mov r0, rPC @ arg0 18155 mov r1, rSELF @ arg1 18156 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18157 18158/* ------------------------------ */ 18159 .balign 64 18160.L_ALT_OP_UNUSED_45FF: /* 0x145 */ 18161/* File: armv5te/ALT_STUB.S */ 18162/* 18163 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18164 * any interesting requests and then jump to the real instruction 18165 * handler. Note that the call to dvmCheckInst is done as a tail call. 18166 */ 18167 adrl lr, dvmAsmInstructionStart + (325 * 64) 18168 mov r0, rPC @ arg0 18169 mov r1, rSELF @ arg1 18170 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18171 18172/* ------------------------------ */ 18173 .balign 64 18174.L_ALT_OP_UNUSED_46FF: /* 0x146 */ 18175/* File: armv5te/ALT_STUB.S */ 18176/* 18177 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18178 * any interesting requests and then jump to the real instruction 18179 * handler. Note that the call to dvmCheckInst is done as a tail call. 18180 */ 18181 adrl lr, dvmAsmInstructionStart + (326 * 64) 18182 mov r0, rPC @ arg0 18183 mov r1, rSELF @ arg1 18184 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18185 18186/* ------------------------------ */ 18187 .balign 64 18188.L_ALT_OP_UNUSED_47FF: /* 0x147 */ 18189/* File: armv5te/ALT_STUB.S */ 18190/* 18191 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18192 * any interesting requests and then jump to the real instruction 18193 * handler. Note that the call to dvmCheckInst is done as a tail call. 18194 */ 18195 adrl lr, dvmAsmInstructionStart + (327 * 64) 18196 mov r0, rPC @ arg0 18197 mov r1, rSELF @ arg1 18198 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18199 18200/* ------------------------------ */ 18201 .balign 64 18202.L_ALT_OP_UNUSED_48FF: /* 0x148 */ 18203/* File: armv5te/ALT_STUB.S */ 18204/* 18205 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18206 * any interesting requests and then jump to the real instruction 18207 * handler. Note that the call to dvmCheckInst is done as a tail call. 18208 */ 18209 adrl lr, dvmAsmInstructionStart + (328 * 64) 18210 mov r0, rPC @ arg0 18211 mov r1, rSELF @ arg1 18212 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18213 18214/* ------------------------------ */ 18215 .balign 64 18216.L_ALT_OP_UNUSED_49FF: /* 0x149 */ 18217/* File: armv5te/ALT_STUB.S */ 18218/* 18219 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18220 * any interesting requests and then jump to the real instruction 18221 * handler. Note that the call to dvmCheckInst is done as a tail call. 18222 */ 18223 adrl lr, dvmAsmInstructionStart + (329 * 64) 18224 mov r0, rPC @ arg0 18225 mov r1, rSELF @ arg1 18226 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18227 18228/* ------------------------------ */ 18229 .balign 64 18230.L_ALT_OP_UNUSED_4AFF: /* 0x14a */ 18231/* File: armv5te/ALT_STUB.S */ 18232/* 18233 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18234 * any interesting requests and then jump to the real instruction 18235 * handler. Note that the call to dvmCheckInst is done as a tail call. 18236 */ 18237 adrl lr, dvmAsmInstructionStart + (330 * 64) 18238 mov r0, rPC @ arg0 18239 mov r1, rSELF @ arg1 18240 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18241 18242/* ------------------------------ */ 18243 .balign 64 18244.L_ALT_OP_UNUSED_4BFF: /* 0x14b */ 18245/* File: armv5te/ALT_STUB.S */ 18246/* 18247 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18248 * any interesting requests and then jump to the real instruction 18249 * handler. Note that the call to dvmCheckInst is done as a tail call. 18250 */ 18251 adrl lr, dvmAsmInstructionStart + (331 * 64) 18252 mov r0, rPC @ arg0 18253 mov r1, rSELF @ arg1 18254 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18255 18256/* ------------------------------ */ 18257 .balign 64 18258.L_ALT_OP_UNUSED_4CFF: /* 0x14c */ 18259/* File: armv5te/ALT_STUB.S */ 18260/* 18261 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18262 * any interesting requests and then jump to the real instruction 18263 * handler. Note that the call to dvmCheckInst is done as a tail call. 18264 */ 18265 adrl lr, dvmAsmInstructionStart + (332 * 64) 18266 mov r0, rPC @ arg0 18267 mov r1, rSELF @ arg1 18268 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18269 18270/* ------------------------------ */ 18271 .balign 64 18272.L_ALT_OP_UNUSED_4DFF: /* 0x14d */ 18273/* File: armv5te/ALT_STUB.S */ 18274/* 18275 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18276 * any interesting requests and then jump to the real instruction 18277 * handler. Note that the call to dvmCheckInst is done as a tail call. 18278 */ 18279 adrl lr, dvmAsmInstructionStart + (333 * 64) 18280 mov r0, rPC @ arg0 18281 mov r1, rSELF @ arg1 18282 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18283 18284/* ------------------------------ */ 18285 .balign 64 18286.L_ALT_OP_UNUSED_4EFF: /* 0x14e */ 18287/* File: armv5te/ALT_STUB.S */ 18288/* 18289 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18290 * any interesting requests and then jump to the real instruction 18291 * handler. Note that the call to dvmCheckInst is done as a tail call. 18292 */ 18293 adrl lr, dvmAsmInstructionStart + (334 * 64) 18294 mov r0, rPC @ arg0 18295 mov r1, rSELF @ arg1 18296 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18297 18298/* ------------------------------ */ 18299 .balign 64 18300.L_ALT_OP_UNUSED_4FFF: /* 0x14f */ 18301/* File: armv5te/ALT_STUB.S */ 18302/* 18303 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18304 * any interesting requests and then jump to the real instruction 18305 * handler. Note that the call to dvmCheckInst is done as a tail call. 18306 */ 18307 adrl lr, dvmAsmInstructionStart + (335 * 64) 18308 mov r0, rPC @ arg0 18309 mov r1, rSELF @ arg1 18310 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18311 18312/* ------------------------------ */ 18313 .balign 64 18314.L_ALT_OP_UNUSED_50FF: /* 0x150 */ 18315/* File: armv5te/ALT_STUB.S */ 18316/* 18317 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18318 * any interesting requests and then jump to the real instruction 18319 * handler. Note that the call to dvmCheckInst is done as a tail call. 18320 */ 18321 adrl lr, dvmAsmInstructionStart + (336 * 64) 18322 mov r0, rPC @ arg0 18323 mov r1, rSELF @ arg1 18324 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18325 18326/* ------------------------------ */ 18327 .balign 64 18328.L_ALT_OP_UNUSED_51FF: /* 0x151 */ 18329/* File: armv5te/ALT_STUB.S */ 18330/* 18331 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18332 * any interesting requests and then jump to the real instruction 18333 * handler. Note that the call to dvmCheckInst is done as a tail call. 18334 */ 18335 adrl lr, dvmAsmInstructionStart + (337 * 64) 18336 mov r0, rPC @ arg0 18337 mov r1, rSELF @ arg1 18338 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18339 18340/* ------------------------------ */ 18341 .balign 64 18342.L_ALT_OP_UNUSED_52FF: /* 0x152 */ 18343/* File: armv5te/ALT_STUB.S */ 18344/* 18345 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18346 * any interesting requests and then jump to the real instruction 18347 * handler. Note that the call to dvmCheckInst is done as a tail call. 18348 */ 18349 adrl lr, dvmAsmInstructionStart + (338 * 64) 18350 mov r0, rPC @ arg0 18351 mov r1, rSELF @ arg1 18352 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18353 18354/* ------------------------------ */ 18355 .balign 64 18356.L_ALT_OP_UNUSED_53FF: /* 0x153 */ 18357/* File: armv5te/ALT_STUB.S */ 18358/* 18359 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18360 * any interesting requests and then jump to the real instruction 18361 * handler. Note that the call to dvmCheckInst is done as a tail call. 18362 */ 18363 adrl lr, dvmAsmInstructionStart + (339 * 64) 18364 mov r0, rPC @ arg0 18365 mov r1, rSELF @ arg1 18366 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18367 18368/* ------------------------------ */ 18369 .balign 64 18370.L_ALT_OP_UNUSED_54FF: /* 0x154 */ 18371/* File: armv5te/ALT_STUB.S */ 18372/* 18373 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18374 * any interesting requests and then jump to the real instruction 18375 * handler. Note that the call to dvmCheckInst is done as a tail call. 18376 */ 18377 adrl lr, dvmAsmInstructionStart + (340 * 64) 18378 mov r0, rPC @ arg0 18379 mov r1, rSELF @ arg1 18380 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18381 18382/* ------------------------------ */ 18383 .balign 64 18384.L_ALT_OP_UNUSED_55FF: /* 0x155 */ 18385/* File: armv5te/ALT_STUB.S */ 18386/* 18387 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18388 * any interesting requests and then jump to the real instruction 18389 * handler. Note that the call to dvmCheckInst is done as a tail call. 18390 */ 18391 adrl lr, dvmAsmInstructionStart + (341 * 64) 18392 mov r0, rPC @ arg0 18393 mov r1, rSELF @ arg1 18394 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18395 18396/* ------------------------------ */ 18397 .balign 64 18398.L_ALT_OP_UNUSED_56FF: /* 0x156 */ 18399/* File: armv5te/ALT_STUB.S */ 18400/* 18401 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18402 * any interesting requests and then jump to the real instruction 18403 * handler. Note that the call to dvmCheckInst is done as a tail call. 18404 */ 18405 adrl lr, dvmAsmInstructionStart + (342 * 64) 18406 mov r0, rPC @ arg0 18407 mov r1, rSELF @ arg1 18408 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18409 18410/* ------------------------------ */ 18411 .balign 64 18412.L_ALT_OP_UNUSED_57FF: /* 0x157 */ 18413/* File: armv5te/ALT_STUB.S */ 18414/* 18415 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18416 * any interesting requests and then jump to the real instruction 18417 * handler. Note that the call to dvmCheckInst is done as a tail call. 18418 */ 18419 adrl lr, dvmAsmInstructionStart + (343 * 64) 18420 mov r0, rPC @ arg0 18421 mov r1, rSELF @ arg1 18422 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18423 18424/* ------------------------------ */ 18425 .balign 64 18426.L_ALT_OP_UNUSED_58FF: /* 0x158 */ 18427/* File: armv5te/ALT_STUB.S */ 18428/* 18429 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18430 * any interesting requests and then jump to the real instruction 18431 * handler. Note that the call to dvmCheckInst is done as a tail call. 18432 */ 18433 adrl lr, dvmAsmInstructionStart + (344 * 64) 18434 mov r0, rPC @ arg0 18435 mov r1, rSELF @ arg1 18436 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18437 18438/* ------------------------------ */ 18439 .balign 64 18440.L_ALT_OP_UNUSED_59FF: /* 0x159 */ 18441/* File: armv5te/ALT_STUB.S */ 18442/* 18443 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18444 * any interesting requests and then jump to the real instruction 18445 * handler. Note that the call to dvmCheckInst is done as a tail call. 18446 */ 18447 adrl lr, dvmAsmInstructionStart + (345 * 64) 18448 mov r0, rPC @ arg0 18449 mov r1, rSELF @ arg1 18450 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18451 18452/* ------------------------------ */ 18453 .balign 64 18454.L_ALT_OP_UNUSED_5AFF: /* 0x15a */ 18455/* File: armv5te/ALT_STUB.S */ 18456/* 18457 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18458 * any interesting requests and then jump to the real instruction 18459 * handler. Note that the call to dvmCheckInst is done as a tail call. 18460 */ 18461 adrl lr, dvmAsmInstructionStart + (346 * 64) 18462 mov r0, rPC @ arg0 18463 mov r1, rSELF @ arg1 18464 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18465 18466/* ------------------------------ */ 18467 .balign 64 18468.L_ALT_OP_UNUSED_5BFF: /* 0x15b */ 18469/* File: armv5te/ALT_STUB.S */ 18470/* 18471 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18472 * any interesting requests and then jump to the real instruction 18473 * handler. Note that the call to dvmCheckInst is done as a tail call. 18474 */ 18475 adrl lr, dvmAsmInstructionStart + (347 * 64) 18476 mov r0, rPC @ arg0 18477 mov r1, rSELF @ arg1 18478 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18479 18480/* ------------------------------ */ 18481 .balign 64 18482.L_ALT_OP_UNUSED_5CFF: /* 0x15c */ 18483/* File: armv5te/ALT_STUB.S */ 18484/* 18485 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18486 * any interesting requests and then jump to the real instruction 18487 * handler. Note that the call to dvmCheckInst is done as a tail call. 18488 */ 18489 adrl lr, dvmAsmInstructionStart + (348 * 64) 18490 mov r0, rPC @ arg0 18491 mov r1, rSELF @ arg1 18492 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18493 18494/* ------------------------------ */ 18495 .balign 64 18496.L_ALT_OP_UNUSED_5DFF: /* 0x15d */ 18497/* File: armv5te/ALT_STUB.S */ 18498/* 18499 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18500 * any interesting requests and then jump to the real instruction 18501 * handler. Note that the call to dvmCheckInst is done as a tail call. 18502 */ 18503 adrl lr, dvmAsmInstructionStart + (349 * 64) 18504 mov r0, rPC @ arg0 18505 mov r1, rSELF @ arg1 18506 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18507 18508/* ------------------------------ */ 18509 .balign 64 18510.L_ALT_OP_UNUSED_5EFF: /* 0x15e */ 18511/* File: armv5te/ALT_STUB.S */ 18512/* 18513 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18514 * any interesting requests and then jump to the real instruction 18515 * handler. Note that the call to dvmCheckInst is done as a tail call. 18516 */ 18517 adrl lr, dvmAsmInstructionStart + (350 * 64) 18518 mov r0, rPC @ arg0 18519 mov r1, rSELF @ arg1 18520 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18521 18522/* ------------------------------ */ 18523 .balign 64 18524.L_ALT_OP_UNUSED_5FFF: /* 0x15f */ 18525/* File: armv5te/ALT_STUB.S */ 18526/* 18527 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18528 * any interesting requests and then jump to the real instruction 18529 * handler. Note that the call to dvmCheckInst is done as a tail call. 18530 */ 18531 adrl lr, dvmAsmInstructionStart + (351 * 64) 18532 mov r0, rPC @ arg0 18533 mov r1, rSELF @ arg1 18534 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18535 18536/* ------------------------------ */ 18537 .balign 64 18538.L_ALT_OP_UNUSED_60FF: /* 0x160 */ 18539/* File: armv5te/ALT_STUB.S */ 18540/* 18541 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18542 * any interesting requests and then jump to the real instruction 18543 * handler. Note that the call to dvmCheckInst is done as a tail call. 18544 */ 18545 adrl lr, dvmAsmInstructionStart + (352 * 64) 18546 mov r0, rPC @ arg0 18547 mov r1, rSELF @ arg1 18548 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18549 18550/* ------------------------------ */ 18551 .balign 64 18552.L_ALT_OP_UNUSED_61FF: /* 0x161 */ 18553/* File: armv5te/ALT_STUB.S */ 18554/* 18555 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18556 * any interesting requests and then jump to the real instruction 18557 * handler. Note that the call to dvmCheckInst is done as a tail call. 18558 */ 18559 adrl lr, dvmAsmInstructionStart + (353 * 64) 18560 mov r0, rPC @ arg0 18561 mov r1, rSELF @ arg1 18562 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18563 18564/* ------------------------------ */ 18565 .balign 64 18566.L_ALT_OP_UNUSED_62FF: /* 0x162 */ 18567/* File: armv5te/ALT_STUB.S */ 18568/* 18569 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18570 * any interesting requests and then jump to the real instruction 18571 * handler. Note that the call to dvmCheckInst is done as a tail call. 18572 */ 18573 adrl lr, dvmAsmInstructionStart + (354 * 64) 18574 mov r0, rPC @ arg0 18575 mov r1, rSELF @ arg1 18576 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18577 18578/* ------------------------------ */ 18579 .balign 64 18580.L_ALT_OP_UNUSED_63FF: /* 0x163 */ 18581/* File: armv5te/ALT_STUB.S */ 18582/* 18583 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18584 * any interesting requests and then jump to the real instruction 18585 * handler. Note that the call to dvmCheckInst is done as a tail call. 18586 */ 18587 adrl lr, dvmAsmInstructionStart + (355 * 64) 18588 mov r0, rPC @ arg0 18589 mov r1, rSELF @ arg1 18590 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18591 18592/* ------------------------------ */ 18593 .balign 64 18594.L_ALT_OP_UNUSED_64FF: /* 0x164 */ 18595/* File: armv5te/ALT_STUB.S */ 18596/* 18597 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18598 * any interesting requests and then jump to the real instruction 18599 * handler. Note that the call to dvmCheckInst is done as a tail call. 18600 */ 18601 adrl lr, dvmAsmInstructionStart + (356 * 64) 18602 mov r0, rPC @ arg0 18603 mov r1, rSELF @ arg1 18604 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18605 18606/* ------------------------------ */ 18607 .balign 64 18608.L_ALT_OP_UNUSED_65FF: /* 0x165 */ 18609/* File: armv5te/ALT_STUB.S */ 18610/* 18611 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18612 * any interesting requests and then jump to the real instruction 18613 * handler. Note that the call to dvmCheckInst is done as a tail call. 18614 */ 18615 adrl lr, dvmAsmInstructionStart + (357 * 64) 18616 mov r0, rPC @ arg0 18617 mov r1, rSELF @ arg1 18618 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18619 18620/* ------------------------------ */ 18621 .balign 64 18622.L_ALT_OP_UNUSED_66FF: /* 0x166 */ 18623/* File: armv5te/ALT_STUB.S */ 18624/* 18625 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18626 * any interesting requests and then jump to the real instruction 18627 * handler. Note that the call to dvmCheckInst is done as a tail call. 18628 */ 18629 adrl lr, dvmAsmInstructionStart + (358 * 64) 18630 mov r0, rPC @ arg0 18631 mov r1, rSELF @ arg1 18632 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18633 18634/* ------------------------------ */ 18635 .balign 64 18636.L_ALT_OP_UNUSED_67FF: /* 0x167 */ 18637/* File: armv5te/ALT_STUB.S */ 18638/* 18639 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18640 * any interesting requests and then jump to the real instruction 18641 * handler. Note that the call to dvmCheckInst is done as a tail call. 18642 */ 18643 adrl lr, dvmAsmInstructionStart + (359 * 64) 18644 mov r0, rPC @ arg0 18645 mov r1, rSELF @ arg1 18646 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18647 18648/* ------------------------------ */ 18649 .balign 64 18650.L_ALT_OP_UNUSED_68FF: /* 0x168 */ 18651/* File: armv5te/ALT_STUB.S */ 18652/* 18653 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18654 * any interesting requests and then jump to the real instruction 18655 * handler. Note that the call to dvmCheckInst is done as a tail call. 18656 */ 18657 adrl lr, dvmAsmInstructionStart + (360 * 64) 18658 mov r0, rPC @ arg0 18659 mov r1, rSELF @ arg1 18660 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18661 18662/* ------------------------------ */ 18663 .balign 64 18664.L_ALT_OP_UNUSED_69FF: /* 0x169 */ 18665/* File: armv5te/ALT_STUB.S */ 18666/* 18667 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18668 * any interesting requests and then jump to the real instruction 18669 * handler. Note that the call to dvmCheckInst is done as a tail call. 18670 */ 18671 adrl lr, dvmAsmInstructionStart + (361 * 64) 18672 mov r0, rPC @ arg0 18673 mov r1, rSELF @ arg1 18674 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18675 18676/* ------------------------------ */ 18677 .balign 64 18678.L_ALT_OP_UNUSED_6AFF: /* 0x16a */ 18679/* File: armv5te/ALT_STUB.S */ 18680/* 18681 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18682 * any interesting requests and then jump to the real instruction 18683 * handler. Note that the call to dvmCheckInst is done as a tail call. 18684 */ 18685 adrl lr, dvmAsmInstructionStart + (362 * 64) 18686 mov r0, rPC @ arg0 18687 mov r1, rSELF @ arg1 18688 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18689 18690/* ------------------------------ */ 18691 .balign 64 18692.L_ALT_OP_UNUSED_6BFF: /* 0x16b */ 18693/* File: armv5te/ALT_STUB.S */ 18694/* 18695 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18696 * any interesting requests and then jump to the real instruction 18697 * handler. Note that the call to dvmCheckInst is done as a tail call. 18698 */ 18699 adrl lr, dvmAsmInstructionStart + (363 * 64) 18700 mov r0, rPC @ arg0 18701 mov r1, rSELF @ arg1 18702 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18703 18704/* ------------------------------ */ 18705 .balign 64 18706.L_ALT_OP_UNUSED_6CFF: /* 0x16c */ 18707/* File: armv5te/ALT_STUB.S */ 18708/* 18709 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18710 * any interesting requests and then jump to the real instruction 18711 * handler. Note that the call to dvmCheckInst is done as a tail call. 18712 */ 18713 adrl lr, dvmAsmInstructionStart + (364 * 64) 18714 mov r0, rPC @ arg0 18715 mov r1, rSELF @ arg1 18716 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18717 18718/* ------------------------------ */ 18719 .balign 64 18720.L_ALT_OP_UNUSED_6DFF: /* 0x16d */ 18721/* File: armv5te/ALT_STUB.S */ 18722/* 18723 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18724 * any interesting requests and then jump to the real instruction 18725 * handler. Note that the call to dvmCheckInst is done as a tail call. 18726 */ 18727 adrl lr, dvmAsmInstructionStart + (365 * 64) 18728 mov r0, rPC @ arg0 18729 mov r1, rSELF @ arg1 18730 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18731 18732/* ------------------------------ */ 18733 .balign 64 18734.L_ALT_OP_UNUSED_6EFF: /* 0x16e */ 18735/* File: armv5te/ALT_STUB.S */ 18736/* 18737 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18738 * any interesting requests and then jump to the real instruction 18739 * handler. Note that the call to dvmCheckInst is done as a tail call. 18740 */ 18741 adrl lr, dvmAsmInstructionStart + (366 * 64) 18742 mov r0, rPC @ arg0 18743 mov r1, rSELF @ arg1 18744 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18745 18746/* ------------------------------ */ 18747 .balign 64 18748.L_ALT_OP_UNUSED_6FFF: /* 0x16f */ 18749/* File: armv5te/ALT_STUB.S */ 18750/* 18751 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18752 * any interesting requests and then jump to the real instruction 18753 * handler. Note that the call to dvmCheckInst is done as a tail call. 18754 */ 18755 adrl lr, dvmAsmInstructionStart + (367 * 64) 18756 mov r0, rPC @ arg0 18757 mov r1, rSELF @ arg1 18758 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18759 18760/* ------------------------------ */ 18761 .balign 64 18762.L_ALT_OP_UNUSED_70FF: /* 0x170 */ 18763/* File: armv5te/ALT_STUB.S */ 18764/* 18765 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18766 * any interesting requests and then jump to the real instruction 18767 * handler. Note that the call to dvmCheckInst is done as a tail call. 18768 */ 18769 adrl lr, dvmAsmInstructionStart + (368 * 64) 18770 mov r0, rPC @ arg0 18771 mov r1, rSELF @ arg1 18772 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18773 18774/* ------------------------------ */ 18775 .balign 64 18776.L_ALT_OP_UNUSED_71FF: /* 0x171 */ 18777/* File: armv5te/ALT_STUB.S */ 18778/* 18779 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18780 * any interesting requests and then jump to the real instruction 18781 * handler. Note that the call to dvmCheckInst is done as a tail call. 18782 */ 18783 adrl lr, dvmAsmInstructionStart + (369 * 64) 18784 mov r0, rPC @ arg0 18785 mov r1, rSELF @ arg1 18786 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18787 18788/* ------------------------------ */ 18789 .balign 64 18790.L_ALT_OP_UNUSED_72FF: /* 0x172 */ 18791/* File: armv5te/ALT_STUB.S */ 18792/* 18793 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18794 * any interesting requests and then jump to the real instruction 18795 * handler. Note that the call to dvmCheckInst is done as a tail call. 18796 */ 18797 adrl lr, dvmAsmInstructionStart + (370 * 64) 18798 mov r0, rPC @ arg0 18799 mov r1, rSELF @ arg1 18800 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18801 18802/* ------------------------------ */ 18803 .balign 64 18804.L_ALT_OP_UNUSED_73FF: /* 0x173 */ 18805/* File: armv5te/ALT_STUB.S */ 18806/* 18807 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18808 * any interesting requests and then jump to the real instruction 18809 * handler. Note that the call to dvmCheckInst is done as a tail call. 18810 */ 18811 adrl lr, dvmAsmInstructionStart + (371 * 64) 18812 mov r0, rPC @ arg0 18813 mov r1, rSELF @ arg1 18814 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18815 18816/* ------------------------------ */ 18817 .balign 64 18818.L_ALT_OP_UNUSED_74FF: /* 0x174 */ 18819/* File: armv5te/ALT_STUB.S */ 18820/* 18821 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18822 * any interesting requests and then jump to the real instruction 18823 * handler. Note that the call to dvmCheckInst is done as a tail call. 18824 */ 18825 adrl lr, dvmAsmInstructionStart + (372 * 64) 18826 mov r0, rPC @ arg0 18827 mov r1, rSELF @ arg1 18828 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18829 18830/* ------------------------------ */ 18831 .balign 64 18832.L_ALT_OP_UNUSED_75FF: /* 0x175 */ 18833/* File: armv5te/ALT_STUB.S */ 18834/* 18835 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18836 * any interesting requests and then jump to the real instruction 18837 * handler. Note that the call to dvmCheckInst is done as a tail call. 18838 */ 18839 adrl lr, dvmAsmInstructionStart + (373 * 64) 18840 mov r0, rPC @ arg0 18841 mov r1, rSELF @ arg1 18842 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18843 18844/* ------------------------------ */ 18845 .balign 64 18846.L_ALT_OP_UNUSED_76FF: /* 0x176 */ 18847/* File: armv5te/ALT_STUB.S */ 18848/* 18849 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18850 * any interesting requests and then jump to the real instruction 18851 * handler. Note that the call to dvmCheckInst is done as a tail call. 18852 */ 18853 adrl lr, dvmAsmInstructionStart + (374 * 64) 18854 mov r0, rPC @ arg0 18855 mov r1, rSELF @ arg1 18856 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18857 18858/* ------------------------------ */ 18859 .balign 64 18860.L_ALT_OP_UNUSED_77FF: /* 0x177 */ 18861/* File: armv5te/ALT_STUB.S */ 18862/* 18863 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18864 * any interesting requests and then jump to the real instruction 18865 * handler. Note that the call to dvmCheckInst is done as a tail call. 18866 */ 18867 adrl lr, dvmAsmInstructionStart + (375 * 64) 18868 mov r0, rPC @ arg0 18869 mov r1, rSELF @ arg1 18870 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18871 18872/* ------------------------------ */ 18873 .balign 64 18874.L_ALT_OP_UNUSED_78FF: /* 0x178 */ 18875/* File: armv5te/ALT_STUB.S */ 18876/* 18877 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18878 * any interesting requests and then jump to the real instruction 18879 * handler. Note that the call to dvmCheckInst is done as a tail call. 18880 */ 18881 adrl lr, dvmAsmInstructionStart + (376 * 64) 18882 mov r0, rPC @ arg0 18883 mov r1, rSELF @ arg1 18884 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18885 18886/* ------------------------------ */ 18887 .balign 64 18888.L_ALT_OP_UNUSED_79FF: /* 0x179 */ 18889/* File: armv5te/ALT_STUB.S */ 18890/* 18891 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18892 * any interesting requests and then jump to the real instruction 18893 * handler. Note that the call to dvmCheckInst is done as a tail call. 18894 */ 18895 adrl lr, dvmAsmInstructionStart + (377 * 64) 18896 mov r0, rPC @ arg0 18897 mov r1, rSELF @ arg1 18898 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18899 18900/* ------------------------------ */ 18901 .balign 64 18902.L_ALT_OP_UNUSED_7AFF: /* 0x17a */ 18903/* File: armv5te/ALT_STUB.S */ 18904/* 18905 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18906 * any interesting requests and then jump to the real instruction 18907 * handler. Note that the call to dvmCheckInst is done as a tail call. 18908 */ 18909 adrl lr, dvmAsmInstructionStart + (378 * 64) 18910 mov r0, rPC @ arg0 18911 mov r1, rSELF @ arg1 18912 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18913 18914/* ------------------------------ */ 18915 .balign 64 18916.L_ALT_OP_UNUSED_7BFF: /* 0x17b */ 18917/* File: armv5te/ALT_STUB.S */ 18918/* 18919 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18920 * any interesting requests and then jump to the real instruction 18921 * handler. Note that the call to dvmCheckInst is done as a tail call. 18922 */ 18923 adrl lr, dvmAsmInstructionStart + (379 * 64) 18924 mov r0, rPC @ arg0 18925 mov r1, rSELF @ arg1 18926 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18927 18928/* ------------------------------ */ 18929 .balign 64 18930.L_ALT_OP_UNUSED_7CFF: /* 0x17c */ 18931/* File: armv5te/ALT_STUB.S */ 18932/* 18933 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18934 * any interesting requests and then jump to the real instruction 18935 * handler. Note that the call to dvmCheckInst is done as a tail call. 18936 */ 18937 adrl lr, dvmAsmInstructionStart + (380 * 64) 18938 mov r0, rPC @ arg0 18939 mov r1, rSELF @ arg1 18940 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18941 18942/* ------------------------------ */ 18943 .balign 64 18944.L_ALT_OP_UNUSED_7DFF: /* 0x17d */ 18945/* File: armv5te/ALT_STUB.S */ 18946/* 18947 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18948 * any interesting requests and then jump to the real instruction 18949 * handler. Note that the call to dvmCheckInst is done as a tail call. 18950 */ 18951 adrl lr, dvmAsmInstructionStart + (381 * 64) 18952 mov r0, rPC @ arg0 18953 mov r1, rSELF @ arg1 18954 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18955 18956/* ------------------------------ */ 18957 .balign 64 18958.L_ALT_OP_UNUSED_7EFF: /* 0x17e */ 18959/* File: armv5te/ALT_STUB.S */ 18960/* 18961 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18962 * any interesting requests and then jump to the real instruction 18963 * handler. Note that the call to dvmCheckInst is done as a tail call. 18964 */ 18965 adrl lr, dvmAsmInstructionStart + (382 * 64) 18966 mov r0, rPC @ arg0 18967 mov r1, rSELF @ arg1 18968 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18969 18970/* ------------------------------ */ 18971 .balign 64 18972.L_ALT_OP_UNUSED_7FFF: /* 0x17f */ 18973/* File: armv5te/ALT_STUB.S */ 18974/* 18975 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18976 * any interesting requests and then jump to the real instruction 18977 * handler. Note that the call to dvmCheckInst is done as a tail call. 18978 */ 18979 adrl lr, dvmAsmInstructionStart + (383 * 64) 18980 mov r0, rPC @ arg0 18981 mov r1, rSELF @ arg1 18982 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18983 18984/* ------------------------------ */ 18985 .balign 64 18986.L_ALT_OP_UNUSED_80FF: /* 0x180 */ 18987/* File: armv5te/ALT_STUB.S */ 18988/* 18989 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 18990 * any interesting requests and then jump to the real instruction 18991 * handler. Note that the call to dvmCheckInst is done as a tail call. 18992 */ 18993 adrl lr, dvmAsmInstructionStart + (384 * 64) 18994 mov r0, rPC @ arg0 18995 mov r1, rSELF @ arg1 18996 b dvmCheckInst @ (dPC,self) tail call to instruction checker 18997 18998/* ------------------------------ */ 18999 .balign 64 19000.L_ALT_OP_UNUSED_81FF: /* 0x181 */ 19001/* File: armv5te/ALT_STUB.S */ 19002/* 19003 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19004 * any interesting requests and then jump to the real instruction 19005 * handler. Note that the call to dvmCheckInst is done as a tail call. 19006 */ 19007 adrl lr, dvmAsmInstructionStart + (385 * 64) 19008 mov r0, rPC @ arg0 19009 mov r1, rSELF @ arg1 19010 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19011 19012/* ------------------------------ */ 19013 .balign 64 19014.L_ALT_OP_UNUSED_82FF: /* 0x182 */ 19015/* File: armv5te/ALT_STUB.S */ 19016/* 19017 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19018 * any interesting requests and then jump to the real instruction 19019 * handler. Note that the call to dvmCheckInst is done as a tail call. 19020 */ 19021 adrl lr, dvmAsmInstructionStart + (386 * 64) 19022 mov r0, rPC @ arg0 19023 mov r1, rSELF @ arg1 19024 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19025 19026/* ------------------------------ */ 19027 .balign 64 19028.L_ALT_OP_UNUSED_83FF: /* 0x183 */ 19029/* File: armv5te/ALT_STUB.S */ 19030/* 19031 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19032 * any interesting requests and then jump to the real instruction 19033 * handler. Note that the call to dvmCheckInst is done as a tail call. 19034 */ 19035 adrl lr, dvmAsmInstructionStart + (387 * 64) 19036 mov r0, rPC @ arg0 19037 mov r1, rSELF @ arg1 19038 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19039 19040/* ------------------------------ */ 19041 .balign 64 19042.L_ALT_OP_UNUSED_84FF: /* 0x184 */ 19043/* File: armv5te/ALT_STUB.S */ 19044/* 19045 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19046 * any interesting requests and then jump to the real instruction 19047 * handler. Note that the call to dvmCheckInst is done as a tail call. 19048 */ 19049 adrl lr, dvmAsmInstructionStart + (388 * 64) 19050 mov r0, rPC @ arg0 19051 mov r1, rSELF @ arg1 19052 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19053 19054/* ------------------------------ */ 19055 .balign 64 19056.L_ALT_OP_UNUSED_85FF: /* 0x185 */ 19057/* File: armv5te/ALT_STUB.S */ 19058/* 19059 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19060 * any interesting requests and then jump to the real instruction 19061 * handler. Note that the call to dvmCheckInst is done as a tail call. 19062 */ 19063 adrl lr, dvmAsmInstructionStart + (389 * 64) 19064 mov r0, rPC @ arg0 19065 mov r1, rSELF @ arg1 19066 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19067 19068/* ------------------------------ */ 19069 .balign 64 19070.L_ALT_OP_UNUSED_86FF: /* 0x186 */ 19071/* File: armv5te/ALT_STUB.S */ 19072/* 19073 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19074 * any interesting requests and then jump to the real instruction 19075 * handler. Note that the call to dvmCheckInst is done as a tail call. 19076 */ 19077 adrl lr, dvmAsmInstructionStart + (390 * 64) 19078 mov r0, rPC @ arg0 19079 mov r1, rSELF @ arg1 19080 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19081 19082/* ------------------------------ */ 19083 .balign 64 19084.L_ALT_OP_UNUSED_87FF: /* 0x187 */ 19085/* File: armv5te/ALT_STUB.S */ 19086/* 19087 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19088 * any interesting requests and then jump to the real instruction 19089 * handler. Note that the call to dvmCheckInst is done as a tail call. 19090 */ 19091 adrl lr, dvmAsmInstructionStart + (391 * 64) 19092 mov r0, rPC @ arg0 19093 mov r1, rSELF @ arg1 19094 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19095 19096/* ------------------------------ */ 19097 .balign 64 19098.L_ALT_OP_UNUSED_88FF: /* 0x188 */ 19099/* File: armv5te/ALT_STUB.S */ 19100/* 19101 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19102 * any interesting requests and then jump to the real instruction 19103 * handler. Note that the call to dvmCheckInst is done as a tail call. 19104 */ 19105 adrl lr, dvmAsmInstructionStart + (392 * 64) 19106 mov r0, rPC @ arg0 19107 mov r1, rSELF @ arg1 19108 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19109 19110/* ------------------------------ */ 19111 .balign 64 19112.L_ALT_OP_UNUSED_89FF: /* 0x189 */ 19113/* File: armv5te/ALT_STUB.S */ 19114/* 19115 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19116 * any interesting requests and then jump to the real instruction 19117 * handler. Note that the call to dvmCheckInst is done as a tail call. 19118 */ 19119 adrl lr, dvmAsmInstructionStart + (393 * 64) 19120 mov r0, rPC @ arg0 19121 mov r1, rSELF @ arg1 19122 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19123 19124/* ------------------------------ */ 19125 .balign 64 19126.L_ALT_OP_UNUSED_8AFF: /* 0x18a */ 19127/* File: armv5te/ALT_STUB.S */ 19128/* 19129 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19130 * any interesting requests and then jump to the real instruction 19131 * handler. Note that the call to dvmCheckInst is done as a tail call. 19132 */ 19133 adrl lr, dvmAsmInstructionStart + (394 * 64) 19134 mov r0, rPC @ arg0 19135 mov r1, rSELF @ arg1 19136 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19137 19138/* ------------------------------ */ 19139 .balign 64 19140.L_ALT_OP_UNUSED_8BFF: /* 0x18b */ 19141/* File: armv5te/ALT_STUB.S */ 19142/* 19143 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19144 * any interesting requests and then jump to the real instruction 19145 * handler. Note that the call to dvmCheckInst is done as a tail call. 19146 */ 19147 adrl lr, dvmAsmInstructionStart + (395 * 64) 19148 mov r0, rPC @ arg0 19149 mov r1, rSELF @ arg1 19150 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19151 19152/* ------------------------------ */ 19153 .balign 64 19154.L_ALT_OP_UNUSED_8CFF: /* 0x18c */ 19155/* File: armv5te/ALT_STUB.S */ 19156/* 19157 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19158 * any interesting requests and then jump to the real instruction 19159 * handler. Note that the call to dvmCheckInst is done as a tail call. 19160 */ 19161 adrl lr, dvmAsmInstructionStart + (396 * 64) 19162 mov r0, rPC @ arg0 19163 mov r1, rSELF @ arg1 19164 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19165 19166/* ------------------------------ */ 19167 .balign 64 19168.L_ALT_OP_UNUSED_8DFF: /* 0x18d */ 19169/* File: armv5te/ALT_STUB.S */ 19170/* 19171 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19172 * any interesting requests and then jump to the real instruction 19173 * handler. Note that the call to dvmCheckInst is done as a tail call. 19174 */ 19175 adrl lr, dvmAsmInstructionStart + (397 * 64) 19176 mov r0, rPC @ arg0 19177 mov r1, rSELF @ arg1 19178 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19179 19180/* ------------------------------ */ 19181 .balign 64 19182.L_ALT_OP_UNUSED_8EFF: /* 0x18e */ 19183/* File: armv5te/ALT_STUB.S */ 19184/* 19185 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19186 * any interesting requests and then jump to the real instruction 19187 * handler. Note that the call to dvmCheckInst is done as a tail call. 19188 */ 19189 adrl lr, dvmAsmInstructionStart + (398 * 64) 19190 mov r0, rPC @ arg0 19191 mov r1, rSELF @ arg1 19192 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19193 19194/* ------------------------------ */ 19195 .balign 64 19196.L_ALT_OP_UNUSED_8FFF: /* 0x18f */ 19197/* File: armv5te/ALT_STUB.S */ 19198/* 19199 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19200 * any interesting requests and then jump to the real instruction 19201 * handler. Note that the call to dvmCheckInst is done as a tail call. 19202 */ 19203 adrl lr, dvmAsmInstructionStart + (399 * 64) 19204 mov r0, rPC @ arg0 19205 mov r1, rSELF @ arg1 19206 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19207 19208/* ------------------------------ */ 19209 .balign 64 19210.L_ALT_OP_UNUSED_90FF: /* 0x190 */ 19211/* File: armv5te/ALT_STUB.S */ 19212/* 19213 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19214 * any interesting requests and then jump to the real instruction 19215 * handler. Note that the call to dvmCheckInst is done as a tail call. 19216 */ 19217 adrl lr, dvmAsmInstructionStart + (400 * 64) 19218 mov r0, rPC @ arg0 19219 mov r1, rSELF @ arg1 19220 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19221 19222/* ------------------------------ */ 19223 .balign 64 19224.L_ALT_OP_UNUSED_91FF: /* 0x191 */ 19225/* File: armv5te/ALT_STUB.S */ 19226/* 19227 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19228 * any interesting requests and then jump to the real instruction 19229 * handler. Note that the call to dvmCheckInst is done as a tail call. 19230 */ 19231 adrl lr, dvmAsmInstructionStart + (401 * 64) 19232 mov r0, rPC @ arg0 19233 mov r1, rSELF @ arg1 19234 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19235 19236/* ------------------------------ */ 19237 .balign 64 19238.L_ALT_OP_UNUSED_92FF: /* 0x192 */ 19239/* File: armv5te/ALT_STUB.S */ 19240/* 19241 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19242 * any interesting requests and then jump to the real instruction 19243 * handler. Note that the call to dvmCheckInst is done as a tail call. 19244 */ 19245 adrl lr, dvmAsmInstructionStart + (402 * 64) 19246 mov r0, rPC @ arg0 19247 mov r1, rSELF @ arg1 19248 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19249 19250/* ------------------------------ */ 19251 .balign 64 19252.L_ALT_OP_UNUSED_93FF: /* 0x193 */ 19253/* File: armv5te/ALT_STUB.S */ 19254/* 19255 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19256 * any interesting requests and then jump to the real instruction 19257 * handler. Note that the call to dvmCheckInst is done as a tail call. 19258 */ 19259 adrl lr, dvmAsmInstructionStart + (403 * 64) 19260 mov r0, rPC @ arg0 19261 mov r1, rSELF @ arg1 19262 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19263 19264/* ------------------------------ */ 19265 .balign 64 19266.L_ALT_OP_UNUSED_94FF: /* 0x194 */ 19267/* File: armv5te/ALT_STUB.S */ 19268/* 19269 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19270 * any interesting requests and then jump to the real instruction 19271 * handler. Note that the call to dvmCheckInst is done as a tail call. 19272 */ 19273 adrl lr, dvmAsmInstructionStart + (404 * 64) 19274 mov r0, rPC @ arg0 19275 mov r1, rSELF @ arg1 19276 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19277 19278/* ------------------------------ */ 19279 .balign 64 19280.L_ALT_OP_UNUSED_95FF: /* 0x195 */ 19281/* File: armv5te/ALT_STUB.S */ 19282/* 19283 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19284 * any interesting requests and then jump to the real instruction 19285 * handler. Note that the call to dvmCheckInst is done as a tail call. 19286 */ 19287 adrl lr, dvmAsmInstructionStart + (405 * 64) 19288 mov r0, rPC @ arg0 19289 mov r1, rSELF @ arg1 19290 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19291 19292/* ------------------------------ */ 19293 .balign 64 19294.L_ALT_OP_UNUSED_96FF: /* 0x196 */ 19295/* File: armv5te/ALT_STUB.S */ 19296/* 19297 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19298 * any interesting requests and then jump to the real instruction 19299 * handler. Note that the call to dvmCheckInst is done as a tail call. 19300 */ 19301 adrl lr, dvmAsmInstructionStart + (406 * 64) 19302 mov r0, rPC @ arg0 19303 mov r1, rSELF @ arg1 19304 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19305 19306/* ------------------------------ */ 19307 .balign 64 19308.L_ALT_OP_UNUSED_97FF: /* 0x197 */ 19309/* File: armv5te/ALT_STUB.S */ 19310/* 19311 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19312 * any interesting requests and then jump to the real instruction 19313 * handler. Note that the call to dvmCheckInst is done as a tail call. 19314 */ 19315 adrl lr, dvmAsmInstructionStart + (407 * 64) 19316 mov r0, rPC @ arg0 19317 mov r1, rSELF @ arg1 19318 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19319 19320/* ------------------------------ */ 19321 .balign 64 19322.L_ALT_OP_UNUSED_98FF: /* 0x198 */ 19323/* File: armv5te/ALT_STUB.S */ 19324/* 19325 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19326 * any interesting requests and then jump to the real instruction 19327 * handler. Note that the call to dvmCheckInst is done as a tail call. 19328 */ 19329 adrl lr, dvmAsmInstructionStart + (408 * 64) 19330 mov r0, rPC @ arg0 19331 mov r1, rSELF @ arg1 19332 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19333 19334/* ------------------------------ */ 19335 .balign 64 19336.L_ALT_OP_UNUSED_99FF: /* 0x199 */ 19337/* File: armv5te/ALT_STUB.S */ 19338/* 19339 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19340 * any interesting requests and then jump to the real instruction 19341 * handler. Note that the call to dvmCheckInst is done as a tail call. 19342 */ 19343 adrl lr, dvmAsmInstructionStart + (409 * 64) 19344 mov r0, rPC @ arg0 19345 mov r1, rSELF @ arg1 19346 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19347 19348/* ------------------------------ */ 19349 .balign 64 19350.L_ALT_OP_UNUSED_9AFF: /* 0x19a */ 19351/* File: armv5te/ALT_STUB.S */ 19352/* 19353 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19354 * any interesting requests and then jump to the real instruction 19355 * handler. Note that the call to dvmCheckInst is done as a tail call. 19356 */ 19357 adrl lr, dvmAsmInstructionStart + (410 * 64) 19358 mov r0, rPC @ arg0 19359 mov r1, rSELF @ arg1 19360 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19361 19362/* ------------------------------ */ 19363 .balign 64 19364.L_ALT_OP_UNUSED_9BFF: /* 0x19b */ 19365/* File: armv5te/ALT_STUB.S */ 19366/* 19367 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19368 * any interesting requests and then jump to the real instruction 19369 * handler. Note that the call to dvmCheckInst is done as a tail call. 19370 */ 19371 adrl lr, dvmAsmInstructionStart + (411 * 64) 19372 mov r0, rPC @ arg0 19373 mov r1, rSELF @ arg1 19374 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19375 19376/* ------------------------------ */ 19377 .balign 64 19378.L_ALT_OP_UNUSED_9CFF: /* 0x19c */ 19379/* File: armv5te/ALT_STUB.S */ 19380/* 19381 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19382 * any interesting requests and then jump to the real instruction 19383 * handler. Note that the call to dvmCheckInst is done as a tail call. 19384 */ 19385 adrl lr, dvmAsmInstructionStart + (412 * 64) 19386 mov r0, rPC @ arg0 19387 mov r1, rSELF @ arg1 19388 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19389 19390/* ------------------------------ */ 19391 .balign 64 19392.L_ALT_OP_UNUSED_9DFF: /* 0x19d */ 19393/* File: armv5te/ALT_STUB.S */ 19394/* 19395 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19396 * any interesting requests and then jump to the real instruction 19397 * handler. Note that the call to dvmCheckInst is done as a tail call. 19398 */ 19399 adrl lr, dvmAsmInstructionStart + (413 * 64) 19400 mov r0, rPC @ arg0 19401 mov r1, rSELF @ arg1 19402 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19403 19404/* ------------------------------ */ 19405 .balign 64 19406.L_ALT_OP_UNUSED_9EFF: /* 0x19e */ 19407/* File: armv5te/ALT_STUB.S */ 19408/* 19409 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19410 * any interesting requests and then jump to the real instruction 19411 * handler. Note that the call to dvmCheckInst is done as a tail call. 19412 */ 19413 adrl lr, dvmAsmInstructionStart + (414 * 64) 19414 mov r0, rPC @ arg0 19415 mov r1, rSELF @ arg1 19416 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19417 19418/* ------------------------------ */ 19419 .balign 64 19420.L_ALT_OP_UNUSED_9FFF: /* 0x19f */ 19421/* File: armv5te/ALT_STUB.S */ 19422/* 19423 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19424 * any interesting requests and then jump to the real instruction 19425 * handler. Note that the call to dvmCheckInst is done as a tail call. 19426 */ 19427 adrl lr, dvmAsmInstructionStart + (415 * 64) 19428 mov r0, rPC @ arg0 19429 mov r1, rSELF @ arg1 19430 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19431 19432/* ------------------------------ */ 19433 .balign 64 19434.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */ 19435/* File: armv5te/ALT_STUB.S */ 19436/* 19437 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19438 * any interesting requests and then jump to the real instruction 19439 * handler. Note that the call to dvmCheckInst is done as a tail call. 19440 */ 19441 adrl lr, dvmAsmInstructionStart + (416 * 64) 19442 mov r0, rPC @ arg0 19443 mov r1, rSELF @ arg1 19444 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19445 19446/* ------------------------------ */ 19447 .balign 64 19448.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */ 19449/* File: armv5te/ALT_STUB.S */ 19450/* 19451 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19452 * any interesting requests and then jump to the real instruction 19453 * handler. Note that the call to dvmCheckInst is done as a tail call. 19454 */ 19455 adrl lr, dvmAsmInstructionStart + (417 * 64) 19456 mov r0, rPC @ arg0 19457 mov r1, rSELF @ arg1 19458 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19459 19460/* ------------------------------ */ 19461 .balign 64 19462.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */ 19463/* File: armv5te/ALT_STUB.S */ 19464/* 19465 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19466 * any interesting requests and then jump to the real instruction 19467 * handler. Note that the call to dvmCheckInst is done as a tail call. 19468 */ 19469 adrl lr, dvmAsmInstructionStart + (418 * 64) 19470 mov r0, rPC @ arg0 19471 mov r1, rSELF @ arg1 19472 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19473 19474/* ------------------------------ */ 19475 .balign 64 19476.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */ 19477/* File: armv5te/ALT_STUB.S */ 19478/* 19479 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19480 * any interesting requests and then jump to the real instruction 19481 * handler. Note that the call to dvmCheckInst is done as a tail call. 19482 */ 19483 adrl lr, dvmAsmInstructionStart + (419 * 64) 19484 mov r0, rPC @ arg0 19485 mov r1, rSELF @ arg1 19486 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19487 19488/* ------------------------------ */ 19489 .balign 64 19490.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */ 19491/* File: armv5te/ALT_STUB.S */ 19492/* 19493 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19494 * any interesting requests and then jump to the real instruction 19495 * handler. Note that the call to dvmCheckInst is done as a tail call. 19496 */ 19497 adrl lr, dvmAsmInstructionStart + (420 * 64) 19498 mov r0, rPC @ arg0 19499 mov r1, rSELF @ arg1 19500 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19501 19502/* ------------------------------ */ 19503 .balign 64 19504.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */ 19505/* File: armv5te/ALT_STUB.S */ 19506/* 19507 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19508 * any interesting requests and then jump to the real instruction 19509 * handler. Note that the call to dvmCheckInst is done as a tail call. 19510 */ 19511 adrl lr, dvmAsmInstructionStart + (421 * 64) 19512 mov r0, rPC @ arg0 19513 mov r1, rSELF @ arg1 19514 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19515 19516/* ------------------------------ */ 19517 .balign 64 19518.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */ 19519/* File: armv5te/ALT_STUB.S */ 19520/* 19521 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19522 * any interesting requests and then jump to the real instruction 19523 * handler. Note that the call to dvmCheckInst is done as a tail call. 19524 */ 19525 adrl lr, dvmAsmInstructionStart + (422 * 64) 19526 mov r0, rPC @ arg0 19527 mov r1, rSELF @ arg1 19528 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19529 19530/* ------------------------------ */ 19531 .balign 64 19532.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */ 19533/* File: armv5te/ALT_STUB.S */ 19534/* 19535 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19536 * any interesting requests and then jump to the real instruction 19537 * handler. Note that the call to dvmCheckInst is done as a tail call. 19538 */ 19539 adrl lr, dvmAsmInstructionStart + (423 * 64) 19540 mov r0, rPC @ arg0 19541 mov r1, rSELF @ arg1 19542 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19543 19544/* ------------------------------ */ 19545 .balign 64 19546.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */ 19547/* File: armv5te/ALT_STUB.S */ 19548/* 19549 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19550 * any interesting requests and then jump to the real instruction 19551 * handler. Note that the call to dvmCheckInst is done as a tail call. 19552 */ 19553 adrl lr, dvmAsmInstructionStart + (424 * 64) 19554 mov r0, rPC @ arg0 19555 mov r1, rSELF @ arg1 19556 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19557 19558/* ------------------------------ */ 19559 .balign 64 19560.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */ 19561/* File: armv5te/ALT_STUB.S */ 19562/* 19563 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19564 * any interesting requests and then jump to the real instruction 19565 * handler. Note that the call to dvmCheckInst is done as a tail call. 19566 */ 19567 adrl lr, dvmAsmInstructionStart + (425 * 64) 19568 mov r0, rPC @ arg0 19569 mov r1, rSELF @ arg1 19570 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19571 19572/* ------------------------------ */ 19573 .balign 64 19574.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */ 19575/* File: armv5te/ALT_STUB.S */ 19576/* 19577 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19578 * any interesting requests and then jump to the real instruction 19579 * handler. Note that the call to dvmCheckInst is done as a tail call. 19580 */ 19581 adrl lr, dvmAsmInstructionStart + (426 * 64) 19582 mov r0, rPC @ arg0 19583 mov r1, rSELF @ arg1 19584 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19585 19586/* ------------------------------ */ 19587 .balign 64 19588.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */ 19589/* File: armv5te/ALT_STUB.S */ 19590/* 19591 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19592 * any interesting requests and then jump to the real instruction 19593 * handler. Note that the call to dvmCheckInst is done as a tail call. 19594 */ 19595 adrl lr, dvmAsmInstructionStart + (427 * 64) 19596 mov r0, rPC @ arg0 19597 mov r1, rSELF @ arg1 19598 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19599 19600/* ------------------------------ */ 19601 .balign 64 19602.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */ 19603/* File: armv5te/ALT_STUB.S */ 19604/* 19605 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19606 * any interesting requests and then jump to the real instruction 19607 * handler. Note that the call to dvmCheckInst is done as a tail call. 19608 */ 19609 adrl lr, dvmAsmInstructionStart + (428 * 64) 19610 mov r0, rPC @ arg0 19611 mov r1, rSELF @ arg1 19612 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19613 19614/* ------------------------------ */ 19615 .balign 64 19616.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */ 19617/* File: armv5te/ALT_STUB.S */ 19618/* 19619 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19620 * any interesting requests and then jump to the real instruction 19621 * handler. Note that the call to dvmCheckInst is done as a tail call. 19622 */ 19623 adrl lr, dvmAsmInstructionStart + (429 * 64) 19624 mov r0, rPC @ arg0 19625 mov r1, rSELF @ arg1 19626 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19627 19628/* ------------------------------ */ 19629 .balign 64 19630.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */ 19631/* File: armv5te/ALT_STUB.S */ 19632/* 19633 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19634 * any interesting requests and then jump to the real instruction 19635 * handler. Note that the call to dvmCheckInst is done as a tail call. 19636 */ 19637 adrl lr, dvmAsmInstructionStart + (430 * 64) 19638 mov r0, rPC @ arg0 19639 mov r1, rSELF @ arg1 19640 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19641 19642/* ------------------------------ */ 19643 .balign 64 19644.L_ALT_OP_UNUSED_AFFF: /* 0x1af */ 19645/* File: armv5te/ALT_STUB.S */ 19646/* 19647 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19648 * any interesting requests and then jump to the real instruction 19649 * handler. Note that the call to dvmCheckInst is done as a tail call. 19650 */ 19651 adrl lr, dvmAsmInstructionStart + (431 * 64) 19652 mov r0, rPC @ arg0 19653 mov r1, rSELF @ arg1 19654 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19655 19656/* ------------------------------ */ 19657 .balign 64 19658.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */ 19659/* File: armv5te/ALT_STUB.S */ 19660/* 19661 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19662 * any interesting requests and then jump to the real instruction 19663 * handler. Note that the call to dvmCheckInst is done as a tail call. 19664 */ 19665 adrl lr, dvmAsmInstructionStart + (432 * 64) 19666 mov r0, rPC @ arg0 19667 mov r1, rSELF @ arg1 19668 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19669 19670/* ------------------------------ */ 19671 .balign 64 19672.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */ 19673/* File: armv5te/ALT_STUB.S */ 19674/* 19675 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19676 * any interesting requests and then jump to the real instruction 19677 * handler. Note that the call to dvmCheckInst is done as a tail call. 19678 */ 19679 adrl lr, dvmAsmInstructionStart + (433 * 64) 19680 mov r0, rPC @ arg0 19681 mov r1, rSELF @ arg1 19682 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19683 19684/* ------------------------------ */ 19685 .balign 64 19686.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */ 19687/* File: armv5te/ALT_STUB.S */ 19688/* 19689 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19690 * any interesting requests and then jump to the real instruction 19691 * handler. Note that the call to dvmCheckInst is done as a tail call. 19692 */ 19693 adrl lr, dvmAsmInstructionStart + (434 * 64) 19694 mov r0, rPC @ arg0 19695 mov r1, rSELF @ arg1 19696 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19697 19698/* ------------------------------ */ 19699 .balign 64 19700.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */ 19701/* File: armv5te/ALT_STUB.S */ 19702/* 19703 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19704 * any interesting requests and then jump to the real instruction 19705 * handler. Note that the call to dvmCheckInst is done as a tail call. 19706 */ 19707 adrl lr, dvmAsmInstructionStart + (435 * 64) 19708 mov r0, rPC @ arg0 19709 mov r1, rSELF @ arg1 19710 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19711 19712/* ------------------------------ */ 19713 .balign 64 19714.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */ 19715/* File: armv5te/ALT_STUB.S */ 19716/* 19717 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19718 * any interesting requests and then jump to the real instruction 19719 * handler. Note that the call to dvmCheckInst is done as a tail call. 19720 */ 19721 adrl lr, dvmAsmInstructionStart + (436 * 64) 19722 mov r0, rPC @ arg0 19723 mov r1, rSELF @ arg1 19724 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19725 19726/* ------------------------------ */ 19727 .balign 64 19728.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */ 19729/* File: armv5te/ALT_STUB.S */ 19730/* 19731 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19732 * any interesting requests and then jump to the real instruction 19733 * handler. Note that the call to dvmCheckInst is done as a tail call. 19734 */ 19735 adrl lr, dvmAsmInstructionStart + (437 * 64) 19736 mov r0, rPC @ arg0 19737 mov r1, rSELF @ arg1 19738 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19739 19740/* ------------------------------ */ 19741 .balign 64 19742.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */ 19743/* File: armv5te/ALT_STUB.S */ 19744/* 19745 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19746 * any interesting requests and then jump to the real instruction 19747 * handler. Note that the call to dvmCheckInst is done as a tail call. 19748 */ 19749 adrl lr, dvmAsmInstructionStart + (438 * 64) 19750 mov r0, rPC @ arg0 19751 mov r1, rSELF @ arg1 19752 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19753 19754/* ------------------------------ */ 19755 .balign 64 19756.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */ 19757/* File: armv5te/ALT_STUB.S */ 19758/* 19759 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19760 * any interesting requests and then jump to the real instruction 19761 * handler. Note that the call to dvmCheckInst is done as a tail call. 19762 */ 19763 adrl lr, dvmAsmInstructionStart + (439 * 64) 19764 mov r0, rPC @ arg0 19765 mov r1, rSELF @ arg1 19766 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19767 19768/* ------------------------------ */ 19769 .balign 64 19770.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */ 19771/* File: armv5te/ALT_STUB.S */ 19772/* 19773 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19774 * any interesting requests and then jump to the real instruction 19775 * handler. Note that the call to dvmCheckInst is done as a tail call. 19776 */ 19777 adrl lr, dvmAsmInstructionStart + (440 * 64) 19778 mov r0, rPC @ arg0 19779 mov r1, rSELF @ arg1 19780 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19781 19782/* ------------------------------ */ 19783 .balign 64 19784.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */ 19785/* File: armv5te/ALT_STUB.S */ 19786/* 19787 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19788 * any interesting requests and then jump to the real instruction 19789 * handler. Note that the call to dvmCheckInst is done as a tail call. 19790 */ 19791 adrl lr, dvmAsmInstructionStart + (441 * 64) 19792 mov r0, rPC @ arg0 19793 mov r1, rSELF @ arg1 19794 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19795 19796/* ------------------------------ */ 19797 .balign 64 19798.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */ 19799/* File: armv5te/ALT_STUB.S */ 19800/* 19801 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19802 * any interesting requests and then jump to the real instruction 19803 * handler. Note that the call to dvmCheckInst is done as a tail call. 19804 */ 19805 adrl lr, dvmAsmInstructionStart + (442 * 64) 19806 mov r0, rPC @ arg0 19807 mov r1, rSELF @ arg1 19808 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19809 19810/* ------------------------------ */ 19811 .balign 64 19812.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */ 19813/* File: armv5te/ALT_STUB.S */ 19814/* 19815 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19816 * any interesting requests and then jump to the real instruction 19817 * handler. Note that the call to dvmCheckInst is done as a tail call. 19818 */ 19819 adrl lr, dvmAsmInstructionStart + (443 * 64) 19820 mov r0, rPC @ arg0 19821 mov r1, rSELF @ arg1 19822 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19823 19824/* ------------------------------ */ 19825 .balign 64 19826.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */ 19827/* File: armv5te/ALT_STUB.S */ 19828/* 19829 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19830 * any interesting requests and then jump to the real instruction 19831 * handler. Note that the call to dvmCheckInst is done as a tail call. 19832 */ 19833 adrl lr, dvmAsmInstructionStart + (444 * 64) 19834 mov r0, rPC @ arg0 19835 mov r1, rSELF @ arg1 19836 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19837 19838/* ------------------------------ */ 19839 .balign 64 19840.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */ 19841/* File: armv5te/ALT_STUB.S */ 19842/* 19843 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19844 * any interesting requests and then jump to the real instruction 19845 * handler. Note that the call to dvmCheckInst is done as a tail call. 19846 */ 19847 adrl lr, dvmAsmInstructionStart + (445 * 64) 19848 mov r0, rPC @ arg0 19849 mov r1, rSELF @ arg1 19850 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19851 19852/* ------------------------------ */ 19853 .balign 64 19854.L_ALT_OP_UNUSED_BEFF: /* 0x1be */ 19855/* File: armv5te/ALT_STUB.S */ 19856/* 19857 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19858 * any interesting requests and then jump to the real instruction 19859 * handler. Note that the call to dvmCheckInst is done as a tail call. 19860 */ 19861 adrl lr, dvmAsmInstructionStart + (446 * 64) 19862 mov r0, rPC @ arg0 19863 mov r1, rSELF @ arg1 19864 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19865 19866/* ------------------------------ */ 19867 .balign 64 19868.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */ 19869/* File: armv5te/ALT_STUB.S */ 19870/* 19871 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19872 * any interesting requests and then jump to the real instruction 19873 * handler. Note that the call to dvmCheckInst is done as a tail call. 19874 */ 19875 adrl lr, dvmAsmInstructionStart + (447 * 64) 19876 mov r0, rPC @ arg0 19877 mov r1, rSELF @ arg1 19878 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19879 19880/* ------------------------------ */ 19881 .balign 64 19882.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */ 19883/* File: armv5te/ALT_STUB.S */ 19884/* 19885 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19886 * any interesting requests and then jump to the real instruction 19887 * handler. Note that the call to dvmCheckInst is done as a tail call. 19888 */ 19889 adrl lr, dvmAsmInstructionStart + (448 * 64) 19890 mov r0, rPC @ arg0 19891 mov r1, rSELF @ arg1 19892 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19893 19894/* ------------------------------ */ 19895 .balign 64 19896.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */ 19897/* File: armv5te/ALT_STUB.S */ 19898/* 19899 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19900 * any interesting requests and then jump to the real instruction 19901 * handler. Note that the call to dvmCheckInst is done as a tail call. 19902 */ 19903 adrl lr, dvmAsmInstructionStart + (449 * 64) 19904 mov r0, rPC @ arg0 19905 mov r1, rSELF @ arg1 19906 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19907 19908/* ------------------------------ */ 19909 .balign 64 19910.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */ 19911/* File: armv5te/ALT_STUB.S */ 19912/* 19913 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19914 * any interesting requests and then jump to the real instruction 19915 * handler. Note that the call to dvmCheckInst is done as a tail call. 19916 */ 19917 adrl lr, dvmAsmInstructionStart + (450 * 64) 19918 mov r0, rPC @ arg0 19919 mov r1, rSELF @ arg1 19920 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19921 19922/* ------------------------------ */ 19923 .balign 64 19924.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */ 19925/* File: armv5te/ALT_STUB.S */ 19926/* 19927 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19928 * any interesting requests and then jump to the real instruction 19929 * handler. Note that the call to dvmCheckInst is done as a tail call. 19930 */ 19931 adrl lr, dvmAsmInstructionStart + (451 * 64) 19932 mov r0, rPC @ arg0 19933 mov r1, rSELF @ arg1 19934 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19935 19936/* ------------------------------ */ 19937 .balign 64 19938.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */ 19939/* File: armv5te/ALT_STUB.S */ 19940/* 19941 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19942 * any interesting requests and then jump to the real instruction 19943 * handler. Note that the call to dvmCheckInst is done as a tail call. 19944 */ 19945 adrl lr, dvmAsmInstructionStart + (452 * 64) 19946 mov r0, rPC @ arg0 19947 mov r1, rSELF @ arg1 19948 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19949 19950/* ------------------------------ */ 19951 .balign 64 19952.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */ 19953/* File: armv5te/ALT_STUB.S */ 19954/* 19955 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19956 * any interesting requests and then jump to the real instruction 19957 * handler. Note that the call to dvmCheckInst is done as a tail call. 19958 */ 19959 adrl lr, dvmAsmInstructionStart + (453 * 64) 19960 mov r0, rPC @ arg0 19961 mov r1, rSELF @ arg1 19962 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19963 19964/* ------------------------------ */ 19965 .balign 64 19966.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */ 19967/* File: armv5te/ALT_STUB.S */ 19968/* 19969 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19970 * any interesting requests and then jump to the real instruction 19971 * handler. Note that the call to dvmCheckInst is done as a tail call. 19972 */ 19973 adrl lr, dvmAsmInstructionStart + (454 * 64) 19974 mov r0, rPC @ arg0 19975 mov r1, rSELF @ arg1 19976 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19977 19978/* ------------------------------ */ 19979 .balign 64 19980.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */ 19981/* File: armv5te/ALT_STUB.S */ 19982/* 19983 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19984 * any interesting requests and then jump to the real instruction 19985 * handler. Note that the call to dvmCheckInst is done as a tail call. 19986 */ 19987 adrl lr, dvmAsmInstructionStart + (455 * 64) 19988 mov r0, rPC @ arg0 19989 mov r1, rSELF @ arg1 19990 b dvmCheckInst @ (dPC,self) tail call to instruction checker 19991 19992/* ------------------------------ */ 19993 .balign 64 19994.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */ 19995/* File: armv5te/ALT_STUB.S */ 19996/* 19997 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 19998 * any interesting requests and then jump to the real instruction 19999 * handler. Note that the call to dvmCheckInst is done as a tail call. 20000 */ 20001 adrl lr, dvmAsmInstructionStart + (456 * 64) 20002 mov r0, rPC @ arg0 20003 mov r1, rSELF @ arg1 20004 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20005 20006/* ------------------------------ */ 20007 .balign 64 20008.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */ 20009/* File: armv5te/ALT_STUB.S */ 20010/* 20011 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20012 * any interesting requests and then jump to the real instruction 20013 * handler. Note that the call to dvmCheckInst is done as a tail call. 20014 */ 20015 adrl lr, dvmAsmInstructionStart + (457 * 64) 20016 mov r0, rPC @ arg0 20017 mov r1, rSELF @ arg1 20018 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20019 20020/* ------------------------------ */ 20021 .balign 64 20022.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */ 20023/* File: armv5te/ALT_STUB.S */ 20024/* 20025 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20026 * any interesting requests and then jump to the real instruction 20027 * handler. Note that the call to dvmCheckInst is done as a tail call. 20028 */ 20029 adrl lr, dvmAsmInstructionStart + (458 * 64) 20030 mov r0, rPC @ arg0 20031 mov r1, rSELF @ arg1 20032 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20033 20034/* ------------------------------ */ 20035 .balign 64 20036.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */ 20037/* File: armv5te/ALT_STUB.S */ 20038/* 20039 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20040 * any interesting requests and then jump to the real instruction 20041 * handler. Note that the call to dvmCheckInst is done as a tail call. 20042 */ 20043 adrl lr, dvmAsmInstructionStart + (459 * 64) 20044 mov r0, rPC @ arg0 20045 mov r1, rSELF @ arg1 20046 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20047 20048/* ------------------------------ */ 20049 .balign 64 20050.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */ 20051/* File: armv5te/ALT_STUB.S */ 20052/* 20053 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20054 * any interesting requests and then jump to the real instruction 20055 * handler. Note that the call to dvmCheckInst is done as a tail call. 20056 */ 20057 adrl lr, dvmAsmInstructionStart + (460 * 64) 20058 mov r0, rPC @ arg0 20059 mov r1, rSELF @ arg1 20060 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20061 20062/* ------------------------------ */ 20063 .balign 64 20064.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */ 20065/* File: armv5te/ALT_STUB.S */ 20066/* 20067 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20068 * any interesting requests and then jump to the real instruction 20069 * handler. Note that the call to dvmCheckInst is done as a tail call. 20070 */ 20071 adrl lr, dvmAsmInstructionStart + (461 * 64) 20072 mov r0, rPC @ arg0 20073 mov r1, rSELF @ arg1 20074 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20075 20076/* ------------------------------ */ 20077 .balign 64 20078.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */ 20079/* File: armv5te/ALT_STUB.S */ 20080/* 20081 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20082 * any interesting requests and then jump to the real instruction 20083 * handler. Note that the call to dvmCheckInst is done as a tail call. 20084 */ 20085 adrl lr, dvmAsmInstructionStart + (462 * 64) 20086 mov r0, rPC @ arg0 20087 mov r1, rSELF @ arg1 20088 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20089 20090/* ------------------------------ */ 20091 .balign 64 20092.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */ 20093/* File: armv5te/ALT_STUB.S */ 20094/* 20095 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20096 * any interesting requests and then jump to the real instruction 20097 * handler. Note that the call to dvmCheckInst is done as a tail call. 20098 */ 20099 adrl lr, dvmAsmInstructionStart + (463 * 64) 20100 mov r0, rPC @ arg0 20101 mov r1, rSELF @ arg1 20102 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20103 20104/* ------------------------------ */ 20105 .balign 64 20106.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */ 20107/* File: armv5te/ALT_STUB.S */ 20108/* 20109 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20110 * any interesting requests and then jump to the real instruction 20111 * handler. Note that the call to dvmCheckInst is done as a tail call. 20112 */ 20113 adrl lr, dvmAsmInstructionStart + (464 * 64) 20114 mov r0, rPC @ arg0 20115 mov r1, rSELF @ arg1 20116 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20117 20118/* ------------------------------ */ 20119 .balign 64 20120.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */ 20121/* File: armv5te/ALT_STUB.S */ 20122/* 20123 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20124 * any interesting requests and then jump to the real instruction 20125 * handler. Note that the call to dvmCheckInst is done as a tail call. 20126 */ 20127 adrl lr, dvmAsmInstructionStart + (465 * 64) 20128 mov r0, rPC @ arg0 20129 mov r1, rSELF @ arg1 20130 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20131 20132/* ------------------------------ */ 20133 .balign 64 20134.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */ 20135/* File: armv5te/ALT_STUB.S */ 20136/* 20137 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20138 * any interesting requests and then jump to the real instruction 20139 * handler. Note that the call to dvmCheckInst is done as a tail call. 20140 */ 20141 adrl lr, dvmAsmInstructionStart + (466 * 64) 20142 mov r0, rPC @ arg0 20143 mov r1, rSELF @ arg1 20144 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20145 20146/* ------------------------------ */ 20147 .balign 64 20148.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */ 20149/* File: armv5te/ALT_STUB.S */ 20150/* 20151 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20152 * any interesting requests and then jump to the real instruction 20153 * handler. Note that the call to dvmCheckInst is done as a tail call. 20154 */ 20155 adrl lr, dvmAsmInstructionStart + (467 * 64) 20156 mov r0, rPC @ arg0 20157 mov r1, rSELF @ arg1 20158 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20159 20160/* ------------------------------ */ 20161 .balign 64 20162.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */ 20163/* File: armv5te/ALT_STUB.S */ 20164/* 20165 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20166 * any interesting requests and then jump to the real instruction 20167 * handler. Note that the call to dvmCheckInst is done as a tail call. 20168 */ 20169 adrl lr, dvmAsmInstructionStart + (468 * 64) 20170 mov r0, rPC @ arg0 20171 mov r1, rSELF @ arg1 20172 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20173 20174/* ------------------------------ */ 20175 .balign 64 20176.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */ 20177/* File: armv5te/ALT_STUB.S */ 20178/* 20179 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20180 * any interesting requests and then jump to the real instruction 20181 * handler. Note that the call to dvmCheckInst is done as a tail call. 20182 */ 20183 adrl lr, dvmAsmInstructionStart + (469 * 64) 20184 mov r0, rPC @ arg0 20185 mov r1, rSELF @ arg1 20186 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20187 20188/* ------------------------------ */ 20189 .balign 64 20190.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */ 20191/* File: armv5te/ALT_STUB.S */ 20192/* 20193 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20194 * any interesting requests and then jump to the real instruction 20195 * handler. Note that the call to dvmCheckInst is done as a tail call. 20196 */ 20197 adrl lr, dvmAsmInstructionStart + (470 * 64) 20198 mov r0, rPC @ arg0 20199 mov r1, rSELF @ arg1 20200 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20201 20202/* ------------------------------ */ 20203 .balign 64 20204.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */ 20205/* File: armv5te/ALT_STUB.S */ 20206/* 20207 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20208 * any interesting requests and then jump to the real instruction 20209 * handler. Note that the call to dvmCheckInst is done as a tail call. 20210 */ 20211 adrl lr, dvmAsmInstructionStart + (471 * 64) 20212 mov r0, rPC @ arg0 20213 mov r1, rSELF @ arg1 20214 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20215 20216/* ------------------------------ */ 20217 .balign 64 20218.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */ 20219/* File: armv5te/ALT_STUB.S */ 20220/* 20221 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20222 * any interesting requests and then jump to the real instruction 20223 * handler. Note that the call to dvmCheckInst is done as a tail call. 20224 */ 20225 adrl lr, dvmAsmInstructionStart + (472 * 64) 20226 mov r0, rPC @ arg0 20227 mov r1, rSELF @ arg1 20228 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20229 20230/* ------------------------------ */ 20231 .balign 64 20232.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */ 20233/* File: armv5te/ALT_STUB.S */ 20234/* 20235 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20236 * any interesting requests and then jump to the real instruction 20237 * handler. Note that the call to dvmCheckInst is done as a tail call. 20238 */ 20239 adrl lr, dvmAsmInstructionStart + (473 * 64) 20240 mov r0, rPC @ arg0 20241 mov r1, rSELF @ arg1 20242 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20243 20244/* ------------------------------ */ 20245 .balign 64 20246.L_ALT_OP_UNUSED_DAFF: /* 0x1da */ 20247/* File: armv5te/ALT_STUB.S */ 20248/* 20249 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20250 * any interesting requests and then jump to the real instruction 20251 * handler. Note that the call to dvmCheckInst is done as a tail call. 20252 */ 20253 adrl lr, dvmAsmInstructionStart + (474 * 64) 20254 mov r0, rPC @ arg0 20255 mov r1, rSELF @ arg1 20256 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20257 20258/* ------------------------------ */ 20259 .balign 64 20260.L_ALT_OP_UNUSED_DBFF: /* 0x1db */ 20261/* File: armv5te/ALT_STUB.S */ 20262/* 20263 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20264 * any interesting requests and then jump to the real instruction 20265 * handler. Note that the call to dvmCheckInst is done as a tail call. 20266 */ 20267 adrl lr, dvmAsmInstructionStart + (475 * 64) 20268 mov r0, rPC @ arg0 20269 mov r1, rSELF @ arg1 20270 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20271 20272/* ------------------------------ */ 20273 .balign 64 20274.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */ 20275/* File: armv5te/ALT_STUB.S */ 20276/* 20277 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20278 * any interesting requests and then jump to the real instruction 20279 * handler. Note that the call to dvmCheckInst is done as a tail call. 20280 */ 20281 adrl lr, dvmAsmInstructionStart + (476 * 64) 20282 mov r0, rPC @ arg0 20283 mov r1, rSELF @ arg1 20284 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20285 20286/* ------------------------------ */ 20287 .balign 64 20288.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */ 20289/* File: armv5te/ALT_STUB.S */ 20290/* 20291 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20292 * any interesting requests and then jump to the real instruction 20293 * handler. Note that the call to dvmCheckInst is done as a tail call. 20294 */ 20295 adrl lr, dvmAsmInstructionStart + (477 * 64) 20296 mov r0, rPC @ arg0 20297 mov r1, rSELF @ arg1 20298 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20299 20300/* ------------------------------ */ 20301 .balign 64 20302.L_ALT_OP_UNUSED_DEFF: /* 0x1de */ 20303/* File: armv5te/ALT_STUB.S */ 20304/* 20305 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20306 * any interesting requests and then jump to the real instruction 20307 * handler. Note that the call to dvmCheckInst is done as a tail call. 20308 */ 20309 adrl lr, dvmAsmInstructionStart + (478 * 64) 20310 mov r0, rPC @ arg0 20311 mov r1, rSELF @ arg1 20312 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20313 20314/* ------------------------------ */ 20315 .balign 64 20316.L_ALT_OP_UNUSED_DFFF: /* 0x1df */ 20317/* File: armv5te/ALT_STUB.S */ 20318/* 20319 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20320 * any interesting requests and then jump to the real instruction 20321 * handler. Note that the call to dvmCheckInst is done as a tail call. 20322 */ 20323 adrl lr, dvmAsmInstructionStart + (479 * 64) 20324 mov r0, rPC @ arg0 20325 mov r1, rSELF @ arg1 20326 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20327 20328/* ------------------------------ */ 20329 .balign 64 20330.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */ 20331/* File: armv5te/ALT_STUB.S */ 20332/* 20333 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20334 * any interesting requests and then jump to the real instruction 20335 * handler. Note that the call to dvmCheckInst is done as a tail call. 20336 */ 20337 adrl lr, dvmAsmInstructionStart + (480 * 64) 20338 mov r0, rPC @ arg0 20339 mov r1, rSELF @ arg1 20340 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20341 20342/* ------------------------------ */ 20343 .balign 64 20344.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */ 20345/* File: armv5te/ALT_STUB.S */ 20346/* 20347 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20348 * any interesting requests and then jump to the real instruction 20349 * handler. Note that the call to dvmCheckInst is done as a tail call. 20350 */ 20351 adrl lr, dvmAsmInstructionStart + (481 * 64) 20352 mov r0, rPC @ arg0 20353 mov r1, rSELF @ arg1 20354 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20355 20356/* ------------------------------ */ 20357 .balign 64 20358.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */ 20359/* File: armv5te/ALT_STUB.S */ 20360/* 20361 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20362 * any interesting requests and then jump to the real instruction 20363 * handler. Note that the call to dvmCheckInst is done as a tail call. 20364 */ 20365 adrl lr, dvmAsmInstructionStart + (482 * 64) 20366 mov r0, rPC @ arg0 20367 mov r1, rSELF @ arg1 20368 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20369 20370/* ------------------------------ */ 20371 .balign 64 20372.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */ 20373/* File: armv5te/ALT_STUB.S */ 20374/* 20375 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20376 * any interesting requests and then jump to the real instruction 20377 * handler. Note that the call to dvmCheckInst is done as a tail call. 20378 */ 20379 adrl lr, dvmAsmInstructionStart + (483 * 64) 20380 mov r0, rPC @ arg0 20381 mov r1, rSELF @ arg1 20382 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20383 20384/* ------------------------------ */ 20385 .balign 64 20386.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */ 20387/* File: armv5te/ALT_STUB.S */ 20388/* 20389 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20390 * any interesting requests and then jump to the real instruction 20391 * handler. Note that the call to dvmCheckInst is done as a tail call. 20392 */ 20393 adrl lr, dvmAsmInstructionStart + (484 * 64) 20394 mov r0, rPC @ arg0 20395 mov r1, rSELF @ arg1 20396 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20397 20398/* ------------------------------ */ 20399 .balign 64 20400.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */ 20401/* File: armv5te/ALT_STUB.S */ 20402/* 20403 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20404 * any interesting requests and then jump to the real instruction 20405 * handler. Note that the call to dvmCheckInst is done as a tail call. 20406 */ 20407 adrl lr, dvmAsmInstructionStart + (485 * 64) 20408 mov r0, rPC @ arg0 20409 mov r1, rSELF @ arg1 20410 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20411 20412/* ------------------------------ */ 20413 .balign 64 20414.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */ 20415/* File: armv5te/ALT_STUB.S */ 20416/* 20417 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20418 * any interesting requests and then jump to the real instruction 20419 * handler. Note that the call to dvmCheckInst is done as a tail call. 20420 */ 20421 adrl lr, dvmAsmInstructionStart + (486 * 64) 20422 mov r0, rPC @ arg0 20423 mov r1, rSELF @ arg1 20424 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20425 20426/* ------------------------------ */ 20427 .balign 64 20428.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */ 20429/* File: armv5te/ALT_STUB.S */ 20430/* 20431 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20432 * any interesting requests and then jump to the real instruction 20433 * handler. Note that the call to dvmCheckInst is done as a tail call. 20434 */ 20435 adrl lr, dvmAsmInstructionStart + (487 * 64) 20436 mov r0, rPC @ arg0 20437 mov r1, rSELF @ arg1 20438 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20439 20440/* ------------------------------ */ 20441 .balign 64 20442.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */ 20443/* File: armv5te/ALT_STUB.S */ 20444/* 20445 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20446 * any interesting requests and then jump to the real instruction 20447 * handler. Note that the call to dvmCheckInst is done as a tail call. 20448 */ 20449 adrl lr, dvmAsmInstructionStart + (488 * 64) 20450 mov r0, rPC @ arg0 20451 mov r1, rSELF @ arg1 20452 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20453 20454/* ------------------------------ */ 20455 .balign 64 20456.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */ 20457/* File: armv5te/ALT_STUB.S */ 20458/* 20459 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20460 * any interesting requests and then jump to the real instruction 20461 * handler. Note that the call to dvmCheckInst is done as a tail call. 20462 */ 20463 adrl lr, dvmAsmInstructionStart + (489 * 64) 20464 mov r0, rPC @ arg0 20465 mov r1, rSELF @ arg1 20466 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20467 20468/* ------------------------------ */ 20469 .balign 64 20470.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */ 20471/* File: armv5te/ALT_STUB.S */ 20472/* 20473 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20474 * any interesting requests and then jump to the real instruction 20475 * handler. Note that the call to dvmCheckInst is done as a tail call. 20476 */ 20477 adrl lr, dvmAsmInstructionStart + (490 * 64) 20478 mov r0, rPC @ arg0 20479 mov r1, rSELF @ arg1 20480 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20481 20482/* ------------------------------ */ 20483 .balign 64 20484.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */ 20485/* File: armv5te/ALT_STUB.S */ 20486/* 20487 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20488 * any interesting requests and then jump to the real instruction 20489 * handler. Note that the call to dvmCheckInst is done as a tail call. 20490 */ 20491 adrl lr, dvmAsmInstructionStart + (491 * 64) 20492 mov r0, rPC @ arg0 20493 mov r1, rSELF @ arg1 20494 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20495 20496/* ------------------------------ */ 20497 .balign 64 20498.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */ 20499/* File: armv5te/ALT_STUB.S */ 20500/* 20501 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20502 * any interesting requests and then jump to the real instruction 20503 * handler. Note that the call to dvmCheckInst is done as a tail call. 20504 */ 20505 adrl lr, dvmAsmInstructionStart + (492 * 64) 20506 mov r0, rPC @ arg0 20507 mov r1, rSELF @ arg1 20508 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20509 20510/* ------------------------------ */ 20511 .balign 64 20512.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */ 20513/* File: armv5te/ALT_STUB.S */ 20514/* 20515 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20516 * any interesting requests and then jump to the real instruction 20517 * handler. Note that the call to dvmCheckInst is done as a tail call. 20518 */ 20519 adrl lr, dvmAsmInstructionStart + (493 * 64) 20520 mov r0, rPC @ arg0 20521 mov r1, rSELF @ arg1 20522 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20523 20524/* ------------------------------ */ 20525 .balign 64 20526.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */ 20527/* File: armv5te/ALT_STUB.S */ 20528/* 20529 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20530 * any interesting requests and then jump to the real instruction 20531 * handler. Note that the call to dvmCheckInst is done as a tail call. 20532 */ 20533 adrl lr, dvmAsmInstructionStart + (494 * 64) 20534 mov r0, rPC @ arg0 20535 mov r1, rSELF @ arg1 20536 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20537 20538/* ------------------------------ */ 20539 .balign 64 20540.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */ 20541/* File: armv5te/ALT_STUB.S */ 20542/* 20543 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20544 * any interesting requests and then jump to the real instruction 20545 * handler. Note that the call to dvmCheckInst is done as a tail call. 20546 */ 20547 adrl lr, dvmAsmInstructionStart + (495 * 64) 20548 mov r0, rPC @ arg0 20549 mov r1, rSELF @ arg1 20550 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20551 20552/* ------------------------------ */ 20553 .balign 64 20554.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */ 20555/* File: armv5te/ALT_STUB.S */ 20556/* 20557 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20558 * any interesting requests and then jump to the real instruction 20559 * handler. Note that the call to dvmCheckInst is done as a tail call. 20560 */ 20561 adrl lr, dvmAsmInstructionStart + (496 * 64) 20562 mov r0, rPC @ arg0 20563 mov r1, rSELF @ arg1 20564 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20565 20566/* ------------------------------ */ 20567 .balign 64 20568.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */ 20569/* File: armv5te/ALT_STUB.S */ 20570/* 20571 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20572 * any interesting requests and then jump to the real instruction 20573 * handler. Note that the call to dvmCheckInst is done as a tail call. 20574 */ 20575 adrl lr, dvmAsmInstructionStart + (497 * 64) 20576 mov r0, rPC @ arg0 20577 mov r1, rSELF @ arg1 20578 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20579 20580/* ------------------------------ */ 20581 .balign 64 20582.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */ 20583/* File: armv5te/ALT_STUB.S */ 20584/* 20585 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20586 * any interesting requests and then jump to the real instruction 20587 * handler. Note that the call to dvmCheckInst is done as a tail call. 20588 */ 20589 adrl lr, dvmAsmInstructionStart + (498 * 64) 20590 mov r0, rPC @ arg0 20591 mov r1, rSELF @ arg1 20592 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20593 20594/* ------------------------------ */ 20595 .balign 64 20596.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */ 20597/* File: armv5te/ALT_STUB.S */ 20598/* 20599 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20600 * any interesting requests and then jump to the real instruction 20601 * handler. Note that the call to dvmCheckInst is done as a tail call. 20602 */ 20603 adrl lr, dvmAsmInstructionStart + (499 * 64) 20604 mov r0, rPC @ arg0 20605 mov r1, rSELF @ arg1 20606 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20607 20608/* ------------------------------ */ 20609 .balign 64 20610.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */ 20611/* File: armv5te/ALT_STUB.S */ 20612/* 20613 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20614 * any interesting requests and then jump to the real instruction 20615 * handler. Note that the call to dvmCheckInst is done as a tail call. 20616 */ 20617 adrl lr, dvmAsmInstructionStart + (500 * 64) 20618 mov r0, rPC @ arg0 20619 mov r1, rSELF @ arg1 20620 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20621 20622/* ------------------------------ */ 20623 .balign 64 20624.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */ 20625/* File: armv5te/ALT_STUB.S */ 20626/* 20627 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20628 * any interesting requests and then jump to the real instruction 20629 * handler. Note that the call to dvmCheckInst is done as a tail call. 20630 */ 20631 adrl lr, dvmAsmInstructionStart + (501 * 64) 20632 mov r0, rPC @ arg0 20633 mov r1, rSELF @ arg1 20634 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20635 20636/* ------------------------------ */ 20637 .balign 64 20638.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */ 20639/* File: armv5te/ALT_STUB.S */ 20640/* 20641 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20642 * any interesting requests and then jump to the real instruction 20643 * handler. Note that the call to dvmCheckInst is done as a tail call. 20644 */ 20645 adrl lr, dvmAsmInstructionStart + (502 * 64) 20646 mov r0, rPC @ arg0 20647 mov r1, rSELF @ arg1 20648 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20649 20650/* ------------------------------ */ 20651 .balign 64 20652.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */ 20653/* File: armv5te/ALT_STUB.S */ 20654/* 20655 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20656 * any interesting requests and then jump to the real instruction 20657 * handler. Note that the call to dvmCheckInst is done as a tail call. 20658 */ 20659 adrl lr, dvmAsmInstructionStart + (503 * 64) 20660 mov r0, rPC @ arg0 20661 mov r1, rSELF @ arg1 20662 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20663 20664/* ------------------------------ */ 20665 .balign 64 20666.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */ 20667/* File: armv5te/ALT_STUB.S */ 20668/* 20669 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20670 * any interesting requests and then jump to the real instruction 20671 * handler. Note that the call to dvmCheckInst is done as a tail call. 20672 */ 20673 adrl lr, dvmAsmInstructionStart + (504 * 64) 20674 mov r0, rPC @ arg0 20675 mov r1, rSELF @ arg1 20676 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20677 20678/* ------------------------------ */ 20679 .balign 64 20680.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */ 20681/* File: armv5te/ALT_STUB.S */ 20682/* 20683 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20684 * any interesting requests and then jump to the real instruction 20685 * handler. Note that the call to dvmCheckInst is done as a tail call. 20686 */ 20687 adrl lr, dvmAsmInstructionStart + (505 * 64) 20688 mov r0, rPC @ arg0 20689 mov r1, rSELF @ arg1 20690 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20691 20692/* ------------------------------ */ 20693 .balign 64 20694.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */ 20695/* File: armv5te/ALT_STUB.S */ 20696/* 20697 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20698 * any interesting requests and then jump to the real instruction 20699 * handler. Note that the call to dvmCheckInst is done as a tail call. 20700 */ 20701 adrl lr, dvmAsmInstructionStart + (506 * 64) 20702 mov r0, rPC @ arg0 20703 mov r1, rSELF @ arg1 20704 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20705 20706/* ------------------------------ */ 20707 .balign 64 20708.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */ 20709/* File: armv5te/ALT_STUB.S */ 20710/* 20711 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20712 * any interesting requests and then jump to the real instruction 20713 * handler. Note that the call to dvmCheckInst is done as a tail call. 20714 */ 20715 adrl lr, dvmAsmInstructionStart + (507 * 64) 20716 mov r0, rPC @ arg0 20717 mov r1, rSELF @ arg1 20718 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20719 20720/* ------------------------------ */ 20721 .balign 64 20722.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */ 20723/* File: armv5te/ALT_STUB.S */ 20724/* 20725 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20726 * any interesting requests and then jump to the real instruction 20727 * handler. Note that the call to dvmCheckInst is done as a tail call. 20728 */ 20729 adrl lr, dvmAsmInstructionStart + (508 * 64) 20730 mov r0, rPC @ arg0 20731 mov r1, rSELF @ arg1 20732 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20733 20734/* ------------------------------ */ 20735 .balign 64 20736.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */ 20737/* File: armv5te/ALT_STUB.S */ 20738/* 20739 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20740 * any interesting requests and then jump to the real instruction 20741 * handler. Note that the call to dvmCheckInst is done as a tail call. 20742 */ 20743 adrl lr, dvmAsmInstructionStart + (509 * 64) 20744 mov r0, rPC @ arg0 20745 mov r1, rSELF @ arg1 20746 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20747 20748/* ------------------------------ */ 20749 .balign 64 20750.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */ 20751/* File: armv5te/ALT_STUB.S */ 20752/* 20753 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20754 * any interesting requests and then jump to the real instruction 20755 * handler. Note that the call to dvmCheckInst is done as a tail call. 20756 */ 20757 adrl lr, dvmAsmInstructionStart + (510 * 64) 20758 mov r0, rPC @ arg0 20759 mov r1, rSELF @ arg1 20760 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20761 20762/* ------------------------------ */ 20763 .balign 64 20764.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 20765/* File: armv5te/ALT_STUB.S */ 20766/* 20767 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle 20768 * any interesting requests and then jump to the real instruction 20769 * handler. Note that the call to dvmCheckInst is done as a tail call. 20770 */ 20771 adrl lr, dvmAsmInstructionStart + (511 * 64) 20772 mov r0, rPC @ arg0 20773 mov r1, rSELF @ arg1 20774 b dvmCheckInst @ (dPC,self) tail call to instruction checker 20775 20776 .balign 64 20777 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 20778 .global dvmAsmAltInstructionEnd 20779dvmAsmAltInstructionEnd: 20780/* File: armv5te/footer.S */ 20781 20782/* 20783 * =========================================================================== 20784 * Common subroutines and data 20785 * =========================================================================== 20786 */ 20787 20788 20789 20790 .text 20791 .align 2 20792 20793#if defined(WITH_JIT) 20794#if defined(WITH_SELF_VERIFICATION) 20795 .global dvmJitToInterpPunt 20796dvmJitToInterpPunt: 20797 mov r2,#kSVSPunt @ r2<- interpreter entry point 20798 mov r3, #0 20799 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20800 b jitSVShadowRunEnd @ doesn't return 20801 20802 .global dvmJitToInterpSingleStep 20803dvmJitToInterpSingleStep: 20804 str lr,[rSELF,#offThread_jitResumeNPC] 20805 str r1,[rSELF,#offThread_jitResumeDPC] 20806 mov r2,#kSVSSingleStep @ r2<- interpreter entry point 20807 b jitSVShadowRunEnd @ doesn't return 20808 20809 .global dvmJitToInterpNoChainNoProfile 20810dvmJitToInterpNoChainNoProfile: 20811 mov r0,rPC @ pass our target PC 20812 mov r2,#kSVSNoProfile @ r2<- interpreter entry point 20813 mov r3, #0 @ 0 means !inJitCodeCache 20814 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 20815 b jitSVShadowRunEnd @ doesn't return 20816 20817 .global dvmJitToInterpTraceSelectNoChain 20818dvmJitToInterpTraceSelectNoChain: 20819 mov r0,rPC @ pass our target PC 20820 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20821 mov r3, #0 @ 0 means !inJitCodeCache 20822 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20823 b jitSVShadowRunEnd @ doesn't return 20824 20825 .global dvmJitToInterpTraceSelect 20826dvmJitToInterpTraceSelect: 20827 ldr r0,[lr, #-1] @ pass our target PC 20828 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 20829 mov r3, #0 @ 0 means !inJitCodeCache 20830 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20831 b jitSVShadowRunEnd @ doesn't return 20832 20833 .global dvmJitToInterpBackwardBranch 20834dvmJitToInterpBackwardBranch: 20835 ldr r0,[lr, #-1] @ pass our target PC 20836 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 20837 mov r3, #0 @ 0 means !inJitCodeCache 20838 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20839 b jitSVShadowRunEnd @ doesn't return 20840 20841 .global dvmJitToInterpNormal 20842dvmJitToInterpNormal: 20843 ldr r0,[lr, #-1] @ pass our target PC 20844 mov r2,#kSVSNormal @ r2<- interpreter entry point 20845 mov r3, #0 @ 0 means !inJitCodeCache 20846 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20847 b jitSVShadowRunEnd @ doesn't return 20848 20849 .global dvmJitToInterpNoChain 20850dvmJitToInterpNoChain: 20851 mov r0,rPC @ pass our target PC 20852 mov r2,#kSVSNoChain @ r2<- interpreter entry point 20853 mov r3, #0 @ 0 means !inJitCodeCache 20854 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20855 b jitSVShadowRunEnd @ doesn't return 20856#else 20857/* 20858 * Return from the translation cache to the interpreter when the compiler is 20859 * having issues translating/executing a Dalvik instruction. We have to skip 20860 * the code cache lookup otherwise it is possible to indefinitely bouce 20861 * between the interpreter and the code cache if the instruction that fails 20862 * to be compiled happens to be at a trace start. 20863 */ 20864 .global dvmJitToInterpPunt 20865dvmJitToInterpPunt: 20866 mov rPC, r0 20867#if defined(WITH_JIT_TUNING) 20868 mov r0,lr 20869 bl dvmBumpPunt; 20870#endif 20871 EXPORT_PC() 20872 mov r0, #0 20873 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 20874 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20875 FETCH_INST() 20876 GET_INST_OPCODE(ip) 20877 GOTO_OPCODE(ip) 20878 20879/* 20880 * Return to the interpreter to handle a single instruction. 20881 * On entry: 20882 * r0 <= PC 20883 * r1 <= PC of resume instruction 20884 * lr <= resume point in translation 20885 */ 20886 .global dvmJitToInterpSingleStep 20887dvmJitToInterpSingleStep: 20888 str lr,[rSELF,#offThread_jitResumeNPC] 20889 str r1,[rSELF,#offThread_jitResumeDPC] 20890 mov r1,#kInterpEntryInstr 20891 @ enum is 4 byte in aapcs-EABI 20892 str r1, [rSELF, #offThread_entryPoint] 20893 mov rPC,r0 20894 EXPORT_PC() 20895 20896 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20897 mov r2,#kJitSingleStep @ Ask for single step and then revert 20898 str r2,[rSELF,#offThread_jitState] 20899 mov r1,#1 @ set changeInterp to bail to debug interp 20900 b common_gotoBail 20901 20902/* 20903 * Return from the translation cache and immediately request 20904 * a translation for the exit target. Commonly used for callees. 20905 */ 20906 .global dvmJitToInterpTraceSelectNoChain 20907dvmJitToInterpTraceSelectNoChain: 20908#if defined(WITH_JIT_TUNING) 20909 bl dvmBumpNoChain 20910#endif 20911 mov r0,rPC 20912 bl dvmJitGetTraceAddr @ Is there a translation? 20913 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20914 mov r1, rPC @ arg1 of translation may need this 20915 mov lr, #0 @ in case target is HANDLER_INTERPRET 20916 cmp r0,#0 @ !0 means translation exists 20917 bxne r0 @ continue native execution if so 20918 b 2f @ branch over to use the interpreter 20919 20920/* 20921 * Return from the translation cache and immediately request 20922 * a translation for the exit target. Commonly used following 20923 * invokes. 20924 */ 20925 .global dvmJitToInterpTraceSelect 20926dvmJitToInterpTraceSelect: 20927 ldr rPC,[lr, #-1] @ get our target PC 20928 add rINST,lr,#-5 @ save start of chain branch 20929 add rINST, #-4 @ .. which is 9 bytes back 20930 mov r0,rPC 20931 bl dvmJitGetTraceAddr @ Is there a translation? 20932 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20933 cmp r0,#0 20934 beq 2f 20935 mov r1,rINST 20936 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20937 mov r1, rPC @ arg1 of translation may need this 20938 mov lr, #0 @ in case target is HANDLER_INTERPRET 20939 cmp r0,#0 @ successful chain? 20940 bxne r0 @ continue native execution 20941 b toInterpreter @ didn't chain - resume with interpreter 20942 20943/* No translation, so request one if profiling isn't disabled*/ 209442: 20945 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20946 GET_JIT_PROF_TABLE(r0) 20947 FETCH_INST() 20948 cmp r0, #0 20949 movne r2,#kJitTSelectRequestHot @ ask for trace selection 20950 bne common_selectTrace 20951 GET_INST_OPCODE(ip) 20952 GOTO_OPCODE(ip) 20953 20954/* 20955 * Return from the translation cache to the interpreter. 20956 * The return was done with a BLX from thumb mode, and 20957 * the following 32-bit word contains the target rPC value. 20958 * Note that lr (r14) will have its low-order bit set to denote 20959 * its thumb-mode origin. 20960 * 20961 * We'll need to stash our lr origin away, recover the new 20962 * target and then check to see if there is a translation available 20963 * for our new target. If so, we do a translation chain and 20964 * go back to native execution. Otherwise, it's back to the 20965 * interpreter (after treating this entry as a potential 20966 * trace start). 20967 */ 20968 .global dvmJitToInterpNormal 20969dvmJitToInterpNormal: 20970 ldr rPC,[lr, #-1] @ get our target PC 20971 add rINST,lr,#-5 @ save start of chain branch 20972 add rINST,#-4 @ .. which is 9 bytes back 20973#if defined(WITH_JIT_TUNING) 20974 bl dvmBumpNormal 20975#endif 20976 mov r0,rPC 20977 bl dvmJitGetTraceAddr @ Is there a translation? 20978 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 20979 cmp r0,#0 20980 beq toInterpreter @ go if not, otherwise do chain 20981 mov r1,rINST 20982 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 20983 mov r1, rPC @ arg1 of translation may need this 20984 mov lr, #0 @ in case target is HANDLER_INTERPRET 20985 cmp r0,#0 @ successful chain? 20986 bxne r0 @ continue native execution 20987 b toInterpreter @ didn't chain - resume with interpreter 20988 20989/* 20990 * Return from the translation cache to the interpreter to do method invocation. 20991 * Check if translation exists for the callee, but don't chain to it. 20992 */ 20993 .global dvmJitToInterpNoChainNoProfile 20994dvmJitToInterpNoChainNoProfile: 20995#if defined(WITH_JIT_TUNING) 20996 bl dvmBumpNoChain 20997#endif 20998 mov r0,rPC 20999 bl dvmJitGetTraceAddr @ Is there a translation? 21000 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21001 mov r1, rPC @ arg1 of translation may need this 21002 mov lr, #0 @ in case target is HANDLER_INTERPRET 21003 cmp r0,#0 21004 bxne r0 @ continue native execution if so 21005 EXPORT_PC() 21006 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21007 FETCH_INST() 21008 GET_INST_OPCODE(ip) @ extract opcode from rINST 21009 GOTO_OPCODE(ip) @ jump to next instruction 21010 21011/* 21012 * Return from the translation cache to the interpreter to do method invocation. 21013 * Check if translation exists for the callee, but don't chain to it. 21014 */ 21015 .global dvmJitToInterpNoChain 21016dvmJitToInterpNoChain: 21017#if defined(WITH_JIT_TUNING) 21018 bl dvmBumpNoChain 21019#endif 21020 mov r0,rPC 21021 bl dvmJitGetTraceAddr @ Is there a translation? 21022 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21023 mov r1, rPC @ arg1 of translation may need this 21024 mov lr, #0 @ in case target is HANDLER_INTERPRET 21025 cmp r0,#0 21026 bxne r0 @ continue native execution if so 21027#endif 21028 21029/* 21030 * No translation, restore interpreter regs and start interpreting. 21031 * rSELF & rFP were preserved in the translated code, and rPC has 21032 * already been restored by the time we get here. We'll need to set 21033 * up rIBASE & rINST, and load the address of the JitTable into r0. 21034 */ 21035toInterpreter: 21036 EXPORT_PC() 21037 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21038 FETCH_INST() 21039 GET_JIT_PROF_TABLE(r0) 21040 @ NOTE: intended fallthrough 21041 21042/* 21043 * Common code to update potential trace start counter, and initiate 21044 * a trace-build if appropriate. On entry, rPC should point to the 21045 * next instruction to execute, and rINST should be already loaded with 21046 * the next opcode word, and r0 holds a pointer to the jit profile 21047 * table (pJitProfTable). 21048 */ 21049common_testUpdateProfile: 21050 cmp r0,#0 21051 GET_INST_OPCODE(ip) 21052 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 21053 21054common_updateProfile: 21055 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 21056 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 21057 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 21058 GET_INST_OPCODE(ip) 21059 subs r1,r1,#1 @ decrement counter 21060 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 21061 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 21062 21063/* 21064 * Here, we switch to the debug interpreter to request 21065 * trace selection. First, though, check to see if there 21066 * is already a native translation in place (and, if so, 21067 * jump to it now). 21068 */ 21069 21070 GET_JIT_THRESHOLD(r1) 21071 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 21072 EXPORT_PC() 21073 mov r0,rPC 21074 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC) 21075 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 21076 mov r1, rPC @ arg1 of translation may need this 21077 mov lr, #0 @ in case target is HANDLER_INTERPRET 21078 cmp r0,#0 21079#if !defined(WITH_SELF_VERIFICATION) 21080 bxne r0 @ jump to the translation 21081 mov r2,#kJitTSelectRequest @ ask for trace selection 21082 @ fall-through to common_selectTrace 21083#else 21084 moveq r2,#kJitTSelectRequest @ ask for trace selection 21085 beq common_selectTrace 21086 /* 21087 * At this point, we have a target translation. However, if 21088 * that translation is actually the interpret-only pseudo-translation 21089 * we want to treat it the same as no translation. 21090 */ 21091 mov r10, r0 @ save target 21092 bl dvmCompilerGetInterpretTemplate 21093 cmp r0, r10 @ special case? 21094 bne jitSVShadowRunStart @ set up self verification shadow space 21095 @ Need to clear the inJitCodeCache flag 21096 mov r3, #0 @ 0 means not in the JIT code cache 21097 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 21098 GET_INST_OPCODE(ip) 21099 GOTO_OPCODE(ip) 21100 /* no return */ 21101#endif 21102 21103/* 21104 * On entry: 21105 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 21106 */ 21107common_selectTrace: 21108 21109 str r2,[rSELF,#offThread_jitState] 21110 mov r2,#kInterpEntryInstr @ normal entry reason 21111 str r2,[rSELF,#offThread_entryPoint] 21112 mov r1,#1 @ set changeInterp 21113 b common_gotoBail 21114 21115#if defined(WITH_SELF_VERIFICATION) 21116/* 21117 * Save PC and registers to shadow memory for self verification mode 21118 * before jumping to native translation. 21119 * On entry: 21120 * rPC, rFP, rSELF: the values that they should contain 21121 * r10: the address of the target translation. 21122 */ 21123jitSVShadowRunStart: 21124 mov r0,rPC @ r0<- program counter 21125 mov r1,rFP @ r1<- frame pointer 21126 mov r2,rSELF @ r2<- self (Thread) pointer 21127 mov r3,r10 @ r3<- target translation 21128 bl dvmSelfVerificationSaveState @ save registers to shadow space 21129 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 21130 bx r10 @ jump to the translation 21131 21132/* 21133 * Restore PC, registers, and interpreter state to original values 21134 * before jumping back to the interpreter. 21135 */ 21136jitSVShadowRunEnd: 21137 mov r1,rFP @ pass ending fp 21138 mov r3,rSELF @ pass self ptr for convenience 21139 bl dvmSelfVerificationRestoreState @ restore pc and fp values 21140 ldr rPC,[rSELF,#offThread_pc] @ restore PC 21141 ldr rFP,[rSELF,#offThread_fp] @ restore FP 21142 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 21143 cmp r1,#0 @ check for punt condition 21144 beq 1f 21145 mov r2,#kJitSelfVerification @ ask for self verification 21146 str r2,[rSELF,#offThread_jitState] 21147 mov r2,#kInterpEntryInstr @ normal entry reason 21148 str r2,[rSELF,#offThread_entryPoint] 21149 mov r1,#1 @ set changeInterp 21150 b common_gotoBail 21151 211521: @ exit to interpreter without check 21153 EXPORT_PC() 21154 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21155 FETCH_INST() 21156 GET_INST_OPCODE(ip) 21157 GOTO_OPCODE(ip) 21158#endif 21159 21160#endif 21161 21162/* 21163 * Common code when a backward branch is taken. 21164 * 21165 * TODO: we could avoid a branch by just setting r0 and falling through 21166 * into the common_periodicChecks code, and having a test on r0 at the 21167 * end determine if we should return to the caller or update & branch to 21168 * the next instr. 21169 * 21170 * On entry: 21171 * r9 is PC adjustment *in bytes* 21172 */ 21173common_backwardBranch: 21174 mov r0, #kInterpEntryInstr 21175 bl common_periodicChecks 21176#if defined(WITH_JIT) 21177 GET_JIT_PROF_TABLE(r0) 21178 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 21179 cmp r0,#0 21180 bne common_updateProfile 21181 GET_INST_OPCODE(ip) 21182 GOTO_OPCODE(ip) 21183#else 21184 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 21185 GET_INST_OPCODE(ip) @ extract opcode from rINST 21186 GOTO_OPCODE(ip) @ jump to next instruction 21187#endif 21188 21189 21190/* 21191 * Need to see if the thread needs to be suspended or debugger/profiler 21192 * activity has begun. If so, we suspend the thread or side-exit to 21193 * the debug interpreter as appropriate. 21194 * 21195 * The common case is no activity on any of these, so we want to figure 21196 * that out quickly. If something is up, we can then sort out what. 21197 * 21198 * We want to be fast if the VM was built without debugger or profiler 21199 * support, but we also need to recognize that the system is usually 21200 * shipped with both of these enabled. 21201 * 21202 * TODO: reduce this so we're just checking a single location. 21203 * 21204 * On entry: 21205 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 21206 * r9 is trampoline PC adjustment *in bytes* 21207 */ 21208common_periodicChecks: 21209/* TUNING - make this a direct load when interpBreak moved to Thread */ 21210 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak 21211 /* speculatively thread-specific suspend count */ 21212 ldr ip, [rSELF, #offThread_suspendCount] 21213 ldr r1, [r1] @ r1<- interpBreak 21214 cmp r1, #0 @ anything unusual? 21215 bxeq lr @ return if not 21216 /* 21217 * One or more interesting events have happened. Figure out what. 21218 * 21219 * r0 still holds the reentry type. 21220 */ 21221 cmp ip, #0 @ want suspend? 21222 beq 3f @ no, must be something else 21223 21224 stmfd sp!, {r0, lr} @ preserve r0 and lr 21225#if defined(WITH_JIT) 21226 /* 21227 * Refresh the Jit's cached copy of profile table pointer. This pointer 21228 * doubles as the Jit's on/off switch. 21229 */ 21230 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 21231 mov r0, rSELF @ r0<- self 21232 ldr r3, [r3] @ r3 <- pJitProfTable 21233 EXPORT_PC() @ need for precise GC 21234 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch 21235#else 21236 mov r0, rSELF @ r0<- self 21237 EXPORT_PC() @ need for precise GC 21238#endif 21239 bl dvmCheckSuspendPending @ do full check, suspend if necessary 21240 ldmfd sp!, {r0, lr} @ restore r0 and lr 21241 21242 /* 21243 * Reload the interpBreak flags - they may have changed while we 21244 * were suspended. 21245 */ 21246/* TUNING - direct load when InterpBreak moved to Thread */ 21247 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak 21248 ldr r1, [r1] @ r1<- interpBreak 212493: 21250 /* 21251 * TODO: this code is too fragile. Need a general mechanism 21252 * to identify what actions to take by submode. Some profiling modes 21253 * (instruction count) need to single-step, while method tracing 21254 * may not. Debugging with breakpoints can run unfettered, but 21255 * source-level single-stepping requires Dalvik singlestepping. 21256 * GC may require a one-shot action and then full-speed resumption. 21257 */ 21258 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting) 21259 bxeq lr @ nothing to do, return 21260 21261 @ debugger/profiler enabled, bail out; self->entryPoint was set above 21262 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof 21263 add rPC, rPC, r9 @ update rPC 21264 mov r1, #1 @ "want switch" = true 21265 b common_gotoBail @ side exit 21266 21267 21268/* 21269 * The equivalent of "goto bail", this calls through the "bail handler". 21270 * 21271 * State registers will be saved to the "thread" area before bailing. 21272 * 21273 * On entry: 21274 * r1 is "bool changeInterp", indicating if we want to switch to the 21275 * other interpreter or just bail all the way out 21276 */ 21277common_gotoBail: 21278 SAVE_PC_FP_TO_SELF() @ export state to "thread" 21279 mov r0, rSELF @ r0<- self ptr 21280 b dvmMterpStdBail @ call(self, changeInterp) 21281 21282 @add r1, r1, #1 @ using (boolean+1) 21283 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf 21284 @bl _longjmp @ does not return 21285 @bl common_abort 21286 21287 21288/* 21289 * Common code for jumbo method invocation. 21290 * NOTE: this adjusts rPC to account for the difference in instruction width. 21291 * As a result, the savedPc in the stack frame will not be wholly accurate. So 21292 * long as that is only used for source file line number calculations, we're 21293 * okay. 21294 * 21295 * On entry: 21296 * r0 is "Method* methodToCall", the method we're trying to call 21297 */ 21298common_invokeMethodJumbo: 21299.LinvokeNewJumbo: 21300 @ prepare to copy args to "outs" area of current frame 21301 add rPC, rPC, #4 @ adjust pc to make return consistent 21302 FETCH(r2, 1) @ r2<- BBBB (arg count) 21303 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21304 cmp r2, #0 @ no args? 21305 beq .LinvokeArgsDone @ if no args, skip the rest 21306 FETCH(r1, 2) @ r1<- CCCC 21307 b .LinvokeRangeArgs @ handle args like invoke range 21308 21309/* 21310 * Common code for method invocation with range. 21311 * 21312 * On entry: 21313 * r0 is "Method* methodToCall", the method we're trying to call 21314 */ 21315common_invokeMethodRange: 21316.LinvokeNewRange: 21317 @ prepare to copy args to "outs" area of current frame 21318 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 21319 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21320 beq .LinvokeArgsDone @ if no args, skip the rest 21321 FETCH(r1, 2) @ r1<- CCCC 21322 21323.LinvokeRangeArgs: 21324 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 21325 @ (very few methods have > 10 args; could unroll for common cases) 21326 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 21327 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 213281: ldr r1, [r3], #4 @ val = *fp++ 21329 subs r2, r2, #1 @ count-- 21330 str r1, [r10], #4 @ *outs++ = val 21331 bne 1b @ ...while count != 0 21332 b .LinvokeArgsDone 21333 21334/* 21335 * Common code for method invocation without range. 21336 * 21337 * On entry: 21338 * r0 is "Method* methodToCall", the method we're trying to call 21339 */ 21340common_invokeMethodNoRange: 21341.LinvokeNewNoRange: 21342 @ prepare to copy args to "outs" area of current frame 21343 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 21344 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 21345 FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 21346 beq .LinvokeArgsDone 21347 21348 @ r0=methodToCall, r1=GFED, r2=count, r10=outs 21349.LinvokeNonRange: 21350 rsb r2, r2, #5 @ r2<- 5-r2 21351 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 21352 bl common_abort @ (skipped due to ARM prefetch) 213535: and ip, rINST, #0x0f00 @ isolate A 21354 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 21355 mov r0, r0 @ nop 21356 str r2, [r10, #-4]! @ *--outs = vA 213574: and ip, r1, #0xf000 @ isolate G 21358 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 21359 mov r0, r0 @ nop 21360 str r2, [r10, #-4]! @ *--outs = vG 213613: and ip, r1, #0x0f00 @ isolate F 21362 ldr r2, [rFP, ip, lsr #6] @ r2<- vF 21363 mov r0, r0 @ nop 21364 str r2, [r10, #-4]! @ *--outs = vF 213652: and ip, r1, #0x00f0 @ isolate E 21366 ldr r2, [rFP, ip, lsr #2] @ r2<- vE 21367 mov r0, r0 @ nop 21368 str r2, [r10, #-4]! @ *--outs = vE 213691: and ip, r1, #0x000f @ isolate D 21370 ldr r2, [rFP, ip, lsl #2] @ r2<- vD 21371 mov r0, r0 @ nop 21372 str r2, [r10, #-4]! @ *--outs = vD 213730: @ fall through to .LinvokeArgsDone 21374 21375.LinvokeArgsDone: @ r0=methodToCall 21376 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 21377 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 21378 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 21379 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 21380 @ find space for the new stack frame, check for overflow 21381 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 21382 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 21383 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 21384@ bl common_dumpRegs 21385 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd 21386 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 21387 cmp r3, r9 @ bottom < interpStackEnd? 21388 ldr lr, [rSELF, #offThread_pInterpBreak] 21389 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 21390 blo .LstackOverflow @ yes, this frame will overflow stack 21391 21392 @ set up newSaveArea 21393 ldr lr, [lr] @ lr<- active submodes 21394#ifdef EASY_GDB 21395 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 21396 str ip, [r10, #offStackSaveArea_prevSave] 21397#endif 21398 str rFP, [r10, #offStackSaveArea_prevFrame] 21399 str rPC, [r10, #offStackSaveArea_savedPc] 21400#if defined(WITH_JIT) 21401 mov r9, #0 21402 str r9, [r10, #offStackSaveArea_returnAddr] 21403#endif 21404 ands lr, #kSubModeMethodTrace @ method tracing? 21405 beq 1f @ skip if not 21406 stmfd sp!, {r0-r3} @ preserve r0-r3 21407 mov r1, r6 21408 @ r0=methodToCall, r1=rSELF 21409 bl dvmFastMethodTraceEnter 21410 ldmfd sp!, {r0-r3} @ restore r0-r3 214111: 21412 str r0, [r10, #offStackSaveArea_method] 21413 tst r3, #ACC_NATIVE 21414 bne .LinvokeNative 21415 21416 /* 21417 stmfd sp!, {r0-r3} 21418 bl common_printNewline 21419 mov r0, rFP 21420 mov r1, #0 21421 bl dvmDumpFp 21422 ldmfd sp!, {r0-r3} 21423 stmfd sp!, {r0-r3} 21424 mov r0, r1 21425 mov r1, r10 21426 bl dvmDumpFp 21427 bl common_printNewline 21428 ldmfd sp!, {r0-r3} 21429 */ 21430 21431 ldrh r9, [r2] @ r9 <- load INST from new PC 21432 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 21433 mov rPC, r2 @ publish new rPC 21434 21435 @ Update state values for the new method 21436 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST 21437 str r0, [rSELF, #offThread_method] @ self->method = methodToCall 21438 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ... 21439#if defined(WITH_JIT) 21440 GET_JIT_PROF_TABLE(r0) 21441 mov rFP, r1 @ fp = newFp 21442 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 21443 mov rINST, r9 @ publish new rINST 21444 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21445 cmp r0,#0 21446 bne common_updateProfile 21447 GOTO_OPCODE(ip) @ jump to next instruction 21448#else 21449 mov rFP, r1 @ fp = newFp 21450 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 21451 mov rINST, r9 @ publish new rINST 21452 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21453 GOTO_OPCODE(ip) @ jump to next instruction 21454#endif 21455 21456.LinvokeNative: 21457 @ Prep for the native call 21458 @ r0=methodToCall, r1=newFp, r10=newSaveArea 21459 ldr lr, [rSELF, #offThread_pInterpBreak] 21460 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->... 21461 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp 21462 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 21463 ldr lr, [lr] @ lr<- active submodes 21464 21465 mov r2, r0 @ r2<- methodToCall 21466 mov r0, r1 @ r0<- newFp (points to args) 21467 add r1, rSELF, #offThread_retval @ r1<- &retval 21468 mov r3, rSELF @ arg3<- self 21469 21470#ifdef ASSIST_DEBUGGER 21471 /* insert fake function header to help gdb find the stack frame */ 21472 b .Lskip 21473 .type dalvik_mterp, %function 21474dalvik_mterp: 21475 .fnstart 21476 MTERP_ENTRY1 21477 MTERP_ENTRY2 21478.Lskip: 21479#endif 21480 21481 ands lr, #kSubModeMethodTrace @ method tracing? 21482 beq 110f @ hop if not 21483 @ r2=JNIMethod, r6=rSELF 21484 stmfd sp!, {r2,r6} 21485 21486 mov lr, pc @ set return addr 21487 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21488 21489 @ r0=JNIMethod, r1=rSELF 21490 ldmfd sp!, {r0-r1} 21491 bl dvmFastNativeMethodTraceExit 21492 b 220f 21493110: 21494 mov lr, pc @ set return addr 21495 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 21496220: 21497#if defined(WITH_JIT) 21498 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status 21499#endif 21500 21501 @ native return; r10=newSaveArea 21502 @ equivalent to dvmPopJniLocals 21503 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 21504 ldr r1, [rSELF, #offThread_exception] @ check for exception 21505#if defined(WITH_JIT) 21506 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 21507#endif 21508 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21509 cmp r1, #0 @ null? 21510 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top 21511#if defined(WITH_JIT) 21512 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch 21513#endif 21514 bne common_exceptionThrown @ no, handle exception 21515 21516 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 21517 GET_INST_OPCODE(ip) @ extract opcode from rINST 21518 GOTO_OPCODE(ip) @ jump to next instruction 21519 21520.LstackOverflow: @ r0=methodToCall 21521 mov r1, r0 @ r1<- methodToCall 21522 mov r0, rSELF @ r0<- self 21523 bl dvmHandleStackOverflow 21524 b common_exceptionThrown 21525#ifdef ASSIST_DEBUGGER 21526 .fnend 21527 .size dalvik_mterp, .-dalvik_mterp 21528#endif 21529 21530 21531 /* 21532 * Common code for method invocation, calling through "glue code". 21533 * 21534 * TODO: now that we have range and non-range invoke handlers, this 21535 * needs to be split into two. Maybe just create entry points 21536 * that set r9 and jump here? 21537 * 21538 * On entry: 21539 * r0 is "Method* methodToCall", the method we're trying to call 21540 * r9 is "bool methodCallRange", indicating if this is a /range variant 21541 */ 21542 .if 0 21543.LinvokeOld: 21544 sub sp, sp, #8 @ space for args + pad 21545 FETCH(ip, 2) @ ip<- FEDC or CCCC 21546 mov r2, r0 @ A2<- methodToCall 21547 mov r0, rSELF @ A0<- self 21548 SAVE_PC_FP_TO_SELF() @ export state to "self" 21549 mov r1, r9 @ A1<- methodCallRange 21550 mov r3, rINST, lsr #8 @ A3<- AA 21551 str ip, [sp, #0] @ A4<- ip 21552 bl dvmMterp_invokeMethod @ call the C invokeMethod 21553 add sp, sp, #8 @ remove arg area 21554 b common_resumeAfterGlueCall @ continue to next instruction 21555 .endif 21556 21557 21558 21559/* 21560 * Common code for handling a return instruction. 21561 * 21562 * This does not return. 21563 */ 21564common_returnFromMethod: 21565.LreturnNew: 21566 mov r0, #kInterpEntryReturn 21567 mov r9, #0 21568 bl common_periodicChecks 21569 21570 ldr lr, [rSELF, #offThread_pInterpBreak] 21571 SAVEAREA_FROM_FP(r0, rFP) 21572 ldr lr, [lr] @ lr<- active submodes 21573 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 21574 ands lr, #kSubModeMethodTrace @ method tracing? 21575 beq 333f 21576 stmfd sp!, {r0-r3} @ preserve r0-r3 21577 mov r0, r6 21578 @ r0=rSELF 21579 bl dvmFastJavaMethodTraceExit 21580 ldmfd sp!, {r0-r3} @ restore r0-r3 21581333: 21582 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 21583 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 21584 @ r2<- method we're returning to 21585 cmp r2, #0 @ is this a break frame? 21586#if defined(WORKAROUND_CORTEX_A9_745320) 21587 /* Don't use conditional loads if the HW defect exists */ 21588 beq 101f 21589 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21590101: 21591#else 21592 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 21593#endif 21594 mov r1, #0 @ "want switch" = false 21595 beq common_gotoBail @ break frame, bail out completely 21596 21597 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 21598 str r2, [rSELF, #offThread_method]@ self->method = newSave->method 21599 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 21600 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp 21601#if defined(WITH_JIT) 21602 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 21603 mov rPC, r9 @ publish new rPC 21604 str r1, [rSELF, #offThread_methodClassDex] 21605 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land 21606 cmp r10, #0 @ caller is compiled code 21607 blxne r10 21608 GET_INST_OPCODE(ip) @ extract opcode from rINST 21609 GOTO_OPCODE(ip) @ jump to next instruction 21610#else 21611 GET_INST_OPCODE(ip) @ extract opcode from rINST 21612 mov rPC, r9 @ publish new rPC 21613 str r1, [rSELF, #offThread_methodClassDex] 21614 GOTO_OPCODE(ip) @ jump to next instruction 21615#endif 21616 21617 /* 21618 * Return handling, calls through "glue code". 21619 */ 21620 .if 0 21621.LreturnOld: 21622 SAVE_PC_FP_TO_SELF() @ export state 21623 mov r0, rSELF @ arg to function 21624 bl dvmMterp_returnFromMethod 21625 b common_resumeAfterGlueCall 21626 .endif 21627 21628 21629/* 21630 * Somebody has thrown an exception. Handle it. 21631 * 21632 * If the exception processing code returns to us (instead of falling 21633 * out of the interpreter), continue with whatever the next instruction 21634 * now happens to be. 21635 * 21636 * This does not return. 21637 */ 21638 .global dvmMterpCommonExceptionThrown 21639dvmMterpCommonExceptionThrown: 21640common_exceptionThrown: 21641.LexceptionNew: 21642 mov r0, #kInterpEntryThrow 21643 mov r9, #0 21644 bl common_periodicChecks 21645 21646 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception 21647 mov r1, rSELF @ r1<- self 21648 mov r0, r9 @ r0<- exception 21649 bl dvmAddTrackedAlloc @ don't let the exception be GCed 21650 mov r3, #0 @ r3<- NULL 21651 str r3, [rSELF, #offThread_exception] @ self->exception = NULL 21652 21653 /* set up args and a local for "&fp" */ 21654 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 21655 str rFP, [sp, #-4]! @ *--sp = fp 21656 mov ip, sp @ ip<- &fp 21657 mov r3, #0 @ r3<- false 21658 str ip, [sp, #-4]! @ *--sp = &fp 21659 ldr r1, [rSELF, #offThread_method] @ r1<- self->method 21660 mov r0, rSELF @ r0<- self 21661 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 21662 mov r2, r9 @ r2<- exception 21663 sub r1, rPC, r1 @ r1<- pc - method->insns 21664 mov r1, r1, asr #1 @ r1<- offset in code units 21665 21666 /* call, r0 gets catchRelPc (a code-unit offset) */ 21667 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 21668 21669 /* fix earlier stack overflow if necessary; may trash rFP */ 21670 ldrb r1, [rSELF, #offThread_stackOverflowed] 21671 cmp r1, #0 @ did we overflow earlier? 21672 beq 1f @ no, skip ahead 21673 mov rFP, r0 @ save relPc result in rFP 21674 mov r0, rSELF @ r0<- self 21675 mov r1, r9 @ r1<- exception 21676 bl dvmCleanupStackOverflow @ call(self) 21677 mov r0, rFP @ restore result 216781: 21679 21680 /* update frame pointer and check result from dvmFindCatchBlock */ 21681 ldr rFP, [sp, #4] @ retrieve the updated rFP 21682 cmp r0, #0 @ is catchRelPc < 0? 21683 add sp, sp, #8 @ restore stack 21684 bmi .LnotCaughtLocally 21685 21686 /* adjust locals to match self->curFrame and updated PC */ 21687 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 21688 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 21689 str r1, [rSELF, #offThread_method] @ self->method = new method 21690 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 21691 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 21692 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 21693 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 21694 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth... 21695 21696 /* release the tracked alloc on the exception */ 21697 mov r0, r9 @ r0<- exception 21698 mov r1, rSELF @ r1<- self 21699 bl dvmReleaseTrackedAlloc @ release the exception 21700 21701 /* restore the exception if the handler wants it */ 21702 FETCH_INST() @ load rINST from rPC 21703 GET_INST_OPCODE(ip) @ extract opcode from rINST 21704 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 21705 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception 21706 GOTO_OPCODE(ip) @ jump to next instruction 21707 21708.LnotCaughtLocally: @ r9=exception 21709 /* fix stack overflow if necessary */ 21710 ldrb r1, [rSELF, #offThread_stackOverflowed] 21711 cmp r1, #0 @ did we overflow earlier? 21712 movne r0, rSELF @ if yes: r0<- self 21713 movne r1, r9 @ if yes: r1<- exception 21714 blne dvmCleanupStackOverflow @ if yes: call(self) 21715 21716 @ may want to show "not caught locally" debug messages here 21717#if DVM_SHOW_EXCEPTION >= 2 21718 /* call __android_log_print(prio, tag, format, ...) */ 21719 /* "Exception %s from %s:%d not caught locally" */ 21720 @ dvmLineNumFromPC(method, pc - method->insns) 21721 ldr r0, [rSELF, #offThread_method] 21722 ldr r1, [r0, #offMethod_insns] 21723 sub r1, rPC, r1 21724 asr r1, r1, #1 21725 bl dvmLineNumFromPC 21726 str r0, [sp, #-4]! 21727 @ dvmGetMethodSourceFile(method) 21728 ldr r0, [rSELF, #offThread_method] 21729 bl dvmGetMethodSourceFile 21730 str r0, [sp, #-4]! 21731 @ exception->clazz->descriptor 21732 ldr r3, [r9, #offObject_clazz] 21733 ldr r3, [r3, #offClassObject_descriptor] 21734 @ 21735 ldr r2, strExceptionNotCaughtLocally 21736 ldr r1, strLogTag 21737 mov r0, #3 @ LOG_DEBUG 21738 bl __android_log_print 21739#endif 21740 str r9, [rSELF, #offThread_exception] @ restore exception 21741 mov r0, r9 @ r0<- exception 21742 mov r1, rSELF @ r1<- self 21743 bl dvmReleaseTrackedAlloc @ release the exception 21744 mov r1, #0 @ "want switch" = false 21745 b common_gotoBail @ bail out 21746 21747 21748 /* 21749 * Exception handling, calls through "glue code". 21750 */ 21751 .if 0 21752.LexceptionOld: 21753 SAVE_PC_FP_TO_SELF() @ export state 21754 mov r0, rSELF @ arg to function 21755 bl dvmMterp_exceptionThrown 21756 b common_resumeAfterGlueCall 21757 .endif 21758 21759 21760/* 21761 * After returning from a "glued" function, pull out the updated 21762 * values and start executing at the next instruction. 21763 */ 21764common_resumeAfterGlueCall: 21765 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread 21766 FETCH_INST() @ load rINST from rPC 21767 GET_INST_OPCODE(ip) @ extract opcode from rINST 21768 GOTO_OPCODE(ip) @ jump to next instruction 21769 21770/* 21771 * Invalid array index. Note that our calling convention is strange; we use r1 21772 * and r3 because those just happen to be the registers all our callers are 21773 * using. We shuffle them here before calling the C function. 21774 * r1: index 21775 * r3: size 21776 */ 21777common_errArrayIndex: 21778 EXPORT_PC() 21779 mov r0, r1 21780 mov r1, r3 21781 bl dvmThrowArrayIndexOutOfBoundsException 21782 b common_exceptionThrown 21783 21784/* 21785 * Integer divide or mod by zero. 21786 */ 21787common_errDivideByZero: 21788 EXPORT_PC() 21789 ldr r0, strDivideByZero 21790 bl dvmThrowArithmeticException 21791 b common_exceptionThrown 21792 21793/* 21794 * Attempt to allocate an array with a negative size. 21795 * On entry: length in r1 21796 */ 21797common_errNegativeArraySize: 21798 EXPORT_PC() 21799 mov r0, r1 @ arg0 <- len 21800 bl dvmThrowNegativeArraySizeException @ (len) 21801 b common_exceptionThrown 21802 21803/* 21804 * Invocation of a non-existent method. 21805 * On entry: method name in r1 21806 */ 21807common_errNoSuchMethod: 21808 EXPORT_PC() 21809 mov r0, r1 21810 bl dvmThrowNoSuchMethodError 21811 b common_exceptionThrown 21812 21813/* 21814 * We encountered a null object when we weren't expecting one. We 21815 * export the PC, throw a NullPointerException, and goto the exception 21816 * processing code. 21817 */ 21818common_errNullObject: 21819 EXPORT_PC() 21820 mov r0, #0 21821 bl dvmThrowNullPointerException 21822 b common_exceptionThrown 21823 21824/* 21825 * For debugging, cause an immediate fault. The source address will 21826 * be in lr (use a bl instruction to jump here). 21827 */ 21828common_abort: 21829 ldr pc, .LdeadFood 21830.LdeadFood: 21831 .word 0xdeadf00d 21832 21833/* 21834 * Spit out a "we were here", preserving all registers. (The attempt 21835 * to save ip won't work, but we need to save an even number of 21836 * registers for EABI 64-bit stack alignment.) 21837 */ 21838 .macro SQUEAK num 21839common_squeak\num: 21840 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21841 ldr r0, strSqueak 21842 mov r1, #\num 21843 bl printf 21844 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21845 bx lr 21846 .endm 21847 21848 SQUEAK 0 21849 SQUEAK 1 21850 SQUEAK 2 21851 SQUEAK 3 21852 SQUEAK 4 21853 SQUEAK 5 21854 21855/* 21856 * Spit out the number in r0, preserving registers. 21857 */ 21858common_printNum: 21859 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21860 mov r1, r0 21861 ldr r0, strSqueak 21862 bl printf 21863 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21864 bx lr 21865 21866/* 21867 * Print a newline, preserving registers. 21868 */ 21869common_printNewline: 21870 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21871 ldr r0, strNewline 21872 bl printf 21873 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21874 bx lr 21875 21876 /* 21877 * Print the 32-bit quantity in r0 as a hex value, preserving registers. 21878 */ 21879common_printHex: 21880 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21881 mov r1, r0 21882 ldr r0, strPrintHex 21883 bl printf 21884 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21885 bx lr 21886 21887/* 21888 * Print the 64-bit quantity in r0-r1, preserving registers. 21889 */ 21890common_printLong: 21891 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21892 mov r3, r1 21893 mov r2, r0 21894 ldr r0, strPrintLong 21895 bl printf 21896 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21897 bx lr 21898 21899/* 21900 * Print full method info. Pass the Method* in r0. Preserves regs. 21901 */ 21902common_printMethod: 21903 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21904 bl dvmMterpPrintMethod 21905 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21906 bx lr 21907 21908/* 21909 * Call a C helper function that dumps regs and possibly some 21910 * additional info. Requires the C function to be compiled in. 21911 */ 21912 .if 0 21913common_dumpRegs: 21914 stmfd sp!, {r0, r1, r2, r3, ip, lr} 21915 bl dvmMterpDumpArmRegs 21916 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 21917 bx lr 21918 .endif 21919 21920#if 0 21921/* 21922 * Experiment on VFP mode. 21923 * 21924 * uint32_t setFPSCR(uint32_t val, uint32_t mask) 21925 * 21926 * Updates the bits specified by "mask", setting them to the values in "val". 21927 */ 21928setFPSCR: 21929 and r0, r0, r1 @ make sure no stray bits are set 21930 fmrx r2, fpscr @ get VFP reg 21931 mvn r1, r1 @ bit-invert mask 21932 and r2, r2, r1 @ clear masked bits 21933 orr r2, r2, r0 @ set specified bits 21934 fmxr fpscr, r2 @ set VFP reg 21935 mov r0, r2 @ return new value 21936 bx lr 21937 21938 .align 2 21939 .global dvmConfigureFP 21940 .type dvmConfigureFP, %function 21941dvmConfigureFP: 21942 stmfd sp!, {ip, lr} 21943 /* 0x03000000 sets DN/FZ */ 21944 /* 0x00009f00 clears the six exception enable flags */ 21945 bl common_squeak0 21946 mov r0, #0x03000000 @ r0<- 0x03000000 21947 add r1, r0, #0x9f00 @ r1<- 0x03009f00 21948 bl setFPSCR 21949 ldmfd sp!, {ip, pc} 21950#endif 21951 21952 21953/* 21954 * String references, must be close to the code that uses them. 21955 */ 21956 .align 2 21957strDivideByZero: 21958 .word .LstrDivideByZero 21959strLogTag: 21960 .word .LstrLogTag 21961strExceptionNotCaughtLocally: 21962 .word .LstrExceptionNotCaughtLocally 21963 21964strNewline: 21965 .word .LstrNewline 21966strSqueak: 21967 .word .LstrSqueak 21968strPrintHex: 21969 .word .LstrPrintHex 21970strPrintLong: 21971 .word .LstrPrintLong 21972 21973/* 21974 * Zero-terminated ASCII string data. 21975 * 21976 * On ARM we have two choices: do like gcc does, and LDR from a .word 21977 * with the address, or use an ADR pseudo-op to get the address 21978 * directly. ADR saves 4 bytes and an indirection, but it's using a 21979 * PC-relative addressing mode and hence has a limited range, which 21980 * makes it not work well with mergeable string sections. 21981 */ 21982 .section .rodata.str1.4,"aMS",%progbits,1 21983 21984.LstrBadEntryPoint: 21985 .asciz "Bad entry point %d\n" 21986.LstrFilledNewArrayNotImpl: 21987 .asciz "filled-new-array only implemented for objects and 'int'" 21988.LstrDivideByZero: 21989 .asciz "divide by zero" 21990.LstrLogTag: 21991 .asciz "mterp" 21992.LstrExceptionNotCaughtLocally: 21993 .asciz "Exception %s from %s:%d not caught locally\n" 21994 21995.LstrNewline: 21996 .asciz "\n" 21997.LstrSqueak: 21998 .asciz "<%d>" 21999.LstrPrintHex: 22000 .asciz "<0x%x>" 22001.LstrPrintLong: 22002 .asciz "<%lld>" 22003 22004