LiveVariables.h revision 6326b0d0f862090c288fc3412b51101800288ac6
1//===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveVariable analysis pass. For each machine 11// instruction in the function, this pass calculates the set of registers that 12// are immediately dead after the instruction (i.e., the instruction calculates 13// the value, but it is never used) and the set of registers that are used by 14// the instruction, but are never used after the instruction (i.e., they are 15// killed). 16// 17// This class computes live variables using a sparse implementation based on 18// the machine code SSA form. This class computes live variable information for 19// each virtual and _register allocatable_ physical register in a function. It 20// uses the dominance properties of SSA form to efficiently compute live 21// variables for virtual registers, and assumes that physical registers are only 22// live within a single basic block (allowing it to do a single local analysis 23// to resolve physical register lifetimes in each basic block). If a physical 24// register is not register allocatable, it is not tracked. This is useful for 25// things like the stack pointer and condition codes. 26// 27//===----------------------------------------------------------------------===// 28 29#ifndef LLVM_CODEGEN_LIVEVARIABLES_H 30#define LLVM_CODEGEN_LIVEVARIABLES_H 31 32#include "llvm/CodeGen/MachineFunctionPass.h" 33#include "llvm/ADT/BitVector.h" 34#include "llvm/ADT/SmallSet.h" 35#include "llvm/ADT/SmallVector.h" 36#include <map> 37 38namespace llvm { 39 40class MRegisterInfo; 41 42class LiveVariables : public MachineFunctionPass { 43public: 44 static char ID; // Pass identification, replacement for typeid 45 LiveVariables() : MachineFunctionPass((intptr_t)&ID) {} 46 47 /// VarInfo - This represents the regions where a virtual register is live in 48 /// the program. We represent this with three different pieces of 49 /// information: the instruction that uniquely defines the value, the set of 50 /// blocks the instruction is live into and live out of, and the set of 51 /// non-phi instructions that are the last users of the value. 52 /// 53 /// In the common case where a value is defined and killed in the same block, 54 /// DefInst is the defining inst, there is one killing instruction, and 55 /// AliveBlocks is empty. 56 /// 57 /// Otherwise, the value is live out of the block. If the value is live 58 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where 59 /// the liveness range ends are not included in AliveBlocks, instead being 60 /// captured by the Kills set. In these blocks, the value is live into the 61 /// block (unless the value is defined and killed in the same block) and lives 62 /// until the specified instruction. Note that there cannot ever be a value 63 /// whose Kills set contains two instructions from the same basic block. 64 /// 65 /// PHI nodes complicate things a bit. If a PHI node is the last user of a 66 /// value in one of its predecessor blocks, it is not listed in the kills set, 67 /// but does include the predecessor block in the AliveBlocks set (unless that 68 /// block also defines the value). This leads to the (perfectly sensical) 69 /// situation where a value is defined in a block, and the last use is a phi 70 /// node in the successor. In this case, DefInst will be the defining 71 /// instruction, AliveBlocks is empty (the value is not live across any 72 /// blocks) and Kills is empty (phi nodes are not included). This is sensical 73 /// because the value must be live to the end of the block, but is not live in 74 /// any successor blocks. 75 struct VarInfo { 76 /// DefInst - The machine instruction that defines this register. 77 /// 78 MachineInstr *DefInst; 79 80 /// AliveBlocks - Set of blocks of which this value is alive completely 81 /// through. This is a bit set which uses the basic block number as an 82 /// index. 83 /// 84 BitVector AliveBlocks; 85 86 /// UsedBlocks - Set of blocks of which this value is actually used. This 87 /// is a bit set which uses the basic block number as an index. 88 BitVector UsedBlocks; 89 90 /// NumUses - Number of uses of this register across the entire function. 91 /// 92 unsigned NumUses; 93 94 /// Kills - List of MachineInstruction's which are the last use of this 95 /// virtual register (kill it) in their basic block. 96 /// 97 std::vector<MachineInstr*> Kills; 98 99 VarInfo() : DefInst(0), NumUses(0) {} 100 101 /// removeKill - Delete a kill corresponding to the specified 102 /// machine instruction. Returns true if there was a kill 103 /// corresponding to this instruction, false otherwise. 104 bool removeKill(MachineInstr *MI) { 105 for (std::vector<MachineInstr*>::iterator i = Kills.begin(), 106 e = Kills.end(); i != e; ++i) 107 if (*i == MI) { 108 Kills.erase(i); 109 return true; 110 } 111 return false; 112 } 113 114 void dump() const; 115 }; 116 117private: 118 /// VirtRegInfo - This list is a mapping from virtual register number to 119 /// variable information. FirstVirtualRegister is subtracted from the virtual 120 /// register number before indexing into this list. 121 /// 122 std::vector<VarInfo> VirtRegInfo; 123 124 /// ReservedRegisters - This vector keeps track of which registers 125 /// are reserved register which are not allocatable by the target machine. 126 /// We can not track liveness for values that are in this set. 127 /// 128 BitVector ReservedRegisters; 129 130private: // Intermediate data structures 131 MachineFunction *MF; 132 133 const MRegisterInfo *RegInfo; 134 135 // PhysRegInfo - Keep track of which instruction was the last def/use of a 136 // physical register. This is a purely local property, because all physical 137 // register references as presumed dead across basic blocks. 138 MachineInstr **PhysRegInfo; 139 140 // PhysRegUsed - Keep track whether the physical register has been used after 141 // its last definition. This is local property. 142 bool *PhysRegUsed; 143 144 // PhysRegPartUse - Keep track of which instruction was the last partial use 145 // of a physical register (e.g. on X86 a def of EAX followed by a use of AX). 146 // This is a purely local property. 147 MachineInstr **PhysRegPartUse; 148 149 // PhysRegPartDef - Keep track of a list of instructions which "partially" 150 // defined the physical register (e.g. on X86 AX partially defines EAX). 151 // These are turned into use/mod/write if there is a use of the register 152 // later in the same block. This is local property. 153 SmallVector<MachineInstr*, 4> *PhysRegPartDef; 154 155 SmallVector<unsigned, 4> *PHIVarInfo; 156 157 void addRegisterKills(unsigned Reg, MachineInstr *MI, 158 SmallSet<unsigned, 4> &SubKills); 159 160 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the 161 /// uses. Pay special attention to the sub-register uses which may come below 162 /// the last use of the whole register. 163 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI, 164 SmallSet<unsigned, 4> &SubKills); 165 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI); 166 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); 167 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI); 168 169 /// analyzePHINodes - Gather information about the PHI nodes in here. In 170 /// particular, we want to map the variable information of a virtual 171 /// register which is used in a PHI node. We map that to the BB the vreg 172 /// is coming from. 173 void analyzePHINodes(const MachineFunction& Fn); 174public: 175 176 virtual bool runOnMachineFunction(MachineFunction &MF); 177 178 /// KillsRegister - Return true if the specified instruction kills the 179 /// specified register. 180 bool KillsRegister(MachineInstr *MI, unsigned Reg) const; 181 182 /// RegisterDefIsDead - Return true if the specified instruction defines the 183 /// specified register, but that definition is dead. 184 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const; 185 186 /// ModifiesRegister - Return true if the specified instruction modifies the 187 /// specified register. 188 bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const; 189 190 //===--------------------------------------------------------------------===// 191 // API to update live variable information 192 193 /// instructionChanged - When the address of an instruction changes, this 194 /// method should be called so that live variables can update its internal 195 /// data structures. This removes the records for OldMI, transfering them to 196 /// the records for NewMI. 197 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI); 198 199 /// addVirtualRegisterKilled - Add information about the fact that the 200 /// specified register is killed after being used by the specified 201 /// instruction. If AddIfNotFound is true, add a implicit operand if it's 202 /// not found. 203 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI, 204 bool AddIfNotFound = false) { 205 if (MI->addRegisterKilled(IncomingReg, RegInfo, AddIfNotFound)) 206 getVarInfo(IncomingReg).Kills.push_back(MI); 207 } 208 209 /// removeVirtualRegisterKilled - Remove the specified virtual 210 /// register from the live variable information. Returns true if the 211 /// variable was marked as killed by the specified instruction, 212 /// false otherwise. 213 bool removeVirtualRegisterKilled(unsigned reg, 214 MachineBasicBlock *MBB, 215 MachineInstr *MI) { 216 if (!getVarInfo(reg).removeKill(MI)) 217 return false; 218 219 bool Removed = false; 220 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 221 MachineOperand &MO = MI->getOperand(i); 222 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) { 223 MO.setIsKill(false); 224 Removed = true; 225 break; 226 } 227 } 228 229 assert(Removed && "Register is not used by this instruction!"); 230 return true; 231 } 232 233 /// removeVirtualRegistersKilled - Remove all killed info for the specified 234 /// instruction. 235 void removeVirtualRegistersKilled(MachineInstr *MI); 236 237 /// addVirtualRegisterDead - Add information about the fact that the specified 238 /// register is dead after being used by the specified instruction. If 239 /// AddIfNotFound is true, add a implicit operand if it's not found. 240 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI, 241 bool AddIfNotFound = false) { 242 if (MI->addRegisterDead(IncomingReg, RegInfo, AddIfNotFound)) 243 getVarInfo(IncomingReg).Kills.push_back(MI); 244 } 245 246 /// removeVirtualRegisterDead - Remove the specified virtual 247 /// register from the live variable information. Returns true if the 248 /// variable was marked dead at the specified instruction, false 249 /// otherwise. 250 bool removeVirtualRegisterDead(unsigned reg, 251 MachineBasicBlock *MBB, 252 MachineInstr *MI) { 253 if (!getVarInfo(reg).removeKill(MI)) 254 return false; 255 256 bool Removed = false; 257 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 258 MachineOperand &MO = MI->getOperand(i); 259 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) { 260 MO.setIsDead(false); 261 Removed = true; 262 break; 263 } 264 } 265 assert(Removed && "Register is not defined by this instruction!"); 266 return true; 267 } 268 269 /// removeVirtualRegistersDead - Remove all of the dead registers for the 270 /// specified instruction from the live variable information. 271 void removeVirtualRegistersDead(MachineInstr *MI); 272 273 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 274 AU.setPreservesAll(); 275 } 276 277 virtual void releaseMemory() { 278 VirtRegInfo.clear(); 279 } 280 281 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL 282 /// register. 283 VarInfo &getVarInfo(unsigned RegIdx); 284 285 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock, 286 MachineBasicBlock *BB); 287 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock, 288 MachineBasicBlock *BB, 289 std::vector<MachineBasicBlock*> &WorkList); 290 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, 291 MachineInstr *MI); 292}; 293 294} // End llvm namespace 295 296#endif 297