MachineInstr.h revision 00c53caa339f954cb3590a05e8653b864b4355cf
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/CodeGen/MachineOperand.h" 20#include "llvm/Target/TargetInstrDesc.h" 21#include "llvm/Target/TargetOpcodes.h" 22#include "llvm/ADT/ilist.h" 23#include "llvm/ADT/ilist_node.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/ADT/DenseMapInfo.h" 26#include "llvm/Support/DebugLoc.h" 27#include <vector> 28 29namespace llvm { 30 31template <typename T> class SmallVectorImpl; 32class AliasAnalysis; 33class TargetInstrDesc; 34class TargetInstrInfo; 35class TargetRegisterInfo; 36class MachineFunction; 37class MachineMemOperand; 38 39//===----------------------------------------------------------------------===// 40/// MachineInstr - Representation of each machine instruction. 41/// 42class MachineInstr : public ilist_node<MachineInstr> { 43public: 44 typedef MachineMemOperand **mmo_iterator; 45 46 /// Flags to specify different kinds of comments to output in 47 /// assembly code. These flags carry semantic information not 48 /// otherwise easily derivable from the IR text. 49 /// 50 enum CommentFlag { 51 ReloadReuse = 0x1 52 }; 53 54private: 55 const TargetInstrDesc *TID; // Instruction descriptor. 56 unsigned short NumImplicitOps; // Number of implicit operands (which 57 // are determined at construction time). 58 59 unsigned short AsmPrinterFlags; // Various bits of information used by 60 // the AsmPrinter to emit helpful 61 // comments. This is *not* semantic 62 // information. Do not use this for 63 // anything other than to convey comment 64 // information to AsmPrinter. 65 66 std::vector<MachineOperand> Operands; // the operands 67 mmo_iterator MemRefs; // information on memory references 68 mmo_iterator MemRefsEnd; 69 MachineBasicBlock *Parent; // Pointer to the owning basic block. 70 DebugLoc debugLoc; // Source line information. 71 72 // OperandComplete - Return true if it's illegal to add a new operand 73 bool OperandsComplete() const; 74 75 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT 76 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 77 78 // Intrusive list support 79 friend struct ilist_traits<MachineInstr>; 80 friend struct ilist_traits<MachineBasicBlock>; 81 void setParent(MachineBasicBlock *P) { Parent = P; } 82 83 /// MachineInstr ctor - This constructor creates a copy of the given 84 /// MachineInstr in the given MachineFunction. 85 MachineInstr(MachineFunction &, const MachineInstr &); 86 87 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with 88 /// TID NULL and no operands. 89 MachineInstr(); 90 91 // The next two constructors have DebugLoc and non-DebugLoc versions; 92 // over time, the non-DebugLoc versions should be phased out and eventually 93 // removed. 94 95 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the 96 /// implicit operands. It reserves space for the number of operands specified 97 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred. 98 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); 99 100 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 101 /// the MachineInstr is created and added to the end of the specified basic 102 /// block. The version with a DebugLoc should be preferred. 103 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); 104 105 /// MachineInstr ctor - This constructor create a MachineInstr and add the 106 /// implicit operands. It reserves space for number of operands specified by 107 /// TargetInstrDesc. An explicit DebugLoc is supplied. 108 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl, 109 bool NoImp = false); 110 111 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 112 /// the MachineInstr is created and added to the end of the specified basic 113 /// block. 114 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 115 const TargetInstrDesc &TID); 116 117 ~MachineInstr(); 118 119 // MachineInstrs are pool-allocated and owned by MachineFunction. 120 friend class MachineFunction; 121 122public: 123 const MachineBasicBlock* getParent() const { return Parent; } 124 MachineBasicBlock* getParent() { return Parent; } 125 126 /// getAsmPrinterFlags - Return the asm printer flags bitvector. 127 /// 128 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; } 129 130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set. 131 /// 132 bool getAsmPrinterFlag(CommentFlag Flag) const { 133 return AsmPrinterFlags & Flag; 134 } 135 136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter. 137 /// 138 void setAsmPrinterFlag(CommentFlag Flag) { 139 AsmPrinterFlags |= (unsigned short)Flag; 140 } 141 142 /// getDebugLoc - Returns the debug location id of this MachineInstr. 143 /// 144 DebugLoc getDebugLoc() const { return debugLoc; } 145 146 /// getDesc - Returns the target instruction descriptor of this 147 /// MachineInstr. 148 const TargetInstrDesc &getDesc() const { return *TID; } 149 150 /// getOpcode - Returns the opcode of this MachineInstr. 151 /// 152 int getOpcode() const { return TID->Opcode; } 153 154 /// Access to explicit operands of the instruction. 155 /// 156 unsigned getNumOperands() const { return (unsigned)Operands.size(); } 157 158 const MachineOperand& getOperand(unsigned i) const { 159 assert(i < getNumOperands() && "getOperand() out of range!"); 160 return Operands[i]; 161 } 162 MachineOperand& getOperand(unsigned i) { 163 assert(i < getNumOperands() && "getOperand() out of range!"); 164 return Operands[i]; 165 } 166 167 /// getNumExplicitOperands - Returns the number of non-implicit operands. 168 /// 169 unsigned getNumExplicitOperands() const; 170 171 /// Access to memory operands of the instruction 172 mmo_iterator memoperands_begin() const { return MemRefs; } 173 mmo_iterator memoperands_end() const { return MemRefsEnd; } 174 bool memoperands_empty() const { return MemRefsEnd == MemRefs; } 175 176 /// hasOneMemOperand - Return true if this instruction has exactly one 177 /// MachineMemOperand. 178 bool hasOneMemOperand() const { 179 return MemRefsEnd - MemRefs == 1; 180 } 181 182 enum MICheckType { 183 CheckDefs, // Check all operands for equality 184 IgnoreDefs, // Ignore all definitions 185 IgnoreVRegDefs // Ignore virtual register definitions 186 }; 187 188 /// isIdenticalTo - Return true if this instruction is identical to (same 189 /// opcode and same operands as) the specified instruction. 190 bool isIdenticalTo(const MachineInstr *Other, 191 MICheckType Check = CheckDefs) const; 192 193 /// removeFromParent - This method unlinks 'this' from the containing basic 194 /// block, and returns it, but does not delete it. 195 MachineInstr *removeFromParent(); 196 197 /// eraseFromParent - This method unlinks 'this' from the containing basic 198 /// block and deletes it. 199 void eraseFromParent(); 200 201 /// isLabel - Returns true if the MachineInstr represents a label. 202 /// 203 bool isLabel() const { 204 return getOpcode() == TargetOpcode::DBG_LABEL || 205 getOpcode() == TargetOpcode::EH_LABEL || 206 getOpcode() == TargetOpcode::GC_LABEL; 207 } 208 209 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } 210 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 211 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 212 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 213 214 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } 215 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 216 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 217 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } 218 bool isExtractSubreg() const { 219 return getOpcode() == TargetOpcode::EXTRACT_SUBREG; 220 } 221 bool isInsertSubreg() const { 222 return getOpcode() == TargetOpcode::INSERT_SUBREG; 223 } 224 bool isSubregToReg() const { 225 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 226 } 227 bool isRegSequence() const { 228 return getOpcode() == TargetOpcode::REG_SEQUENCE; 229 } 230 231 /// readsRegister - Return true if the MachineInstr reads the specified 232 /// register. If TargetRegisterInfo is passed, then it also checks if there 233 /// is a read of a super-register. 234 /// This does not count partial redefines of virtual registers as reads: 235 /// %reg1024:6 = OP. 236 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 237 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 238 } 239 240 /// readsVirtualRegister - Return true if the MachineInstr reads the specified 241 /// virtual register. Take into account that a partial define is a 242 /// read-modify-write operation. 243 bool readsVirtualRegister(unsigned Reg) const { 244 return readsWritesVirtualRegister(Reg).first; 245 } 246 247 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 248 /// indicating if this instruction reads or writes Reg. This also considers 249 /// partial defines. 250 /// If Ops is not null, all operand indices for Reg are added. 251 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg, 252 SmallVectorImpl<unsigned> *Ops = 0) const; 253 254 /// killsRegister - Return true if the MachineInstr kills the specified 255 /// register. If TargetRegisterInfo is passed, then it also checks if there is 256 /// a kill of a super-register. 257 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 258 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 259 } 260 261 /// modifiesRegister - Return true if the MachineInstr modifies the 262 /// specified register. If TargetRegisterInfo is passed, then it also checks 263 /// if there is a def of a super-register. 264 bool modifiesRegister(unsigned Reg, 265 const TargetRegisterInfo *TRI = NULL) const { 266 return findRegisterDefOperandIdx(Reg, false, TRI) != -1; 267 } 268 269 /// registerDefIsDead - Returns true if the register is dead in this machine 270 /// instruction. If TargetRegisterInfo is passed, then it also checks 271 /// if there is a dead def of a super-register. 272 bool registerDefIsDead(unsigned Reg, 273 const TargetRegisterInfo *TRI = NULL) const { 274 return findRegisterDefOperandIdx(Reg, true, TRI) != -1; 275 } 276 277 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of 278 /// the specific register or -1 if it is not found. It further tightens 279 /// the search criteria to a use that kills the register if isKill is true. 280 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 281 const TargetRegisterInfo *TRI = NULL) const; 282 283 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns 284 /// a pointer to the MachineOperand rather than an index. 285 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, 286 const TargetRegisterInfo *TRI = NULL) { 287 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 288 return (Idx == -1) ? NULL : &getOperand(Idx); 289 } 290 291 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of 292 /// the specified register or -1 if it is not found. If isDead is true, defs 293 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 294 /// also checks if there is a def of a super-register. 295 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false, 296 const TargetRegisterInfo *TRI = NULL) const; 297 298 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns 299 /// a pointer to the MachineOperand rather than an index. 300 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, 301 const TargetRegisterInfo *TRI = NULL) { 302 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI); 303 return (Idx == -1) ? NULL : &getOperand(Idx); 304 } 305 306 /// findFirstPredOperandIdx() - Find the index of the first operand in the 307 /// operand list that is used to represent the predicate. It returns -1 if 308 /// none is found. 309 int findFirstPredOperandIdx() const; 310 311 /// isRegTiedToUseOperand - Given the index of a register def operand, 312 /// check if the register def is tied to a source operand, due to either 313 /// two-address elimination or inline assembly constraints. Returns the 314 /// first tied use operand index by reference is UseOpIdx is not null. 315 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const; 316 317 /// isRegTiedToDefOperand - Return true if the use operand of the specified 318 /// index is tied to an def operand. It also returns the def operand index by 319 /// reference if DefOpIdx is not null. 320 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const; 321 322 /// clearKillInfo - Clears kill flags on all operands. 323 /// 324 void clearKillInfo(); 325 326 /// copyKillDeadInfo - Copies kill / dead operand properties from MI. 327 /// 328 void copyKillDeadInfo(const MachineInstr *MI); 329 330 /// copyPredicates - Copies predicate operand(s) from MI. 331 void copyPredicates(const MachineInstr *MI); 332 333 /// addRegisterKilled - We have determined MI kills a register. Look for the 334 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 335 /// add a implicit operand if it's not found. Returns true if the operand 336 /// exists / is added. 337 bool addRegisterKilled(unsigned IncomingReg, 338 const TargetRegisterInfo *RegInfo, 339 bool AddIfNotFound = false); 340 341 /// addRegisterDead - We have determined MI defined a register without a use. 342 /// Look for the operand that defines it and mark it as IsDead. If 343 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 344 /// true if the operand exists / is added. 345 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, 346 bool AddIfNotFound = false); 347 348 /// addRegisterDefined - We have determined MI defines a register. Make sure 349 /// there is an operand defining Reg. 350 void addRegisterDefined(unsigned IncomingReg, 351 const TargetRegisterInfo *RegInfo = 0); 352 353 /// isSafeToMove - Return true if it is safe to move this instruction. If 354 /// SawStore is set to true, it means that there is a store (or call) between 355 /// the instruction's location and its intended destination. 356 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA, 357 bool &SawStore) const; 358 359 /// isSafeToReMat - Return true if it's safe to rematerialize the specified 360 /// instruction which defined the specified register instead of copying it. 361 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA, 362 unsigned DstReg) const; 363 364 /// hasVolatileMemoryRef - Return true if this instruction may have a 365 /// volatile memory reference, or if the information describing the 366 /// memory reference is not available. Return false if it is known to 367 /// have no volatile memory references. 368 bool hasVolatileMemoryRef() const; 369 370 /// isInvariantLoad - Return true if this instruction is loading from a 371 /// location whose value is invariant across the function. For example, 372 /// loading a value from the constant pool or from the argument area of 373 /// a function if it does not change. This should only return true of *all* 374 /// loads the instruction does are invariant (if it does multiple loads). 375 bool isInvariantLoad(AliasAnalysis *AA) const; 376 377 /// isConstantValuePHI - If the specified instruction is a PHI that always 378 /// merges together the same virtual register, return the register, otherwise 379 /// return 0. 380 unsigned isConstantValuePHI() const; 381 382 /// allDefsAreDead - Return true if all the defs of this instruction are dead. 383 /// 384 bool allDefsAreDead() const; 385 386 // 387 // Debugging support 388 // 389 void print(raw_ostream &OS, const TargetMachine *TM = 0) const; 390 void dump() const; 391 392 //===--------------------------------------------------------------------===// 393 // Accessors used to build up machine instructions. 394 395 /// addOperand - Add the specified operand to the instruction. If it is an 396 /// implicit operand, it is added to the end of the operand list. If it is 397 /// an explicit operand it is added at the end of the explicit operand list 398 /// (before the first implicit operand). 399 void addOperand(const MachineOperand &Op); 400 401 /// setDesc - Replace the instruction descriptor (thus opcode) of 402 /// the current instruction with a new one. 403 /// 404 void setDesc(const TargetInstrDesc &tid) { TID = &tid; } 405 406 /// setDebugLoc - Replace current source information with new such. 407 /// Avoid using this, the constructor argument is preferable. 408 /// 409 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } 410 411 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 412 /// fewer operand than it started with. 413 /// 414 void RemoveOperand(unsigned i); 415 416 /// addMemOperand - Add a MachineMemOperand to the machine instruction. 417 /// This function should be used only occasionally. The setMemRefs function 418 /// is the primary method for setting up a MachineInstr's MemRefs list. 419 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 420 421 /// setMemRefs - Assign this MachineInstr's memory reference descriptor 422 /// list. This does not transfer ownership. 423 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) { 424 MemRefs = NewMemRefs; 425 MemRefsEnd = NewMemRefsEnd; 426 } 427 428private: 429 /// getRegInfo - If this instruction is embedded into a MachineFunction, 430 /// return the MachineRegisterInfo object for the current function, otherwise 431 /// return null. 432 MachineRegisterInfo *getRegInfo(); 433 434 /// addImplicitDefUseOperands - Add all implicit def and use operands to 435 /// this instruction. 436 void addImplicitDefUseOperands(); 437 438 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 439 /// this instruction from their respective use lists. This requires that the 440 /// operands already be on their use lists. 441 void RemoveRegOperandsFromUseLists(); 442 443 /// AddRegOperandsToUseLists - Add all of the register operands in 444 /// this instruction from their respective use lists. This requires that the 445 /// operands not be on their use lists yet. 446 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); 447}; 448 449/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare 450/// MachineInstr* by *value* of the instruction rather than by pointer value. 451/// The hashing and equality testing functions ignore definitions so this is 452/// useful for CSE, etc. 453struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { 454 static inline MachineInstr *getEmptyKey() { 455 return 0; 456 } 457 458 static inline MachineInstr *getTombstoneKey() { 459 return reinterpret_cast<MachineInstr*>(-1); 460 } 461 462 static unsigned getHashValue(const MachineInstr* const &MI); 463 464 static bool isEqual(const MachineInstr* const &LHS, 465 const MachineInstr* const &RHS) { 466 if (RHS == getEmptyKey() || RHS == getTombstoneKey() || 467 LHS == getEmptyKey() || LHS == getTombstoneKey()) 468 return LHS == RHS; 469 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs); 470 } 471}; 472 473//===----------------------------------------------------------------------===// 474// Debugging Support 475 476inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 477 MI.print(OS); 478 return OS; 479} 480 481} // End llvm namespace 482 483#endif 484