MachineInstr.h revision 27a08935ca4ccf2121c2cf4bfbf148e2382c7762
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=// 2// 3// This file contains the declaration of the MachineInstr class, which is the 4// basic representation for all target dependant machine instructions used by 5// the back end. 6// 7//===----------------------------------------------------------------------===// 8 9#ifndef LLVM_CODEGEN_MACHINEINSTR_H 10#define LLVM_CODEGEN_MACHINEINSTR_H 11 12#include "llvm/Target/MachineInstrInfo.h" 13#include "llvm/Annotation.h" 14#include <Support/iterator> 15class Instruction; 16 17//--------------------------------------------------------------------------- 18// class MachineOperand 19// 20// Purpose: 21// Representation of each machine instruction operand. 22// This class is designed so that you can allocate a vector of operands 23// first and initialize each one later. 24// 25// E.g, for this VM instruction: 26// ptr = alloca type, numElements 27// we generate 2 machine instructions on the SPARC: 28// 29// mul Constant, Numelements -> Reg 30// add %sp, Reg -> Ptr 31// 32// Each instruction has 3 operands, listed above. Of those: 33// - Reg, NumElements, and Ptr are of operand type MO_Register. 34// - Constant is of operand type MO_SignExtendedImmed on the SPARC. 35// 36// For the register operands, the virtual register type is as follows: 37// 38// - Reg will be of virtual register type MO_MInstrVirtualReg. The field 39// MachineInstr* minstr will point to the instruction that computes reg. 40// 41// - %sp will be of virtual register type MO_MachineReg. 42// The field regNum identifies the machine register. 43// 44// - NumElements will be of virtual register type MO_VirtualReg. 45// The field Value* value identifies the value. 46// 47// - Ptr will also be of virtual register type MO_VirtualReg. 48// Again, the field Value* value identifies the value. 49// 50//--------------------------------------------------------------------------- 51 52 53class MachineOperand { 54public: 55 enum MachineOperandType { 56 MO_VirtualRegister, // virtual register for *value 57 MO_MachineRegister, // pre-assigned machine register `regNum' 58 MO_CCRegister, 59 MO_SignExtendedImmed, 60 MO_UnextendedImmed, 61 MO_PCRelativeDisp, 62 }; 63 64private: 65 // Bit fields of the flags variable used for different operand properties 66 static const char DEFFLAG = 0x1; // this is a def of the operand 67 static const char DEFUSEFLAG = 0x2; // this is both a def and a use 68 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal) 69 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal) 70 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal) 71 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal) 72 73private: 74 union { 75 Value* value; // BasicBlockVal for a label operand. 76 // ConstantVal for a non-address immediate. 77 // Virtual register for an SSA operand, 78 // including hidden operands required for 79 // the generated machine code. 80 int64_t immedVal; // constant value for an explicit constant 81 }; 82 83 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 84 char flags; // see bit field definitions above 85 int regNum; // register number for an explicit register 86 // will be set for a value after reg allocation 87public: 88 /*ctor*/ MachineOperand (); 89 /*ctor*/ MachineOperand (MachineOperandType operandType, 90 Value* _val); 91 /*copy ctor*/ MachineOperand (const MachineOperand&); 92 /*dtor*/ ~MachineOperand () {} 93 94 // Accessor methods. Caller is responsible for checking the 95 // operand type before invoking the corresponding accessor. 96 // 97 inline MachineOperandType getOperandType() const { 98 return opType; 99 } 100 inline Value* getVRegValue () const { 101 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 102 opType == MO_PCRelativeDisp); 103 return value; 104 } 105 inline Value* getVRegValueOrNull() const { 106 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 107 opType == MO_PCRelativeDisp)? value : NULL; 108 } 109 inline int getMachineRegNum() const { 110 assert(opType == MO_MachineRegister); 111 return regNum; 112 } 113 inline int64_t getImmedValue () const { 114 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed); 115 return immedVal; 116 } 117 inline bool opIsDef () const { 118 return flags & DEFFLAG; 119 } 120 inline bool opIsDefAndUse () const { 121 return flags & DEFUSEFLAG; 122 } 123 inline bool opHiBits32 () const { 124 return flags & HIFLAG32; 125 } 126 inline bool opLoBits32 () const { 127 return flags & LOFLAG32; 128 } 129 inline bool opHiBits64 () const { 130 return flags & HIFLAG64; 131 } 132 inline bool opLoBits64 () const { 133 return flags & LOFLAG64; 134 } 135 136 // used to check if a machine register has been allocated to this operand 137 inline bool hasAllocatedReg() const { 138 return (regNum >= 0 && 139 (opType == MO_VirtualRegister || opType == MO_CCRegister || 140 opType == MO_MachineRegister)); 141 } 142 143 // used to get the reg number if when one is allocated 144 inline int getAllocatedRegNum() const { 145 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 146 opType == MO_MachineRegister); 147 return regNum; 148 } 149 150 151public: 152 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 153 154private: 155 // These functions are provided so that a vector of operands can be 156 // statically allocated and individual ones can be initialized later. 157 // Give class MachineInstr access to these functions. 158 // 159 void Initialize (MachineOperandType operandType, 160 Value* _val); 161 void InitializeConst (MachineOperandType operandType, 162 int64_t intValue); 163 void InitializeReg (int regNum, 164 bool isCCReg); 165 166 // Construction methods needed for fine-grain control. 167 // These must be accessed via coresponding methods in MachineInstr. 168 void markDef() { flags |= DEFFLAG; } 169 void markDefAndUse() { flags |= DEFUSEFLAG; } 170 void markHi32() { flags |= HIFLAG32; } 171 void markLo32() { flags |= LOFLAG32; } 172 void markHi64() { flags |= HIFLAG64; } 173 void markLo64() { flags |= LOFLAG64; } 174 175 // Replaces the Value with its corresponding physical register after 176 // register allocation is complete 177 void setRegForValue(int reg) { 178 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 179 opType == MO_MachineRegister); 180 regNum = reg; 181 } 182 183 friend class MachineInstr; 184}; 185 186 187inline 188MachineOperand::MachineOperand() 189 : immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1) 190{} 191 192inline 193MachineOperand::MachineOperand(MachineOperandType operandType, 194 Value* _val) 195 : immedVal(0), opType(operandType), flags(0), regNum(-1) 196{} 197 198inline 199MachineOperand::MachineOperand(const MachineOperand& mo) 200 : opType(mo.opType), flags(mo.flags) 201{ 202 switch(opType) { 203 case MO_VirtualRegister: 204 case MO_CCRegister: value = mo.value; break; 205 case MO_MachineRegister: regNum = mo.regNum; break; 206 case MO_SignExtendedImmed: 207 case MO_UnextendedImmed: 208 case MO_PCRelativeDisp: immedVal = mo.immedVal; break; 209 default: assert(0); 210 } 211} 212 213inline void 214MachineOperand::Initialize(MachineOperandType operandType, 215 Value* _val) 216{ 217 opType = operandType; 218 value = _val; 219 regNum = -1; 220 flags = 0; 221} 222 223inline void 224MachineOperand::InitializeConst(MachineOperandType operandType, 225 int64_t intValue) 226{ 227 opType = operandType; 228 value = NULL; 229 immedVal = intValue; 230 regNum = -1; 231 flags = 0; 232} 233 234inline void 235MachineOperand::InitializeReg(int _regNum, bool isCCReg) 236{ 237 opType = isCCReg? MO_CCRegister : MO_MachineRegister; 238 value = NULL; 239 regNum = (int) _regNum; 240 flags = 0; 241} 242 243 244//--------------------------------------------------------------------------- 245// class MachineInstr 246// 247// Purpose: 248// Representation of each machine instruction. 249// 250// MachineOpCode must be an enum, defined separately for each target. 251// E.g., It is defined in SparcInstructionSelection.h for the SPARC. 252// 253// opCodeMask is used to record variants of an instruction. 254// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants): 255// ANNUL: if 1: Annul delay slot instruction. 256// PREDICT-NOT-TAKEN: if 1: predict branch not taken. 257// Instead of creating 4 different opcodes for BNZ, we create a single 258// opcode and set bits in opCodeMask for each of these flags. 259// 260// There are 2 kinds of operands: 261// 262// (1) Explicit operands of the machine instruction in vector operands[] 263// 264// (2) "Implicit operands" are values implicitly used or defined by the 265// machine instruction, such as arguments to a CALL, return value of 266// a CALL (if any), and return value of a RETURN. 267//--------------------------------------------------------------------------- 268 269class MachineInstr : public Annotable, // MachineInstrs are annotable 270 public NonCopyable { // Disable copy operations 271 MachineOpCode opCode; // the opcode 272 OpCodeMask opCodeMask; // extra bits for variants of an opcode 273 std::vector<MachineOperand> operands; // the operands 274 275 struct ImplicitRef { 276 Value *Val; 277 bool isDef, isDefAndUse; 278 279 ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){} 280 }; 281 282 // implicitRefs - Values implicitly referenced by this machine instruction 283 // (eg, call args) 284 std::vector<ImplicitRef> implicitRefs; 285 286 // regsUsed - all machine registers used for this instruction, including regs 287 // used to save values across the instruction. This is a bitset of registers. 288 std::vector<bool> regsUsed; 289public: 290 /*ctor*/ MachineInstr (MachineOpCode _opCode, 291 OpCodeMask _opCodeMask = 0x0); 292 /*ctor*/ MachineInstr (MachineOpCode _opCode, 293 unsigned numOperands, 294 OpCodeMask _opCodeMask = 0x0); 295 inline ~MachineInstr () {} 296 297 // 298 // Support to rewrite a machine instruction in place: for now, simply 299 // replace() and then set new operands with Set.*Operand methods below. 300 // 301 void replace (MachineOpCode _opCode, 302 unsigned numOperands, 303 OpCodeMask _opCodeMask = 0x0); 304 305 // 306 // The op code. Note that MachineOpCode is a target-specific type. 307 // 308 const MachineOpCode getOpCode () const { return opCode; } 309 310 // 311 // Information about explicit operands of the instruction 312 // 313 unsigned int getNumOperands () const { return operands.size(); } 314 315 bool operandIsDefined(unsigned i) const; 316 bool operandIsDefinedAndUsed(unsigned i) const; 317 318 const MachineOperand& getOperand (unsigned i) const; 319 MachineOperand& getOperand (unsigned i); 320 321 // 322 // Information about implicit operands of the instruction 323 // 324 unsigned getNumImplicitRefs() const{ return implicitRefs.size();} 325 326 bool implicitRefIsDefined(unsigned i) const; 327 bool implicitRefIsDefinedAndUsed(unsigned i) const; 328 329 const Value* getImplicitRef (unsigned i) const; 330 Value* getImplicitRef (unsigned i); 331 332 // 333 // Information about registers used in this instruction 334 // 335 const std::vector<bool> &getRegsUsed () const { return regsUsed; } 336 337 // insertUsedReg - Add a register to the Used registers set... 338 void insertUsedReg(unsigned Reg) { 339 if (Reg >= regsUsed.size()) 340 regsUsed.resize(Reg+1); 341 regsUsed[Reg] = true; 342 } 343 344 // 345 // Debugging support 346 // 347 void dump () const; 348 friend std::ostream& operator<< (std::ostream& os, 349 const MachineInstr& minstr); 350 351 // 352 // Define iterators to access the Value operands of the Machine Instruction. 353 // begin() and end() are defined to produce these iterators... 354 // 355 template<class _MI, class _V> class ValOpIterator; 356 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 357 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 358 359 360 // Access to set the operands when building the machine instruction 361 // 362 void SetMachineOperandVal(unsigned i, 363 MachineOperand::MachineOperandType 364 operandType, 365 Value* _val, 366 bool isDef=false, 367 bool isDefAndUse=false); 368 void SetMachineOperandConst(unsigned i, 369 MachineOperand::MachineOperandType 370 operandType, 371 int64_t intValue); 372 void SetMachineOperandReg(unsigned i, int regNum, 373 bool isDef=false, 374 bool isDefAndUse=false, 375 bool isCCReg=false); 376 377 void addImplicitRef (Value* val, 378 bool isDef=false, 379 bool isDefAndUse=false); 380 381 void setImplicitRef (unsigned i, 382 Value* val, 383 bool isDef=false, 384 bool isDefAndUse=false); 385 386 unsigned substituteValue (const Value* oldVal, 387 Value* newVal, 388 bool defsOnly = true); 389 390 void setOperandHi32 (unsigned i); 391 void setOperandLo32 (unsigned i); 392 void setOperandHi64 (unsigned i); 393 void setOperandLo64 (unsigned i); 394 395 396 // Replaces the Value for the operand with its allocated 397 // physical register after register allocation is complete. 398 // 399 void SetRegForOperand(unsigned i, int regNum); 400 401 // 402 // Iterator to enumerate machine operands. 403 // 404 template<class MITy, class VTy> 405 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 406 unsigned i; 407 MITy MI; 408 409 inline void skipToNextVal() { 410 while (i < MI->getNumOperands() && 411 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister || 412 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister) 413 && MI->getOperand(i).getVRegValue() != 0)) 414 ++i; 415 } 416 417 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 418 skipToNextVal(); 419 } 420 421 public: 422 typedef ValOpIterator<MITy, VTy> _Self; 423 424 inline VTy operator*() const { 425 return MI->getOperand(i).getVRegValue(); 426 } 427 428 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 429 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 430 431 inline VTy operator->() const { return operator*(); } 432 433 inline bool isDef() const { return MI->getOperand(i).opIsDef(); } 434 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();} 435 436 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 437 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 438 439 inline bool operator==(const _Self &y) const { 440 return i == y.i; 441 } 442 inline bool operator!=(const _Self &y) const { 443 return !operator==(y); 444 } 445 446 static _Self begin(MITy MI) { 447 return _Self(MI, 0); 448 } 449 static _Self end(MITy MI) { 450 return _Self(MI, MI->getNumOperands()); 451 } 452 }; 453 454 // define begin() and end() 455 val_op_iterator begin() { return val_op_iterator::begin(this); } 456 val_op_iterator end() { return val_op_iterator::end(this); } 457 458 const_val_op_iterator begin() const { 459 return const_val_op_iterator::begin(this); 460 } 461 const_val_op_iterator end() const { 462 return const_val_op_iterator::end(this); 463 } 464}; 465 466 467inline MachineOperand& 468MachineInstr::getOperand(unsigned int i) 469{ 470 assert(i < operands.size() && "getOperand() out of range!"); 471 return operands[i]; 472} 473 474inline const MachineOperand& 475MachineInstr::getOperand(unsigned int i) const 476{ 477 assert(i < operands.size() && "getOperand() out of range!"); 478 return operands[i]; 479} 480 481inline bool 482MachineInstr::operandIsDefined(unsigned int i) const 483{ 484 return getOperand(i).opIsDef(); 485} 486 487inline bool 488MachineInstr::operandIsDefinedAndUsed(unsigned int i) const 489{ 490 return getOperand(i).opIsDefAndUse(); 491} 492 493inline bool 494MachineInstr::implicitRefIsDefined(unsigned i) const 495{ 496 assert(i < implicitRefs.size() && "operand out of range!"); 497 return implicitRefs[i].isDef; 498} 499 500inline bool 501MachineInstr::implicitRefIsDefinedAndUsed(unsigned i) const 502{ 503 assert(i < implicitRefs.size() && "operand out of range!"); 504 return implicitRefs[i].isDefAndUse; 505} 506 507inline const Value* 508MachineInstr::getImplicitRef(unsigned i) const 509{ 510 assert(i < implicitRefs.size() && "getImplicitRef() out of range!"); 511 return implicitRefs[i].Val; 512} 513 514inline Value* 515MachineInstr::getImplicitRef(unsigned i) 516{ 517 assert(i < implicitRefs.size() && "getImplicitRef() out of range!"); 518 return implicitRefs[i].Val; 519} 520 521inline void 522MachineInstr::addImplicitRef(Value* val, 523 bool isDef, 524 bool isDefAndUse) { 525 implicitRefs.push_back(ImplicitRef(val, isDef, isDefAndUse)); 526} 527 528inline void 529MachineInstr::setImplicitRef(unsigned int i, 530 Value* val, 531 bool isDef, 532 bool isDefAndUse) 533{ 534 assert(i < implicitRefs.size() && "setImplicitRef() out of range!"); 535 implicitRefs[i].Val = val; 536 implicitRefs[i].isDef = isDef; 537 implicitRefs[i].isDefAndUse = isDefAndUse; 538} 539 540inline void 541MachineInstr::setOperandHi32(unsigned i) 542{ 543 operands[i].markHi32(); 544} 545 546inline void 547MachineInstr::setOperandLo32(unsigned i) 548{ 549 operands[i].markLo32(); 550} 551 552inline void 553MachineInstr::setOperandHi64(unsigned i) 554{ 555 operands[i].markHi64(); 556} 557 558inline void 559MachineInstr::setOperandLo64(unsigned i) 560{ 561 operands[i].markLo64(); 562} 563 564 565//--------------------------------------------------------------------------- 566// Debugging Support 567//--------------------------------------------------------------------------- 568 569std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr); 570 571std::ostream& operator<< (std::ostream& os, const MachineOperand& mop); 572 573void PrintMachineInstructions(const Function *F); 574 575#endif 576