MachineInstr.h revision 376ad9fa9f66facc7100186f0a1f56c1be858ff5
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "Support/Annotation.h" 20#include "Support/iterator" 21#include <vector> 22 23namespace llvm { 24 25class Value; 26class Function; 27class MachineBasicBlock; 28class TargetMachine; 29class GlobalValue; 30 31typedef int MachineOpCode; 32 33//===----------------------------------------------------------------------===// 34/// Special flags on instructions that modify the opcode. 35/// These flags are unused for now, but having them enforces that some 36/// changes will be needed if they are used. 37/// 38enum MachineOpCodeFlags { 39 AnnulFlag, /// 1 if annul bit is set on a branch 40 PredTakenFlag, /// 1 if branch should be predicted taken 41 PredNotTakenFlag /// 1 if branch should be predicted not taken 42}; 43 44//===----------------------------------------------------------------------===// 45/// MOTy - MachineOperandType - This namespace contains an enum that describes 46/// how the machine operand is used by the instruction: is it read, defined, or 47/// both? Note that the MachineInstr/Operator class currently uses bool 48/// arguments to represent this information instead of an enum. Eventually this 49/// should change over to use this _easier to read_ representation instead. 50/// 51namespace MOTy { 52 enum UseType { 53 Use, /// This machine operand is only read by the instruction 54 Def, /// This machine operand is only written by the instruction 55 UseAndDef /// This machine operand is read AND written 56 }; 57} 58 59//===----------------------------------------------------------------------===// 60// class MachineOperand 61// 62// Purpose: 63// Representation of each machine instruction operand. 64// This class is designed so that you can allocate a vector of operands 65// first and initialize each one later. 66// 67// E.g, for this VM instruction: 68// ptr = alloca type, numElements 69// we generate 2 machine instructions on the SPARC: 70// 71// mul Constant, Numelements -> Reg 72// add %sp, Reg -> Ptr 73// 74// Each instruction has 3 operands, listed above. Of those: 75// - Reg, NumElements, and Ptr are of operand type MO_Register. 76// - Constant is of operand type MO_SignExtendedImmed on the SPARC. 77// 78// For the register operands, the virtual register type is as follows: 79// 80// - Reg will be of virtual register type MO_MInstrVirtualReg. The field 81// MachineInstr* minstr will point to the instruction that computes reg. 82// 83// - %sp will be of virtual register type MO_MachineReg. 84// The field regNum identifies the machine register. 85// 86// - NumElements will be of virtual register type MO_VirtualReg. 87// The field Value* value identifies the value. 88// 89// - Ptr will also be of virtual register type MO_VirtualReg. 90// Again, the field Value* value identifies the value. 91// 92//===----------------------------------------------------------------------===// 93 94struct MachineOperand { 95 enum MachineOperandType { 96 MO_VirtualRegister, // virtual register for *value 97 MO_MachineRegister, // pre-assigned machine register `regNum' 98 MO_CCRegister, 99 MO_SignExtendedImmed, 100 MO_UnextendedImmed, 101 MO_PCRelativeDisp, 102 MO_MachineBasicBlock, // MachineBasicBlock reference 103 MO_FrameIndex, // Abstract Stack Frame Index 104 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool 105 MO_ExternalSymbol, // Name of external global symbol 106 MO_GlobalAddress, // Address of a global value 107 }; 108 109private: 110 // Bit fields of the flags variable used for different operand properties 111 enum { 112 DEFFLAG = 0x01, // this is a def of the operand 113 USEFLAG = 0x02, // this is a use of the operand 114 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) 115 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) 116 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) 117 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) 118 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address 119 }; 120 121private: 122 union { 123 Value* value; // BasicBlockVal for a label operand. 124 // ConstantVal for a non-address immediate. 125 // Virtual register for an SSA operand, 126 // including hidden operands required for 127 // the generated machine code. 128 // LLVM global for MO_GlobalAddress. 129 130 int64_t immedVal; // Constant value for an explicit constant 131 132 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type 133 std::string *SymbolName; // For MO_ExternalSymbol type 134 }; 135 136 char flags; // see bit field definitions above 137 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 138 int regNum; // register number for an explicit register 139 // will be set for a value after reg allocation 140private: 141 MachineOperand() 142 : immedVal(0), 143 flags(0), 144 opType(MO_VirtualRegister), 145 regNum(-1) {} 146 147 MachineOperand(int64_t ImmVal, MachineOperandType OpTy) 148 : immedVal(ImmVal), 149 flags(0), 150 opType(OpTy), 151 regNum(-1) {} 152 153 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy) 154 : immedVal(0), 155 opType(OpTy), 156 regNum(Reg) { 157 switch (UseTy) { 158 case MOTy::Use: flags = USEFLAG; break; 159 case MOTy::Def: flags = DEFFLAG; break; 160 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break; 161 default: assert(0 && "Invalid value for UseTy!"); 162 } 163 } 164 165 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy, 166 bool isPCRelative = false) 167 : value(V), opType(OpTy), regNum(-1) { 168 switch (UseTy) { 169 case MOTy::Use: flags = USEFLAG; break; 170 case MOTy::Def: flags = DEFFLAG; break; 171 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break; 172 default: assert(0 && "Invalid value for UseTy!"); 173 } 174 if (isPCRelative) flags |= PCRELATIVE; 175 } 176 177 MachineOperand(MachineBasicBlock *mbb) 178 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {} 179 180 MachineOperand(const std::string &SymName, bool isPCRelative) 181 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0), 182 opType(MO_ExternalSymbol), regNum(-1) {} 183 184public: 185 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal), 186 flags(M.flags), 187 opType(M.opType), 188 regNum(M.regNum) { 189 if (isExternalSymbol()) 190 SymbolName = new std::string(M.getSymbolName()); 191 } 192 193 ~MachineOperand() { 194 if (isExternalSymbol()) 195 delete SymbolName; 196 } 197 198 const MachineOperand &operator=(const MachineOperand &MO) { 199 if (isExternalSymbol()) // if old operand had a symbol name, 200 delete SymbolName; // release old memory 201 immedVal = MO.immedVal; 202 flags = MO.flags; 203 opType = MO.opType; 204 regNum = MO.regNum; 205 if (isExternalSymbol()) 206 SymbolName = new std::string(MO.getSymbolName()); 207 return *this; 208 } 209 210 // Accessor methods. Caller is responsible for checking the 211 // operand type before invoking the corresponding accessor. 212 // 213 MachineOperandType getType() const { return opType; } 214 215 /// isPCRelative - This returns the value of the PCRELATIVE flag, which 216 /// indicates whether this operand should be emitted as a PC relative value 217 /// instead of a global address. This is used for operands of the forms: 218 /// MachineBasicBlock, GlobalAddress, ExternalSymbol 219 /// 220 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } 221 222 223 /// isRegister - Return true if this operand is a register operand. 224 /// 225 /// Note: In the sparc backend, this only returns true for "machine 226 /// registers", not for "virtual registers". 227 /// 228 bool isRegister() const { return opType == MO_MachineRegister; } 229 230 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } 231 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } 232 bool isImmediate() const { 233 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; 234 } 235 bool isFrameIndex() const { return opType == MO_FrameIndex; } 236 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } 237 bool isGlobalAddress() const { return opType == MO_GlobalAddress; } 238 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } 239 240 Value* getVRegValue() const { 241 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 242 isPCRelativeDisp()); 243 return value; 244 } 245 Value* getVRegValueOrNull() const { 246 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 247 isPCRelativeDisp()) ? value : NULL; 248 } 249 int getMachineRegNum() const { 250 assert(opType == MO_MachineRegister); 251 return regNum; 252 } 253 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; } 254 void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; } 255 256 MachineBasicBlock *getMachineBasicBlock() const { 257 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!"); 258 return MBB; 259 } 260 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; } 261 unsigned getConstantPoolIndex() const { 262 assert(isConstantPoolIndex()); 263 return immedVal; 264 } 265 266 GlobalValue *getGlobal() const { 267 assert(isGlobalAddress()); 268 return (GlobalValue*)value; 269 } 270 271 const std::string &getSymbolName() const { 272 assert(isExternalSymbol()); 273 return *SymbolName; 274 } 275 276 bool isUse () const { return flags & USEFLAG; } 277 MachineOperand& setUse () { flags |= USEFLAG; return *this; } 278 bool isDef () const { return flags & DEFFLAG; } 279 MachineOperand& setDef () { flags |= DEFFLAG; return *this; } 280 bool isHiBits32 () const { return flags & HIFLAG32; } 281 bool isLoBits32 () const { return flags & LOFLAG32; } 282 bool isHiBits64 () const { return flags & HIFLAG64; } 283 bool isLoBits64 () const { return flags & LOFLAG64; } 284 285 // used to check if a machine register has been allocated to this operand 286 bool hasAllocatedReg() const { 287 return (regNum >= 0 && 288 (opType == MO_VirtualRegister || opType == MO_CCRegister || 289 opType == MO_MachineRegister)); 290 } 291 292 // used to get the reg number if when one is allocated 293 int getAllocatedRegNum() const { 294 assert(hasAllocatedReg()); 295 return regNum; 296 } 297 298 // ********** TODO: get rid of this duplicate code! *********** 299 unsigned getReg() const { 300 return getAllocatedRegNum(); 301 } 302 void setReg(unsigned Reg) { 303 assert(hasAllocatedReg() && "This operand cannot have a register number!"); 304 regNum = Reg; 305 } 306 307 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 308 309private: 310 311 // Construction methods needed for fine-grain control. 312 // These must be accessed via coresponding methods in MachineInstr. 313 void markHi32() { flags |= HIFLAG32; } 314 void markLo32() { flags |= LOFLAG32; } 315 void markHi64() { flags |= HIFLAG64; } 316 void markLo64() { flags |= LOFLAG64; } 317 318 // Replaces the Value with its corresponding physical register after 319 // register allocation is complete 320 void setRegForValue(int reg) { 321 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 322 opType == MO_MachineRegister); 323 regNum = reg; 324 } 325 326 friend class MachineInstr; 327}; 328 329 330//===----------------------------------------------------------------------===// 331// class MachineInstr 332// 333// Purpose: 334// Representation of each machine instruction. 335// 336// MachineOpCode must be an enum, defined separately for each target. 337// E.g., It is defined in SparcInstructionSelection.h for the SPARC. 338// 339// There are 2 kinds of operands: 340// 341// (1) Explicit operands of the machine instruction in vector operands[] 342// 343// (2) "Implicit operands" are values implicitly used or defined by the 344// machine instruction, such as arguments to a CALL, return value of 345// a CALL (if any), and return value of a RETURN. 346//===----------------------------------------------------------------------===// 347 348class MachineInstr { 349 int opCode; // the opcode 350 unsigned opCodeFlags; // flags modifying instrn behavior 351 std::vector<MachineOperand> operands; // the operands 352 unsigned numImplicitRefs; // number of implicit operands 353 354 // OperandComplete - Return true if it's illegal to add a new operand 355 bool OperandsComplete() const; 356 357 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT 358 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 359public: 360 MachineInstr(int Opcode, unsigned numOperands); 361 362 /// MachineInstr ctor - This constructor only does a _reserve_ of the 363 /// operands, not a resize for them. It is expected that if you use this that 364 /// you call add* methods below to fill up the operands, instead of the Set 365 /// methods. Eventually, the "resizing" ctors will be phased out. 366 /// 367 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY); 368 369 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 370 /// the MachineInstr is created and added to the end of the specified basic 371 /// block. 372 /// 373 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps); 374 375 376 // The opcode. 377 // 378 const int getOpcode() const { return opCode; } 379 const int getOpCode() const { return opCode; } 380 381 // Opcode flags. 382 // 383 unsigned getOpCodeFlags() const { return opCodeFlags; } 384 385 // 386 // Access to explicit operands of the instruction 387 // 388 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 389 390 const MachineOperand& getOperand(unsigned i) const { 391 assert(i < getNumOperands() && "getOperand() out of range!"); 392 return operands[i]; 393 } 394 MachineOperand& getOperand(unsigned i) { 395 assert(i < getNumOperands() && "getOperand() out of range!"); 396 return operands[i]; 397 } 398 399 // 400 // Access to explicit or implicit operands of the instruction 401 // This returns the i'th entry in the operand vector. 402 // That represents the i'th explicit operand or the (i-N)'th implicit operand, 403 // depending on whether i < N or i >= N. 404 // 405 const MachineOperand& getExplOrImplOperand(unsigned i) const { 406 assert(i < operands.size() && "getExplOrImplOperand() out of range!"); 407 return (i < getNumOperands()? getOperand(i) 408 : getImplicitOp(i - getNumOperands())); 409 } 410 411 // 412 // Access to implicit operands of the instruction 413 // 414 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 415 416 MachineOperand& getImplicitOp(unsigned i) { 417 assert(i < numImplicitRefs && "implicit ref# out of range!"); 418 return operands[i + operands.size() - numImplicitRefs]; 419 } 420 const MachineOperand& getImplicitOp(unsigned i) const { 421 assert(i < numImplicitRefs && "implicit ref# out of range!"); 422 return operands[i + operands.size() - numImplicitRefs]; 423 } 424 425 Value* getImplicitRef(unsigned i) { 426 return getImplicitOp(i).getVRegValue(); 427 } 428 const Value* getImplicitRef(unsigned i) const { 429 return getImplicitOp(i).getVRegValue(); 430 } 431 432 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) { 433 ++numImplicitRefs; 434 addRegOperand(V, isDef, isDefAndUse); 435 } 436 void setImplicitRef(unsigned i, Value* V) { 437 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 438 SetMachineOperandVal(i + getNumOperands(), 439 MachineOperand::MO_VirtualRegister, V); 440 } 441 442 // 443 // Debugging support 444 // 445 void print(std::ostream &OS, const TargetMachine &TM) const; 446 void dump() const; 447 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 448 449 // 450 // Define iterators to access the Value operands of the Machine Instruction. 451 // Note that these iterators only enumerate the explicit operands. 452 // begin() and end() are defined to produce these iterators... 453 // 454 template<class _MI, class _V> class ValOpIterator; 455 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 456 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 457 458 459 //===--------------------------------------------------------------------===// 460 // Accessors to add operands when building up machine instructions 461 // 462 463 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 464 /// operands list... 465 /// 466 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 467 assert(!OperandsComplete() && 468 "Trying to add an operand to a machine instr that is already done!"); 469 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 470 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def))); 471 } 472 473 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use, 474 bool isPCRelative = false) { 475 assert(!OperandsComplete() && 476 "Trying to add an operand to a machine instr that is already done!"); 477 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 478 UTy, isPCRelative)); 479 } 480 481 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) { 482 assert(!OperandsComplete() && 483 "Trying to add an operand to a machine instr that is already done!"); 484 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, 485 false)); 486 } 487 488 489 /// addRegOperand - Add a symbolic virtual register reference... 490 /// 491 void addRegOperand(int reg, bool isDef) { 492 assert(!OperandsComplete() && 493 "Trying to add an operand to a machine instr that is already done!"); 494 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 495 isDef ? MOTy::Def : MOTy::Use)); 496 } 497 498 /// addRegOperand - Add a symbolic virtual register reference... 499 /// 500 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 501 assert(!OperandsComplete() && 502 "Trying to add an operand to a machine instr that is already done!"); 503 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 504 UTy)); 505 } 506 507 /// addPCDispOperand - Add a PC relative displacement operand to the MI 508 /// 509 void addPCDispOperand(Value *V) { 510 assert(!OperandsComplete() && 511 "Trying to add an operand to a machine instr that is already done!"); 512 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp, 513 MOTy::Use)); 514 } 515 516 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 517 /// 518 void addMachineRegOperand(int reg, bool isDef) { 519 assert(!OperandsComplete() && 520 "Trying to add an operand to a machine instr that is already done!"); 521 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 522 isDef ? MOTy::Def : MOTy::Use)); 523 } 524 525 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 526 /// 527 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 528 assert(!OperandsComplete() && 529 "Trying to add an operand to a machine instr that is already done!"); 530 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 531 UTy)); 532 } 533 534 /// addZeroExtImmOperand - Add a zero extended constant argument to the 535 /// machine instruction. 536 /// 537 void addZeroExtImmOperand(int64_t intValue) { 538 assert(!OperandsComplete() && 539 "Trying to add an operand to a machine instr that is already done!"); 540 operands.push_back(MachineOperand(intValue, 541 MachineOperand::MO_UnextendedImmed)); 542 } 543 544 /// addSignExtImmOperand - Add a zero extended constant argument to the 545 /// machine instruction. 546 /// 547 void addSignExtImmOperand(int64_t intValue) { 548 assert(!OperandsComplete() && 549 "Trying to add an operand to a machine instr that is already done!"); 550 operands.push_back(MachineOperand(intValue, 551 MachineOperand::MO_SignExtendedImmed)); 552 } 553 554 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { 555 assert(!OperandsComplete() && 556 "Trying to add an operand to a machine instr that is already done!"); 557 operands.push_back(MachineOperand(MBB)); 558 } 559 560 /// addFrameIndexOperand - Add an abstract frame index to the instruction 561 /// 562 void addFrameIndexOperand(unsigned Idx) { 563 assert(!OperandsComplete() && 564 "Trying to add an operand to a machine instr that is already done!"); 565 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); 566 } 567 568 /// addConstantPoolndexOperand - Add a constant pool object index to the 569 /// instruction. 570 /// 571 void addConstantPoolIndexOperand(unsigned I) { 572 assert(!OperandsComplete() && 573 "Trying to add an operand to a machine instr that is already done!"); 574 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); 575 } 576 577 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) { 578 assert(!OperandsComplete() && 579 "Trying to add an operand to a machine instr that is already done!"); 580 operands.push_back(MachineOperand((Value*)GV, 581 MachineOperand::MO_GlobalAddress, 582 MOTy::Use, isPCRelative)); 583 } 584 585 /// addExternalSymbolOperand - Add an external symbol operand to this instr 586 /// 587 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) { 588 operands.push_back(MachineOperand(SymName, isPCRelative)); 589 } 590 591 //===--------------------------------------------------------------------===// 592 // Accessors used to modify instructions in place. 593 // 594 // FIXME: Move this stuff to MachineOperand itself! 595 596 /// replace - Support to rewrite a machine instruction in place: for now, 597 /// simply replace() and then set new operands with Set.*Operand methods 598 /// below. 599 /// 600 void replace(int Opcode, unsigned numOperands); 601 602 /// setOpcode - Replace the opcode of the current instruction with a new one. 603 /// 604 void setOpcode(unsigned Op) { opCode = Op; } 605 606 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 607 /// fewer operand than it started with. 608 /// 609 void RemoveOperand(unsigned i) { 610 operands.erase(operands.begin()+i); 611 } 612 613 // Access to set the operands when building the machine instruction 614 // 615 void SetMachineOperandVal (unsigned i, 616 MachineOperand::MachineOperandType operandType, 617 Value* V); 618 619 void SetMachineOperandConst (unsigned i, 620 MachineOperand::MachineOperandType operandType, 621 int64_t intValue); 622 623 void SetMachineOperandReg(unsigned i, int regNum); 624 625 626 unsigned substituteValue(const Value* oldVal, Value* newVal, 627 bool defsOnly, bool notDefsAndUses, 628 bool& someArgsWereIgnored); 629 630 void setOperandHi32(unsigned i) { operands[i].markHi32(); } 631 void setOperandLo32(unsigned i) { operands[i].markLo32(); } 632 void setOperandHi64(unsigned i) { operands[i].markHi64(); } 633 void setOperandLo64(unsigned i) { operands[i].markLo64(); } 634 635 636 // SetRegForOperand - 637 // SetRegForImplicitRef - 638 // Mark an explicit or implicit operand with its allocated physical register. 639 // 640 void SetRegForOperand(unsigned i, int regNum); 641 void SetRegForImplicitRef(unsigned i, int regNum); 642 643 // 644 // Iterator to enumerate machine operands. 645 // 646 template<class MITy, class VTy> 647 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 648 unsigned i; 649 MITy MI; 650 651 void skipToNextVal() { 652 while (i < MI->getNumOperands() && 653 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || 654 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister) 655 && MI->getOperand(i).getVRegValue() != 0)) 656 ++i; 657 } 658 659 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 660 skipToNextVal(); 661 } 662 663 public: 664 typedef ValOpIterator<MITy, VTy> _Self; 665 666 inline VTy operator*() const { 667 return MI->getOperand(i).getVRegValue(); 668 } 669 670 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 671 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 672 673 inline VTy operator->() const { return operator*(); } 674 675 inline bool isUse() const { return MI->getOperand(i).isUse(); } 676 inline bool isDef() const { return MI->getOperand(i).isDef(); } 677 678 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 679 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 680 681 inline bool operator==(const _Self &y) const { 682 return i == y.i; 683 } 684 inline bool operator!=(const _Self &y) const { 685 return !operator==(y); 686 } 687 688 static _Self begin(MITy MI) { 689 return _Self(MI, 0); 690 } 691 static _Self end(MITy MI) { 692 return _Self(MI, MI->getNumOperands()); 693 } 694 }; 695 696 // define begin() and end() 697 val_op_iterator begin() { return val_op_iterator::begin(this); } 698 val_op_iterator end() { return val_op_iterator::end(this); } 699 700 const_val_op_iterator begin() const { 701 return const_val_op_iterator::begin(this); 702 } 703 const_val_op_iterator end() const { 704 return const_val_op_iterator::end(this); 705 } 706}; 707 708 709//===----------------------------------------------------------------------===// 710// Debugging Support 711 712std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI); 713std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO); 714void PrintMachineInstructions(const Function *F); 715 716} // End llvm namespace 717 718#endif 719