MachineInstr.h revision 518bb53485df640d7b7e3f6b0544099020c42aa7
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/ADT/ilist.h" 20#include "llvm/ADT/ilist_node.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/CodeGen/AsmPrinter.h" 23#include "llvm/CodeGen/MachineOperand.h" 24#include "llvm/Target/TargetInstrDesc.h" 25#include "llvm/Target/TargetOpcodes.h" 26#include "llvm/Support/DebugLoc.h" 27#include <vector> 28 29namespace llvm { 30 31class AliasAnalysis; 32class TargetInstrDesc; 33class TargetInstrInfo; 34class TargetRegisterInfo; 35class MachineFunction; 36class MachineMemOperand; 37 38//===----------------------------------------------------------------------===// 39/// MachineInstr - Representation of each machine instruction. 40/// 41class MachineInstr : public ilist_node<MachineInstr> { 42public: 43 typedef MachineMemOperand **mmo_iterator; 44 45private: 46 const TargetInstrDesc *TID; // Instruction descriptor. 47 unsigned short NumImplicitOps; // Number of implicit operands (which 48 // are determined at construction time). 49 50 unsigned short AsmPrinterFlags; // Various bits of information used by 51 // the AsmPrinter to emit helpful 52 // comments. This is *not* semantic 53 // information. Do not use this for 54 // anything other than to convey comment 55 // information to AsmPrinter. 56 57 std::vector<MachineOperand> Operands; // the operands 58 mmo_iterator MemRefs; // information on memory references 59 mmo_iterator MemRefsEnd; 60 MachineBasicBlock *Parent; // Pointer to the owning basic block. 61 DebugLoc debugLoc; // Source line information. 62 63 // OperandComplete - Return true if it's illegal to add a new operand 64 bool OperandsComplete() const; 65 66 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT 67 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 68 69 // Intrusive list support 70 friend struct ilist_traits<MachineInstr>; 71 friend struct ilist_traits<MachineBasicBlock>; 72 void setParent(MachineBasicBlock *P) { Parent = P; } 73 74 /// MachineInstr ctor - This constructor creates a copy of the given 75 /// MachineInstr in the given MachineFunction. 76 MachineInstr(MachineFunction &, const MachineInstr &); 77 78 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with 79 /// TID NULL and no operands. 80 MachineInstr(); 81 82 // The next two constructors have DebugLoc and non-DebugLoc versions; 83 // over time, the non-DebugLoc versions should be phased out and eventually 84 // removed. 85 86 /// MachineInstr ctor - This constructor create a MachineInstr and add the 87 /// implicit operands. It reserves space for number of operands specified by 88 /// TargetInstrDesc. The version with a DebugLoc should be preferred. 89 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); 90 91 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 92 /// the MachineInstr is created and added to the end of the specified basic 93 /// block. The version with a DebugLoc should be preferred. 94 /// 95 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); 96 97 /// MachineInstr ctor - This constructor create a MachineInstr and add the 98 /// implicit operands. It reserves space for number of operands specified by 99 /// TargetInstrDesc. An explicit DebugLoc is supplied. 100 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl, 101 bool NoImp = false); 102 103 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 104 /// the MachineInstr is created and added to the end of the specified basic 105 /// block. 106 /// 107 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 108 const TargetInstrDesc &TID); 109 110 ~MachineInstr(); 111 112 // MachineInstrs are pool-allocated and owned by MachineFunction. 113 friend class MachineFunction; 114 115public: 116 const MachineBasicBlock* getParent() const { return Parent; } 117 MachineBasicBlock* getParent() { return Parent; } 118 119 /// getAsmPrinterFlags - Return the asm printer flags bitvector. 120 /// 121 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; } 122 123 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set. 124 /// 125 bool getAsmPrinterFlag(AsmPrinter::CommentFlag Flag) const { 126 return AsmPrinterFlags & Flag; 127 } 128 129 /// setAsmPrinterFlag - Set a flag for the AsmPrinter. 130 /// 131 void setAsmPrinterFlag(unsigned short Flag) { 132 AsmPrinterFlags |= Flag; 133 } 134 135 /// getDebugLoc - Returns the debug location id of this MachineInstr. 136 /// 137 DebugLoc getDebugLoc() const { return debugLoc; } 138 139 /// getDesc - Returns the target instruction descriptor of this 140 /// MachineInstr. 141 const TargetInstrDesc &getDesc() const { return *TID; } 142 143 /// getOpcode - Returns the opcode of this MachineInstr. 144 /// 145 int getOpcode() const { return TID->Opcode; } 146 147 /// Access to explicit operands of the instruction. 148 /// 149 unsigned getNumOperands() const { return (unsigned)Operands.size(); } 150 151 const MachineOperand& getOperand(unsigned i) const { 152 assert(i < getNumOperands() && "getOperand() out of range!"); 153 return Operands[i]; 154 } 155 MachineOperand& getOperand(unsigned i) { 156 assert(i < getNumOperands() && "getOperand() out of range!"); 157 return Operands[i]; 158 } 159 160 /// getNumExplicitOperands - Returns the number of non-implicit operands. 161 /// 162 unsigned getNumExplicitOperands() const; 163 164 /// Access to memory operands of the instruction 165 mmo_iterator memoperands_begin() const { return MemRefs; } 166 mmo_iterator memoperands_end() const { return MemRefsEnd; } 167 bool memoperands_empty() const { return MemRefsEnd == MemRefs; } 168 169 /// hasOneMemOperand - Return true if this instruction has exactly one 170 /// MachineMemOperand. 171 bool hasOneMemOperand() const { 172 return MemRefsEnd - MemRefs == 1; 173 } 174 175 /// isIdenticalTo - Return true if this instruction is identical to (same 176 /// opcode and same operands as) the specified instruction. 177 bool isIdenticalTo(const MachineInstr *Other) const { 178 if (Other->getOpcode() != getOpcode() || 179 Other->getNumOperands() != getNumOperands()) 180 return false; 181 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 182 if (!getOperand(i).isIdenticalTo(Other->getOperand(i))) 183 return false; 184 return true; 185 } 186 187 /// removeFromParent - This method unlinks 'this' from the containing basic 188 /// block, and returns it, but does not delete it. 189 MachineInstr *removeFromParent(); 190 191 /// eraseFromParent - This method unlinks 'this' from the containing basic 192 /// block and deletes it. 193 void eraseFromParent(); 194 195 /// isLabel - Returns true if the MachineInstr represents a label. 196 /// 197 bool isLabel() const { 198 return getOpcode() == TargetOpcode::DBG_LABEL || 199 getOpcode() == TargetOpcode::EH_LABEL || 200 getOpcode() == TargetOpcode::GC_LABEL; 201 } 202 203 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } 204 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 205 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 206 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 207 208 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } 209 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 210 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 211 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } 212 bool isExtractSubreg() const { 213 return getOpcode() == TargetOpcode::EXTRACT_SUBREG; 214 } 215 bool isInsertSubreg() const { 216 return getOpcode() == TargetOpcode::INSERT_SUBREG; 217 } 218 bool isSubregToReg() const { 219 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 220 } 221 222 /// readsRegister - Return true if the MachineInstr reads the specified 223 /// register. If TargetRegisterInfo is passed, then it also checks if there 224 /// is a read of a super-register. 225 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 226 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 227 } 228 229 /// killsRegister - Return true if the MachineInstr kills the specified 230 /// register. If TargetRegisterInfo is passed, then it also checks if there is 231 /// a kill of a super-register. 232 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 233 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 234 } 235 236 /// modifiesRegister - Return true if the MachineInstr modifies the 237 /// specified register. If TargetRegisterInfo is passed, then it also checks 238 /// if there is a def of a super-register. 239 bool modifiesRegister(unsigned Reg, 240 const TargetRegisterInfo *TRI = NULL) const { 241 return findRegisterDefOperandIdx(Reg, false, TRI) != -1; 242 } 243 244 /// registerDefIsDead - Returns true if the register is dead in this machine 245 /// instruction. If TargetRegisterInfo is passed, then it also checks 246 /// if there is a dead def of a super-register. 247 bool registerDefIsDead(unsigned Reg, 248 const TargetRegisterInfo *TRI = NULL) const { 249 return findRegisterDefOperandIdx(Reg, true, TRI) != -1; 250 } 251 252 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of 253 /// the specific register or -1 if it is not found. It further tightens 254 /// the search criteria to a use that kills the register if isKill is true. 255 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 256 const TargetRegisterInfo *TRI = NULL) const; 257 258 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns 259 /// a pointer to the MachineOperand rather than an index. 260 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, 261 const TargetRegisterInfo *TRI = NULL) { 262 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 263 return (Idx == -1) ? NULL : &getOperand(Idx); 264 } 265 266 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of 267 /// the specified register or -1 if it is not found. If isDead is true, defs 268 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 269 /// also checks if there is a def of a super-register. 270 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false, 271 const TargetRegisterInfo *TRI = NULL) const; 272 273 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns 274 /// a pointer to the MachineOperand rather than an index. 275 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, 276 const TargetRegisterInfo *TRI = NULL) { 277 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI); 278 return (Idx == -1) ? NULL : &getOperand(Idx); 279 } 280 281 /// findFirstPredOperandIdx() - Find the index of the first operand in the 282 /// operand list that is used to represent the predicate. It returns -1 if 283 /// none is found. 284 int findFirstPredOperandIdx() const; 285 286 /// isRegTiedToUseOperand - Given the index of a register def operand, 287 /// check if the register def is tied to a source operand, due to either 288 /// two-address elimination or inline assembly constraints. Returns the 289 /// first tied use operand index by reference is UseOpIdx is not null. 290 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const; 291 292 /// isRegTiedToDefOperand - Return true if the use operand of the specified 293 /// index is tied to an def operand. It also returns the def operand index by 294 /// reference if DefOpIdx is not null. 295 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const; 296 297 /// copyKillDeadInfo - Copies kill / dead operand properties from MI. 298 /// 299 void copyKillDeadInfo(const MachineInstr *MI); 300 301 /// copyPredicates - Copies predicate operand(s) from MI. 302 void copyPredicates(const MachineInstr *MI); 303 304 /// addRegisterKilled - We have determined MI kills a register. Look for the 305 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 306 /// add a implicit operand if it's not found. Returns true if the operand 307 /// exists / is added. 308 bool addRegisterKilled(unsigned IncomingReg, 309 const TargetRegisterInfo *RegInfo, 310 bool AddIfNotFound = false); 311 312 /// addRegisterDead - We have determined MI defined a register without a use. 313 /// Look for the operand that defines it and mark it as IsDead. If 314 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 315 /// true if the operand exists / is added. 316 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, 317 bool AddIfNotFound = false); 318 319 /// addRegisterDefined - We have determined MI defines a register. Make sure 320 /// there is an operand defining Reg. 321 void addRegisterDefined(unsigned IncomingReg, 322 const TargetRegisterInfo *RegInfo); 323 324 /// isSafeToMove - Return true if it is safe to move this instruction. If 325 /// SawStore is set to true, it means that there is a store (or call) between 326 /// the instruction's location and its intended destination. 327 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore, 328 AliasAnalysis *AA) const; 329 330 /// isSafeToReMat - Return true if it's safe to rematerialize the specified 331 /// instruction which defined the specified register instead of copying it. 332 bool isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg, 333 AliasAnalysis *AA) const; 334 335 /// hasVolatileMemoryRef - Return true if this instruction may have a 336 /// volatile memory reference, or if the information describing the 337 /// memory reference is not available. Return false if it is known to 338 /// have no volatile memory references. 339 bool hasVolatileMemoryRef() const; 340 341 /// isInvariantLoad - Return true if this instruction is loading from a 342 /// location whose value is invariant across the function. For example, 343 /// loading a value from the constant pool or from from the argument area of 344 /// a function if it does not change. This should only return true of *all* 345 /// loads the instruction does are invariant (if it does multiple loads). 346 bool isInvariantLoad(AliasAnalysis *AA) const; 347 348 /// isConstantValuePHI - If the specified instruction is a PHI that always 349 /// merges together the same virtual register, return the register, otherwise 350 /// return 0. 351 unsigned isConstantValuePHI() const; 352 353 // 354 // Debugging support 355 // 356 void print(raw_ostream &OS, const TargetMachine *TM = 0) const; 357 void dump() const; 358 359 //===--------------------------------------------------------------------===// 360 // Accessors used to build up machine instructions. 361 362 /// addOperand - Add the specified operand to the instruction. If it is an 363 /// implicit operand, it is added to the end of the operand list. If it is 364 /// an explicit operand it is added at the end of the explicit operand list 365 /// (before the first implicit operand). 366 void addOperand(const MachineOperand &Op); 367 368 /// setDesc - Replace the instruction descriptor (thus opcode) of 369 /// the current instruction with a new one. 370 /// 371 void setDesc(const TargetInstrDesc &tid) { TID = &tid; } 372 373 /// setDebugLoc - Replace current source information with new such. 374 /// Avoid using this, the constructor argument is preferable. 375 /// 376 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } 377 378 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 379 /// fewer operand than it started with. 380 /// 381 void RemoveOperand(unsigned i); 382 383 /// addMemOperand - Add a MachineMemOperand to the machine instruction. 384 /// This function should be used only occasionally. The setMemRefs function 385 /// is the primary method for setting up a MachineInstr's MemRefs list. 386 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 387 388 /// setMemRefs - Assign this MachineInstr's memory reference descriptor 389 /// list. This does not transfer ownership. 390 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) { 391 MemRefs = NewMemRefs; 392 MemRefsEnd = NewMemRefsEnd; 393 } 394 395private: 396 /// getRegInfo - If this instruction is embedded into a MachineFunction, 397 /// return the MachineRegisterInfo object for the current function, otherwise 398 /// return null. 399 MachineRegisterInfo *getRegInfo(); 400 401 /// addImplicitDefUseOperands - Add all implicit def and use operands to 402 /// this instruction. 403 void addImplicitDefUseOperands(); 404 405 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 406 /// this instruction from their respective use lists. This requires that the 407 /// operands already be on their use lists. 408 void RemoveRegOperandsFromUseLists(); 409 410 /// AddRegOperandsToUseLists - Add all of the register operands in 411 /// this instruction from their respective use lists. This requires that the 412 /// operands not be on their use lists yet. 413 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); 414}; 415 416//===----------------------------------------------------------------------===// 417// Debugging Support 418 419inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 420 MI.print(OS); 421 return OS; 422} 423 424} // End llvm namespace 425 426#endif 427