MachineInstr.h revision 782ce955b2553305d9958a17d6482fe87243303d
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/Target/MRegisterInfo.h" 20#include "Support/Annotation.h" 21#include "Support/iterator" 22 23namespace llvm { 24 25class Value; 26class Function; 27class MachineBasicBlock; 28class TargetMachine; 29class GlobalValue; 30 31typedef int MachineOpCode; 32 33//===----------------------------------------------------------------------===// 34/// Special flags on instructions that modify the opcode. 35/// These flags are unused for now, but having them enforces that some 36/// changes will be needed if they are used. 37/// 38enum MachineOpCodeFlags { 39 AnnulFlag, /// 1 if annul bit is set on a branch 40 PredTakenFlag, /// 1 if branch should be predicted taken 41 PredNotTakenFlag /// 1 if branch should be predicted not taken 42}; 43 44//===----------------------------------------------------------------------===// 45/// MOTy - MachineOperandType - This namespace contains an enum that describes 46/// how the machine operand is used by the instruction: is it read, defined, or 47/// both? Note that the MachineInstr/Operator class currently uses bool 48/// arguments to represent this information instead of an enum. Eventually this 49/// should change over to use this _easier to read_ representation instead. 50/// 51namespace MOTy { 52 enum UseType { 53 Use, /// This machine operand is only read by the instruction 54 Def, /// This machine operand is only written by the instruction 55 UseAndDef /// This machine operand is read AND written 56 }; 57} 58 59//===----------------------------------------------------------------------===// 60// class MachineOperand 61// 62// Purpose: 63// Representation of each machine instruction operand. 64// This class is designed so that you can allocate a vector of operands 65// first and initialize each one later. 66// 67// E.g, for this VM instruction: 68// ptr = alloca type, numElements 69// we generate 2 machine instructions on the SPARC: 70// 71// mul Constant, Numelements -> Reg 72// add %sp, Reg -> Ptr 73// 74// Each instruction has 3 operands, listed above. Of those: 75// - Reg, NumElements, and Ptr are of operand type MO_Register. 76// - Constant is of operand type MO_SignExtendedImmed on the SPARC. 77// 78// For the register operands, the virtual register type is as follows: 79// 80// - Reg will be of virtual register type MO_MInstrVirtualReg. The field 81// MachineInstr* minstr will point to the instruction that computes reg. 82// 83// - %sp will be of virtual register type MO_MachineReg. 84// The field regNum identifies the machine register. 85// 86// - NumElements will be of virtual register type MO_VirtualReg. 87// The field Value* value identifies the value. 88// 89// - Ptr will also be of virtual register type MO_VirtualReg. 90// Again, the field Value* value identifies the value. 91// 92//===----------------------------------------------------------------------===// 93 94struct MachineOperand { 95 enum MachineOperandType { 96 MO_VirtualRegister, // virtual register for *value 97 MO_MachineRegister, // pre-assigned machine register `regNum' 98 MO_CCRegister, 99 MO_SignExtendedImmed, 100 MO_UnextendedImmed, 101 MO_PCRelativeDisp, 102 MO_MachineBasicBlock, // MachineBasicBlock reference 103 MO_FrameIndex, // Abstract Stack Frame Index 104 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool 105 MO_ExternalSymbol, // Name of external global symbol 106 MO_GlobalAddress, // Address of a global value 107 }; 108 109private: 110 // Bit fields of the flags variable used for different operand properties 111 enum { 112 DEFFLAG = 0x01, // this is a def of the operand 113 USEFLAG = 0x02, // this is a use of the operand 114 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) 115 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) 116 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) 117 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) 118 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address 119 }; 120 121private: 122 union { 123 Value* value; // BasicBlockVal for a label operand. 124 // ConstantVal for a non-address immediate. 125 // Virtual register for an SSA operand, 126 // including hidden operands required for 127 // the generated machine code. 128 // LLVM global for MO_GlobalAddress. 129 130 int64_t immedVal; // Constant value for an explicit constant 131 132 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type 133 std::string *SymbolName; // For MO_ExternalSymbol type 134 }; 135 136 char flags; // see bit field definitions above 137 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 138 int regNum; // register number for an explicit register 139 // will be set for a value after reg allocation 140private: 141 MachineOperand() 142 : immedVal(0), 143 flags(0), 144 opType(MO_VirtualRegister), 145 regNum(-1) {} 146 147 MachineOperand(int64_t ImmVal, MachineOperandType OpTy) 148 : immedVal(ImmVal), 149 flags(0), 150 opType(OpTy), 151 regNum(-1) {} 152 153 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy) 154 : immedVal(0), 155 opType(OpTy), 156 regNum(Reg) { 157 switch (UseTy) { 158 case MOTy::Use: flags = USEFLAG; break; 159 case MOTy::Def: flags = DEFFLAG; break; 160 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break; 161 default: assert(0 && "Invalid value for UseTy!"); 162 } 163 } 164 165 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy, 166 bool isPCRelative = false) 167 : value(V), opType(OpTy), regNum(-1) { 168 switch (UseTy) { 169 case MOTy::Use: flags = USEFLAG; break; 170 case MOTy::Def: flags = DEFFLAG; break; 171 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break; 172 default: assert(0 && "Invalid value for UseTy!"); 173 } 174 if (isPCRelative) flags |= PCRELATIVE; 175 } 176 177 MachineOperand(MachineBasicBlock *mbb) 178 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {} 179 180 MachineOperand(const std::string &SymName, bool isPCRelative) 181 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0), 182 opType(MO_ExternalSymbol), regNum(-1) {} 183 184public: 185 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal), 186 flags(M.flags), 187 opType(M.opType), 188 regNum(M.regNum) { 189 if (isExternalSymbol()) 190 SymbolName = new std::string(M.getSymbolName()); 191 } 192 193 ~MachineOperand() { 194 if (isExternalSymbol()) 195 delete SymbolName; 196 } 197 198 const MachineOperand &operator=(const MachineOperand &MO) { 199 if (isExternalSymbol()) // if old operand had a symbol name, 200 delete SymbolName; // release old memory 201 immedVal = MO.immedVal; 202 flags = MO.flags; 203 opType = MO.opType; 204 regNum = MO.regNum; 205 if (isExternalSymbol()) 206 SymbolName = new std::string(MO.getSymbolName()); 207 return *this; 208 } 209 210 // Accessor methods. Caller is responsible for checking the 211 // operand type before invoking the corresponding accessor. 212 // 213 MachineOperandType getType() const { return opType; } 214 215 /// isPCRelative - This returns the value of the PCRELATIVE flag, which 216 /// indicates whether this operand should be emitted as a PC relative value 217 /// instead of a global address. This is used for operands of the forms: 218 /// MachineBasicBlock, GlobalAddress, ExternalSymbol 219 /// 220 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } 221 222 223 // This is to finally stop caring whether we have a virtual or machine 224 // register -- an easier interface is to simply call both virtual and machine 225 // registers essentially the same, yet be able to distinguish when 226 // necessary. Thus the instruction selector can just add registers without 227 // abandon, and the register allocator won't be confused. 228 bool isVirtualRegister() const { 229 return (opType == MO_VirtualRegister || opType == MO_MachineRegister) 230 && regNum >= MRegisterInfo::FirstVirtualRegister; 231 } 232 bool isPhysicalRegister() const { 233 return (opType == MO_VirtualRegister || opType == MO_MachineRegister) 234 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister; 235 } 236 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();} 237 bool isMachineRegister() const { return !isVirtualRegister(); } 238 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } 239 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } 240 bool isImmediate() const { 241 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; 242 } 243 bool isFrameIndex() const { return opType == MO_FrameIndex; } 244 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } 245 bool isGlobalAddress() const { return opType == MO_GlobalAddress; } 246 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } 247 248 Value* getVRegValue() const { 249 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 250 isPCRelativeDisp()); 251 return value; 252 } 253 Value* getVRegValueOrNull() const { 254 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 255 isPCRelativeDisp()) ? value : NULL; 256 } 257 int getMachineRegNum() const { 258 assert(opType == MO_MachineRegister); 259 return regNum; 260 } 261 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; } 262 void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; } 263 264 MachineBasicBlock *getMachineBasicBlock() const { 265 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!"); 266 return MBB; 267 } 268 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; } 269 unsigned getConstantPoolIndex() const { 270 assert(isConstantPoolIndex()); 271 return immedVal; 272 } 273 274 GlobalValue *getGlobal() const { 275 assert(isGlobalAddress()); 276 return (GlobalValue*)value; 277 } 278 279 const std::string &getSymbolName() const { 280 assert(isExternalSymbol()); 281 return *SymbolName; 282 } 283 284 bool isUse () const { return flags & USEFLAG; } 285 bool isDef () const { return flags & DEFFLAG; } 286 bool isHiBits32 () const { return flags & HIFLAG32; } 287 bool isLoBits32 () const { return flags & LOFLAG32; } 288 bool isHiBits64 () const { return flags & HIFLAG64; } 289 bool isLoBits64 () const { return flags & LOFLAG64; } 290 291 MachineOperand& setUse () { flags |= USEFLAG; return *this; } 292 MachineOperand& setDef () { flags |= DEFFLAG; return *this; } 293 294 // used to check if a machine register has been allocated to this operand 295 bool hasAllocatedReg() const { 296 return (regNum >= 0 && 297 (opType == MO_VirtualRegister || opType == MO_CCRegister || 298 opType == MO_MachineRegister)); 299 } 300 301 // used to get the reg number if when one is allocated 302 int getAllocatedRegNum() const { 303 assert(hasAllocatedReg()); 304 return regNum; 305 } 306 307 // ********** TODO: get rid of this duplicate code! *********** 308 unsigned getReg() const { 309 return getAllocatedRegNum(); 310 } 311 void setReg(unsigned Reg) { 312 assert(hasAllocatedReg() && "This operand cannot have a register number!"); 313 regNum = Reg; 314 } 315 316 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 317 318private: 319 320 // Construction methods needed for fine-grain control. 321 // These must be accessed via coresponding methods in MachineInstr. 322 void markHi32() { flags |= HIFLAG32; } 323 void markLo32() { flags |= LOFLAG32; } 324 void markHi64() { flags |= HIFLAG64; } 325 void markLo64() { flags |= LOFLAG64; } 326 327 // Replaces the Value with its corresponding physical register after 328 // register allocation is complete 329 void setRegForValue(int reg) { 330 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 331 opType == MO_MachineRegister); 332 regNum = reg; 333 } 334 335 friend class MachineInstr; 336}; 337 338 339//===----------------------------------------------------------------------===// 340// class MachineInstr 341// 342// Purpose: 343// Representation of each machine instruction. 344// 345// MachineOpCode must be an enum, defined separately for each target. 346// E.g., It is defined in SparcInstructionSelection.h for the SPARC. 347// 348// There are 2 kinds of operands: 349// 350// (1) Explicit operands of the machine instruction in vector operands[] 351// 352// (2) "Implicit operands" are values implicitly used or defined by the 353// machine instruction, such as arguments to a CALL, return value of 354// a CALL (if any), and return value of a RETURN. 355//===----------------------------------------------------------------------===// 356 357class MachineInstr { 358 int opCode; // the opcode 359 unsigned opCodeFlags; // flags modifying instrn behavior 360 std::vector<MachineOperand> operands; // the operands 361 unsigned numImplicitRefs; // number of implicit operands 362 363 // OperandComplete - Return true if it's illegal to add a new operand 364 bool OperandsComplete() const; 365 366 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT 367 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 368public: 369 MachineInstr(int Opcode, unsigned numOperands); 370 371 /// MachineInstr ctor - This constructor only does a _reserve_ of the 372 /// operands, not a resize for them. It is expected that if you use this that 373 /// you call add* methods below to fill up the operands, instead of the Set 374 /// methods. Eventually, the "resizing" ctors will be phased out. 375 /// 376 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY); 377 378 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 379 /// the MachineInstr is created and added to the end of the specified basic 380 /// block. 381 /// 382 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps); 383 384 385 // The opcode. 386 // 387 const int getOpcode() const { return opCode; } 388 const int getOpCode() const { return opCode; } 389 390 // Opcode flags. 391 // 392 unsigned getOpCodeFlags() const { return opCodeFlags; } 393 394 // 395 // Access to explicit operands of the instruction 396 // 397 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 398 399 const MachineOperand& getOperand(unsigned i) const { 400 assert(i < getNumOperands() && "getOperand() out of range!"); 401 return operands[i]; 402 } 403 MachineOperand& getOperand(unsigned i) { 404 assert(i < getNumOperands() && "getOperand() out of range!"); 405 return operands[i]; 406 } 407 408 // 409 // Access to explicit or implicit operands of the instruction 410 // This returns the i'th entry in the operand vector. 411 // That represents the i'th explicit operand or the (i-N)'th implicit operand, 412 // depending on whether i < N or i >= N. 413 // 414 const MachineOperand& getExplOrImplOperand(unsigned i) const { 415 assert(i < operands.size() && "getExplOrImplOperand() out of range!"); 416 return (i < getNumOperands()? getOperand(i) 417 : getImplicitOp(i - getNumOperands())); 418 } 419 420 // 421 // Access to implicit operands of the instruction 422 // 423 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 424 425 MachineOperand& getImplicitOp(unsigned i) { 426 assert(i < numImplicitRefs && "implicit ref# out of range!"); 427 return operands[i + operands.size() - numImplicitRefs]; 428 } 429 const MachineOperand& getImplicitOp(unsigned i) const { 430 assert(i < numImplicitRefs && "implicit ref# out of range!"); 431 return operands[i + operands.size() - numImplicitRefs]; 432 } 433 434 Value* getImplicitRef(unsigned i) { 435 return getImplicitOp(i).getVRegValue(); 436 } 437 const Value* getImplicitRef(unsigned i) const { 438 return getImplicitOp(i).getVRegValue(); 439 } 440 441 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) { 442 ++numImplicitRefs; 443 addRegOperand(V, isDef, isDefAndUse); 444 } 445 void setImplicitRef(unsigned i, Value* V) { 446 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 447 SetMachineOperandVal(i + getNumOperands(), 448 MachineOperand::MO_VirtualRegister, V); 449 } 450 451 // 452 // Debugging support 453 // 454 void print(std::ostream &OS, const TargetMachine &TM) const; 455 void dump() const; 456 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 457 458 // 459 // Define iterators to access the Value operands of the Machine Instruction. 460 // Note that these iterators only enumerate the explicit operands. 461 // begin() and end() are defined to produce these iterators... 462 // 463 template<class _MI, class _V> class ValOpIterator; 464 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 465 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 466 467 468 //===--------------------------------------------------------------------===// 469 // Accessors to add operands when building up machine instructions 470 // 471 472 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 473 /// operands list... 474 /// 475 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 476 assert(!OperandsComplete() && 477 "Trying to add an operand to a machine instr that is already done!"); 478 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 479 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def))); 480 } 481 482 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use, 483 bool isPCRelative = false) { 484 assert(!OperandsComplete() && 485 "Trying to add an operand to a machine instr that is already done!"); 486 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 487 UTy, isPCRelative)); 488 } 489 490 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) { 491 assert(!OperandsComplete() && 492 "Trying to add an operand to a machine instr that is already done!"); 493 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, 494 false)); 495 } 496 497 498 /// addRegOperand - Add a symbolic virtual register reference... 499 /// 500 void addRegOperand(int reg, bool isDef) { 501 assert(!OperandsComplete() && 502 "Trying to add an operand to a machine instr that is already done!"); 503 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 504 isDef ? MOTy::Def : MOTy::Use)); 505 } 506 507 /// addRegOperand - Add a symbolic virtual register reference... 508 /// 509 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 510 assert(!OperandsComplete() && 511 "Trying to add an operand to a machine instr that is already done!"); 512 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 513 UTy)); 514 } 515 516 /// addPCDispOperand - Add a PC relative displacement operand to the MI 517 /// 518 void addPCDispOperand(Value *V) { 519 assert(!OperandsComplete() && 520 "Trying to add an operand to a machine instr that is already done!"); 521 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp, 522 MOTy::Use)); 523 } 524 525 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 526 /// 527 void addMachineRegOperand(int reg, bool isDef) { 528 assert(!OperandsComplete() && 529 "Trying to add an operand to a machine instr that is already done!"); 530 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 531 isDef ? MOTy::Def : MOTy::Use)); 532 } 533 534 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 535 /// 536 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 537 assert(!OperandsComplete() && 538 "Trying to add an operand to a machine instr that is already done!"); 539 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 540 UTy)); 541 } 542 543 /// addZeroExtImmOperand - Add a zero extended constant argument to the 544 /// machine instruction. 545 /// 546 void addZeroExtImmOperand(int64_t intValue) { 547 assert(!OperandsComplete() && 548 "Trying to add an operand to a machine instr that is already done!"); 549 operands.push_back(MachineOperand(intValue, 550 MachineOperand::MO_UnextendedImmed)); 551 } 552 553 /// addSignExtImmOperand - Add a zero extended constant argument to the 554 /// machine instruction. 555 /// 556 void addSignExtImmOperand(int64_t intValue) { 557 assert(!OperandsComplete() && 558 "Trying to add an operand to a machine instr that is already done!"); 559 operands.push_back(MachineOperand(intValue, 560 MachineOperand::MO_SignExtendedImmed)); 561 } 562 563 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { 564 assert(!OperandsComplete() && 565 "Trying to add an operand to a machine instr that is already done!"); 566 operands.push_back(MachineOperand(MBB)); 567 } 568 569 /// addFrameIndexOperand - Add an abstract frame index to the instruction 570 /// 571 void addFrameIndexOperand(unsigned Idx) { 572 assert(!OperandsComplete() && 573 "Trying to add an operand to a machine instr that is already done!"); 574 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); 575 } 576 577 /// addConstantPoolndexOperand - Add a constant pool object index to the 578 /// instruction. 579 /// 580 void addConstantPoolIndexOperand(unsigned I) { 581 assert(!OperandsComplete() && 582 "Trying to add an operand to a machine instr that is already done!"); 583 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); 584 } 585 586 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) { 587 assert(!OperandsComplete() && 588 "Trying to add an operand to a machine instr that is already done!"); 589 operands.push_back(MachineOperand((Value*)GV, 590 MachineOperand::MO_GlobalAddress, 591 MOTy::Use, isPCRelative)); 592 } 593 594 /// addExternalSymbolOperand - Add an external symbol operand to this instr 595 /// 596 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) { 597 operands.push_back(MachineOperand(SymName, isPCRelative)); 598 } 599 600 //===--------------------------------------------------------------------===// 601 // Accessors used to modify instructions in place. 602 // 603 // FIXME: Move this stuff to MachineOperand itself! 604 605 /// replace - Support to rewrite a machine instruction in place: for now, 606 /// simply replace() and then set new operands with Set.*Operand methods 607 /// below. 608 /// 609 void replace(int Opcode, unsigned numOperands); 610 611 /// setOpcode - Replace the opcode of the current instruction with a new one. 612 /// 613 void setOpcode(unsigned Op) { opCode = Op; } 614 615 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 616 /// fewer operand than it started with. 617 /// 618 void RemoveOperand(unsigned i) { 619 operands.erase(operands.begin()+i); 620 } 621 622 // Access to set the operands when building the machine instruction 623 // 624 void SetMachineOperandVal (unsigned i, 625 MachineOperand::MachineOperandType operandType, 626 Value* V); 627 628 void SetMachineOperandConst (unsigned i, 629 MachineOperand::MachineOperandType operandType, 630 int64_t intValue); 631 632 void SetMachineOperandReg(unsigned i, int regNum); 633 634 635 unsigned substituteValue(const Value* oldVal, Value* newVal, 636 bool defsOnly, bool notDefsAndUses, 637 bool& someArgsWereIgnored); 638 639 void setOperandHi32(unsigned i) { operands[i].markHi32(); } 640 void setOperandLo32(unsigned i) { operands[i].markLo32(); } 641 void setOperandHi64(unsigned i) { operands[i].markHi64(); } 642 void setOperandLo64(unsigned i) { operands[i].markLo64(); } 643 644 645 // SetRegForOperand - 646 // SetRegForImplicitRef - 647 // Mark an explicit or implicit operand with its allocated physical register. 648 // 649 void SetRegForOperand(unsigned i, int regNum); 650 void SetRegForImplicitRef(unsigned i, int regNum); 651 652 // 653 // Iterator to enumerate machine operands. 654 // 655 template<class MITy, class VTy> 656 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 657 unsigned i; 658 MITy MI; 659 660 void skipToNextVal() { 661 while (i < MI->getNumOperands() && 662 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || 663 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister) 664 && MI->getOperand(i).getVRegValue() != 0)) 665 ++i; 666 } 667 668 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 669 skipToNextVal(); 670 } 671 672 public: 673 typedef ValOpIterator<MITy, VTy> _Self; 674 675 inline VTy operator*() const { 676 return MI->getOperand(i).getVRegValue(); 677 } 678 679 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 680 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 681 682 inline VTy operator->() const { return operator*(); } 683 684 inline bool isUse() const { return MI->getOperand(i).isUse(); } 685 inline bool isDef() const { return MI->getOperand(i).isDef(); } 686 687 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 688 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 689 690 inline bool operator==(const _Self &y) const { 691 return i == y.i; 692 } 693 inline bool operator!=(const _Self &y) const { 694 return !operator==(y); 695 } 696 697 static _Self begin(MITy MI) { 698 return _Self(MI, 0); 699 } 700 static _Self end(MITy MI) { 701 return _Self(MI, MI->getNumOperands()); 702 } 703 }; 704 705 // define begin() and end() 706 val_op_iterator begin() { return val_op_iterator::begin(this); } 707 val_op_iterator end() { return val_op_iterator::end(this); } 708 709 const_val_op_iterator begin() const { 710 return const_val_op_iterator::begin(this); 711 } 712 const_val_op_iterator end() const { 713 return const_val_op_iterator::end(this); 714 } 715}; 716 717 718//===----------------------------------------------------------------------===// 719// Debugging Support 720 721std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI); 722std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO); 723void PrintMachineInstructions(const Function *F); 724 725} // End llvm namespace 726 727#endif 728