MachineInstr.h revision 7b55d4fce2c2b8eebbb1fc654400c7d46fd6bfba
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/ADT/iterator" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class Value; 26class Function; 27class MachineBasicBlock; 28class TargetMachine; 29class GlobalValue; 30 31template <typename T> struct ilist_traits; 32template <typename T> struct ilist; 33 34typedef short MachineOpCode; 35 36//===----------------------------------------------------------------------===// 37// class MachineOperand 38// 39// Purpose: 40// Representation of each machine instruction operand. 41// This class is designed so that you can allocate a vector of operands 42// first and initialize each one later. 43// 44// E.g, for this VM instruction: 45// ptr = alloca type, numElements 46// we generate 2 machine instructions on the SPARC: 47// 48// mul Constant, Numelements -> Reg 49// add %sp, Reg -> Ptr 50// 51// Each instruction has 3 operands, listed above. Of those: 52// - Reg, NumElements, and Ptr are of operand type MO_Register. 53// - Constant is of operand type MO_SignExtendedImmed on the SPARC. 54// 55// For the register operands, the virtual register type is as follows: 56// 57// - Reg will be of virtual register type MO_MInstrVirtualReg. The field 58// MachineInstr* minstr will point to the instruction that computes reg. 59// 60// - %sp will be of virtual register type MO_MachineReg. 61// The field regNum identifies the machine register. 62// 63// - NumElements will be of virtual register type MO_VirtualReg. 64// The field Value* value identifies the value. 65// 66// - Ptr will also be of virtual register type MO_VirtualReg. 67// Again, the field Value* value identifies the value. 68// 69//===----------------------------------------------------------------------===// 70 71struct MachineOperand { 72private: 73 // Bit fields of the flags variable used for different operand properties 74 enum { 75 DEFFLAG = 0x01, // this is a def of the operand 76 USEFLAG = 0x02, // this is a use of the operand 77 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) 78 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) 79 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) 80 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) 81 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address 82 }; 83 84public: 85 // UseType - This enum describes how the machine operand is used by 86 // the instruction. Note that the MachineInstr/Operator class 87 // currently uses bool arguments to represent this information 88 // instead of an enum. Eventually this should change over to use 89 // this _easier to read_ representation instead. 90 // 91 enum UseType { 92 Use = USEFLAG, /// only read 93 Def = DEFFLAG, /// only written 94 UseAndDef = Use | Def /// read AND written 95 }; 96 97 enum MachineOperandType { 98 MO_VirtualRegister, // virtual register for *value 99 MO_MachineRegister, // pre-assigned machine register `regNum' 100 MO_CCRegister, 101 MO_SignExtendedImmed, 102 MO_UnextendedImmed, 103 MO_PCRelativeDisp, 104 MO_MachineBasicBlock, // MachineBasicBlock reference 105 MO_FrameIndex, // Abstract Stack Frame Index 106 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool 107 MO_ExternalSymbol, // Name of external global symbol 108 MO_GlobalAddress, // Address of a global value 109 }; 110 111private: 112 union { 113 Value* value; // BasicBlockVal for a label operand. 114 // ConstantVal for a non-address immediate. 115 // Virtual register for an SSA operand, 116 // including hidden operands required for 117 // the generated machine code. 118 // LLVM global for MO_GlobalAddress. 119 120 int immedVal; // Constant value for an explicit constant 121 122 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type 123 const char *SymbolName; // For MO_ExternalSymbol type 124 } contents; 125 126 char flags; // see bit field definitions above 127 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 128 union { 129 int regNum; // register number for an explicit register 130 // will be set for a value after reg allocation 131 132 int offset; // Offset to address of global or external, only 133 // valid for MO_GlobalAddress and MO_ExternalSym 134 } extra; 135 136 void zeroContents () { 137 memset (&contents, 0, sizeof (contents)); 138 memset (&extra, 0, sizeof (extra)); 139 } 140 141 MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister) 142 : flags(0), opType(OpTy) { 143 zeroContents (); 144 contents.immedVal = ImmVal; 145 extra.regNum = -1; 146 } 147 148 MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) 149 : flags(UseTy), opType(OpTy) { 150 zeroContents (); 151 extra.regNum = Reg; 152 } 153 154 MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy, 155 bool isPCRelative = false) 156 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { 157 assert(OpTy != MachineOperand::MO_GlobalAddress); 158 zeroContents(); 159 contents.value = V; 160 extra.regNum = -1; 161 } 162 163 MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy, 164 bool isPCRelative = false, int Offset = 0) 165 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { 166 assert(OpTy == MachineOperand::MO_GlobalAddress); 167 zeroContents (); 168 contents.value = (Value*)V; 169 extra.offset = Offset; 170 } 171 172 MachineOperand(MachineBasicBlock *mbb) 173 : flags(0), opType(MO_MachineBasicBlock) { 174 zeroContents (); 175 contents.MBB = mbb; 176 extra.regNum = -1; 177 } 178 179 MachineOperand(const char *SymName, bool isPCRelative, int Offset) 180 : flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) { 181 zeroContents (); 182 contents.SymbolName = SymName; 183 extra.offset = Offset; 184 } 185 186public: 187 MachineOperand(const MachineOperand &M) 188 : flags(M.flags), opType(M.opType) { 189 zeroContents (); 190 contents = M.contents; 191 extra = M.extra; 192 } 193 194 195 ~MachineOperand() {} 196 197 const MachineOperand &operator=(const MachineOperand &MO) { 198 contents = MO.contents; 199 flags = MO.flags; 200 opType = MO.opType; 201 extra = MO.extra; 202 return *this; 203 } 204 205 /// getType - Returns the MachineOperandType for this operand. 206 /// 207 MachineOperandType getType() const { return opType; } 208 209 /// getUseType - Returns the MachineOperandUseType of this operand. 210 /// 211 UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } 212 213 /// isPCRelative - This returns the value of the PCRELATIVE flag, which 214 /// indicates whether this operand should be emitted as a PC relative value 215 /// instead of a global address. This is used for operands of the forms: 216 /// MachineBasicBlock, GlobalAddress, ExternalSymbol 217 /// 218 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } 219 220 /// isRegister - Return true if this operand is a register operand. The X86 221 /// backend currently can't decide whether to use MO_MR or MO_VR to represent 222 /// them, so we accept both. 223 /// 224 /// Note: The sparc backend should not use this method. 225 /// 226 bool isRegister() const { 227 return opType == MO_MachineRegister || opType == MO_VirtualRegister; 228 } 229 230 /// Accessors that tell you what kind of MachineOperand you're looking at. 231 /// 232 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } 233 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } 234 bool isImmediate() const { 235 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; 236 } 237 bool isFrameIndex() const { return opType == MO_FrameIndex; } 238 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } 239 bool isGlobalAddress() const { return opType == MO_GlobalAddress; } 240 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } 241 242 /// getVRegValueOrNull - Get the Value* out of a MachineOperand if it 243 /// has one. This is deprecated and only used by the SPARC v9 backend. 244 /// 245 Value* getVRegValueOrNull() const { 246 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 247 isPCRelativeDisp()) ? contents.value : NULL; 248 } 249 250 /// MachineOperand accessors that only work on certain types of 251 /// MachineOperand... 252 /// 253 Value* getVRegValue() const { 254 assert ((opType == MO_VirtualRegister || opType == MO_CCRegister 255 || isPCRelativeDisp()) && "Wrong MachineOperand accessor"); 256 return contents.value; 257 } 258 int getMachineRegNum() const { 259 assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor"); 260 return extra.regNum; 261 } 262 int getImmedValue() const { 263 assert(isImmediate() && "Wrong MachineOperand accessor"); 264 return contents.immedVal; 265 } 266 MachineBasicBlock *getMachineBasicBlock() const { 267 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); 268 return contents.MBB; 269 } 270 void setMachineBasicBlock(MachineBasicBlock *MBB) { 271 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); 272 contents.MBB = MBB; 273 } 274 int getFrameIndex() const { 275 assert(isFrameIndex() && "Wrong MachineOperand accessor"); 276 return contents.immedVal; 277 } 278 unsigned getConstantPoolIndex() const { 279 assert(isConstantPoolIndex() && "Wrong MachineOperand accessor"); 280 return contents.immedVal; 281 } 282 GlobalValue *getGlobal() const { 283 assert(isGlobalAddress() && "Wrong MachineOperand accessor"); 284 return (GlobalValue*)contents.value; 285 } 286 int getOffset() const { 287 assert((isGlobalAddress() || isExternalSymbol()) && 288 "Wrong MachineOperand accessor"); 289 return extra.offset; 290 } 291 const char *getSymbolName() const { 292 assert(isExternalSymbol() && "Wrong MachineOperand accessor"); 293 return contents.SymbolName; 294 } 295 296 /// MachineOperand methods for testing that work on any kind of 297 /// MachineOperand... 298 /// 299 bool isUse () const { return flags & USEFLAG; } 300 MachineOperand& setUse () { flags |= USEFLAG; return *this; } 301 bool isDef () const { return flags & DEFFLAG; } 302 MachineOperand& setDef () { flags |= DEFFLAG; return *this; } 303 bool isHiBits32 () const { return flags & HIFLAG32; } 304 bool isLoBits32 () const { return flags & LOFLAG32; } 305 bool isHiBits64 () const { return flags & HIFLAG64; } 306 bool isLoBits64 () const { return flags & LOFLAG64; } 307 308 /// hasAllocatedReg - Returns true iff a machine register has been 309 /// allocated to this operand. 310 /// 311 bool hasAllocatedReg() const { 312 return (extra.regNum >= 0 && 313 (opType == MO_VirtualRegister || opType == MO_CCRegister || 314 opType == MO_MachineRegister)); 315 } 316 317 /// getReg - Returns the register number. It is a runtime error to call this 318 /// if a register is not allocated. 319 /// 320 unsigned getReg() const { 321 assert(hasAllocatedReg()); 322 return extra.regNum; 323 } 324 325 /// MachineOperand mutators... 326 /// 327 void setReg(unsigned Reg) { 328 // This method's comment used to say: 'TODO: get rid of this duplicate 329 // code.' It's not clear where the duplication is. 330 assert(hasAllocatedReg() && "This operand cannot have a register number!"); 331 extra.regNum = Reg; 332 } 333 334 void setValueReg(Value *val) { 335 assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*"); 336 contents.value = val; 337 } 338 339 void setImmedValue(int immVal) { 340 assert(isImmediate() && "Wrong MachineOperand mutator"); 341 contents.immedVal = immVal; 342 } 343 344 void setOffset(int Offset) { 345 assert((isGlobalAddress() || isExternalSymbol()) && 346 "Wrong MachineOperand accessor"); 347 extra.offset = Offset; 348 } 349 350 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 351 352 /// markHi32, markLo32, etc. - These methods are deprecated and only used by 353 /// the SPARC v9 back-end. 354 /// 355 void markHi32() { flags |= HIFLAG32; } 356 void markLo32() { flags |= LOFLAG32; } 357 void markHi64() { flags |= HIFLAG64; } 358 void markLo64() { flags |= LOFLAG64; } 359 360private: 361 /// setRegForValue - Replaces the Value with its corresponding physical 362 /// register after register allocation is complete. This is deprecated 363 /// and only used by the SPARC v9 back-end. 364 /// 365 void setRegForValue(int reg) { 366 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 367 opType == MO_MachineRegister); 368 extra.regNum = reg; 369 } 370 371 friend class MachineInstr; 372}; 373 374 375//===----------------------------------------------------------------------===// 376// class MachineInstr 377// 378// Purpose: 379// Representation of each machine instruction. 380// 381// MachineOpCode must be an enum, defined separately for each target. 382// E.g., It is defined in SparcInstructionSelection.h for the SPARC. 383// 384// There are 2 kinds of operands: 385// 386// (1) Explicit operands of the machine instruction in vector operands[] 387// 388// (2) "Implicit operands" are values implicitly used or defined by the 389// machine instruction, such as arguments to a CALL, return value of 390// a CALL (if any), and return value of a RETURN. 391//===----------------------------------------------------------------------===// 392 393class MachineInstr { 394 short Opcode; // the opcode 395 unsigned char numImplicitRefs; // number of implicit operands 396 std::vector<MachineOperand> operands; // the operands 397 MachineInstr* prev, *next; // links for our intrusive list 398 MachineBasicBlock* parent; // pointer to the owning basic block 399 400 // OperandComplete - Return true if it's illegal to add a new operand 401 bool OperandsComplete() const; 402 403 //Constructor used by clone() method 404 MachineInstr(const MachineInstr&); 405 406 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 407 408 // Intrusive list support 409 // 410 friend struct ilist_traits<MachineInstr>; 411 412public: 413 MachineInstr(short Opcode, unsigned numOperands); 414 415 /// MachineInstr ctor - This constructor only does a _reserve_ of the 416 /// operands, not a resize for them. It is expected that if you use this that 417 /// you call add* methods below to fill up the operands, instead of the Set 418 /// methods. Eventually, the "resizing" ctors will be phased out. 419 /// 420 MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY); 421 422 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 423 /// the MachineInstr is created and added to the end of the specified basic 424 /// block. 425 /// 426 MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps); 427 428 ~MachineInstr(); 429 430 const MachineBasicBlock* getParent() const { return parent; } 431 MachineBasicBlock* getParent() { return parent; } 432 433 /// getOpcode - Returns the opcode of this MachineInstr. 434 /// 435 const int getOpcode() const { return Opcode; } 436 437 /// Access to explicit operands of the instruction. 438 /// 439 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 440 441 const MachineOperand& getOperand(unsigned i) const { 442 assert(i < getNumOperands() && "getOperand() out of range!"); 443 return operands[i]; 444 } 445 MachineOperand& getOperand(unsigned i) { 446 assert(i < getNumOperands() && "getOperand() out of range!"); 447 return operands[i]; 448 } 449 450 // 451 // Access to explicit or implicit operands of the instruction 452 // This returns the i'th entry in the operand vector. 453 // That represents the i'th explicit operand or the (i-N)'th implicit operand, 454 // depending on whether i < N or i >= N. 455 // 456 const MachineOperand& getExplOrImplOperand(unsigned i) const { 457 assert(i < operands.size() && "getExplOrImplOperand() out of range!"); 458 return (i < getNumOperands()? getOperand(i) 459 : getImplicitOp(i - getNumOperands())); 460 } 461 462 // 463 // Access to implicit operands of the instruction 464 // 465 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 466 467 MachineOperand& getImplicitOp(unsigned i) { 468 assert(i < numImplicitRefs && "implicit ref# out of range!"); 469 return operands[i + operands.size() - numImplicitRefs]; 470 } 471 const MachineOperand& getImplicitOp(unsigned i) const { 472 assert(i < numImplicitRefs && "implicit ref# out of range!"); 473 return operands[i + operands.size() - numImplicitRefs]; 474 } 475 476 Value* getImplicitRef(unsigned i) { 477 return getImplicitOp(i).getVRegValue(); 478 } 479 const Value* getImplicitRef(unsigned i) const { 480 return getImplicitOp(i).getVRegValue(); 481 } 482 483 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) { 484 ++numImplicitRefs; 485 addRegOperand(V, isDef, isDefAndUse); 486 } 487 void setImplicitRef(unsigned i, Value* V) { 488 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 489 SetMachineOperandVal(i + getNumOperands(), 490 MachineOperand::MO_VirtualRegister, V); 491 } 492 493 /// clone - Create a copy of 'this' instruction that is identical in 494 /// all ways except the the instruction has no parent, prev, or next. 495 MachineInstr* clone() const; 496 497 // 498 // Debugging support 499 // 500 void print(std::ostream &OS, const TargetMachine *TM) const; 501 void dump() const; 502 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 503 504 // 505 // Define iterators to access the Value operands of the Machine Instruction. 506 // Note that these iterators only enumerate the explicit operands. 507 // begin() and end() are defined to produce these iterators... 508 // 509 template<class _MI, class _V> class ValOpIterator; 510 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 511 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 512 513 514 //===--------------------------------------------------------------------===// 515 // Accessors to add operands when building up machine instructions 516 // 517 518 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 519 /// operands list... 520 /// 521 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 522 assert(!OperandsComplete() && 523 "Trying to add an operand to a machine instr that is already done!"); 524 operands.push_back( 525 MachineOperand(V, MachineOperand::MO_VirtualRegister, 526 !isDef ? MachineOperand::Use : 527 (isDefAndUse ? MachineOperand::UseAndDef : 528 MachineOperand::Def))); 529 } 530 531 void addRegOperand(Value *V, 532 MachineOperand::UseType UTy = MachineOperand::Use, 533 bool isPCRelative = false) { 534 assert(!OperandsComplete() && 535 "Trying to add an operand to a machine instr that is already done!"); 536 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 537 UTy, isPCRelative)); 538 } 539 540 void addCCRegOperand(Value *V, 541 MachineOperand::UseType UTy = MachineOperand::Use) { 542 assert(!OperandsComplete() && 543 "Trying to add an operand to a machine instr that is already done!"); 544 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, 545 false)); 546 } 547 548 549 /// addRegOperand - Add a symbolic virtual register reference... 550 /// 551 void addRegOperand(int reg, bool isDef) { 552 assert(!OperandsComplete() && 553 "Trying to add an operand to a machine instr that is already done!"); 554 operands.push_back( 555 MachineOperand(reg, MachineOperand::MO_VirtualRegister, 556 isDef ? MachineOperand::Def : MachineOperand::Use)); 557 } 558 559 /// addRegOperand - Add a symbolic virtual register reference... 560 /// 561 void addRegOperand(int reg, 562 MachineOperand::UseType UTy = MachineOperand::Use) { 563 assert(!OperandsComplete() && 564 "Trying to add an operand to a machine instr that is already done!"); 565 operands.push_back( 566 MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy)); 567 } 568 569 /// addPCDispOperand - Add a PC relative displacement operand to the MI 570 /// 571 void addPCDispOperand(Value *V) { 572 assert(!OperandsComplete() && 573 "Trying to add an operand to a machine instr that is already done!"); 574 operands.push_back( 575 MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use)); 576 } 577 578 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 579 /// 580 void addMachineRegOperand(int reg, bool isDef) { 581 assert(!OperandsComplete() && 582 "Trying to add an operand to a machine instr that is already done!"); 583 operands.push_back( 584 MachineOperand(reg, MachineOperand::MO_MachineRegister, 585 isDef ? MachineOperand::Def : MachineOperand::Use)); 586 } 587 588 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 589 /// 590 void addMachineRegOperand(int reg, 591 MachineOperand::UseType UTy = MachineOperand::Use) { 592 assert(!OperandsComplete() && 593 "Trying to add an operand to a machine instr that is already done!"); 594 operands.push_back( 595 MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy)); 596 } 597 598 /// addZeroExtImmOperand - Add a zero extended constant argument to the 599 /// machine instruction. 600 /// 601 void addZeroExtImmOperand(int intValue) { 602 assert(!OperandsComplete() && 603 "Trying to add an operand to a machine instr that is already done!"); 604 operands.push_back( 605 MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); 606 } 607 608 /// addSignExtImmOperand - Add a zero extended constant argument to the 609 /// machine instruction. 610 /// 611 void addSignExtImmOperand(int intValue) { 612 assert(!OperandsComplete() && 613 "Trying to add an operand to a machine instr that is already done!"); 614 operands.push_back( 615 MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed)); 616 } 617 618 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { 619 assert(!OperandsComplete() && 620 "Trying to add an operand to a machine instr that is already done!"); 621 operands.push_back(MachineOperand(MBB)); 622 } 623 624 /// addFrameIndexOperand - Add an abstract frame index to the instruction 625 /// 626 void addFrameIndexOperand(unsigned Idx) { 627 assert(!OperandsComplete() && 628 "Trying to add an operand to a machine instr that is already done!"); 629 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); 630 } 631 632 /// addConstantPoolndexOperand - Add a constant pool object index to the 633 /// instruction. 634 /// 635 void addConstantPoolIndexOperand(unsigned I) { 636 assert(!OperandsComplete() && 637 "Trying to add an operand to a machine instr that is already done!"); 638 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); 639 } 640 641 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) { 642 assert(!OperandsComplete() && 643 "Trying to add an operand to a machine instr that is already done!"); 644 operands.push_back( 645 MachineOperand(GV, MachineOperand::MO_GlobalAddress, 646 MachineOperand::Use, isPCRelative, Offset)); 647 } 648 649 /// addExternalSymbolOperand - Add an external symbol operand to this instr 650 /// 651 void addExternalSymbolOperand(const char *SymName, bool isPCRelative) { 652 operands.push_back(MachineOperand(SymName, isPCRelative, 0)); 653 } 654 655 //===--------------------------------------------------------------------===// 656 // Accessors used to modify instructions in place. 657 // 658 // FIXME: Move this stuff to MachineOperand itself! 659 660 /// replace - Support to rewrite a machine instruction in place: for now, 661 /// simply replace() and then set new operands with Set.*Operand methods 662 /// below. 663 /// 664 void replace(short Opcode, unsigned numOperands); 665 666 /// setOpcode - Replace the opcode of the current instruction with a new one. 667 /// 668 void setOpcode(unsigned Op) { Opcode = Op; } 669 670 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 671 /// fewer operand than it started with. 672 /// 673 void RemoveOperand(unsigned i) { 674 operands.erase(operands.begin()+i); 675 } 676 677 // Access to set the operands when building the machine instruction 678 // 679 void SetMachineOperandVal(unsigned i, 680 MachineOperand::MachineOperandType operandType, 681 Value* V); 682 683 void SetMachineOperandConst(unsigned i, 684 MachineOperand::MachineOperandType operandType, 685 int intValue); 686 687 void SetMachineOperandReg(unsigned i, int regNum); 688 689 690 unsigned substituteValue(const Value* oldVal, Value* newVal, 691 bool defsOnly, bool notDefsAndUses, 692 bool& someArgsWereIgnored); 693 694 // SetRegForOperand - 695 // SetRegForImplicitRef - 696 // Mark an explicit or implicit operand with its allocated physical register. 697 // 698 void SetRegForOperand(unsigned i, int regNum); 699 void SetRegForImplicitRef(unsigned i, int regNum); 700 701 // 702 // Iterator to enumerate machine operands. 703 // 704 template<class MITy, class VTy> 705 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 706 unsigned i; 707 MITy MI; 708 709 void skipToNextVal() { 710 while (i < MI->getNumOperands() && 711 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || 712 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister) 713 && MI->getOperand(i).getVRegValue() != 0)) 714 ++i; 715 } 716 717 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 718 skipToNextVal(); 719 } 720 721 public: 722 typedef ValOpIterator<MITy, VTy> _Self; 723 724 inline VTy operator*() const { 725 return MI->getOperand(i).getVRegValue(); 726 } 727 728 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 729 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 730 731 inline VTy operator->() const { return operator*(); } 732 733 inline bool isUse() const { return MI->getOperand(i).isUse(); } 734 inline bool isDef() const { return MI->getOperand(i).isDef(); } 735 736 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 737 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 738 739 inline bool operator==(const _Self &y) const { 740 return i == y.i; 741 } 742 inline bool operator!=(const _Self &y) const { 743 return !operator==(y); 744 } 745 746 static _Self begin(MITy MI) { 747 return _Self(MI, 0); 748 } 749 static _Self end(MITy MI) { 750 return _Self(MI, MI->getNumOperands()); 751 } 752 }; 753 754 // define begin() and end() 755 val_op_iterator begin() { return val_op_iterator::begin(this); } 756 val_op_iterator end() { return val_op_iterator::end(this); } 757 758 const_val_op_iterator begin() const { 759 return const_val_op_iterator::begin(this); 760 } 761 const_val_op_iterator end() const { 762 return const_val_op_iterator::end(this); 763 } 764}; 765 766//===----------------------------------------------------------------------===// 767// Debugging Support 768 769std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI); 770std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO); 771void PrintMachineInstructions(const Function *F); 772 773} // End llvm namespace 774 775#endif 776