MachineInstr.h revision 7ebc4d63db05ac214d36bc01b4d60adadaf923e5
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/CodeGen/MachineOperand.h" 20#include "llvm/Target/TargetInstrDesc.h" 21#include "llvm/Target/TargetOpcodes.h" 22#include "llvm/ADT/ilist.h" 23#include "llvm/ADT/ilist_node.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/ADT/DenseMapInfo.h" 26#include "llvm/Support/DebugLoc.h" 27#include <vector> 28 29namespace llvm { 30 31class AliasAnalysis; 32class TargetInstrDesc; 33class TargetInstrInfo; 34class TargetRegisterInfo; 35class MachineFunction; 36class MachineMemOperand; 37 38//===----------------------------------------------------------------------===// 39/// MachineInstr - Representation of each machine instruction. 40/// 41class MachineInstr : public ilist_node<MachineInstr> { 42public: 43 typedef MachineMemOperand **mmo_iterator; 44 45 /// Flags to specify different kinds of comments to output in 46 /// assembly code. These flags carry semantic information not 47 /// otherwise easily derivable from the IR text. 48 /// 49 enum CommentFlag { 50 ReloadReuse = 0x1 51 }; 52 53private: 54 const TargetInstrDesc *TID; // Instruction descriptor. 55 unsigned short NumImplicitOps; // Number of implicit operands (which 56 // are determined at construction time). 57 58 unsigned short AsmPrinterFlags; // Various bits of information used by 59 // the AsmPrinter to emit helpful 60 // comments. This is *not* semantic 61 // information. Do not use this for 62 // anything other than to convey comment 63 // information to AsmPrinter. 64 65 std::vector<MachineOperand> Operands; // the operands 66 mmo_iterator MemRefs; // information on memory references 67 mmo_iterator MemRefsEnd; 68 MachineBasicBlock *Parent; // Pointer to the owning basic block. 69 DebugLoc debugLoc; // Source line information. 70 71 // OperandComplete - Return true if it's illegal to add a new operand 72 bool OperandsComplete() const; 73 74 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT 75 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 76 77 // Intrusive list support 78 friend struct ilist_traits<MachineInstr>; 79 friend struct ilist_traits<MachineBasicBlock>; 80 void setParent(MachineBasicBlock *P) { Parent = P; } 81 82 /// MachineInstr ctor - This constructor creates a copy of the given 83 /// MachineInstr in the given MachineFunction. 84 MachineInstr(MachineFunction &, const MachineInstr &); 85 86 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with 87 /// TID NULL and no operands. 88 MachineInstr(); 89 90 // The next two constructors have DebugLoc and non-DebugLoc versions; 91 // over time, the non-DebugLoc versions should be phased out and eventually 92 // removed. 93 94 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the 95 /// implicit operands. It reserves space for the number of operands specified 96 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred. 97 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); 98 99 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 100 /// the MachineInstr is created and added to the end of the specified basic 101 /// block. The version with a DebugLoc should be preferred. 102 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); 103 104 /// MachineInstr ctor - This constructor create a MachineInstr and add the 105 /// implicit operands. It reserves space for number of operands specified by 106 /// TargetInstrDesc. An explicit DebugLoc is supplied. 107 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl, 108 bool NoImp = false); 109 110 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 111 /// the MachineInstr is created and added to the end of the specified basic 112 /// block. 113 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 114 const TargetInstrDesc &TID); 115 116 ~MachineInstr(); 117 118 // MachineInstrs are pool-allocated and owned by MachineFunction. 119 friend class MachineFunction; 120 121public: 122 const MachineBasicBlock* getParent() const { return Parent; } 123 MachineBasicBlock* getParent() { return Parent; } 124 125 /// getAsmPrinterFlags - Return the asm printer flags bitvector. 126 /// 127 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; } 128 129 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set. 130 /// 131 bool getAsmPrinterFlag(CommentFlag Flag) const { 132 return AsmPrinterFlags & Flag; 133 } 134 135 /// setAsmPrinterFlag - Set a flag for the AsmPrinter. 136 /// 137 void setAsmPrinterFlag(CommentFlag Flag) { 138 AsmPrinterFlags |= (unsigned short)Flag; 139 } 140 141 /// getDebugLoc - Returns the debug location id of this MachineInstr. 142 /// 143 DebugLoc getDebugLoc() const { return debugLoc; } 144 145 /// getDesc - Returns the target instruction descriptor of this 146 /// MachineInstr. 147 const TargetInstrDesc &getDesc() const { return *TID; } 148 149 /// getOpcode - Returns the opcode of this MachineInstr. 150 /// 151 int getOpcode() const { return TID->Opcode; } 152 153 /// Access to explicit operands of the instruction. 154 /// 155 unsigned getNumOperands() const { return (unsigned)Operands.size(); } 156 157 const MachineOperand& getOperand(unsigned i) const { 158 assert(i < getNumOperands() && "getOperand() out of range!"); 159 return Operands[i]; 160 } 161 MachineOperand& getOperand(unsigned i) { 162 assert(i < getNumOperands() && "getOperand() out of range!"); 163 return Operands[i]; 164 } 165 166 /// getNumExplicitOperands - Returns the number of non-implicit operands. 167 /// 168 unsigned getNumExplicitOperands() const; 169 170 /// Access to memory operands of the instruction 171 mmo_iterator memoperands_begin() const { return MemRefs; } 172 mmo_iterator memoperands_end() const { return MemRefsEnd; } 173 bool memoperands_empty() const { return MemRefsEnd == MemRefs; } 174 175 /// hasOneMemOperand - Return true if this instruction has exactly one 176 /// MachineMemOperand. 177 bool hasOneMemOperand() const { 178 return MemRefsEnd - MemRefs == 1; 179 } 180 181 enum MICheckType { 182 CheckDefs, // Check all operands for equality 183 IgnoreDefs, // Ignore all definitions 184 IgnoreVRegDefs // Ignore virtual register definitions 185 }; 186 187 /// isIdenticalTo - Return true if this instruction is identical to (same 188 /// opcode and same operands as) the specified instruction. 189 bool isIdenticalTo(const MachineInstr *Other, 190 MICheckType Check = CheckDefs) const; 191 192 /// removeFromParent - This method unlinks 'this' from the containing basic 193 /// block, and returns it, but does not delete it. 194 MachineInstr *removeFromParent(); 195 196 /// eraseFromParent - This method unlinks 'this' from the containing basic 197 /// block and deletes it. 198 void eraseFromParent(); 199 200 /// isLabel - Returns true if the MachineInstr represents a label. 201 /// 202 bool isLabel() const { 203 return getOpcode() == TargetOpcode::DBG_LABEL || 204 getOpcode() == TargetOpcode::EH_LABEL || 205 getOpcode() == TargetOpcode::GC_LABEL; 206 } 207 208 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } 209 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 210 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 211 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 212 213 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } 214 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 215 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 216 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } 217 bool isExtractSubreg() const { 218 return getOpcode() == TargetOpcode::EXTRACT_SUBREG; 219 } 220 bool isInsertSubreg() const { 221 return getOpcode() == TargetOpcode::INSERT_SUBREG; 222 } 223 bool isSubregToReg() const { 224 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 225 } 226 bool isRegSequence() const { 227 return getOpcode() == TargetOpcode::REG_SEQUENCE; 228 } 229 230 /// readsRegister - Return true if the MachineInstr reads the specified 231 /// register. If TargetRegisterInfo is passed, then it also checks if there 232 /// is a read of a super-register. 233 /// This does not count partial redefines of virtual registers as reads: 234 /// %reg1024:6 = OP. 235 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 236 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 237 } 238 239 /// readsVirtualRegister - Return true if the MachineInstr reads the specified 240 /// virtual register. Take into account that a partial define is a 241 /// read-modify-write operation. 242 bool readsVirtualRegister(unsigned Reg) const; 243 244 /// killsRegister - Return true if the MachineInstr kills the specified 245 /// register. If TargetRegisterInfo is passed, then it also checks if there is 246 /// a kill of a super-register. 247 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 248 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 249 } 250 251 /// modifiesRegister - Return true if the MachineInstr modifies the 252 /// specified register. If TargetRegisterInfo is passed, then it also checks 253 /// if there is a def of a super-register. 254 bool modifiesRegister(unsigned Reg, 255 const TargetRegisterInfo *TRI = NULL) const { 256 return findRegisterDefOperandIdx(Reg, false, TRI) != -1; 257 } 258 259 /// registerDefIsDead - Returns true if the register is dead in this machine 260 /// instruction. If TargetRegisterInfo is passed, then it also checks 261 /// if there is a dead def of a super-register. 262 bool registerDefIsDead(unsigned Reg, 263 const TargetRegisterInfo *TRI = NULL) const { 264 return findRegisterDefOperandIdx(Reg, true, TRI) != -1; 265 } 266 267 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of 268 /// the specific register or -1 if it is not found. It further tightens 269 /// the search criteria to a use that kills the register if isKill is true. 270 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 271 const TargetRegisterInfo *TRI = NULL) const; 272 273 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns 274 /// a pointer to the MachineOperand rather than an index. 275 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, 276 const TargetRegisterInfo *TRI = NULL) { 277 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 278 return (Idx == -1) ? NULL : &getOperand(Idx); 279 } 280 281 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of 282 /// the specified register or -1 if it is not found. If isDead is true, defs 283 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 284 /// also checks if there is a def of a super-register. 285 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false, 286 const TargetRegisterInfo *TRI = NULL) const; 287 288 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns 289 /// a pointer to the MachineOperand rather than an index. 290 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, 291 const TargetRegisterInfo *TRI = NULL) { 292 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI); 293 return (Idx == -1) ? NULL : &getOperand(Idx); 294 } 295 296 /// findFirstPredOperandIdx() - Find the index of the first operand in the 297 /// operand list that is used to represent the predicate. It returns -1 if 298 /// none is found. 299 int findFirstPredOperandIdx() const; 300 301 /// isRegTiedToUseOperand - Given the index of a register def operand, 302 /// check if the register def is tied to a source operand, due to either 303 /// two-address elimination or inline assembly constraints. Returns the 304 /// first tied use operand index by reference is UseOpIdx is not null. 305 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const; 306 307 /// isRegTiedToDefOperand - Return true if the use operand of the specified 308 /// index is tied to an def operand. It also returns the def operand index by 309 /// reference if DefOpIdx is not null. 310 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const; 311 312 /// clearKillInfo - Clears kill flags on all operands. 313 /// 314 void clearKillInfo(); 315 316 /// copyKillDeadInfo - Copies kill / dead operand properties from MI. 317 /// 318 void copyKillDeadInfo(const MachineInstr *MI); 319 320 /// copyPredicates - Copies predicate operand(s) from MI. 321 void copyPredicates(const MachineInstr *MI); 322 323 /// addRegisterKilled - We have determined MI kills a register. Look for the 324 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 325 /// add a implicit operand if it's not found. Returns true if the operand 326 /// exists / is added. 327 bool addRegisterKilled(unsigned IncomingReg, 328 const TargetRegisterInfo *RegInfo, 329 bool AddIfNotFound = false); 330 331 /// addRegisterDead - We have determined MI defined a register without a use. 332 /// Look for the operand that defines it and mark it as IsDead. If 333 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 334 /// true if the operand exists / is added. 335 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, 336 bool AddIfNotFound = false); 337 338 /// addRegisterDefined - We have determined MI defines a register. Make sure 339 /// there is an operand defining Reg. 340 void addRegisterDefined(unsigned IncomingReg, 341 const TargetRegisterInfo *RegInfo); 342 343 /// isSafeToMove - Return true if it is safe to move this instruction. If 344 /// SawStore is set to true, it means that there is a store (or call) between 345 /// the instruction's location and its intended destination. 346 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA, 347 bool &SawStore) const; 348 349 /// isSafeToReMat - Return true if it's safe to rematerialize the specified 350 /// instruction which defined the specified register instead of copying it. 351 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA, 352 unsigned DstReg) const; 353 354 /// hasVolatileMemoryRef - Return true if this instruction may have a 355 /// volatile memory reference, or if the information describing the 356 /// memory reference is not available. Return false if it is known to 357 /// have no volatile memory references. 358 bool hasVolatileMemoryRef() const; 359 360 /// isInvariantLoad - Return true if this instruction is loading from a 361 /// location whose value is invariant across the function. For example, 362 /// loading a value from the constant pool or from the argument area of 363 /// a function if it does not change. This should only return true of *all* 364 /// loads the instruction does are invariant (if it does multiple loads). 365 bool isInvariantLoad(AliasAnalysis *AA) const; 366 367 /// isConstantValuePHI - If the specified instruction is a PHI that always 368 /// merges together the same virtual register, return the register, otherwise 369 /// return 0. 370 unsigned isConstantValuePHI() const; 371 372 /// allDefsAreDead - Return true if all the defs of this instruction are dead. 373 /// 374 bool allDefsAreDead() const; 375 376 // 377 // Debugging support 378 // 379 void print(raw_ostream &OS, const TargetMachine *TM = 0) const; 380 void dump() const; 381 382 //===--------------------------------------------------------------------===// 383 // Accessors used to build up machine instructions. 384 385 /// addOperand - Add the specified operand to the instruction. If it is an 386 /// implicit operand, it is added to the end of the operand list. If it is 387 /// an explicit operand it is added at the end of the explicit operand list 388 /// (before the first implicit operand). 389 void addOperand(const MachineOperand &Op); 390 391 /// setDesc - Replace the instruction descriptor (thus opcode) of 392 /// the current instruction with a new one. 393 /// 394 void setDesc(const TargetInstrDesc &tid) { TID = &tid; } 395 396 /// setDebugLoc - Replace current source information with new such. 397 /// Avoid using this, the constructor argument is preferable. 398 /// 399 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } 400 401 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 402 /// fewer operand than it started with. 403 /// 404 void RemoveOperand(unsigned i); 405 406 /// addMemOperand - Add a MachineMemOperand to the machine instruction. 407 /// This function should be used only occasionally. The setMemRefs function 408 /// is the primary method for setting up a MachineInstr's MemRefs list. 409 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 410 411 /// setMemRefs - Assign this MachineInstr's memory reference descriptor 412 /// list. This does not transfer ownership. 413 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) { 414 MemRefs = NewMemRefs; 415 MemRefsEnd = NewMemRefsEnd; 416 } 417 418private: 419 /// getRegInfo - If this instruction is embedded into a MachineFunction, 420 /// return the MachineRegisterInfo object for the current function, otherwise 421 /// return null. 422 MachineRegisterInfo *getRegInfo(); 423 424 /// addImplicitDefUseOperands - Add all implicit def and use operands to 425 /// this instruction. 426 void addImplicitDefUseOperands(); 427 428 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 429 /// this instruction from their respective use lists. This requires that the 430 /// operands already be on their use lists. 431 void RemoveRegOperandsFromUseLists(); 432 433 /// AddRegOperandsToUseLists - Add all of the register operands in 434 /// this instruction from their respective use lists. This requires that the 435 /// operands not be on their use lists yet. 436 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); 437}; 438 439/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare 440/// MachineInstr* by *value* of the instruction rather than by pointer value. 441/// The hashing and equality testing functions ignore definitions so this is 442/// useful for CSE, etc. 443struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { 444 static inline MachineInstr *getEmptyKey() { 445 return 0; 446 } 447 448 static inline MachineInstr *getTombstoneKey() { 449 return reinterpret_cast<MachineInstr*>(-1); 450 } 451 452 static unsigned getHashValue(const MachineInstr* const &MI); 453 454 static bool isEqual(const MachineInstr* const &LHS, 455 const MachineInstr* const &RHS) { 456 if (RHS == getEmptyKey() || RHS == getTombstoneKey() || 457 LHS == getEmptyKey() || LHS == getTombstoneKey()) 458 return LHS == RHS; 459 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs); 460 } 461}; 462 463//===----------------------------------------------------------------------===// 464// Debugging Support 465 466inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 467 MI.print(OS); 468 return OS; 469} 470 471} // End llvm namespace 472 473#endif 474