MachineInstr.h revision af55be15dfa5321f470ce9734fabd858f5af7a88
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=// 2// 3// This file contains the declaration of the MachineInstr class, which is the 4// basic representation for all target dependant machine instructions used by 5// the back end. 6// 7//===----------------------------------------------------------------------===// 8 9#ifndef LLVM_CODEGEN_MACHINEINSTR_H 10#define LLVM_CODEGEN_MACHINEINSTR_H 11 12#include "llvm/Annotation.h" 13#include "Support/iterator" 14#include "Support/NonCopyable.h" 15#include <vector> 16class Value; 17class Function; 18class MachineBasicBlock; 19class TargetMachine; 20 21typedef int MachineOpCode; 22 23/// MOTy - MachineOperandType - This namespace contains an enum that describes 24/// how the machine operand is used by the instruction: is it read, defined, or 25/// both? Note that the MachineInstr/Operator class currently uses bool 26/// arguments to represent this information instead of an enum. Eventually this 27/// should change over to use this _easier to read_ representation instead. 28/// 29namespace MOTy { 30 enum UseType { 31 Use, /// This machine operand is only read by the instruction 32 Def, /// This machine operand is only written by the instruction 33 UseAndDef /// This machine operand is read AND written 34 }; 35} 36 37//--------------------------------------------------------------------------- 38// class MachineOperand 39// 40// Purpose: 41// Representation of each machine instruction operand. 42// This class is designed so that you can allocate a vector of operands 43// first and initialize each one later. 44// 45// E.g, for this VM instruction: 46// ptr = alloca type, numElements 47// we generate 2 machine instructions on the SPARC: 48// 49// mul Constant, Numelements -> Reg 50// add %sp, Reg -> Ptr 51// 52// Each instruction has 3 operands, listed above. Of those: 53// - Reg, NumElements, and Ptr are of operand type MO_Register. 54// - Constant is of operand type MO_SignExtendedImmed on the SPARC. 55// 56// For the register operands, the virtual register type is as follows: 57// 58// - Reg will be of virtual register type MO_MInstrVirtualReg. The field 59// MachineInstr* minstr will point to the instruction that computes reg. 60// 61// - %sp will be of virtual register type MO_MachineReg. 62// The field regNum identifies the machine register. 63// 64// - NumElements will be of virtual register type MO_VirtualReg. 65// The field Value* value identifies the value. 66// 67// - Ptr will also be of virtual register type MO_VirtualReg. 68// Again, the field Value* value identifies the value. 69// 70//--------------------------------------------------------------------------- 71 72class MachineOperand { 73public: 74 enum MachineOperandType { 75 MO_VirtualRegister, // virtual register for *value 76 MO_MachineRegister, // pre-assigned machine register `regNum' 77 MO_CCRegister, 78 MO_SignExtendedImmed, 79 MO_UnextendedImmed, 80 MO_PCRelativeDisp, 81 }; 82 83private: 84 // Bit fields of the flags variable used for different operand properties 85 static const char DEFFLAG = 0x1; // this is a def of the operand 86 static const char DEFUSEFLAG = 0x2; // this is both a def and a use 87 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal) 88 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal) 89 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal) 90 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal) 91 92private: 93 union { 94 Value* value; // BasicBlockVal for a label operand. 95 // ConstantVal for a non-address immediate. 96 // Virtual register for an SSA operand, 97 // including hidden operands required for 98 // the generated machine code. 99 int64_t immedVal; // constant value for an explicit constant 100 }; 101 102 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 103 char flags; // see bit field definitions above 104 int regNum; // register number for an explicit register 105 // will be set for a value after reg allocation 106private: 107 MachineOperand() 108 : immedVal(0), 109 opType(MO_VirtualRegister), 110 flags(0), 111 regNum(-1) {} 112 113 MachineOperand(int64_t ImmVal, MachineOperandType OpTy) 114 : immedVal(ImmVal), 115 opType(OpTy), 116 flags(0), 117 regNum(-1) {} 118 119 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy) 120 : immedVal(0), 121 opType(OpTy), 122 regNum(Reg) { 123 switch (UseTy) { 124 case MOTy::Use: flags = 0; break; 125 case MOTy::Def: flags = DEFFLAG; break; 126 case MOTy::UseAndDef: flags = DEFUSEFLAG; break; 127 default: assert(0 && "Invalid value for UseTy!"); 128 } 129 } 130 131 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy) 132 : value(V), opType(OpTy), regNum(-1) { 133 switch (UseTy) { 134 case MOTy::Use: flags = 0; break; 135 case MOTy::Def: flags = DEFFLAG; break; 136 case MOTy::UseAndDef: flags = DEFUSEFLAG; break; 137 default: assert(0 && "Invalid value for UseTy!"); 138 } 139 } 140 141public: 142 MachineOperand(const MachineOperand &M) 143 : immedVal(M.immedVal), 144 opType(M.opType), 145 flags(M.flags), 146 regNum(M.regNum) {} 147 148 ~MachineOperand() {} 149 150 // Accessor methods. Caller is responsible for checking the 151 // operand type before invoking the corresponding accessor. 152 // 153 MachineOperandType getType() const { return opType; } 154 155 inline Value* getVRegValue () const { 156 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 157 opType == MO_PCRelativeDisp); 158 return value; 159 } 160 inline Value* getVRegValueOrNull() const { 161 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 162 opType == MO_PCRelativeDisp)? value : NULL; 163 } 164 inline int getMachineRegNum() const { 165 assert(opType == MO_MachineRegister); 166 return regNum; 167 } 168 inline int64_t getImmedValue () const { 169 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed); 170 return immedVal; 171 } 172 bool opIsDef () const { return flags & DEFFLAG; } 173 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; } 174 bool opHiBits32 () const { return flags & HIFLAG32; } 175 bool opLoBits32 () const { return flags & LOFLAG32; } 176 bool opHiBits64 () const { return flags & HIFLAG64; } 177 bool opLoBits64 () const { return flags & LOFLAG64; } 178 179 // used to check if a machine register has been allocated to this operand 180 inline bool hasAllocatedReg() const { 181 return (regNum >= 0 && 182 (opType == MO_VirtualRegister || opType == MO_CCRegister || 183 opType == MO_MachineRegister)); 184 } 185 186 // used to get the reg number if when one is allocated 187 inline int getAllocatedRegNum() const { 188 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 189 opType == MO_MachineRegister); 190 return regNum; 191 } 192 193 194 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 195 196private: 197 198 // Construction methods needed for fine-grain control. 199 // These must be accessed via coresponding methods in MachineInstr. 200 void markHi32() { flags |= HIFLAG32; } 201 void markLo32() { flags |= LOFLAG32; } 202 void markHi64() { flags |= HIFLAG64; } 203 void markLo64() { flags |= LOFLAG64; } 204 205 // Replaces the Value with its corresponding physical register after 206 // register allocation is complete 207 void setRegForValue(int reg) { 208 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 209 opType == MO_MachineRegister); 210 regNum = reg; 211 } 212 213 friend class MachineInstr; 214}; 215 216 217//--------------------------------------------------------------------------- 218// class MachineInstr 219// 220// Purpose: 221// Representation of each machine instruction. 222// 223// MachineOpCode must be an enum, defined separately for each target. 224// E.g., It is defined in SparcInstructionSelection.h for the SPARC. 225// 226// There are 2 kinds of operands: 227// 228// (1) Explicit operands of the machine instruction in vector operands[] 229// 230// (2) "Implicit operands" are values implicitly used or defined by the 231// machine instruction, such as arguments to a CALL, return value of 232// a CALL (if any), and return value of a RETURN. 233//--------------------------------------------------------------------------- 234 235class MachineInstr: public NonCopyable { // Disable copy operations 236 237 MachineOpCode opCode; // the opcode 238 std::vector<MachineOperand> operands; // the operands 239 unsigned numImplicitRefs; // number of implicit operands 240 241 MachineOperand& getImplicitOp(unsigned i) { 242 assert(i < numImplicitRefs && "implicit ref# out of range!"); 243 return operands[i + operands.size() - numImplicitRefs]; 244 } 245 const MachineOperand& getImplicitOp(unsigned i) const { 246 assert(i < numImplicitRefs && "implicit ref# out of range!"); 247 return operands[i + operands.size() - numImplicitRefs]; 248 } 249 250 // regsUsed - all machine registers used for this instruction, including regs 251 // used to save values across the instruction. This is a bitset of registers. 252 std::vector<bool> regsUsed; 253 254 // OperandComplete - Return true if it's illegal to add a new operand 255 bool OperandsComplete() const; 256 257public: 258 MachineInstr(MachineOpCode Opcode); 259 MachineInstr(MachineOpCode Opcode, unsigned numOperands); 260 261 /// MachineInstr ctor - This constructor only does a _reserve_ of the 262 /// operands, not a resize for them. It is expected that if you use this that 263 /// you call add* methods below to fill up the operands, instead of the Set 264 /// methods. Eventually, the "resizing" ctors will be phased out. 265 /// 266 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY); 267 268 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 269 /// the MachineInstr is created and added to the end of the specified basic 270 /// block. 271 /// 272 MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps); 273 274 275 /// replace - Support to rewrite a machine instruction in place: for now, 276 /// simply replace() and then set new operands with Set.*Operand methods 277 /// below. 278 /// 279 void replace(MachineOpCode Opcode, unsigned numOperands); 280 281 // The opcode. 282 // 283 const MachineOpCode getOpcode() const { return opCode; } 284 const MachineOpCode getOpCode() const { return opCode; } 285 286 // 287 // Information about explicit operands of the instruction 288 // 289 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 290 291 const MachineOperand& getOperand(unsigned i) const { 292 assert(i < getNumOperands() && "getOperand() out of range!"); 293 return operands[i]; 294 } 295 MachineOperand& getOperand(unsigned i) { 296 assert(i < getNumOperands() && "getOperand() out of range!"); 297 return operands[i]; 298 } 299 300 MachineOperand::MachineOperandType getOperandType(unsigned i) const { 301 return getOperand(i).getType(); 302 } 303 304 bool operandIsDefined(unsigned i) const { 305 return getOperand(i).opIsDef(); 306 } 307 308 bool operandIsDefinedAndUsed(unsigned i) const { 309 return getOperand(i).opIsDefAndUse(); 310 } 311 312 // 313 // Information about implicit operands of the instruction 314 // 315 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 316 317 const Value* getImplicitRef(unsigned i) const { 318 return getImplicitOp(i).getVRegValue(); 319 } 320 Value* getImplicitRef(unsigned i) { 321 return getImplicitOp(i).getVRegValue(); 322 } 323 324 bool implicitRefIsDefined(unsigned i) const { 325 return getImplicitOp(i).opIsDef(); 326 } 327 bool implicitRefIsDefinedAndUsed(unsigned i) const { 328 return getImplicitOp(i).opIsDefAndUse(); 329 } 330 inline void addImplicitRef (Value* V, 331 bool isDef=false,bool isDefAndUse=false); 332 inline void setImplicitRef (unsigned i, Value* V, 333 bool isDef=false, bool isDefAndUse=false); 334 335 // 336 // Information about registers used in this instruction 337 // 338 const std::vector<bool> &getRegsUsed() const { return regsUsed; } 339 340 // insertUsedReg - Add a register to the Used registers set... 341 void insertUsedReg(unsigned Reg) { 342 if (Reg >= regsUsed.size()) 343 regsUsed.resize(Reg+1); 344 regsUsed[Reg] = true; 345 } 346 347 // 348 // Debugging support 349 // 350 void print(std::ostream &OS, const TargetMachine &TM) const; 351 void dump() const; 352 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 353 354 // 355 // Define iterators to access the Value operands of the Machine Instruction. 356 // Note that these iterators only enumerate the explicit operands. 357 // begin() and end() are defined to produce these iterators... 358 // 359 template<class _MI, class _V> class ValOpIterator; 360 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 361 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 362 363 // Access to set the operands when building the machine instruction 364 // 365 void SetMachineOperandVal (unsigned i, 366 MachineOperand::MachineOperandType operandType, 367 Value* V, 368 bool isDef=false, 369 bool isDefAndUse=false); 370 371 void SetMachineOperandConst (unsigned i, 372 MachineOperand::MachineOperandType operandType, 373 int64_t intValue); 374 375 void SetMachineOperandReg (unsigned i, 376 int regNum, 377 bool isDef=false); 378 379 //===--------------------------------------------------------------------===// 380 // Accessors to add operands when building up machine instructions 381 // 382 383 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 384 /// operands list... 385 /// 386 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 387 assert(!OperandsComplete() && 388 "Trying to add an operand to a machine instr that is already done!"); 389 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 390 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def))); 391 } 392 393 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) { 394 assert(!OperandsComplete() && 395 "Trying to add an operand to a machine instr that is already done!"); 396 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 397 UTy)); 398 } 399 400 /// addRegOperand - Add a symbolic virtual register reference... 401 /// 402 void addRegOperand(int reg, bool isDef) { 403 assert(!OperandsComplete() && 404 "Trying to add an operand to a machine instr that is already done!"); 405 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 406 isDef ? MOTy::Def : MOTy::Use)); 407 } 408 409 /// addRegOperand - Add a symbolic virtual register reference... 410 /// 411 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 412 assert(!OperandsComplete() && 413 "Trying to add an operand to a machine instr that is already done!"); 414 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 415 UTy)); 416 } 417 418 /// addPCDispOperand - Add a PC relative displacement operand to the MI 419 /// 420 void addPCDispOperand(Value *V) { 421 assert(!OperandsComplete() && 422 "Trying to add an operand to a machine instr that is already done!"); 423 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp, 424 MOTy::Use)); 425 } 426 427 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 428 /// 429 void addMachineRegOperand(int reg, bool isDef) { 430 assert(!OperandsComplete() && 431 "Trying to add an operand to a machine instr that is already done!"); 432 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 433 isDef ? MOTy::Def : MOTy::Use)); 434 insertUsedReg(reg); 435 } 436 437 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 438 /// 439 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 440 assert(!OperandsComplete() && 441 "Trying to add an operand to a machine instr that is already done!"); 442 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 443 UTy)); 444 insertUsedReg(reg); 445 } 446 447 /// addZeroExtImmOperand - Add a zero extended constant argument to the 448 /// machine instruction. 449 /// 450 void addZeroExtImmOperand(int64_t intValue) { 451 assert(!OperandsComplete() && 452 "Trying to add an operand to a machine instr that is already done!"); 453 operands.push_back(MachineOperand(intValue, 454 MachineOperand::MO_UnextendedImmed)); 455 } 456 457 /// addSignExtImmOperand - Add a zero extended constant argument to the 458 /// machine instruction. 459 /// 460 void addSignExtImmOperand(int64_t intValue) { 461 assert(!OperandsComplete() && 462 "Trying to add an operand to a machine instr that is already done!"); 463 operands.push_back(MachineOperand(intValue, 464 MachineOperand::MO_SignExtendedImmed)); 465 } 466 467 468 unsigned substituteValue(const Value* oldVal, Value* newVal, 469 bool defsOnly = true); 470 471 void setOperandHi32(unsigned i) { operands[i].markHi32(); } 472 void setOperandLo32(unsigned i) { operands[i].markLo32(); } 473 void setOperandHi64(unsigned i) { operands[i].markHi64(); } 474 void setOperandLo64(unsigned i) { operands[i].markLo64(); } 475 476 477 // SetRegForOperand - Replaces the Value for the operand with its allocated 478 // physical register after register allocation is complete. 479 // 480 void SetRegForOperand(unsigned i, int regNum); 481 482 // 483 // Iterator to enumerate machine operands. 484 // 485 template<class MITy, class VTy> 486 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 487 unsigned i; 488 MITy MI; 489 490 void skipToNextVal() { 491 while (i < MI->getNumOperands() && 492 !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister || 493 MI->getOperandType(i) == MachineOperand::MO_CCRegister) 494 && MI->getOperand(i).getVRegValue() != 0)) 495 ++i; 496 } 497 498 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 499 skipToNextVal(); 500 } 501 502 public: 503 typedef ValOpIterator<MITy, VTy> _Self; 504 505 inline VTy operator*() const { 506 return MI->getOperand(i).getVRegValue(); 507 } 508 509 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 510 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 511 512 inline VTy operator->() const { return operator*(); } 513 514 inline bool isDef() const { return MI->getOperand(i).opIsDef(); } 515 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();} 516 517 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 518 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 519 520 inline bool operator==(const _Self &y) const { 521 return i == y.i; 522 } 523 inline bool operator!=(const _Self &y) const { 524 return !operator==(y); 525 } 526 527 static _Self begin(MITy MI) { 528 return _Self(MI, 0); 529 } 530 static _Self end(MITy MI) { 531 return _Self(MI, MI->getNumOperands()); 532 } 533 }; 534 535 // define begin() and end() 536 val_op_iterator begin() { return val_op_iterator::begin(this); } 537 val_op_iterator end() { return val_op_iterator::end(this); } 538 539 const_val_op_iterator begin() const { 540 return const_val_op_iterator::begin(this); 541 } 542 const_val_op_iterator end() const { 543 return const_val_op_iterator::end(this); 544 } 545}; 546 547 548// Define here to enable inlining of the functions used. 549// 550void MachineInstr::addImplicitRef(Value* V, 551 bool isDef, 552 bool isDefAndUse) 553{ 554 ++numImplicitRefs; 555 addRegOperand(V, isDef, isDefAndUse); 556} 557 558void MachineInstr::setImplicitRef(unsigned i, 559 Value* V, 560 bool isDef, 561 bool isDefAndUse) 562{ 563 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 564 SetMachineOperandVal(i + getNumOperands(), 565 MachineOperand::MO_VirtualRegister, 566 V, isDef, isDefAndUse); 567} 568 569 570//--------------------------------------------------------------------------- 571// Debugging Support 572//--------------------------------------------------------------------------- 573 574std::ostream& operator<< (std::ostream& os, 575 const MachineInstr& minstr); 576 577std::ostream& operator<< (std::ostream& os, 578 const MachineOperand& mop); 579 580void PrintMachineInstructions (const Function *F); 581 582#endif 583