MachineInstr.h revision b5159ed0cb7943e5938782f7693beb18342165ce
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "Support/iterator" 20#include <string> 21#include <vector> 22#include <cassert> 23 24namespace llvm { 25 26class Value; 27class Function; 28class MachineBasicBlock; 29class TargetMachine; 30class GlobalValue; 31 32template <typename T> class ilist_traits; 33template <typename T> class ilist; 34 35typedef short MachineOpCode; 36 37//===----------------------------------------------------------------------===// 38// class MachineOperand 39// 40// Purpose: 41// Representation of each machine instruction operand. 42// This class is designed so that you can allocate a vector of operands 43// first and initialize each one later. 44// 45// E.g, for this VM instruction: 46// ptr = alloca type, numElements 47// we generate 2 machine instructions on the SPARC: 48// 49// mul Constant, Numelements -> Reg 50// add %sp, Reg -> Ptr 51// 52// Each instruction has 3 operands, listed above. Of those: 53// - Reg, NumElements, and Ptr are of operand type MO_Register. 54// - Constant is of operand type MO_SignExtendedImmed on the SPARC. 55// 56// For the register operands, the virtual register type is as follows: 57// 58// - Reg will be of virtual register type MO_MInstrVirtualReg. The field 59// MachineInstr* minstr will point to the instruction that computes reg. 60// 61// - %sp will be of virtual register type MO_MachineReg. 62// The field regNum identifies the machine register. 63// 64// - NumElements will be of virtual register type MO_VirtualReg. 65// The field Value* value identifies the value. 66// 67// - Ptr will also be of virtual register type MO_VirtualReg. 68// Again, the field Value* value identifies the value. 69// 70//===----------------------------------------------------------------------===// 71 72struct MachineOperand { 73private: 74 // Bit fields of the flags variable used for different operand properties 75 enum { 76 DEFFLAG = 0x01, // this is a def of the operand 77 USEFLAG = 0x02, // this is a use of the operand 78 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) 79 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) 80 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) 81 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) 82 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address 83 }; 84 85public: 86 // UseType - This enum describes how the machine operand is used by 87 // the instruction. Note that the MachineInstr/Operator class 88 // currently uses bool arguments to represent this information 89 // instead of an enum. Eventually this should change over to use 90 // this _easier to read_ representation instead. 91 // 92 enum UseType { 93 Use = USEFLAG, /// only read 94 Def = DEFFLAG, /// only written 95 UseAndDef = Use | Def /// read AND written 96 }; 97 98 enum MachineOperandType { 99 MO_VirtualRegister, // virtual register for *value 100 MO_MachineRegister, // pre-assigned machine register `regNum' 101 MO_CCRegister, 102 MO_SignExtendedImmed, 103 MO_UnextendedImmed, 104 MO_PCRelativeDisp, 105 MO_MachineBasicBlock, // MachineBasicBlock reference 106 MO_FrameIndex, // Abstract Stack Frame Index 107 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool 108 MO_ExternalSymbol, // Name of external global symbol 109 MO_GlobalAddress, // Address of a global value 110 }; 111 112private: 113 union { 114 Value* value; // BasicBlockVal for a label operand. 115 // ConstantVal for a non-address immediate. 116 // Virtual register for an SSA operand, 117 // including hidden operands required for 118 // the generated machine code. 119 // LLVM global for MO_GlobalAddress. 120 121 int immedVal; // Constant value for an explicit constant 122 123 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type 124 std::string *SymbolName; // For MO_ExternalSymbol type 125 } contents; 126 127 char flags; // see bit field definitions above 128 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 129 int regNum; // register number for an explicit register 130 // will be set for a value after reg allocation 131private: 132 void zeroContents () { 133 memset (&contents, 0, sizeof (contents)); 134 } 135 136 MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister) 137 : flags(0), opType(OpTy), regNum(-1) { 138 zeroContents (); 139 contents.immedVal = ImmVal; 140 } 141 142 MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) 143 : flags(UseTy), opType(OpTy), regNum(Reg) { 144 zeroContents (); 145 } 146 147 MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy, 148 bool isPCRelative = false) 149 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy), regNum(-1) { 150 zeroContents (); 151 contents.value = V; 152 } 153 154 MachineOperand(MachineBasicBlock *mbb) 155 : flags(0), opType(MO_MachineBasicBlock), regNum(-1) { 156 zeroContents (); 157 contents.MBB = mbb; 158 } 159 160 MachineOperand(const std::string &SymName, bool isPCRelative) 161 : flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol), regNum(-1) { 162 zeroContents (); 163 contents.SymbolName = new std::string (SymName); 164 } 165 166public: 167 MachineOperand(const MachineOperand &M) 168 : flags(M.flags), opType(M.opType), regNum(M.regNum) { 169 zeroContents (); 170 contents = M.contents; 171 if (isExternalSymbol()) 172 contents.SymbolName = new std::string(M.getSymbolName()); 173 } 174 175 176 ~MachineOperand() { 177 if (isExternalSymbol()) 178 delete contents.SymbolName; 179 } 180 181 const MachineOperand &operator=(const MachineOperand &MO) { 182 if (isExternalSymbol()) // if old operand had a symbol name, 183 delete contents.SymbolName; // release old memory 184 contents = MO.contents; 185 flags = MO.flags; 186 opType = MO.opType; 187 regNum = MO.regNum; 188 if (isExternalSymbol()) 189 contents.SymbolName = new std::string(MO.getSymbolName()); 190 return *this; 191 } 192 193 /// getType - Returns the MachineOperandType for this operand. 194 /// 195 MachineOperandType getType() const { return opType; } 196 197 /// getUseType - Returns the MachineOperandUseType of this operand. 198 /// 199 UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } 200 201 /// isPCRelative - This returns the value of the PCRELATIVE flag, which 202 /// indicates whether this operand should be emitted as a PC relative value 203 /// instead of a global address. This is used for operands of the forms: 204 /// MachineBasicBlock, GlobalAddress, ExternalSymbol 205 /// 206 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } 207 208 /// isRegister - Return true if this operand is a register operand. The X86 209 /// backend currently can't decide whether to use MO_MR or MO_VR to represent 210 /// them, so we accept both. 211 /// 212 /// Note: The sparc backend should not use this method. 213 /// 214 bool isRegister() const { 215 return opType == MO_MachineRegister || opType == MO_VirtualRegister; 216 } 217 218 /// Accessors that tell you what kind of MachineOperand you're looking at. 219 /// 220 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } 221 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } 222 bool isImmediate() const { 223 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; 224 } 225 bool isFrameIndex() const { return opType == MO_FrameIndex; } 226 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } 227 bool isGlobalAddress() const { return opType == MO_GlobalAddress; } 228 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } 229 230 /// getVRegValueOrNull - Get the Value* out of a MachineOperand if it 231 /// has one. This is deprecated and only used by the SPARC v9 backend. 232 /// 233 Value* getVRegValueOrNull() const { 234 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 235 isPCRelativeDisp()) ? contents.value : NULL; 236 } 237 238 /// MachineOperand accessors that only work on certain types of 239 /// MachineOperand... 240 /// 241 Value* getVRegValue() const { 242 assert ((opType == MO_VirtualRegister || opType == MO_CCRegister 243 || isPCRelativeDisp()) && "Wrong MachineOperand accessor"); 244 return contents.value; 245 } 246 int getMachineRegNum() const { 247 assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor"); 248 return regNum; 249 } 250 int getImmedValue() const { 251 assert(isImmediate() && "Wrong MachineOperand accessor"); 252 return contents.immedVal; 253 } 254 MachineBasicBlock *getMachineBasicBlock() const { 255 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); 256 return contents.MBB; 257 } 258 int getFrameIndex() const { 259 assert(isFrameIndex() && "Wrong MachineOperand accessor"); 260 return contents.immedVal; 261 } 262 unsigned getConstantPoolIndex() const { 263 assert(isConstantPoolIndex() && "Wrong MachineOperand accessor"); 264 return contents.immedVal; 265 } 266 GlobalValue *getGlobal() const { 267 assert(isGlobalAddress() && "Wrong MachineOperand accessor"); 268 return (GlobalValue*)contents.value; 269 } 270 const std::string &getSymbolName() const { 271 assert(isExternalSymbol() && "Wrong MachineOperand accessor"); 272 return *contents.SymbolName; 273 } 274 275 /// MachineOperand methods for testing that work on any kind of 276 /// MachineOperand... 277 /// 278 bool isUse () const { return flags & USEFLAG; } 279 MachineOperand& setUse () { flags |= USEFLAG; return *this; } 280 bool isDef () const { return flags & DEFFLAG; } 281 MachineOperand& setDef () { flags |= DEFFLAG; return *this; } 282 bool isHiBits32 () const { return flags & HIFLAG32; } 283 bool isLoBits32 () const { return flags & LOFLAG32; } 284 bool isHiBits64 () const { return flags & HIFLAG64; } 285 bool isLoBits64 () const { return flags & LOFLAG64; } 286 287 /// hasAllocatedReg - Returns true iff a machine register has been 288 /// allocated to this operand. 289 /// 290 bool hasAllocatedReg() const { 291 return (regNum >= 0 && 292 (opType == MO_VirtualRegister || opType == MO_CCRegister || 293 opType == MO_MachineRegister)); 294 } 295 296 /// getReg - Returns the register number. It is a runtime error to call this 297 /// if a register is not allocated. 298 /// 299 unsigned getReg() const { 300 assert(hasAllocatedReg()); 301 return regNum; 302 } 303 304 /// MachineOperand mutators... 305 /// 306 void setReg(unsigned Reg) { 307 // This method's comment used to say: 'TODO: get rid of this duplicate 308 // code.' It's not clear where the duplication is. 309 assert(hasAllocatedReg() && "This operand cannot have a register number!"); 310 regNum = Reg; 311 } 312 void setImmedValue(int immVal) { 313 assert(isImmediate() && "Wrong MachineOperand mutator"); 314 contents.immedVal = immVal; 315 } 316 317 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 318 319private: 320 /// markHi32, markLo32, etc. - These methods must be accessed via 321 /// corresponding methods in MachineInstr. These methods are deprecated 322 /// and only used by the SPARC v9 back-end. 323 /// 324 void markHi32() { flags |= HIFLAG32; } 325 void markLo32() { flags |= LOFLAG32; } 326 void markHi64() { flags |= HIFLAG64; } 327 void markLo64() { flags |= LOFLAG64; } 328 329 /// setRegForValue - Replaces the Value with its corresponding physical 330 /// register after register allocation is complete. This is deprecated 331 /// and only used by the SPARC v9 back-end. 332 /// 333 void setRegForValue(int reg) { 334 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 335 opType == MO_MachineRegister); 336 regNum = reg; 337 } 338 339 friend class MachineInstr; 340}; 341 342 343//===----------------------------------------------------------------------===// 344// class MachineInstr 345// 346// Purpose: 347// Representation of each machine instruction. 348// 349// MachineOpCode must be an enum, defined separately for each target. 350// E.g., It is defined in SparcInstructionSelection.h for the SPARC. 351// 352// There are 2 kinds of operands: 353// 354// (1) Explicit operands of the machine instruction in vector operands[] 355// 356// (2) "Implicit operands" are values implicitly used or defined by the 357// machine instruction, such as arguments to a CALL, return value of 358// a CALL (if any), and return value of a RETURN. 359//===----------------------------------------------------------------------===// 360 361class MachineInstr { 362 short Opcode; // the opcode 363 unsigned char numImplicitRefs; // number of implicit operands 364 std::vector<MachineOperand> operands; // the operands 365 MachineInstr* prev, *next; // links for our intrusive list 366 MachineBasicBlock* parent; // pointer to the owning basic block 367 368 // OperandComplete - Return true if it's illegal to add a new operand 369 bool OperandsComplete() const; 370 371 //Constructor used by clone() method 372 MachineInstr(const MachineInstr&); 373 374 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 375 376 // Intrusive list support 377 // 378 friend class ilist_traits<MachineInstr>; 379 380public: 381 MachineInstr(short Opcode, unsigned numOperands); 382 383 /// MachineInstr ctor - This constructor only does a _reserve_ of the 384 /// operands, not a resize for them. It is expected that if you use this that 385 /// you call add* methods below to fill up the operands, instead of the Set 386 /// methods. Eventually, the "resizing" ctors will be phased out. 387 /// 388 MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY); 389 390 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 391 /// the MachineInstr is created and added to the end of the specified basic 392 /// block. 393 /// 394 MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps); 395 396 ~MachineInstr(); 397 398 const MachineBasicBlock* getParent() const { return parent; } 399 MachineBasicBlock* getParent() { return parent; } 400 401 /// getOpcode - Returns the opcode of this MachineInstr. 402 /// 403 const int getOpcode() const { return Opcode; } 404 405 /// Access to explicit operands of the instruction. 406 /// 407 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 408 409 const MachineOperand& getOperand(unsigned i) const { 410 assert(i < getNumOperands() && "getOperand() out of range!"); 411 return operands[i]; 412 } 413 MachineOperand& getOperand(unsigned i) { 414 assert(i < getNumOperands() && "getOperand() out of range!"); 415 return operands[i]; 416 } 417 418 // 419 // Access to explicit or implicit operands of the instruction 420 // This returns the i'th entry in the operand vector. 421 // That represents the i'th explicit operand or the (i-N)'th implicit operand, 422 // depending on whether i < N or i >= N. 423 // 424 const MachineOperand& getExplOrImplOperand(unsigned i) const { 425 assert(i < operands.size() && "getExplOrImplOperand() out of range!"); 426 return (i < getNumOperands()? getOperand(i) 427 : getImplicitOp(i - getNumOperands())); 428 } 429 430 // 431 // Access to implicit operands of the instruction 432 // 433 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 434 435 MachineOperand& getImplicitOp(unsigned i) { 436 assert(i < numImplicitRefs && "implicit ref# out of range!"); 437 return operands[i + operands.size() - numImplicitRefs]; 438 } 439 const MachineOperand& getImplicitOp(unsigned i) const { 440 assert(i < numImplicitRefs && "implicit ref# out of range!"); 441 return operands[i + operands.size() - numImplicitRefs]; 442 } 443 444 Value* getImplicitRef(unsigned i) { 445 return getImplicitOp(i).getVRegValue(); 446 } 447 const Value* getImplicitRef(unsigned i) const { 448 return getImplicitOp(i).getVRegValue(); 449 } 450 451 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) { 452 ++numImplicitRefs; 453 addRegOperand(V, isDef, isDefAndUse); 454 } 455 void setImplicitRef(unsigned i, Value* V) { 456 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 457 SetMachineOperandVal(i + getNumOperands(), 458 MachineOperand::MO_VirtualRegister, V); 459 } 460 461 /// clone - Create a copy of 'this' instruction that is identical in 462 /// all ways except the the instruction has no parent, prev, or next. 463 MachineInstr* clone(); 464 465 // 466 // Debugging support 467 // 468 void print(std::ostream &OS, const TargetMachine &TM) const; 469 void dump() const; 470 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 471 472 // 473 // Define iterators to access the Value operands of the Machine Instruction. 474 // Note that these iterators only enumerate the explicit operands. 475 // begin() and end() are defined to produce these iterators... 476 // 477 template<class _MI, class _V> class ValOpIterator; 478 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 479 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 480 481 482 //===--------------------------------------------------------------------===// 483 // Accessors to add operands when building up machine instructions 484 // 485 486 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 487 /// operands list... 488 /// 489 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 490 assert(!OperandsComplete() && 491 "Trying to add an operand to a machine instr that is already done!"); 492 operands.push_back( 493 MachineOperand(V, MachineOperand::MO_VirtualRegister, 494 !isDef ? MachineOperand::Use : 495 (isDefAndUse ? MachineOperand::UseAndDef : 496 MachineOperand::Def))); 497 } 498 499 void addRegOperand(Value *V, 500 MachineOperand::UseType UTy = MachineOperand::Use, 501 bool isPCRelative = false) { 502 assert(!OperandsComplete() && 503 "Trying to add an operand to a machine instr that is already done!"); 504 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 505 UTy, isPCRelative)); 506 } 507 508 void addCCRegOperand(Value *V, 509 MachineOperand::UseType UTy = MachineOperand::Use) { 510 assert(!OperandsComplete() && 511 "Trying to add an operand to a machine instr that is already done!"); 512 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, 513 false)); 514 } 515 516 517 /// addRegOperand - Add a symbolic virtual register reference... 518 /// 519 void addRegOperand(int reg, bool isDef) { 520 assert(!OperandsComplete() && 521 "Trying to add an operand to a machine instr that is already done!"); 522 operands.push_back( 523 MachineOperand(reg, MachineOperand::MO_VirtualRegister, 524 isDef ? MachineOperand::Def : MachineOperand::Use)); 525 } 526 527 /// addRegOperand - Add a symbolic virtual register reference... 528 /// 529 void addRegOperand(int reg, 530 MachineOperand::UseType UTy = MachineOperand::Use) { 531 assert(!OperandsComplete() && 532 "Trying to add an operand to a machine instr that is already done!"); 533 operands.push_back( 534 MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy)); 535 } 536 537 /// addPCDispOperand - Add a PC relative displacement operand to the MI 538 /// 539 void addPCDispOperand(Value *V) { 540 assert(!OperandsComplete() && 541 "Trying to add an operand to a machine instr that is already done!"); 542 operands.push_back( 543 MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use)); 544 } 545 546 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 547 /// 548 void addMachineRegOperand(int reg, bool isDef) { 549 assert(!OperandsComplete() && 550 "Trying to add an operand to a machine instr that is already done!"); 551 operands.push_back( 552 MachineOperand(reg, MachineOperand::MO_MachineRegister, 553 isDef ? MachineOperand::Def : MachineOperand::Use)); 554 } 555 556 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 557 /// 558 void addMachineRegOperand(int reg, 559 MachineOperand::UseType UTy = MachineOperand::Use) { 560 assert(!OperandsComplete() && 561 "Trying to add an operand to a machine instr that is already done!"); 562 operands.push_back( 563 MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy)); 564 } 565 566 /// addZeroExtImmOperand - Add a zero extended constant argument to the 567 /// machine instruction. 568 /// 569 void addZeroExtImmOperand(int intValue) { 570 assert(!OperandsComplete() && 571 "Trying to add an operand to a machine instr that is already done!"); 572 operands.push_back( 573 MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); 574 } 575 576 /// addSignExtImmOperand - Add a zero extended constant argument to the 577 /// machine instruction. 578 /// 579 void addSignExtImmOperand(int intValue) { 580 assert(!OperandsComplete() && 581 "Trying to add an operand to a machine instr that is already done!"); 582 operands.push_back( 583 MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed)); 584 } 585 586 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { 587 assert(!OperandsComplete() && 588 "Trying to add an operand to a machine instr that is already done!"); 589 operands.push_back(MachineOperand(MBB)); 590 } 591 592 /// addFrameIndexOperand - Add an abstract frame index to the instruction 593 /// 594 void addFrameIndexOperand(unsigned Idx) { 595 assert(!OperandsComplete() && 596 "Trying to add an operand to a machine instr that is already done!"); 597 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); 598 } 599 600 /// addConstantPoolndexOperand - Add a constant pool object index to the 601 /// instruction. 602 /// 603 void addConstantPoolIndexOperand(unsigned I) { 604 assert(!OperandsComplete() && 605 "Trying to add an operand to a machine instr that is already done!"); 606 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); 607 } 608 609 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) { 610 assert(!OperandsComplete() && 611 "Trying to add an operand to a machine instr that is already done!"); 612 operands.push_back( 613 MachineOperand((Value*)GV, MachineOperand::MO_GlobalAddress, 614 MachineOperand::Use, isPCRelative)); 615 } 616 617 /// addExternalSymbolOperand - Add an external symbol operand to this instr 618 /// 619 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) { 620 operands.push_back(MachineOperand(SymName, isPCRelative)); 621 } 622 623 //===--------------------------------------------------------------------===// 624 // Accessors used to modify instructions in place. 625 // 626 // FIXME: Move this stuff to MachineOperand itself! 627 628 /// replace - Support to rewrite a machine instruction in place: for now, 629 /// simply replace() and then set new operands with Set.*Operand methods 630 /// below. 631 /// 632 void replace(short Opcode, unsigned numOperands); 633 634 /// setOpcode - Replace the opcode of the current instruction with a new one. 635 /// 636 void setOpcode(unsigned Op) { Opcode = Op; } 637 638 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 639 /// fewer operand than it started with. 640 /// 641 void RemoveOperand(unsigned i) { 642 operands.erase(operands.begin()+i); 643 } 644 645 // Access to set the operands when building the machine instruction 646 // 647 void SetMachineOperandVal(unsigned i, 648 MachineOperand::MachineOperandType operandType, 649 Value* V); 650 651 void SetMachineOperandConst(unsigned i, 652 MachineOperand::MachineOperandType operandType, 653 int intValue); 654 655 void SetMachineOperandReg(unsigned i, int regNum); 656 657 658 unsigned substituteValue(const Value* oldVal, Value* newVal, 659 bool defsOnly, bool notDefsAndUses, 660 bool& someArgsWereIgnored); 661 662 void setOperandHi32(unsigned i) { operands[i].markHi32(); } 663 void setOperandLo32(unsigned i) { operands[i].markLo32(); } 664 void setOperandHi64(unsigned i) { operands[i].markHi64(); } 665 void setOperandLo64(unsigned i) { operands[i].markLo64(); } 666 667 668 // SetRegForOperand - 669 // SetRegForImplicitRef - 670 // Mark an explicit or implicit operand with its allocated physical register. 671 // 672 void SetRegForOperand(unsigned i, int regNum); 673 void SetRegForImplicitRef(unsigned i, int regNum); 674 675 // 676 // Iterator to enumerate machine operands. 677 // 678 template<class MITy, class VTy> 679 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 680 unsigned i; 681 MITy MI; 682 683 void skipToNextVal() { 684 while (i < MI->getNumOperands() && 685 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || 686 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister) 687 && MI->getOperand(i).getVRegValue() != 0)) 688 ++i; 689 } 690 691 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 692 skipToNextVal(); 693 } 694 695 public: 696 typedef ValOpIterator<MITy, VTy> _Self; 697 698 inline VTy operator*() const { 699 return MI->getOperand(i).getVRegValue(); 700 } 701 702 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 703 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 704 705 inline VTy operator->() const { return operator*(); } 706 707 inline bool isUse() const { return MI->getOperand(i).isUse(); } 708 inline bool isDef() const { return MI->getOperand(i).isDef(); } 709 710 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 711 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 712 713 inline bool operator==(const _Self &y) const { 714 return i == y.i; 715 } 716 inline bool operator!=(const _Self &y) const { 717 return !operator==(y); 718 } 719 720 static _Self begin(MITy MI) { 721 return _Self(MI, 0); 722 } 723 static _Self end(MITy MI) { 724 return _Self(MI, MI->getNumOperands()); 725 } 726 }; 727 728 // define begin() and end() 729 val_op_iterator begin() { return val_op_iterator::begin(this); } 730 val_op_iterator end() { return val_op_iterator::end(this); } 731 732 const_val_op_iterator begin() const { 733 return const_val_op_iterator::begin(this); 734 } 735 const_val_op_iterator end() const { 736 return const_val_op_iterator::end(this); 737 } 738}; 739 740//===----------------------------------------------------------------------===// 741// Debugging Support 742 743std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI); 744std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO); 745void PrintMachineInstructions(const Function *F); 746 747} // End llvm namespace 748 749#endif 750