MachineInstr.h revision ef6a6a69ff1e1b709d0acb315b9f6c926c67a778
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=// 2// 3// This file contains the declaration of the MachineInstr class, which is the 4// basic representation for all target dependent machine instructions used by 5// the back end. 6// 7//===----------------------------------------------------------------------===// 8 9#ifndef LLVM_CODEGEN_MACHINEINSTR_H 10#define LLVM_CODEGEN_MACHINEINSTR_H 11 12#include "llvm/Target/MRegisterInfo.h" 13#include "Support/Annotation.h" 14#include "Support/iterator" 15#include <set> 16 17class Value; 18class Function; 19class MachineBasicBlock; 20class TargetMachine; 21class GlobalValue; 22 23typedef int MachineOpCode; 24 25//===----------------------------------------------------------------------===// 26/// Special flags on instructions that modify the opcode. 27/// These flags are unused for now, but having them enforces that some 28/// changes will be needed if they are used. 29/// 30enum MachineOpCodeFlags { 31 AnnulFlag, /// 1 if annul bit is set on a branch 32 PredTakenFlag, /// 1 if branch should be predicted taken 33 PredNotTakenFlag /// 1 if branch should be predicted not taken 34}; 35 36//===----------------------------------------------------------------------===// 37/// MOTy - MachineOperandType - This namespace contains an enum that describes 38/// how the machine operand is used by the instruction: is it read, defined, or 39/// both? Note that the MachineInstr/Operator class currently uses bool 40/// arguments to represent this information instead of an enum. Eventually this 41/// should change over to use this _easier to read_ representation instead. 42/// 43namespace MOTy { 44 enum UseType { 45 Use, /// This machine operand is only read by the instruction 46 Def, /// This machine operand is only written by the instruction 47 UseAndDef /// This machine operand is read AND written 48 }; 49} 50 51//===----------------------------------------------------------------------===// 52// class MachineOperand 53// 54// Purpose: 55// Representation of each machine instruction operand. 56// This class is designed so that you can allocate a vector of operands 57// first and initialize each one later. 58// 59// E.g, for this VM instruction: 60// ptr = alloca type, numElements 61// we generate 2 machine instructions on the SPARC: 62// 63// mul Constant, Numelements -> Reg 64// add %sp, Reg -> Ptr 65// 66// Each instruction has 3 operands, listed above. Of those: 67// - Reg, NumElements, and Ptr are of operand type MO_Register. 68// - Constant is of operand type MO_SignExtendedImmed on the SPARC. 69// 70// For the register operands, the virtual register type is as follows: 71// 72// - Reg will be of virtual register type MO_MInstrVirtualReg. The field 73// MachineInstr* minstr will point to the instruction that computes reg. 74// 75// - %sp will be of virtual register type MO_MachineReg. 76// The field regNum identifies the machine register. 77// 78// - NumElements will be of virtual register type MO_VirtualReg. 79// The field Value* value identifies the value. 80// 81// - Ptr will also be of virtual register type MO_VirtualReg. 82// Again, the field Value* value identifies the value. 83// 84//===----------------------------------------------------------------------===// 85 86struct MachineOperand { 87 enum MachineOperandType { 88 MO_VirtualRegister, // virtual register for *value 89 MO_MachineRegister, // pre-assigned machine register `regNum' 90 MO_CCRegister, 91 MO_SignExtendedImmed, 92 MO_UnextendedImmed, 93 MO_PCRelativeDisp, 94 MO_MachineBasicBlock, // MachineBasicBlock reference 95 MO_FrameIndex, // Abstract Stack Frame Index 96 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool 97 MO_ExternalSymbol, // Name of external global symbol 98 MO_GlobalAddress, // Address of a global value 99 }; 100 101private: 102 // Bit fields of the flags variable used for different operand properties 103 enum { 104 DEFONLYFLAG = 0x01, // this is a def but not a use of the operand 105 DEFUSEFLAG = 0x02, // this is both a def and a use 106 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) 107 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) 108 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) 109 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) 110 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address 111 112 USEDEFMASK = 0x03, 113 }; 114 115private: 116 union { 117 Value* value; // BasicBlockVal for a label operand. 118 // ConstantVal for a non-address immediate. 119 // Virtual register for an SSA operand, 120 // including hidden operands required for 121 // the generated machine code. 122 // LLVM global for MO_GlobalAddress. 123 124 int64_t immedVal; // Constant value for an explicit constant 125 126 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type 127 std::string *SymbolName; // For MO_ExternalSymbol type 128 }; 129 130 char flags; // see bit field definitions above 131 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 132 int regNum; // register number for an explicit register 133 // will be set for a value after reg allocation 134private: 135 MachineOperand() 136 : immedVal(0), 137 flags(0), 138 opType(MO_VirtualRegister), 139 regNum(-1) {} 140 141 MachineOperand(int64_t ImmVal, MachineOperandType OpTy) 142 : immedVal(ImmVal), 143 flags(0), 144 opType(OpTy), 145 regNum(-1) {} 146 147 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy) 148 : immedVal(0), 149 opType(OpTy), 150 regNum(Reg) { 151 switch (UseTy) { 152 case MOTy::Use: flags = 0; break; 153 case MOTy::Def: flags = DEFONLYFLAG; break; 154 case MOTy::UseAndDef: flags = DEFUSEFLAG; break; 155 default: assert(0 && "Invalid value for UseTy!"); 156 } 157 } 158 159 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy, 160 bool isPCRelative = false) 161 : value(V), opType(OpTy), regNum(-1) { 162 switch (UseTy) { 163 case MOTy::Use: flags = 0; break; 164 case MOTy::Def: flags = DEFONLYFLAG; break; 165 case MOTy::UseAndDef: flags = DEFUSEFLAG; break; 166 default: assert(0 && "Invalid value for UseTy!"); 167 } 168 if (isPCRelative) flags |= PCRELATIVE; 169 } 170 171 MachineOperand(MachineBasicBlock *mbb) 172 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {} 173 174 MachineOperand(const std::string &SymName, bool isPCRelative) 175 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0), 176 opType(MO_ExternalSymbol), regNum(-1) {} 177 178public: 179 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal), 180 flags(M.flags), 181 opType(M.opType), 182 regNum(M.regNum) { 183 if (isExternalSymbol()) 184 SymbolName = new std::string(M.getSymbolName()); 185 } 186 187 ~MachineOperand() { 188 if (isExternalSymbol()) 189 delete SymbolName; 190 } 191 192 const MachineOperand &operator=(const MachineOperand &MO) { 193 if (isExternalSymbol()) // if old operand had a symbol name, 194 delete SymbolName; // release old memory 195 immedVal = MO.immedVal; 196 flags = MO.flags; 197 opType = MO.opType; 198 regNum = MO.regNum; 199 if (isExternalSymbol()) 200 SymbolName = new std::string(MO.getSymbolName()); 201 return *this; 202 } 203 204 // Accessor methods. Caller is responsible for checking the 205 // operand type before invoking the corresponding accessor. 206 // 207 MachineOperandType getType() const { return opType; } 208 209 /// isPCRelative - This returns the value of the PCRELATIVE flag, which 210 /// indicates whether this operand should be emitted as a PC relative value 211 /// instead of a global address. This is used for operands of the forms: 212 /// MachineBasicBlock, GlobalAddress, ExternalSymbol 213 /// 214 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } 215 216 217 // This is to finally stop caring whether we have a virtual or machine 218 // register -- an easier interface is to simply call both virtual and machine 219 // registers essentially the same, yet be able to distinguish when 220 // necessary. Thus the instruction selector can just add registers without 221 // abandon, and the register allocator won't be confused. 222 bool isVirtualRegister() const { 223 return (opType == MO_VirtualRegister || opType == MO_MachineRegister) 224 && regNum >= MRegisterInfo::FirstVirtualRegister; 225 } 226 bool isPhysicalRegister() const { 227 return (opType == MO_VirtualRegister || opType == MO_MachineRegister) 228 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister; 229 } 230 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();} 231 bool isMachineRegister() const { return !isVirtualRegister(); } 232 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } 233 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } 234 bool isImmediate() const { 235 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; 236 } 237 bool isFrameIndex() const { return opType == MO_FrameIndex; } 238 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } 239 bool isGlobalAddress() const { return opType == MO_GlobalAddress; } 240 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } 241 242 Value* getVRegValue() const { 243 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 244 isPCRelativeDisp()); 245 return value; 246 } 247 Value* getVRegValueOrNull() const { 248 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 249 isPCRelativeDisp()) ? value : NULL; 250 } 251 int getMachineRegNum() const { 252 assert(opType == MO_MachineRegister); 253 return regNum; 254 } 255 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; } 256 MachineBasicBlock *getMachineBasicBlock() const { 257 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!"); 258 return MBB; 259 } 260 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; } 261 unsigned getConstantPoolIndex() const { 262 assert(isConstantPoolIndex()); 263 return immedVal; 264 } 265 266 GlobalValue *getGlobal() const { 267 assert(isGlobalAddress()); 268 return (GlobalValue*)value; 269 } 270 271 const std::string &getSymbolName() const { 272 assert(isExternalSymbol()); 273 return *SymbolName; 274 } 275 276 bool opIsUse () const { return (flags & USEDEFMASK) == 0; } 277 bool opIsDefOnly () const { return flags & DEFONLYFLAG; } 278 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; } 279 bool opHiBits32 () const { return flags & HIFLAG32; } 280 bool opLoBits32 () const { return flags & LOFLAG32; } 281 bool opHiBits64 () const { return flags & HIFLAG64; } 282 bool opLoBits64 () const { return flags & LOFLAG64; } 283 284 // used to check if a machine register has been allocated to this operand 285 bool hasAllocatedReg() const { 286 return (regNum >= 0 && 287 (opType == MO_VirtualRegister || opType == MO_CCRegister || 288 opType == MO_MachineRegister)); 289 } 290 291 // used to get the reg number if when one is allocated 292 int getAllocatedRegNum() const { 293 assert(hasAllocatedReg()); 294 return regNum; 295 } 296 297 // ********** TODO: get rid of this duplicate code! *********** 298 unsigned getReg() const { 299 return getAllocatedRegNum(); 300 } 301 302 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 303 304private: 305 306 // Construction methods needed for fine-grain control. 307 // These must be accessed via coresponding methods in MachineInstr. 308 void markHi32() { flags |= HIFLAG32; } 309 void markLo32() { flags |= LOFLAG32; } 310 void markHi64() { flags |= HIFLAG64; } 311 void markLo64() { flags |= LOFLAG64; } 312 313 // Replaces the Value with its corresponding physical register after 314 // register allocation is complete 315 void setRegForValue(int reg) { 316 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 317 opType == MO_MachineRegister); 318 regNum = reg; 319 } 320 321 friend class MachineInstr; 322}; 323 324 325//===----------------------------------------------------------------------===// 326// class MachineInstr 327// 328// Purpose: 329// Representation of each machine instruction. 330// 331// MachineOpCode must be an enum, defined separately for each target. 332// E.g., It is defined in SparcInstructionSelection.h for the SPARC. 333// 334// There are 2 kinds of operands: 335// 336// (1) Explicit operands of the machine instruction in vector operands[] 337// 338// (2) "Implicit operands" are values implicitly used or defined by the 339// machine instruction, such as arguments to a CALL, return value of 340// a CALL (if any), and return value of a RETURN. 341//===----------------------------------------------------------------------===// 342 343class MachineInstr { 344 int opCode; // the opcode 345 unsigned opCodeFlags; // flags modifying instrn behavior 346 std::vector<MachineOperand> operands; // the operands 347 unsigned numImplicitRefs; // number of implicit operands 348 349 // OperandComplete - Return true if it's illegal to add a new operand 350 bool OperandsComplete() const; 351 352 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT 353 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 354public: 355 MachineInstr(int Opcode, unsigned numOperands); 356 357 /// MachineInstr ctor - This constructor only does a _reserve_ of the 358 /// operands, not a resize for them. It is expected that if you use this that 359 /// you call add* methods below to fill up the operands, instead of the Set 360 /// methods. Eventually, the "resizing" ctors will be phased out. 361 /// 362 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY); 363 364 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 365 /// the MachineInstr is created and added to the end of the specified basic 366 /// block. 367 /// 368 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps); 369 370 371 // The opcode. 372 // 373 const int getOpcode() const { return opCode; } 374 const int getOpCode() const { return opCode; } 375 376 // Opcode flags. 377 // 378 unsigned getOpCodeFlags() const { return opCodeFlags; } 379 380 // 381 // Access to explicit operands of the instruction 382 // 383 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 384 385 const MachineOperand& getOperand(unsigned i) const { 386 assert(i < getNumOperands() && "getOperand() out of range!"); 387 return operands[i]; 388 } 389 MachineOperand& getOperand(unsigned i) { 390 assert(i < getNumOperands() && "getOperand() out of range!"); 391 return operands[i]; 392 } 393 394 // 395 // Access to explicit or implicit operands of the instruction 396 // This returns the i'th entry in the operand vector. 397 // That represents the i'th explicit operand or the (i-N)'th implicit operand, 398 // depending on whether i < N or i >= N. 399 // 400 const MachineOperand& getExplOrImplOperand(unsigned i) const { 401 assert(i < operands.size() && "getExplOrImplOperand() out of range!"); 402 return (i < getNumOperands()? getOperand(i) 403 : getImplicitOp(i - getNumOperands())); 404 } 405 406 // 407 // Access to implicit operands of the instruction 408 // 409 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 410 411 MachineOperand& getImplicitOp(unsigned i) { 412 assert(i < numImplicitRefs && "implicit ref# out of range!"); 413 return operands[i + operands.size() - numImplicitRefs]; 414 } 415 const MachineOperand& getImplicitOp(unsigned i) const { 416 assert(i < numImplicitRefs && "implicit ref# out of range!"); 417 return operands[i + operands.size() - numImplicitRefs]; 418 } 419 420 Value* getImplicitRef(unsigned i) { 421 return getImplicitOp(i).getVRegValue(); 422 } 423 const Value* getImplicitRef(unsigned i) const { 424 return getImplicitOp(i).getVRegValue(); 425 } 426 427 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) { 428 ++numImplicitRefs; 429 addRegOperand(V, isDef, isDefAndUse); 430 } 431 void setImplicitRef(unsigned i, Value* V) { 432 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 433 SetMachineOperandVal(i + getNumOperands(), 434 MachineOperand::MO_VirtualRegister, V); 435 } 436 437 // 438 // Debugging support 439 // 440 void print(std::ostream &OS, const TargetMachine &TM) const; 441 void dump() const; 442 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 443 444 // 445 // Define iterators to access the Value operands of the Machine Instruction. 446 // Note that these iterators only enumerate the explicit operands. 447 // begin() and end() are defined to produce these iterators... 448 // 449 template<class _MI, class _V> class ValOpIterator; 450 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 451 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 452 453 454 //===--------------------------------------------------------------------===// 455 // Accessors to add operands when building up machine instructions 456 // 457 458 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 459 /// operands list... 460 /// 461 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 462 assert(!OperandsComplete() && 463 "Trying to add an operand to a machine instr that is already done!"); 464 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 465 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def))); 466 } 467 468 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use, 469 bool isPCRelative = false) { 470 assert(!OperandsComplete() && 471 "Trying to add an operand to a machine instr that is already done!"); 472 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 473 UTy, isPCRelative)); 474 } 475 476 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) { 477 assert(!OperandsComplete() && 478 "Trying to add an operand to a machine instr that is already done!"); 479 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, 480 false)); 481 } 482 483 484 /// addRegOperand - Add a symbolic virtual register reference... 485 /// 486 void addRegOperand(int reg, bool isDef) { 487 assert(!OperandsComplete() && 488 "Trying to add an operand to a machine instr that is already done!"); 489 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 490 isDef ? MOTy::Def : MOTy::Use)); 491 } 492 493 /// addRegOperand - Add a symbolic virtual register reference... 494 /// 495 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 496 assert(!OperandsComplete() && 497 "Trying to add an operand to a machine instr that is already done!"); 498 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, 499 UTy)); 500 } 501 502 /// addPCDispOperand - Add a PC relative displacement operand to the MI 503 /// 504 void addPCDispOperand(Value *V) { 505 assert(!OperandsComplete() && 506 "Trying to add an operand to a machine instr that is already done!"); 507 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp, 508 MOTy::Use)); 509 } 510 511 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 512 /// 513 void addMachineRegOperand(int reg, bool isDef) { 514 assert(!OperandsComplete() && 515 "Trying to add an operand to a machine instr that is already done!"); 516 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 517 isDef ? MOTy::Def : MOTy::Use)); 518 } 519 520 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 521 /// 522 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { 523 assert(!OperandsComplete() && 524 "Trying to add an operand to a machine instr that is already done!"); 525 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, 526 UTy)); 527 } 528 529 /// addZeroExtImmOperand - Add a zero extended constant argument to the 530 /// machine instruction. 531 /// 532 void addZeroExtImmOperand(int64_t intValue) { 533 assert(!OperandsComplete() && 534 "Trying to add an operand to a machine instr that is already done!"); 535 operands.push_back(MachineOperand(intValue, 536 MachineOperand::MO_UnextendedImmed)); 537 } 538 539 /// addSignExtImmOperand - Add a zero extended constant argument to the 540 /// machine instruction. 541 /// 542 void addSignExtImmOperand(int64_t intValue) { 543 assert(!OperandsComplete() && 544 "Trying to add an operand to a machine instr that is already done!"); 545 operands.push_back(MachineOperand(intValue, 546 MachineOperand::MO_SignExtendedImmed)); 547 } 548 549 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { 550 assert(!OperandsComplete() && 551 "Trying to add an operand to a machine instr that is already done!"); 552 operands.push_back(MachineOperand(MBB)); 553 } 554 555 /// addFrameIndexOperand - Add an abstract frame index to the instruction 556 /// 557 void addFrameIndexOperand(unsigned Idx) { 558 assert(!OperandsComplete() && 559 "Trying to add an operand to a machine instr that is already done!"); 560 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); 561 } 562 563 /// addConstantPoolndexOperand - Add a constant pool object index to the 564 /// instruction. 565 /// 566 void addConstantPoolIndexOperand(unsigned I) { 567 assert(!OperandsComplete() && 568 "Trying to add an operand to a machine instr that is already done!"); 569 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); 570 } 571 572 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) { 573 assert(!OperandsComplete() && 574 "Trying to add an operand to a machine instr that is already done!"); 575 operands.push_back(MachineOperand((Value*)GV, 576 MachineOperand::MO_GlobalAddress, 577 MOTy::Use, isPCRelative)); 578 } 579 580 /// addExternalSymbolOperand - Add an external symbol operand to this instr 581 /// 582 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) { 583 operands.push_back(MachineOperand(SymName, isPCRelative)); 584 } 585 586 //===--------------------------------------------------------------------===// 587 // Accessors used to modify instructions in place. 588 // 589 // FIXME: Move this stuff to MachineOperand itself! 590 591 /// replace - Support to rewrite a machine instruction in place: for now, 592 /// simply replace() and then set new operands with Set.*Operand methods 593 /// below. 594 /// 595 void replace(int Opcode, unsigned numOperands); 596 597 /// setOpcode - Replace the opcode of the current instruction with a new one. 598 /// 599 void setOpcode(unsigned Op) { opCode = Op; } 600 601 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 602 /// fewer operand than it started with. 603 /// 604 void RemoveOperand(unsigned i) { 605 operands.erase(operands.begin()+i); 606 } 607 608 // Access to set the operands when building the machine instruction 609 // 610 void SetMachineOperandVal (unsigned i, 611 MachineOperand::MachineOperandType operandType, 612 Value* V); 613 614 void SetMachineOperandConst (unsigned i, 615 MachineOperand::MachineOperandType operandType, 616 int64_t intValue); 617 618 void SetMachineOperandReg(unsigned i, int regNum); 619 620 621 unsigned substituteValue(const Value* oldVal, Value* newVal, 622 bool defsOnly, bool notDefsAndUses, 623 bool& someArgsWereIgnored); 624 625 void setOperandHi32(unsigned i) { operands[i].markHi32(); } 626 void setOperandLo32(unsigned i) { operands[i].markLo32(); } 627 void setOperandHi64(unsigned i) { operands[i].markHi64(); } 628 void setOperandLo64(unsigned i) { operands[i].markLo64(); } 629 630 631 // SetRegForOperand - 632 // SetRegForImplicitRef - 633 // Mark an explicit or implicit operand with its allocated physical register. 634 // 635 void SetRegForOperand(unsigned i, int regNum); 636 void SetRegForImplicitRef(unsigned i, int regNum); 637 638 // 639 // Iterator to enumerate machine operands. 640 // 641 template<class MITy, class VTy> 642 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 643 unsigned i; 644 MITy MI; 645 646 void skipToNextVal() { 647 while (i < MI->getNumOperands() && 648 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || 649 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister) 650 && MI->getOperand(i).getVRegValue() != 0)) 651 ++i; 652 } 653 654 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 655 skipToNextVal(); 656 } 657 658 public: 659 typedef ValOpIterator<MITy, VTy> _Self; 660 661 inline VTy operator*() const { 662 return MI->getOperand(i).getVRegValue(); 663 } 664 665 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 666 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 667 668 inline VTy operator->() const { return operator*(); } 669 670 inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); } 671 inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); } 672 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();} 673 674 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 675 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 676 677 inline bool operator==(const _Self &y) const { 678 return i == y.i; 679 } 680 inline bool operator!=(const _Self &y) const { 681 return !operator==(y); 682 } 683 684 static _Self begin(MITy MI) { 685 return _Self(MI, 0); 686 } 687 static _Self end(MITy MI) { 688 return _Self(MI, MI->getNumOperands()); 689 } 690 }; 691 692 // define begin() and end() 693 val_op_iterator begin() { return val_op_iterator::begin(this); } 694 val_op_iterator end() { return val_op_iterator::end(this); } 695 696 const_val_op_iterator begin() const { 697 return const_val_op_iterator::begin(this); 698 } 699 const_val_op_iterator end() const { 700 return const_val_op_iterator::end(this); 701 } 702}; 703 704 705//===----------------------------------------------------------------------===// 706// Debugging Support 707 708std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI); 709std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO); 710void PrintMachineInstructions(const Function *F); 711 712#endif 713