MachineOperand.h revision 4ba6916a98fffd9dedac5945ac51d40c8948069e
1//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineOperand class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEOPERAND_H 15#define LLVM_CODEGEN_MACHINEOPERAND_H 16 17#include "llvm/ADT/Hashing.h" 18#include "llvm/Support/DataTypes.h" 19#include <cassert> 20 21namespace llvm { 22 23class BlockAddress; 24class ConstantFP; 25class ConstantInt; 26class GlobalValue; 27class MachineBasicBlock; 28class MachineInstr; 29class MachineRegisterInfo; 30class MDNode; 31class TargetMachine; 32class TargetRegisterInfo; 33class raw_ostream; 34class MCSymbol; 35 36/// MachineOperand class - Representation of each machine instruction operand. 37/// 38class MachineOperand { 39public: 40 enum MachineOperandType { 41 MO_Register, ///< Register operand. 42 MO_Immediate, ///< Immediate operand 43 MO_CImmediate, ///< Immediate >64bit operand 44 MO_FPImmediate, ///< Floating-point immediate operand 45 MO_MachineBasicBlock, ///< MachineBasicBlock reference 46 MO_FrameIndex, ///< Abstract Stack Frame Index 47 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool 48 MO_TargetIndex, ///< Target-dependent index+offset operand. 49 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch 50 MO_ExternalSymbol, ///< Name of external global symbol 51 MO_GlobalAddress, ///< Address of a global value 52 MO_BlockAddress, ///< Address of a basic block 53 MO_RegisterMask, ///< Mask of preserved registers. 54 MO_Metadata, ///< Metadata reference (for debug info) 55 MO_MCSymbol ///< MCSymbol reference (for debug/eh info) 56 }; 57 58private: 59 /// OpKind - Specify what kind of operand this is. This discriminates the 60 /// union. 61 unsigned char OpKind; // MachineOperandType 62 63 // This union is discriminated by OpKind. 64 union { 65 /// SubReg - Subregister number, only valid for MO_Register. A value of 0 66 /// indicates the MO_Register has no subReg. 67 unsigned char SubReg; 68 69 /// TargetFlags - This is a set of target-specific operand flags. 70 unsigned char TargetFlags; 71 }; 72 73 /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register 74 /// operands. 75 76 /// IsDef - True if this is a def, false if this is a use of the register. 77 /// 78 bool IsDef : 1; 79 80 /// IsImp - True if this is an implicit def or use, false if it is explicit. 81 /// 82 bool IsImp : 1; 83 84 /// IsKill - True if this instruction is the last use of the register on this 85 /// path through the function. This is only valid on uses of registers. 86 bool IsKill : 1; 87 88 /// IsDead - True if this register is never used by a subsequent instruction. 89 /// This is only valid on definitions of registers. 90 bool IsDead : 1; 91 92 /// IsUndef - True if this register operand reads an "undef" value, i.e. the 93 /// read value doesn't matter. This flag can be set on both use and def 94 /// operands. On a sub-register def operand, it refers to the part of the 95 /// register that isn't written. On a full-register def operand, it is a 96 /// noop. See readsReg(). 97 /// 98 /// This is only valid on registers. 99 /// 100 /// Note that an instruction may have multiple <undef> operands referring to 101 /// the same register. In that case, the instruction may depend on those 102 /// operands reading the same dont-care value. For example: 103 /// 104 /// %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef> 105 /// 106 /// Any register can be used for %vreg2, and its value doesn't matter, but 107 /// the two operands must be the same register. 108 /// 109 bool IsUndef : 1; 110 111 /// IsInternalRead - True if this operand reads a value that was defined 112 /// inside the same instruction or bundle. This flag can be set on both use 113 /// and def operands. On a sub-register def operand, it refers to the part 114 /// of the register that isn't written. On a full-register def operand, it 115 /// is a noop. 116 /// 117 /// When this flag is set, the instruction bundle must contain at least one 118 /// other def of the register. If multiple instructions in the bundle define 119 /// the register, the meaning is target-defined. 120 bool IsInternalRead : 1; 121 122 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to 123 /// by the MachineInstr before all input registers are read. This is used to 124 /// model the GCC inline asm '&' constraint modifier. 125 bool IsEarlyClobber : 1; 126 127 /// IsTied - True if this MO_Register operand is tied to another operand on 128 /// the instruction. Tied operands form def-use pairs that must be assigned 129 /// the same physical register by the register allocator, but they will have 130 /// different virtual registers while the code is in SSA form. 131 /// 132 /// See MachineInstr::isRegTiedToUseOperand() and isRegTiedToDefOperand(). 133 bool IsTied : 1; 134 135 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, 136 /// not a real instruction. Such uses should be ignored during codegen. 137 bool IsDebug : 1; 138 139 /// SmallContents - This really should be part of the Contents union, but 140 /// lives out here so we can get a better packed struct. 141 /// MO_Register: Register number. 142 /// OffsetedInfo: Low bits of offset. 143 union { 144 unsigned RegNo; // For MO_Register. 145 unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi. 146 } SmallContents; 147 148 /// ParentMI - This is the instruction that this operand is embedded into. 149 /// This is valid for all operand types, when the operand is in an instr. 150 MachineInstr *ParentMI; 151 152 /// Contents union - This contains the payload for the various operand types. 153 union { 154 MachineBasicBlock *MBB; // For MO_MachineBasicBlock. 155 const ConstantFP *CFP; // For MO_FPImmediate. 156 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit. 157 int64_t ImmVal; // For MO_Immediate. 158 const uint32_t *RegMask; // For MO_RegisterMask. 159 const MDNode *MD; // For MO_Metadata. 160 MCSymbol *Sym; // For MO_MCSymbol 161 162 struct { // For MO_Register. 163 // Register number is in SmallContents.RegNo. 164 MachineOperand *Prev; // Access list for register. See MRI. 165 MachineOperand *Next; 166 } Reg; 167 168 /// OffsetedInfo - This struct contains the offset and an object identifier. 169 /// this represent the object as with an optional offset from it. 170 struct { 171 union { 172 int Index; // For MO_*Index - The index itself. 173 const char *SymbolName; // For MO_ExternalSymbol. 174 const GlobalValue *GV; // For MO_GlobalAddress. 175 const BlockAddress *BA; // For MO_BlockAddress. 176 } Val; 177 // Low bits of offset are in SmallContents.OffsetLo. 178 int OffsetHi; // An offset from the object, high 32 bits. 179 } OffsetedInfo; 180 } Contents; 181 182 explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) { 183 TargetFlags = 0; 184 } 185public: 186 /// getType - Returns the MachineOperandType for this operand. 187 /// 188 MachineOperandType getType() const { return (MachineOperandType)OpKind; } 189 190 unsigned char getTargetFlags() const { 191 return isReg() ? 0 : TargetFlags; 192 } 193 void setTargetFlags(unsigned char F) { 194 assert(!isReg() && "Register operands can't have target flags"); 195 TargetFlags = F; 196 } 197 void addTargetFlag(unsigned char F) { 198 assert(!isReg() && "Register operands can't have target flags"); 199 TargetFlags |= F; 200 } 201 202 203 /// getParent - Return the instruction that this operand belongs to. 204 /// 205 MachineInstr *getParent() { return ParentMI; } 206 const MachineInstr *getParent() const { return ParentMI; } 207 208 /// clearParent - Reset the parent pointer. 209 /// 210 /// The MachineOperand copy constructor also copies ParentMI, expecting the 211 /// original to be deleted. If a MachineOperand is ever stored outside a 212 /// MachineInstr, the parent pointer must be cleared. 213 /// 214 /// Never call clearParent() on an operand in a MachineInstr. 215 /// 216 void clearParent() { ParentMI = 0; } 217 218 void print(raw_ostream &os, const TargetMachine *TM = 0) const; 219 220 //===--------------------------------------------------------------------===// 221 // Accessors that tell you what kind of MachineOperand you're looking at. 222 //===--------------------------------------------------------------------===// 223 224 /// isReg - Tests if this is a MO_Register operand. 225 bool isReg() const { return OpKind == MO_Register; } 226 /// isImm - Tests if this is a MO_Immediate operand. 227 bool isImm() const { return OpKind == MO_Immediate; } 228 /// isCImm - Test if t his is a MO_CImmediate operand. 229 bool isCImm() const { return OpKind == MO_CImmediate; } 230 /// isFPImm - Tests if this is a MO_FPImmediate operand. 231 bool isFPImm() const { return OpKind == MO_FPImmediate; } 232 /// isMBB - Tests if this is a MO_MachineBasicBlock operand. 233 bool isMBB() const { return OpKind == MO_MachineBasicBlock; } 234 /// isFI - Tests if this is a MO_FrameIndex operand. 235 bool isFI() const { return OpKind == MO_FrameIndex; } 236 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand. 237 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; } 238 /// isTargetIndex - Tests if this is a MO_TargetIndex operand. 239 bool isTargetIndex() const { return OpKind == MO_TargetIndex; } 240 /// isJTI - Tests if this is a MO_JumpTableIndex operand. 241 bool isJTI() const { return OpKind == MO_JumpTableIndex; } 242 /// isGlobal - Tests if this is a MO_GlobalAddress operand. 243 bool isGlobal() const { return OpKind == MO_GlobalAddress; } 244 /// isSymbol - Tests if this is a MO_ExternalSymbol operand. 245 bool isSymbol() const { return OpKind == MO_ExternalSymbol; } 246 /// isBlockAddress - Tests if this is a MO_BlockAddress operand. 247 bool isBlockAddress() const { return OpKind == MO_BlockAddress; } 248 /// isRegMask - Tests if this is a MO_RegisterMask operand. 249 bool isRegMask() const { return OpKind == MO_RegisterMask; } 250 /// isMetadata - Tests if this is a MO_Metadata operand. 251 bool isMetadata() const { return OpKind == MO_Metadata; } 252 bool isMCSymbol() const { return OpKind == MO_MCSymbol; } 253 254 255 //===--------------------------------------------------------------------===// 256 // Accessors for Register Operands 257 //===--------------------------------------------------------------------===// 258 259 /// getReg - Returns the register number. 260 unsigned getReg() const { 261 assert(isReg() && "This is not a register operand!"); 262 return SmallContents.RegNo; 263 } 264 265 unsigned getSubReg() const { 266 assert(isReg() && "Wrong MachineOperand accessor"); 267 return (unsigned)SubReg; 268 } 269 270 bool isUse() const { 271 assert(isReg() && "Wrong MachineOperand accessor"); 272 return !IsDef; 273 } 274 275 bool isDef() const { 276 assert(isReg() && "Wrong MachineOperand accessor"); 277 return IsDef; 278 } 279 280 bool isImplicit() const { 281 assert(isReg() && "Wrong MachineOperand accessor"); 282 return IsImp; 283 } 284 285 bool isDead() const { 286 assert(isReg() && "Wrong MachineOperand accessor"); 287 return IsDead; 288 } 289 290 bool isKill() const { 291 assert(isReg() && "Wrong MachineOperand accessor"); 292 return IsKill; 293 } 294 295 bool isUndef() const { 296 assert(isReg() && "Wrong MachineOperand accessor"); 297 return IsUndef; 298 } 299 300 bool isInternalRead() const { 301 assert(isReg() && "Wrong MachineOperand accessor"); 302 return IsInternalRead; 303 } 304 305 bool isEarlyClobber() const { 306 assert(isReg() && "Wrong MachineOperand accessor"); 307 return IsEarlyClobber; 308 } 309 310 bool isTied() const { 311 assert(isReg() && "Wrong MachineOperand accessor"); 312 return IsTied; 313 } 314 315 bool isDebug() const { 316 assert(isReg() && "Wrong MachineOperand accessor"); 317 return IsDebug; 318 } 319 320 /// readsReg - Returns true if this operand reads the previous value of its 321 /// register. A use operand with the <undef> flag set doesn't read its 322 /// register. A sub-register def implicitly reads the other parts of the 323 /// register being redefined unless the <undef> flag is set. 324 /// 325 /// This refers to reading the register value from before the current 326 /// instruction or bundle. Internal bundle reads are not included. 327 bool readsReg() const { 328 assert(isReg() && "Wrong MachineOperand accessor"); 329 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); 330 } 331 332 //===--------------------------------------------------------------------===// 333 // Mutators for Register Operands 334 //===--------------------------------------------------------------------===// 335 336 /// Change the register this operand corresponds to. 337 /// 338 void setReg(unsigned Reg); 339 340 void setSubReg(unsigned subReg) { 341 assert(isReg() && "Wrong MachineOperand accessor"); 342 SubReg = (unsigned char)subReg; 343 } 344 345 /// substVirtReg - Substitute the current register with the virtual 346 /// subregister Reg:SubReg. Take any existing SubReg index into account, 347 /// using TargetRegisterInfo to compose the subreg indices if necessary. 348 /// Reg must be a virtual register, SubIdx can be 0. 349 /// 350 void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&); 351 352 /// substPhysReg - Substitute the current register with the physical register 353 /// Reg, taking any existing SubReg into account. For instance, 354 /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL. 355 /// 356 void substPhysReg(unsigned Reg, const TargetRegisterInfo&); 357 358 void setIsUse(bool Val = true) { setIsDef(!Val); } 359 360 void setIsDef(bool Val = true); 361 362 void setImplicit(bool Val = true) { 363 assert(isReg() && "Wrong MachineOperand accessor"); 364 IsImp = Val; 365 } 366 367 void setIsKill(bool Val = true) { 368 assert(isReg() && !IsDef && "Wrong MachineOperand accessor"); 369 assert((!Val || !isDebug()) && "Marking a debug operation as kill"); 370 IsKill = Val; 371 } 372 373 void setIsDead(bool Val = true) { 374 assert(isReg() && IsDef && "Wrong MachineOperand accessor"); 375 IsDead = Val; 376 } 377 378 void setIsUndef(bool Val = true) { 379 assert(isReg() && "Wrong MachineOperand accessor"); 380 IsUndef = Val; 381 } 382 383 void setIsInternalRead(bool Val = true) { 384 assert(isReg() && "Wrong MachineOperand accessor"); 385 IsInternalRead = Val; 386 } 387 388 void setIsEarlyClobber(bool Val = true) { 389 assert(isReg() && IsDef && "Wrong MachineOperand accessor"); 390 IsEarlyClobber = Val; 391 } 392 393 void setIsTied(bool Val = true) { 394 assert(isReg() && "Wrong MachineOperand accessor"); 395 IsTied = Val; 396 } 397 398 void setIsDebug(bool Val = true) { 399 assert(isReg() && IsDef && "Wrong MachineOperand accessor"); 400 IsDebug = Val; 401 } 402 403 //===--------------------------------------------------------------------===// 404 // Accessors for various operand types. 405 //===--------------------------------------------------------------------===// 406 407 int64_t getImm() const { 408 assert(isImm() && "Wrong MachineOperand accessor"); 409 return Contents.ImmVal; 410 } 411 412 const ConstantInt *getCImm() const { 413 assert(isCImm() && "Wrong MachineOperand accessor"); 414 return Contents.CI; 415 } 416 417 const ConstantFP *getFPImm() const { 418 assert(isFPImm() && "Wrong MachineOperand accessor"); 419 return Contents.CFP; 420 } 421 422 MachineBasicBlock *getMBB() const { 423 assert(isMBB() && "Wrong MachineOperand accessor"); 424 return Contents.MBB; 425 } 426 427 int getIndex() const { 428 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && 429 "Wrong MachineOperand accessor"); 430 return Contents.OffsetedInfo.Val.Index; 431 } 432 433 const GlobalValue *getGlobal() const { 434 assert(isGlobal() && "Wrong MachineOperand accessor"); 435 return Contents.OffsetedInfo.Val.GV; 436 } 437 438 const BlockAddress *getBlockAddress() const { 439 assert(isBlockAddress() && "Wrong MachineOperand accessor"); 440 return Contents.OffsetedInfo.Val.BA; 441 } 442 443 MCSymbol *getMCSymbol() const { 444 assert(isMCSymbol() && "Wrong MachineOperand accessor"); 445 return Contents.Sym; 446 } 447 448 /// getOffset - Return the offset from the symbol in this operand. This always 449 /// returns 0 for ExternalSymbol operands. 450 int64_t getOffset() const { 451 assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() || 452 isBlockAddress()) && "Wrong MachineOperand accessor"); 453 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) | 454 SmallContents.OffsetLo; 455 } 456 457 const char *getSymbolName() const { 458 assert(isSymbol() && "Wrong MachineOperand accessor"); 459 return Contents.OffsetedInfo.Val.SymbolName; 460 } 461 462 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 463 /// It is sometimes necessary to detach the register mask pointer from its 464 /// machine operand. This static method can be used for such detached bit 465 /// mask pointers. 466 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { 467 // See TargetRegisterInfo.h. 468 assert(PhysReg < (1u << 30) && "Not a physical register"); 469 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); 470 } 471 472 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 473 bool clobbersPhysReg(unsigned PhysReg) const { 474 return clobbersPhysReg(getRegMask(), PhysReg); 475 } 476 477 /// getRegMask - Returns a bit mask of registers preserved by this RegMask 478 /// operand. 479 const uint32_t *getRegMask() const { 480 assert(isRegMask() && "Wrong MachineOperand accessor"); 481 return Contents.RegMask; 482 } 483 484 const MDNode *getMetadata() const { 485 assert(isMetadata() && "Wrong MachineOperand accessor"); 486 return Contents.MD; 487 } 488 489 //===--------------------------------------------------------------------===// 490 // Mutators for various operand types. 491 //===--------------------------------------------------------------------===// 492 493 void setImm(int64_t immVal) { 494 assert(isImm() && "Wrong MachineOperand mutator"); 495 Contents.ImmVal = immVal; 496 } 497 498 void setOffset(int64_t Offset) { 499 assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() || 500 isBlockAddress()) && "Wrong MachineOperand accessor"); 501 SmallContents.OffsetLo = unsigned(Offset); 502 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32); 503 } 504 505 void setIndex(int Idx) { 506 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && 507 "Wrong MachineOperand accessor"); 508 Contents.OffsetedInfo.Val.Index = Idx; 509 } 510 511 void setMBB(MachineBasicBlock *MBB) { 512 assert(isMBB() && "Wrong MachineOperand accessor"); 513 Contents.MBB = MBB; 514 } 515 516 //===--------------------------------------------------------------------===// 517 // Other methods. 518 //===--------------------------------------------------------------------===// 519 520 /// isIdenticalTo - Return true if this operand is identical to the specified 521 /// operand. Note: This method ignores isKill and isDead properties. 522 bool isIdenticalTo(const MachineOperand &Other) const; 523 524 /// \brief MachineOperand hash_value overload. 525 /// 526 /// Note that this includes the same information in the hash that 527 /// isIdenticalTo uses for comparison. It is thus suited for use in hash 528 /// tables which use that function for equality comparisons only. 529 friend hash_code hash_value(const MachineOperand &MO); 530 531 /// ChangeToImmediate - Replace this operand with a new immediate operand of 532 /// the specified value. If an operand is known to be an immediate already, 533 /// the setImm method should be used. 534 void ChangeToImmediate(int64_t ImmVal); 535 536 /// ChangeToRegister - Replace this operand with a new register operand of 537 /// the specified value. If an operand is known to be an register already, 538 /// the setReg method should be used. 539 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 540 bool isKill = false, bool isDead = false, 541 bool isUndef = false, bool isDebug = false); 542 543 //===--------------------------------------------------------------------===// 544 // Construction methods. 545 //===--------------------------------------------------------------------===// 546 547 static MachineOperand CreateImm(int64_t Val) { 548 MachineOperand Op(MachineOperand::MO_Immediate); 549 Op.setImm(Val); 550 return Op; 551 } 552 553 static MachineOperand CreateCImm(const ConstantInt *CI) { 554 MachineOperand Op(MachineOperand::MO_CImmediate); 555 Op.Contents.CI = CI; 556 return Op; 557 } 558 559 static MachineOperand CreateFPImm(const ConstantFP *CFP) { 560 MachineOperand Op(MachineOperand::MO_FPImmediate); 561 Op.Contents.CFP = CFP; 562 return Op; 563 } 564 565 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 566 bool isKill = false, bool isDead = false, 567 bool isUndef = false, 568 bool isEarlyClobber = false, 569 unsigned SubReg = 0, 570 bool isDebug = false, 571 bool isInternalRead = false) { 572 MachineOperand Op(MachineOperand::MO_Register); 573 Op.IsDef = isDef; 574 Op.IsImp = isImp; 575 Op.IsKill = isKill; 576 Op.IsDead = isDead; 577 Op.IsUndef = isUndef; 578 Op.IsInternalRead = isInternalRead; 579 Op.IsEarlyClobber = isEarlyClobber; 580 Op.IsTied = false; 581 Op.IsDebug = isDebug; 582 Op.SmallContents.RegNo = Reg; 583 Op.Contents.Reg.Prev = 0; 584 Op.Contents.Reg.Next = 0; 585 Op.SubReg = SubReg; 586 return Op; 587 } 588 static MachineOperand CreateMBB(MachineBasicBlock *MBB, 589 unsigned char TargetFlags = 0) { 590 MachineOperand Op(MachineOperand::MO_MachineBasicBlock); 591 Op.setMBB(MBB); 592 Op.setTargetFlags(TargetFlags); 593 return Op; 594 } 595 static MachineOperand CreateFI(int Idx) { 596 MachineOperand Op(MachineOperand::MO_FrameIndex); 597 Op.setIndex(Idx); 598 return Op; 599 } 600 static MachineOperand CreateCPI(unsigned Idx, int Offset, 601 unsigned char TargetFlags = 0) { 602 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex); 603 Op.setIndex(Idx); 604 Op.setOffset(Offset); 605 Op.setTargetFlags(TargetFlags); 606 return Op; 607 } 608 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, 609 unsigned char TargetFlags = 0) { 610 MachineOperand Op(MachineOperand::MO_TargetIndex); 611 Op.setIndex(Idx); 612 Op.setOffset(Offset); 613 Op.setTargetFlags(TargetFlags); 614 return Op; 615 } 616 static MachineOperand CreateJTI(unsigned Idx, 617 unsigned char TargetFlags = 0) { 618 MachineOperand Op(MachineOperand::MO_JumpTableIndex); 619 Op.setIndex(Idx); 620 Op.setTargetFlags(TargetFlags); 621 return Op; 622 } 623 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, 624 unsigned char TargetFlags = 0) { 625 MachineOperand Op(MachineOperand::MO_GlobalAddress); 626 Op.Contents.OffsetedInfo.Val.GV = GV; 627 Op.setOffset(Offset); 628 Op.setTargetFlags(TargetFlags); 629 return Op; 630 } 631 static MachineOperand CreateES(const char *SymName, 632 unsigned char TargetFlags = 0) { 633 MachineOperand Op(MachineOperand::MO_ExternalSymbol); 634 Op.Contents.OffsetedInfo.Val.SymbolName = SymName; 635 Op.setOffset(0); // Offset is always 0. 636 Op.setTargetFlags(TargetFlags); 637 return Op; 638 } 639 static MachineOperand CreateBA(const BlockAddress *BA, 640 unsigned char TargetFlags = 0) { 641 MachineOperand Op(MachineOperand::MO_BlockAddress); 642 Op.Contents.OffsetedInfo.Val.BA = BA; 643 Op.setOffset(0); // Offset is always 0. 644 Op.setTargetFlags(TargetFlags); 645 return Op; 646 } 647 /// CreateRegMask - Creates a register mask operand referencing Mask. The 648 /// operand does not take ownership of the memory referenced by Mask, it must 649 /// remain valid for the lifetime of the operand. 650 /// 651 /// A RegMask operand represents a set of non-clobbered physical registers on 652 /// an instruction that clobbers many registers, typically a call. The bit 653 /// mask has a bit set for each physreg that is preserved by this 654 /// instruction, as described in the documentation for 655 /// TargetRegisterInfo::getCallPreservedMask(). 656 /// 657 /// Any physreg with a 0 bit in the mask is clobbered by the instruction. 658 /// 659 static MachineOperand CreateRegMask(const uint32_t *Mask) { 660 assert(Mask && "Missing register mask"); 661 MachineOperand Op(MachineOperand::MO_RegisterMask); 662 Op.Contents.RegMask = Mask; 663 return Op; 664 } 665 static MachineOperand CreateMetadata(const MDNode *Meta) { 666 MachineOperand Op(MachineOperand::MO_Metadata); 667 Op.Contents.MD = Meta; 668 return Op; 669 } 670 671 static MachineOperand CreateMCSymbol(MCSymbol *Sym) { 672 MachineOperand Op(MachineOperand::MO_MCSymbol); 673 Op.Contents.Sym = Sym; 674 return Op; 675 } 676 677 friend class MachineInstr; 678 friend class MachineRegisterInfo; 679private: 680 //===--------------------------------------------------------------------===// 681 // Methods for handling register use/def lists. 682 //===--------------------------------------------------------------------===// 683 684 /// isOnRegUseList - Return true if this operand is on a register use/def list 685 /// or false if not. This can only be called for register operands that are 686 /// part of a machine instruction. 687 bool isOnRegUseList() const { 688 assert(isReg() && "Can only add reg operand to use lists"); 689 return Contents.Reg.Prev != 0; 690 } 691}; 692 693inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) { 694 MO.print(OS, 0); 695 return OS; 696} 697 698} // End llvm namespace 699 700#endif 701