MCInst.h revision b6a2fc080f47eabdcaabf0101e9ca7c95e9d8bdc
1//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MCInst and MCOperand classes, which 11// is the basic representation used to represent low-level machine code 12// instructions. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCINST_H 17#define LLVM_MC_MCINST_H 18 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/Support/DataTypes.h" 21 22namespace llvm { 23class raw_ostream; 24class MCAsmInfo; 25class MCExpr; 26 27/// MCOperand - Instances of this class represent operands of the MCInst class. 28/// This is a simple discriminated union. 29class MCOperand { 30 enum MachineOperandType { 31 kInvalid, ///< Uninitialized. 32 kRegister, ///< Register operand. 33 kImmediate, ///< Immediate operand. 34 kExpr ///< Relocatable immediate operand. 35 }; 36 unsigned char Kind; 37 38 union { 39 unsigned RegVal; 40 int64_t ImmVal; 41 const MCExpr *ExprVal; 42 }; 43public: 44 45 MCOperand() : Kind(kInvalid) {} 46 MCOperand(const MCOperand &RHS) { *this = RHS; } 47 48 bool isValid() const { return Kind != kInvalid; } 49 bool isReg() const { return Kind == kRegister; } 50 bool isImm() const { return Kind == kImmediate; } 51 bool isExpr() const { return Kind == kExpr; } 52 53 /// getReg - Returns the register number. 54 unsigned getReg() const { 55 assert(isReg() && "This is not a register operand!"); 56 return RegVal; 57 } 58 59 /// setReg - Set the register number. 60 void setReg(unsigned Reg) { 61 assert(isReg() && "This is not a register operand!"); 62 RegVal = Reg; 63 } 64 65 int64_t getImm() const { 66 assert(isImm() && "This is not an immediate"); 67 return ImmVal; 68 } 69 void setImm(int64_t Val) { 70 assert(isImm() && "This is not an immediate"); 71 ImmVal = Val; 72 } 73 74 const MCExpr *getExpr() const { 75 assert(isExpr() && "This is not an expression"); 76 return ExprVal; 77 } 78 void setExpr(const MCExpr *Val) { 79 assert(isExpr() && "This is not an expression"); 80 ExprVal = Val; 81 } 82 83 static MCOperand CreateReg(unsigned Reg) { 84 MCOperand Op; 85 Op.Kind = kRegister; 86 Op.RegVal = Reg; 87 return Op; 88 } 89 static MCOperand CreateImm(int64_t Val) { 90 MCOperand Op; 91 Op.Kind = kImmediate; 92 Op.ImmVal = Val; 93 return Op; 94 } 95 static MCOperand CreateExpr(const MCExpr *Val) { 96 MCOperand Op; 97 Op.Kind = kExpr; 98 Op.ExprVal = Val; 99 return Op; 100 } 101 102 void print(raw_ostream &OS, const MCAsmInfo *MAI) const; 103 void dump() const; 104}; 105 106 107/// MCInst - Instances of this class represent a single low-level machine 108/// instruction. 109class MCInst { 110 unsigned Opcode; 111 SmallVector<MCOperand, 8> Operands; 112public: 113 MCInst() : Opcode(0) {} 114 115 void setOpcode(unsigned Op) { Opcode = Op; } 116 117 unsigned getOpcode() const { return Opcode; } 118 119 const MCOperand &getOperand(unsigned i) const { return Operands[i]; } 120 MCOperand &getOperand(unsigned i) { return Operands[i]; } 121 unsigned getNumOperands() const { return Operands.size(); } 122 123 void addOperand(const MCOperand &Op) { 124 Operands.push_back(Op); 125 } 126 127 void print(raw_ostream &OS, const MCAsmInfo *MAI) const; 128 void dump() const; 129}; 130 131 132} // end namespace llvm 133 134#endif 135