MachineInstr.cpp revision 2ccc83966914593d98af5671ce10a3bf2dcf7513
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Constants.h" 15#include "llvm/CodeGen/MachineInstr.h" 16#include "llvm/Value.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineRegisterInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include "llvm/Target/TargetInstrDesc.h" 23#include "llvm/Target/TargetRegisterInfo.h" 24#include "llvm/Support/LeakDetector.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/Streams.h" 27#include "llvm/Support/raw_ostream.h" 28#include "llvm/ADT/FoldingSet.h" 29#include <ostream> 30using namespace llvm; 31 32//===----------------------------------------------------------------------===// 33// MachineOperand Implementation 34//===----------------------------------------------------------------------===// 35 36/// AddRegOperandToRegInfo - Add this register operand to the specified 37/// MachineRegisterInfo. If it is null, then the next/prev fields should be 38/// explicitly nulled out. 39void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 40 assert(isReg() && "Can only add reg operand to use lists"); 41 42 // If the reginfo pointer is null, just explicitly null out or next/prev 43 // pointers, to ensure they are not garbage. 44 if (RegInfo == 0) { 45 Contents.Reg.Prev = 0; 46 Contents.Reg.Next = 0; 47 return; 48 } 49 50 // Otherwise, add this operand to the head of the registers use/def list. 51 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 52 53 // For SSA values, we prefer to keep the definition at the start of the list. 54 // we do this by skipping over the definition if it is at the head of the 55 // list. 56 if (*Head && (*Head)->isDef()) 57 Head = &(*Head)->Contents.Reg.Next; 58 59 Contents.Reg.Next = *Head; 60 if (Contents.Reg.Next) { 61 assert(getReg() == Contents.Reg.Next->getReg() && 62 "Different regs on the same list!"); 63 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 64 } 65 66 Contents.Reg.Prev = Head; 67 *Head = this; 68} 69 70void MachineOperand::setReg(unsigned Reg) { 71 if (getReg() == Reg) return; // No change. 72 73 // Otherwise, we have to change the register. If this operand is embedded 74 // into a machine function, we need to update the old and new register's 75 // use/def lists. 76 if (MachineInstr *MI = getParent()) 77 if (MachineBasicBlock *MBB = MI->getParent()) 78 if (MachineFunction *MF = MBB->getParent()) { 79 RemoveRegOperandFromRegInfo(); 80 Contents.Reg.RegNo = Reg; 81 AddRegOperandToRegInfo(&MF->getRegInfo()); 82 return; 83 } 84 85 // Otherwise, just change the register, no problem. :) 86 Contents.Reg.RegNo = Reg; 87} 88 89/// ChangeToImmediate - Replace this operand with a new immediate operand of 90/// the specified value. If an operand is known to be an immediate already, 91/// the setImm method should be used. 92void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 93 // If this operand is currently a register operand, and if this is in a 94 // function, deregister the operand from the register's use/def list. 95 if (isReg() && getParent() && getParent()->getParent() && 96 getParent()->getParent()->getParent()) 97 RemoveRegOperandFromRegInfo(); 98 99 OpKind = MO_Immediate; 100 Contents.ImmVal = ImmVal; 101} 102 103/// ChangeToRegister - Replace this operand with a new register operand of 104/// the specified value. If an operand is known to be an register already, 105/// the setReg method should be used. 106void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 107 bool isKill, bool isDead) { 108 // If this operand is already a register operand, use setReg to update the 109 // register's use/def lists. 110 if (isReg()) { 111 assert(!isEarlyClobber()); 112 setReg(Reg); 113 } else { 114 // Otherwise, change this to a register and set the reg#. 115 OpKind = MO_Register; 116 Contents.Reg.RegNo = Reg; 117 118 // If this operand is embedded in a function, add the operand to the 119 // register's use/def list. 120 if (MachineInstr *MI = getParent()) 121 if (MachineBasicBlock *MBB = MI->getParent()) 122 if (MachineFunction *MF = MBB->getParent()) 123 AddRegOperandToRegInfo(&MF->getRegInfo()); 124 } 125 126 IsDef = isDef; 127 IsImp = isImp; 128 IsKill = isKill; 129 IsDead = isDead; 130 IsEarlyClobber = false; 131 SubReg = 0; 132} 133 134/// isIdenticalTo - Return true if this operand is identical to the specified 135/// operand. 136bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 137 if (getType() != Other.getType()) return false; 138 139 switch (getType()) { 140 default: assert(0 && "Unrecognized operand type"); 141 case MachineOperand::MO_Register: 142 return getReg() == Other.getReg() && isDef() == Other.isDef() && 143 getSubReg() == Other.getSubReg(); 144 case MachineOperand::MO_Immediate: 145 return getImm() == Other.getImm(); 146 case MachineOperand::MO_FPImmediate: 147 return getFPImm() == Other.getFPImm(); 148 case MachineOperand::MO_MachineBasicBlock: 149 return getMBB() == Other.getMBB(); 150 case MachineOperand::MO_FrameIndex: 151 return getIndex() == Other.getIndex(); 152 case MachineOperand::MO_ConstantPoolIndex: 153 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 154 case MachineOperand::MO_JumpTableIndex: 155 return getIndex() == Other.getIndex(); 156 case MachineOperand::MO_GlobalAddress: 157 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 158 case MachineOperand::MO_ExternalSymbol: 159 return !strcmp(getSymbolName(), Other.getSymbolName()) && 160 getOffset() == Other.getOffset(); 161 } 162} 163 164/// print - Print the specified machine operand. 165/// 166void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { 167 raw_os_ostream RawOS(OS); 168 print(RawOS, TM); 169} 170 171void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 172 switch (getType()) { 173 case MachineOperand::MO_Register: 174 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 175 OS << "%reg" << getReg(); 176 } else { 177 // If the instruction is embedded into a basic block, we can find the 178 // target info for the instruction. 179 if (TM == 0) 180 if (const MachineInstr *MI = getParent()) 181 if (const MachineBasicBlock *MBB = MI->getParent()) 182 if (const MachineFunction *MF = MBB->getParent()) 183 TM = &MF->getTarget(); 184 185 if (TM) 186 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 187 else 188 OS << "%mreg" << getReg(); 189 } 190 191 if (getSubReg() != 0) { 192 OS << ":" << getSubReg(); 193 } 194 195 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) { 196 OS << "<"; 197 bool NeedComma = false; 198 if (isImplicit()) { 199 if (NeedComma) OS << ","; 200 OS << (isDef() ? "imp-def" : "imp-use"); 201 NeedComma = true; 202 } else if (isDef()) { 203 if (NeedComma) OS << ","; 204 if (isEarlyClobber()) 205 OS << "earlyclobber,"; 206 OS << "def"; 207 NeedComma = true; 208 } 209 if (isKill() || isDead()) { 210 if (NeedComma) OS << ","; 211 if (isKill()) OS << "kill"; 212 if (isDead()) OS << "dead"; 213 } 214 OS << ">"; 215 } 216 break; 217 case MachineOperand::MO_Immediate: 218 OS << getImm(); 219 break; 220 case MachineOperand::MO_FPImmediate: 221 if (getFPImm()->getType() == Type::FloatTy) { 222 OS << getFPImm()->getValueAPF().convertToFloat(); 223 } else { 224 OS << getFPImm()->getValueAPF().convertToDouble(); 225 } 226 break; 227 case MachineOperand::MO_MachineBasicBlock: 228 OS << "mbb<" 229 << ((Value*)getMBB()->getBasicBlock())->getName() 230 << "," << (void*)getMBB() << ">"; 231 break; 232 case MachineOperand::MO_FrameIndex: 233 OS << "<fi#" << getIndex() << ">"; 234 break; 235 case MachineOperand::MO_ConstantPoolIndex: 236 OS << "<cp#" << getIndex(); 237 if (getOffset()) OS << "+" << getOffset(); 238 OS << ">"; 239 break; 240 case MachineOperand::MO_JumpTableIndex: 241 OS << "<jt#" << getIndex() << ">"; 242 break; 243 case MachineOperand::MO_GlobalAddress: 244 OS << "<ga:" << ((Value*)getGlobal())->getName(); 245 if (getOffset()) OS << "+" << getOffset(); 246 OS << ">"; 247 break; 248 case MachineOperand::MO_ExternalSymbol: 249 OS << "<es:" << getSymbolName(); 250 if (getOffset()) OS << "+" << getOffset(); 251 OS << ">"; 252 break; 253 default: 254 assert(0 && "Unrecognized operand type"); 255 } 256} 257 258//===----------------------------------------------------------------------===// 259// MachineMemOperand Implementation 260//===----------------------------------------------------------------------===// 261 262MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 263 int64_t o, uint64_t s, unsigned int a) 264 : Offset(o), Size(s), V(v), 265 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) { 266 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!"); 267 assert((isLoad() || isStore()) && "Not a load/store!"); 268} 269 270/// Profile - Gather unique data for the object. 271/// 272void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 273 ID.AddInteger(Offset); 274 ID.AddInteger(Size); 275 ID.AddPointer(V); 276 ID.AddInteger(Flags); 277} 278 279//===----------------------------------------------------------------------===// 280// MachineInstr Implementation 281//===----------------------------------------------------------------------===// 282 283/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 284/// TID NULL and no operands. 285MachineInstr::MachineInstr() 286 : TID(0), NumImplicitOps(0), Parent(0) { 287 // Make sure that we get added to a machine basicblock 288 LeakDetector::addGarbageObject(this); 289} 290 291void MachineInstr::addImplicitDefUseOperands() { 292 if (TID->ImplicitDefs) 293 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 294 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 295 if (TID->ImplicitUses) 296 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 297 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 298} 299 300/// MachineInstr ctor - This constructor create a MachineInstr and add the 301/// implicit operands. It reserves space for number of operands specified by 302/// TargetInstrDesc or the numOperands if it is not zero. (for 303/// instructions with variable number of operands). 304MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 305 : TID(&tid), NumImplicitOps(0), Parent(0) { 306 if (!NoImp && TID->getImplicitDefs()) 307 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 308 NumImplicitOps++; 309 if (!NoImp && TID->getImplicitUses()) 310 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 311 NumImplicitOps++; 312 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 313 if (!NoImp) 314 addImplicitDefUseOperands(); 315 // Make sure that we get added to a machine basicblock 316 LeakDetector::addGarbageObject(this); 317} 318 319/// MachineInstr ctor - Work exactly the same as the ctor above, except that the 320/// MachineInstr is created and added to the end of the specified basic block. 321/// 322MachineInstr::MachineInstr(MachineBasicBlock *MBB, 323 const TargetInstrDesc &tid) 324 : TID(&tid), NumImplicitOps(0), Parent(0) { 325 assert(MBB && "Cannot use inserting ctor with null basic block!"); 326 if (TID->ImplicitDefs) 327 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 328 NumImplicitOps++; 329 if (TID->ImplicitUses) 330 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 331 NumImplicitOps++; 332 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 333 addImplicitDefUseOperands(); 334 // Make sure that we get added to a machine basicblock 335 LeakDetector::addGarbageObject(this); 336 MBB->push_back(this); // Add instruction to end of basic block! 337} 338 339/// MachineInstr ctor - Copies MachineInstr arg exactly 340/// 341MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 342 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) { 343 Operands.reserve(MI.getNumOperands()); 344 345 // Add operands 346 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 347 addOperand(MI.getOperand(i)); 348 NumImplicitOps = MI.NumImplicitOps; 349 350 // Add memory operands. 351 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(), 352 j = MI.memoperands_end(); i != j; ++i) 353 addMemOperand(MF, *i); 354 355 // Set parent to null. 356 Parent = 0; 357 358 LeakDetector::addGarbageObject(this); 359} 360 361MachineInstr::~MachineInstr() { 362 LeakDetector::removeGarbageObject(this); 363 assert(MemOperands.empty() && 364 "MachineInstr being deleted with live memoperands!"); 365#ifndef NDEBUG 366 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 367 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 368 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 369 "Reg operand def/use list corrupted"); 370 } 371#endif 372} 373 374/// getRegInfo - If this instruction is embedded into a MachineFunction, 375/// return the MachineRegisterInfo object for the current function, otherwise 376/// return null. 377MachineRegisterInfo *MachineInstr::getRegInfo() { 378 if (MachineBasicBlock *MBB = getParent()) 379 return &MBB->getParent()->getRegInfo(); 380 return 0; 381} 382 383/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 384/// this instruction from their respective use lists. This requires that the 385/// operands already be on their use lists. 386void MachineInstr::RemoveRegOperandsFromUseLists() { 387 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 388 if (Operands[i].isReg()) 389 Operands[i].RemoveRegOperandFromRegInfo(); 390 } 391} 392 393/// AddRegOperandsToUseLists - Add all of the register operands in 394/// this instruction from their respective use lists. This requires that the 395/// operands not be on their use lists yet. 396void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 397 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 398 if (Operands[i].isReg()) 399 Operands[i].AddRegOperandToRegInfo(&RegInfo); 400 } 401} 402 403 404/// addOperand - Add the specified operand to the instruction. If it is an 405/// implicit operand, it is added to the end of the operand list. If it is 406/// an explicit operand it is added at the end of the explicit operand list 407/// (before the first implicit operand). 408void MachineInstr::addOperand(const MachineOperand &Op) { 409 bool isImpReg = Op.isReg() && Op.isImplicit(); 410 assert((isImpReg || !OperandsComplete()) && 411 "Trying to add an operand to a machine instr that is already done!"); 412 413 MachineRegisterInfo *RegInfo = getRegInfo(); 414 415 // If we are adding the operand to the end of the list, our job is simpler. 416 // This is true most of the time, so this is a reasonable optimization. 417 if (isImpReg || NumImplicitOps == 0) { 418 // We can only do this optimization if we know that the operand list won't 419 // reallocate. 420 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 421 Operands.push_back(Op); 422 423 // Set the parent of the operand. 424 Operands.back().ParentMI = this; 425 426 // If the operand is a register, update the operand's use list. 427 if (Op.isReg()) 428 Operands.back().AddRegOperandToRegInfo(RegInfo); 429 return; 430 } 431 } 432 433 // Otherwise, we have to insert a real operand before any implicit ones. 434 unsigned OpNo = Operands.size()-NumImplicitOps; 435 436 // If this instruction isn't embedded into a function, then we don't need to 437 // update any operand lists. 438 if (RegInfo == 0) { 439 // Simple insertion, no reginfo update needed for other register operands. 440 Operands.insert(Operands.begin()+OpNo, Op); 441 Operands[OpNo].ParentMI = this; 442 443 // Do explicitly set the reginfo for this operand though, to ensure the 444 // next/prev fields are properly nulled out. 445 if (Operands[OpNo].isReg()) 446 Operands[OpNo].AddRegOperandToRegInfo(0); 447 448 } else if (Operands.size()+1 <= Operands.capacity()) { 449 // Otherwise, we have to remove register operands from their register use 450 // list, add the operand, then add the register operands back to their use 451 // list. This also must handle the case when the operand list reallocates 452 // to somewhere else. 453 454 // If insertion of this operand won't cause reallocation of the operand 455 // list, just remove the implicit operands, add the operand, then re-add all 456 // the rest of the operands. 457 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 458 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 459 Operands[i].RemoveRegOperandFromRegInfo(); 460 } 461 462 // Add the operand. If it is a register, add it to the reg list. 463 Operands.insert(Operands.begin()+OpNo, Op); 464 Operands[OpNo].ParentMI = this; 465 466 if (Operands[OpNo].isReg()) 467 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 468 469 // Re-add all the implicit ops. 470 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 471 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 472 Operands[i].AddRegOperandToRegInfo(RegInfo); 473 } 474 } else { 475 // Otherwise, we will be reallocating the operand list. Remove all reg 476 // operands from their list, then readd them after the operand list is 477 // reallocated. 478 RemoveRegOperandsFromUseLists(); 479 480 Operands.insert(Operands.begin()+OpNo, Op); 481 Operands[OpNo].ParentMI = this; 482 483 // Re-add all the operands. 484 AddRegOperandsToUseLists(*RegInfo); 485 } 486} 487 488/// RemoveOperand - Erase an operand from an instruction, leaving it with one 489/// fewer operand than it started with. 490/// 491void MachineInstr::RemoveOperand(unsigned OpNo) { 492 assert(OpNo < Operands.size() && "Invalid operand number"); 493 494 // Special case removing the last one. 495 if (OpNo == Operands.size()-1) { 496 // If needed, remove from the reg def/use list. 497 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 498 Operands.back().RemoveRegOperandFromRegInfo(); 499 500 Operands.pop_back(); 501 return; 502 } 503 504 // Otherwise, we are removing an interior operand. If we have reginfo to 505 // update, remove all operands that will be shifted down from their reg lists, 506 // move everything down, then re-add them. 507 MachineRegisterInfo *RegInfo = getRegInfo(); 508 if (RegInfo) { 509 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 510 if (Operands[i].isReg()) 511 Operands[i].RemoveRegOperandFromRegInfo(); 512 } 513 } 514 515 Operands.erase(Operands.begin()+OpNo); 516 517 if (RegInfo) { 518 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 519 if (Operands[i].isReg()) 520 Operands[i].AddRegOperandToRegInfo(RegInfo); 521 } 522 } 523} 524 525/// addMemOperand - Add a MachineMemOperand to the machine instruction, 526/// referencing arbitrary storage. 527void MachineInstr::addMemOperand(MachineFunction &MF, 528 const MachineMemOperand &MO) { 529 MemOperands.push_back(MO); 530} 531 532/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands. 533void MachineInstr::clearMemOperands(MachineFunction &MF) { 534 MemOperands.clear(); 535} 536 537 538/// removeFromParent - This method unlinks 'this' from the containing basic 539/// block, and returns it, but does not delete it. 540MachineInstr *MachineInstr::removeFromParent() { 541 assert(getParent() && "Not embedded in a basic block!"); 542 getParent()->remove(this); 543 return this; 544} 545 546 547/// eraseFromParent - This method unlinks 'this' from the containing basic 548/// block, and deletes it. 549void MachineInstr::eraseFromParent() { 550 assert(getParent() && "Not embedded in a basic block!"); 551 getParent()->erase(this); 552} 553 554 555/// OperandComplete - Return true if it's illegal to add a new operand 556/// 557bool MachineInstr::OperandsComplete() const { 558 unsigned short NumOperands = TID->getNumOperands(); 559 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 560 return true; // Broken: we have all the operands of this instruction! 561 return false; 562} 563 564/// getNumExplicitOperands - Returns the number of non-implicit operands. 565/// 566unsigned MachineInstr::getNumExplicitOperands() const { 567 unsigned NumOperands = TID->getNumOperands(); 568 if (!TID->isVariadic()) 569 return NumOperands; 570 571 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { 572 const MachineOperand &MO = getOperand(NumOperands); 573 if (!MO.isReg() || !MO.isImplicit()) 574 NumOperands++; 575 } 576 return NumOperands; 577} 578 579 580/// isLabel - Returns true if the MachineInstr represents a label. 581/// 582bool MachineInstr::isLabel() const { 583 return getOpcode() == TargetInstrInfo::DBG_LABEL || 584 getOpcode() == TargetInstrInfo::EH_LABEL || 585 getOpcode() == TargetInstrInfo::GC_LABEL; 586} 587 588/// isDebugLabel - Returns true if the MachineInstr represents a debug label. 589/// 590bool MachineInstr::isDebugLabel() const { 591 return getOpcode() == TargetInstrInfo::DBG_LABEL; 592} 593 594/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 595/// the specific register or -1 if it is not found. It further tightening 596/// the search criteria to a use that kills the register if isKill is true. 597int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 598 const TargetRegisterInfo *TRI) const { 599 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 600 const MachineOperand &MO = getOperand(i); 601 if (!MO.isReg() || !MO.isUse()) 602 continue; 603 unsigned MOReg = MO.getReg(); 604 if (!MOReg) 605 continue; 606 if (MOReg == Reg || 607 (TRI && 608 TargetRegisterInfo::isPhysicalRegister(MOReg) && 609 TargetRegisterInfo::isPhysicalRegister(Reg) && 610 TRI->isSubRegister(MOReg, Reg))) 611 if (!isKill || MO.isKill()) 612 return i; 613 } 614 return -1; 615} 616 617/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 618/// the specified register or -1 if it is not found. If isDead is true, defs 619/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 620/// also checks if there is a def of a super-register. 621int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 622 const TargetRegisterInfo *TRI) const { 623 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 624 const MachineOperand &MO = getOperand(i); 625 if (!MO.isReg() || !MO.isDef()) 626 continue; 627 unsigned MOReg = MO.getReg(); 628 if (MOReg == Reg || 629 (TRI && 630 TargetRegisterInfo::isPhysicalRegister(MOReg) && 631 TargetRegisterInfo::isPhysicalRegister(Reg) && 632 TRI->isSubRegister(MOReg, Reg))) 633 if (!isDead || MO.isDead()) 634 return i; 635 } 636 return -1; 637} 638 639/// findFirstPredOperandIdx() - Find the index of the first operand in the 640/// operand list that is used to represent the predicate. It returns -1 if 641/// none is found. 642int MachineInstr::findFirstPredOperandIdx() const { 643 const TargetInstrDesc &TID = getDesc(); 644 if (TID.isPredicable()) { 645 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 646 if (TID.OpInfo[i].isPredicate()) 647 return i; 648 } 649 650 return -1; 651} 652 653/// isRegReDefinedByTwoAddr - Given the index of a register def operand, 654/// check if the register def is a re-definition due to two addr elimination. 655bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{ 656 assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!"); 657 const TargetInstrDesc &TID = getDesc(); 658 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 659 const MachineOperand &MO = getOperand(i); 660 if (MO.isReg() && MO.isUse() && 661 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx) 662 return true; 663 } 664 return false; 665} 666 667/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 668/// 669void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 670 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 671 const MachineOperand &MO = MI->getOperand(i); 672 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 673 continue; 674 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 675 MachineOperand &MOp = getOperand(j); 676 if (!MOp.isIdenticalTo(MO)) 677 continue; 678 if (MO.isKill()) 679 MOp.setIsKill(); 680 else 681 MOp.setIsDead(); 682 break; 683 } 684 } 685} 686 687/// copyPredicates - Copies predicate operand(s) from MI. 688void MachineInstr::copyPredicates(const MachineInstr *MI) { 689 const TargetInstrDesc &TID = MI->getDesc(); 690 if (!TID.isPredicable()) 691 return; 692 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 693 if (TID.OpInfo[i].isPredicate()) { 694 // Predicated operands must be last operands. 695 addOperand(MI->getOperand(i)); 696 } 697 } 698} 699 700/// isSafeToMove - Return true if it is safe to move this instruction. If 701/// SawStore is set to true, it means that there is a store (or call) between 702/// the instruction's location and its intended destination. 703bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 704 bool &SawStore) const { 705 // Ignore stuff that we obviously can't move. 706 if (TID->mayStore() || TID->isCall()) { 707 SawStore = true; 708 return false; 709 } 710 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects()) 711 return false; 712 713 // See if this instruction does a load. If so, we have to guarantee that the 714 // loaded value doesn't change between the load and the its intended 715 // destination. The check for isInvariantLoad gives the targe the chance to 716 // classify the load as always returning a constant, e.g. a constant pool 717 // load. 718 if (TID->mayLoad() && !TII->isInvariantLoad(this)) 719 // Otherwise, this is a real load. If there is a store between the load and 720 // end of block, or if the laod is volatile, we can't move it. 721 return !SawStore && !hasVolatileMemoryRef(); 722 723 return true; 724} 725 726/// isSafeToReMat - Return true if it's safe to rematerialize the specified 727/// instruction which defined the specified register instead of copying it. 728bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 729 unsigned DstReg) const { 730 bool SawStore = false; 731 if (!getDesc().isRematerializable() || 732 !TII->isTriviallyReMaterializable(this) || 733 !isSafeToMove(TII, SawStore)) 734 return false; 735 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 736 const MachineOperand &MO = getOperand(i); 737 if (!MO.isReg()) 738 continue; 739 // FIXME: For now, do not remat any instruction with register operands. 740 // Later on, we can loosen the restriction is the register operands have 741 // not been modified between the def and use. Note, this is different from 742 // MachineSink because the code is no longer in two-address form (at least 743 // partially). 744 if (MO.isUse()) 745 return false; 746 else if (!MO.isDead() && MO.getReg() != DstReg) 747 return false; 748 } 749 return true; 750} 751 752/// hasVolatileMemoryRef - Return true if this instruction may have a 753/// volatile memory reference, or if the information describing the 754/// memory reference is not available. Return false if it is known to 755/// have no volatile memory references. 756bool MachineInstr::hasVolatileMemoryRef() const { 757 // An instruction known never to access memory won't have a volatile access. 758 if (!TID->mayStore() && 759 !TID->mayLoad() && 760 !TID->isCall() && 761 !TID->hasUnmodeledSideEffects()) 762 return false; 763 764 // Otherwise, if the instruction has no memory reference information, 765 // conservatively assume it wasn't preserved. 766 if (memoperands_empty()) 767 return true; 768 769 // Check the memory reference information for volatile references. 770 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(), 771 E = memoperands_end(); I != E; ++I) 772 if (I->isVolatile()) 773 return true; 774 775 return false; 776} 777 778void MachineInstr::dump() const { 779 cerr << " " << *this; 780} 781 782void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { 783 raw_os_ostream RawOS(OS); 784 print(RawOS, TM); 785} 786 787void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 788 // Specialize printing if op#0 is definition 789 unsigned StartOp = 0; 790 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) { 791 getOperand(0).print(OS, TM); 792 OS << " = "; 793 ++StartOp; // Don't print this operand again! 794 } 795 796 OS << getDesc().getName(); 797 798 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 799 if (i != StartOp) 800 OS << ","; 801 OS << " "; 802 getOperand(i).print(OS, TM); 803 } 804 805 if (!memoperands_empty()) { 806 OS << ", Mem:"; 807 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(), 808 e = memoperands_end(); i != e; ++i) { 809 const MachineMemOperand &MRO = *i; 810 const Value *V = MRO.getValue(); 811 812 assert((MRO.isLoad() || MRO.isStore()) && 813 "SV has to be a load, store or both."); 814 815 if (MRO.isVolatile()) 816 OS << "Volatile "; 817 818 if (MRO.isLoad()) 819 OS << "LD"; 820 if (MRO.isStore()) 821 OS << "ST"; 822 823 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") ["; 824 825 if (!V) 826 OS << "<unknown>"; 827 else if (!V->getName().empty()) 828 OS << V->getName(); 829 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 830 PSV->print(OS); 831 } else 832 OS << V; 833 834 OS << " + " << MRO.getOffset() << "]"; 835 } 836 } 837 838 OS << "\n"; 839} 840 841bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 842 const TargetRegisterInfo *RegInfo, 843 bool AddIfNotFound) { 844 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 845 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 846 bool Found = false; 847 SmallVector<unsigned,4> DeadOps; 848 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 849 MachineOperand &MO = getOperand(i); 850 if (!MO.isReg() || !MO.isUse()) 851 continue; 852 unsigned Reg = MO.getReg(); 853 if (!Reg) 854 continue; 855 856 if (Reg == IncomingReg) { 857 if (!Found) { 858 if (MO.isKill()) 859 // The register is already marked kill. 860 return true; 861 MO.setIsKill(); 862 Found = true; 863 } 864 } else if (hasAliases && MO.isKill() && 865 TargetRegisterInfo::isPhysicalRegister(Reg)) { 866 // A super-register kill already exists. 867 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 868 return true; 869 if (RegInfo->isSubRegister(IncomingReg, Reg)) 870 DeadOps.push_back(i); 871 } 872 } 873 874 // Trim unneeded kill operands. 875 while (!DeadOps.empty()) { 876 unsigned OpIdx = DeadOps.back(); 877 if (getOperand(OpIdx).isImplicit()) 878 RemoveOperand(OpIdx); 879 else 880 getOperand(OpIdx).setIsKill(false); 881 DeadOps.pop_back(); 882 } 883 884 // If not found, this means an alias of one of the operands is killed. Add a 885 // new implicit operand if required. 886 if (!Found && AddIfNotFound) { 887 addOperand(MachineOperand::CreateReg(IncomingReg, 888 false /*IsDef*/, 889 true /*IsImp*/, 890 true /*IsKill*/)); 891 return true; 892 } 893 return Found; 894} 895 896bool MachineInstr::addRegisterDead(unsigned IncomingReg, 897 const TargetRegisterInfo *RegInfo, 898 bool AddIfNotFound) { 899 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 900 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 901 bool Found = false; 902 SmallVector<unsigned,4> DeadOps; 903 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 904 MachineOperand &MO = getOperand(i); 905 if (!MO.isReg() || !MO.isDef()) 906 continue; 907 unsigned Reg = MO.getReg(); 908 if (!Reg) 909 continue; 910 911 if (Reg == IncomingReg) { 912 if (!Found) { 913 if (MO.isDead()) 914 // The register is already marked dead. 915 return true; 916 MO.setIsDead(); 917 Found = true; 918 } 919 } else if (hasAliases && MO.isDead() && 920 TargetRegisterInfo::isPhysicalRegister(Reg)) { 921 // There exists a super-register that's marked dead. 922 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 923 return true; 924 if (RegInfo->getSubRegisters(IncomingReg) && 925 RegInfo->getSuperRegisters(Reg) && 926 RegInfo->isSubRegister(IncomingReg, Reg)) 927 DeadOps.push_back(i); 928 } 929 } 930 931 // Trim unneeded dead operands. 932 while (!DeadOps.empty()) { 933 unsigned OpIdx = DeadOps.back(); 934 if (getOperand(OpIdx).isImplicit()) 935 RemoveOperand(OpIdx); 936 else 937 getOperand(OpIdx).setIsDead(false); 938 DeadOps.pop_back(); 939 } 940 941 // If not found, this means an alias of one of the operands is dead. Add a 942 // new implicit operand if required. 943 if (!Found && AddIfNotFound) { 944 addOperand(MachineOperand::CreateReg(IncomingReg, 945 true /*IsDef*/, 946 true /*IsImp*/, 947 false /*IsKill*/, 948 true /*IsDead*/)); 949 return true; 950 } 951 return Found; 952} 953