FunctionLoweringInfo.cpp revision d858e90f039f5fcdc2fa93035e911a5a9505cc50
1//===-- FunctionLoweringInfo.cpp ------------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating functions from LLVM IR into 11// Machine IR. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "function-lowering-info" 16#include "FunctionLoweringInfo.h" 17#include "llvm/CallingConv.h" 18#include "llvm/DerivedTypes.h" 19#include "llvm/Function.h" 20#include "llvm/Instructions.h" 21#include "llvm/IntrinsicInst.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/Module.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineModuleInfo.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/Analysis/DebugInfo.h" 30#include "llvm/Target/TargetRegisterInfo.h" 31#include "llvm/Target/TargetData.h" 32#include "llvm/Target/TargetFrameInfo.h" 33#include "llvm/Target/TargetInstrInfo.h" 34#include "llvm/Target/TargetIntrinsicInfo.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetOptions.h" 37#include "llvm/Support/Compiler.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Support/ErrorHandling.h" 40#include "llvm/Support/MathExtras.h" 41#include "llvm/Support/raw_ostream.h" 42#include <algorithm> 43using namespace llvm; 44 45/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence 46/// of insertvalue or extractvalue indices that identify a member, return 47/// the linearized index of the start of the member. 48/// 49unsigned llvm::ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, 50 const unsigned *Indices, 51 const unsigned *IndicesEnd, 52 unsigned CurIndex) { 53 // Base case: We're done. 54 if (Indices && Indices == IndicesEnd) 55 return CurIndex; 56 57 // Given a struct type, recursively traverse the elements. 58 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 59 for (StructType::element_iterator EB = STy->element_begin(), 60 EI = EB, 61 EE = STy->element_end(); 62 EI != EE; ++EI) { 63 if (Indices && *Indices == unsigned(EI - EB)) 64 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex); 65 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex); 66 } 67 return CurIndex; 68 } 69 // Given an array type, recursively traverse the elements. 70 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 71 const Type *EltTy = ATy->getElementType(); 72 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) { 73 if (Indices && *Indices == i) 74 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex); 75 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex); 76 } 77 return CurIndex; 78 } 79 // We haven't found the type we're looking for, so keep searching. 80 return CurIndex + 1; 81} 82 83/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of 84/// EVTs that represent all the individual underlying 85/// non-aggregate types that comprise it. 86/// 87/// If Offsets is non-null, it points to a vector to be filled in 88/// with the in-memory offsets of each of the individual values. 89/// 90void llvm::ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, 91 SmallVectorImpl<EVT> &ValueVTs, 92 SmallVectorImpl<uint64_t> *Offsets, 93 uint64_t StartingOffset) { 94 // Given a struct type, recursively traverse the elements. 95 if (const StructType *STy = dyn_cast<StructType>(Ty)) { 96 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy); 97 for (StructType::element_iterator EB = STy->element_begin(), 98 EI = EB, 99 EE = STy->element_end(); 100 EI != EE; ++EI) 101 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets, 102 StartingOffset + SL->getElementOffset(EI - EB)); 103 return; 104 } 105 // Given an array type, recursively traverse the elements. 106 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 107 const Type *EltTy = ATy->getElementType(); 108 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy); 109 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) 110 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, 111 StartingOffset + i * EltSize); 112 return; 113 } 114 // Interpret void as zero return values. 115 if (Ty->isVoidTy()) 116 return; 117 // Base case: we can get an EVT for this LLVM IR type. 118 ValueVTs.push_back(TLI.getValueType(Ty)); 119 if (Offsets) 120 Offsets->push_back(StartingOffset); 121} 122 123/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 124/// PHI nodes or outside of the basic block that defines it, or used by a 125/// switch or atomic instruction, which may expand to multiple basic blocks. 126static bool isUsedOutsideOfDefiningBlock(const Instruction *I) { 127 if (isa<PHINode>(I)) return true; 128 const BasicBlock *BB = I->getParent(); 129 for (Value::const_use_iterator UI = I->use_begin(), E = I->use_end(); 130 UI != E; ++UI) 131 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI)) 132 return true; 133 return false; 134} 135 136/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 137/// entry block, return true. This includes arguments used by switches, since 138/// the switch may expand into multiple basic blocks. 139static bool isOnlyUsedInEntryBlock(const Argument *A, bool EnableFastISel) { 140 // With FastISel active, we may be splitting blocks, so force creation 141 // of virtual registers for all non-dead arguments. 142 // Don't force virtual registers for byval arguments though, because 143 // fast-isel can't handle those in all cases. 144 if (EnableFastISel && !A->hasByValAttr()) 145 return A->use_empty(); 146 147 const BasicBlock *Entry = A->getParent()->begin(); 148 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 149 UI != E; ++UI) 150 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 151 return false; // Use not in entry block. 152 return true; 153} 154 155FunctionLoweringInfo::FunctionLoweringInfo(const TargetLowering &tli) 156 : TLI(tli) { 157} 158 159void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, 160 bool EnableFastISel) { 161 Fn = &fn; 162 MF = &mf; 163 RegInfo = &MF->getRegInfo(); 164 165 // Create a vreg for each argument register that is not dead and is used 166 // outside of the entry block for the function. 167 for (Function::const_arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end(); 168 AI != E; ++AI) 169 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel)) 170 InitializeRegForValue(AI); 171 172 // Initialize the mapping of values to registers. This is only set up for 173 // instruction values that are used outside of the block that defines 174 // them. 175 Function::const_iterator BB = Fn->begin(), EB = Fn->end(); 176 for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) 177 if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) 178 if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 179 const Type *Ty = AI->getAllocatedType(); 180 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 181 unsigned Align = 182 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 183 AI->getAlignment()); 184 185 TySize *= CUI->getZExtValue(); // Get total allocated size. 186 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 187 StaticAllocaMap[AI] = 188 MF->getFrameInfo()->CreateStackObject(TySize, Align, false); 189 } 190 191 for (; BB != EB; ++BB) 192 for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) 193 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 194 if (!isa<AllocaInst>(I) || 195 !StaticAllocaMap.count(cast<AllocaInst>(I))) 196 InitializeRegForValue(I); 197 198 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 199 // also creates the initial PHI MachineInstrs, though none of the input 200 // operands are populated. 201 for (BB = Fn->begin(); BB != EB; ++BB) { 202 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); 203 MBBMap[BB] = MBB; 204 MF->push_back(MBB); 205 206 // Transfer the address-taken flag. This is necessary because there could 207 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only 208 // the first one should be marked. 209 if (BB->hasAddressTaken()) 210 MBB->setHasAddressTaken(); 211 212 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 213 // appropriate. 214 const PHINode *PN; 215 DebugLoc DL; 216 for (BasicBlock::const_iterator 217 I = BB->begin(), E = BB->end(); I != E; ++I) { 218 219 PN = dyn_cast<PHINode>(I); 220 if (!PN || PN->use_empty()) continue; 221 222 unsigned PHIReg = ValueMap[PN]; 223 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 224 225 SmallVector<EVT, 4> ValueVTs; 226 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 227 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 228 EVT VT = ValueVTs[vti]; 229 unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT); 230 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 231 for (unsigned i = 0; i != NumRegisters; ++i) 232 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i); 233 PHIReg += NumRegisters; 234 } 235 } 236 } 237 238 // Mark landing pad blocks. 239 for (BB = Fn->begin(); BB != EB; ++BB) 240 if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator())) 241 MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 242} 243 244/// clear - Clear out all the function-specific state. This returns this 245/// FunctionLoweringInfo to an empty state, ready to be used for a 246/// different function. 247void FunctionLoweringInfo::clear() { 248 assert(CatchInfoFound.size() == CatchInfoLost.size() && 249 "Not all catch info was assigned to a landing pad!"); 250 251 MBBMap.clear(); 252 ValueMap.clear(); 253 StaticAllocaMap.clear(); 254#ifndef NDEBUG 255 CatchInfoLost.clear(); 256 CatchInfoFound.clear(); 257#endif 258 LiveOutRegInfo.clear(); 259} 260 261unsigned FunctionLoweringInfo::MakeReg(EVT VT) { 262 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 263} 264 265/// CreateRegForValue - Allocate the appropriate number of virtual registers of 266/// the correctly promoted or expanded types. Assign these registers 267/// consecutive vreg numbers and return the first assigned number. 268/// 269/// In the case that the given value has struct or array type, this function 270/// will assign registers for each member or element. 271/// 272unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 273 SmallVector<EVT, 4> ValueVTs; 274 ComputeValueVTs(TLI, V->getType(), ValueVTs); 275 276 unsigned FirstReg = 0; 277 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 278 EVT ValueVT = ValueVTs[Value]; 279 EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT); 280 281 unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT); 282 for (unsigned i = 0; i != NumRegs; ++i) { 283 unsigned R = MakeReg(RegisterVT); 284 if (!FirstReg) FirstReg = R; 285 } 286 } 287 return FirstReg; 288} 289 290/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. 291GlobalVariable *llvm::ExtractTypeInfo(Value *V) { 292 V = V->stripPointerCasts(); 293 GlobalVariable *GV = dyn_cast<GlobalVariable>(V); 294 295 if (GV && GV->getName() == ".llvm.eh.catch.all.value") { 296 assert(GV->hasInitializer() && 297 "The EH catch-all value must have an initializer"); 298 Value *Init = GV->getInitializer(); 299 GV = dyn_cast<GlobalVariable>(Init); 300 if (!GV) V = cast<ConstantPointerNull>(Init); 301 } 302 303 assert((GV || isa<ConstantPointerNull>(V)) && 304 "TypeInfo must be a global variable or NULL"); 305 return GV; 306} 307 308/// AddCatchInfo - Extract the personality and type infos from an eh.selector 309/// call, and add them to the specified machine basic block. 310void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI, 311 MachineBasicBlock *MBB) { 312 // Inform the MachineModuleInfo of the personality for this landing pad. 313 const ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2)); 314 assert(CE->getOpcode() == Instruction::BitCast && 315 isa<Function>(CE->getOperand(0)) && 316 "Personality should be a function"); 317 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0))); 318 319 // Gather all the type infos for this landing pad and pass them along to 320 // MachineModuleInfo. 321 std::vector<const GlobalVariable *> TyInfo; 322 unsigned N = I.getNumOperands(); 323 324 for (unsigned i = N - 1; i > 2; --i) { 325 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) { 326 unsigned FilterLength = CI->getZExtValue(); 327 unsigned FirstCatch = i + FilterLength + !FilterLength; 328 assert (FirstCatch <= N && "Invalid filter length"); 329 330 if (FirstCatch < N) { 331 TyInfo.reserve(N - FirstCatch); 332 for (unsigned j = FirstCatch; j < N; ++j) 333 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 334 MMI->addCatchTypeInfo(MBB, TyInfo); 335 TyInfo.clear(); 336 } 337 338 if (!FilterLength) { 339 // Cleanup. 340 MMI->addCleanup(MBB); 341 } else { 342 // Filter. 343 TyInfo.reserve(FilterLength - 1); 344 for (unsigned j = i + 1; j < FirstCatch; ++j) 345 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 346 MMI->addFilterTypeInfo(MBB, TyInfo); 347 TyInfo.clear(); 348 } 349 350 N = i; 351 } 352 } 353 354 if (N > 3) { 355 TyInfo.reserve(N - 3); 356 for (unsigned j = 3; j < N; ++j) 357 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); 358 MMI->addCatchTypeInfo(MBB, TyInfo); 359 } 360} 361 362void llvm::CopyCatchInfo(const BasicBlock *SrcBB, const BasicBlock *DestBB, 363 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) { 364 for (BasicBlock::const_iterator I = SrcBB->begin(), E = --SrcBB->end(); 365 I != E; ++I) 366 if (const EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) { 367 // Apply the catch info to DestBB. 368 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]); 369#ifndef NDEBUG 370 if (!FLI.MBBMap[SrcBB]->isLandingPad()) 371 FLI.CatchInfoFound.insert(EHSel); 372#endif 373 } 374} 375 376/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being 377/// processed uses a memory 'm' constraint. 378bool 379llvm::hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos, 380 const TargetLowering &TLI) { 381 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) { 382 InlineAsm::ConstraintInfo &CI = CInfos[i]; 383 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) { 384 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]); 385 if (CType == TargetLowering::C_Memory) 386 return true; 387 } 388 389 // Indirect operand accesses access memory. 390 if (CI.isIndirect) 391 return true; 392 } 393 394 return false; 395} 396 397/// getFCmpCondCode - Return the ISD condition code corresponding to 398/// the given LLVM IR floating-point condition code. This includes 399/// consideration of global floating-point math flags. 400/// 401ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 402 ISD::CondCode FPC, FOC; 403 switch (Pred) { 404 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break; 405 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; 406 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break; 407 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; 408 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break; 409 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break; 410 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; 411 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break; 412 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break; 413 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; 414 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; 415 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; 416 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; 417 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; 418 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; 419 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; 420 default: 421 llvm_unreachable("Invalid FCmp predicate opcode!"); 422 FOC = FPC = ISD::SETFALSE; 423 break; 424 } 425 if (FiniteOnlyFPMath()) 426 return FOC; 427 else 428 return FPC; 429} 430 431/// getICmpCondCode - Return the ISD condition code corresponding to 432/// the given LLVM IR integer condition code. 433/// 434ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { 435 switch (Pred) { 436 case ICmpInst::ICMP_EQ: return ISD::SETEQ; 437 case ICmpInst::ICMP_NE: return ISD::SETNE; 438 case ICmpInst::ICMP_SLE: return ISD::SETLE; 439 case ICmpInst::ICMP_ULE: return ISD::SETULE; 440 case ICmpInst::ICMP_SGE: return ISD::SETGE; 441 case ICmpInst::ICMP_UGE: return ISD::SETUGE; 442 case ICmpInst::ICMP_SLT: return ISD::SETLT; 443 case ICmpInst::ICMP_ULT: return ISD::SETULT; 444 case ICmpInst::ICMP_SGT: return ISD::SETGT; 445 case ICmpInst::ICMP_UGT: return ISD::SETUGT; 446 default: 447 llvm_unreachable("Invalid ICmp predicate opcode!"); 448 return ISD::SETNE; 449 } 450} 451