1//===- Memory.cpp - Memory Handling Support ---------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines some helpful functions for allocating memory and dealing
11// with memory mapped files
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/Support/Memory.h"
16#include "llvm/Support/Valgrind.h"
17#include "llvm/Config/config.h"
18
19#if defined(__mips__)
20#include <sys/cachectl.h>
21#endif
22
23namespace llvm {
24using namespace sys;
25}
26
27// Include the platform-specific parts of this class.
28#ifdef LLVM_ON_UNIX
29#include "Unix/Memory.inc"
30#endif
31#ifdef LLVM_ON_WIN32
32#include "Windows/Memory.inc"
33#endif
34
35extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
36
37/// InvalidateInstructionCache - Before the JIT can run a block of code
38/// that has been emitted it must invalidate the instruction cache on some
39/// platforms.
40void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
41                                                   size_t Len) {
42
43// icache invalidation for PPC and ARM.
44#if defined(__APPLE__)
45
46#  if (defined(__POWERPC__) || defined (__ppc__) || \
47     defined(_POWER) || defined(_ARCH_PPC)) || defined(__arm__)
48  sys_icache_invalidate(const_cast<void *>(Addr), Len);
49#  endif
50
51#else
52
53#  if (defined(__POWERPC__) || defined (__ppc__) || \
54       defined(_POWER) || defined(_ARCH_PPC)) && defined(__GNUC__)
55  const size_t LineSize = 32;
56
57  const intptr_t Mask = ~(LineSize - 1);
58  const intptr_t StartLine = ((intptr_t) Addr) & Mask;
59  const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask;
60
61  for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
62    asm volatile("dcbf 0, %0" : : "r"(Line));
63  asm volatile("sync");
64
65  for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
66    asm volatile("icbi 0, %0" : : "r"(Line));
67  asm volatile("isync");
68#  elif defined(__arm__) && defined(__GNUC__)
69  // FIXME: Can we safely always call this for __GNUC__ everywhere?
70  const char *Start = static_cast<const char *>(Addr);
71  const char *End = Start + Len;
72  __clear_cache(const_cast<char *>(Start), const_cast<char *>(End));
73#  elif defined(__mips__) && defined(ANDROID)
74  // NOTE: The declaration of "cacheflush" in bionic:
75  // extern int cacheflush(long start, long end, long flags);
76  cacheflush((long)Addr, (long)(Addr+Len), BCACHE);
77#  elif defined(__mips__)
78  const char *Start = static_cast<const char *>(Addr);
79  cacheflush(const_cast<char *>(Start), Len, BCACHE);
80#  endif
81
82#endif  // end apple
83
84  ValgrindDiscardTranslations(Addr, Len);
85}
86