ARMExpandPseudoInsts.cpp revision df1c637ac4b6f6587c037be55cafed665c732d8f
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 3b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// The LLVM Compiler Infrastructure 4b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 5b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// This file is distributed under the University of Illinois Open Source 6b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// License. See LICENSE.TXT for details. 7b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 8b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 9b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 10656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// This file contains a pass that expands pseudo instructions into target 11b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// instructions to allow proper scheduling, if-conversion, and other late 12b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// optimizations. This pass should be run after register allocation but before 13656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// the post-regalloc scheduling pass. 14b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 15b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 16b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 17b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#define DEBUG_TYPE "arm-pseudo" 18b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARM.h" 19b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARMBaseInstrInfo.h" 20e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMBaseRegisterInfo.h" 21e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMMachineFunctionInfo.h" 22ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 23e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/CodeGen/MachineFrameInfo.h" 24b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineFunctionPass.h" 25b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 2616c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 274dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "llvm/Target/TargetRegisterInfo.h" 28e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen#include "llvm/Support/CommandLine.h" 29e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 30b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengusing namespace llvm; 31b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 32a67f14bf53737f9bb0afefa28e08c4aac6ec4804Benjamin Kramerstatic cl::opt<bool> 33e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund OlesenVerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 34e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen cl::desc("Verify machine code after expanding ARM pseudos")); 35e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen 36b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengnamespace { 37b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng class ARMExpandPseudo : public MachineFunctionPass { 38b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng public: 39b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng static char ID; 4090c579de5a383cee278acc3f7e7b9d0a656e6a35Owen Anderson ARMExpandPseudo() : MachineFunctionPass(ID) {} 41b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 42e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *TII; 43d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng const TargetRegisterInfo *TRI; 44893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng const ARMSubtarget *STI; 459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ARMFunctionInfo *AFI; 46b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 47b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual bool runOnMachineFunction(MachineFunction &Fn); 48b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 49b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual const char *getPassName() const { 50b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return "ARM pseudo instruction expansion pass"; 51b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 52b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 53b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng private: 54431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng void TransferImpOps(MachineInstr &OldMI, 55431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool ExpandMI(MachineBasicBlock &MBB, 579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI); 58b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool ExpandMBB(MachineBasicBlock &MBB); 598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVLD(MachineBasicBlock::iterator &MBBI); 608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVST(MachineBasicBlock::iterator &MBBI); 618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 62bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 6360d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach unsigned Opc, bool IsExt); 649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng void ExpandMOV32BitImm(MachineBasicBlock &MBB, 659fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI); 66b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng }; 67b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng char ARMExpandPseudo::ID = 0; 68b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 69b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 70431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// TransferImpOps - Transfer implicit operands on the pseudo instruction to 71431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// the instructions created from the expansion. 72431300797b84600fc9b4eb8ca283277d3e0674ebEvan Chengvoid ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 73431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, 74431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &DefMI) { 75e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = OldMI.getDesc(); 76431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 77431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng i != e; ++i) { 78431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const MachineOperand &MO = OldMI.getOperand(i); 79431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng assert(MO.isReg() && MO.getReg()); 80431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isUse()) 8163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson UseMI.addOperand(MO); 82431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng else 8363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson DefMI.addOperand(MO); 84431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } 85431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng} 86431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonnamespace { 888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Constants for register spacing in NEON load/store instructions. 898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // For quad-register load-lane and store-lane pseudo instructors, the 908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // spacing is initially assumed to be EvenDblSpc, and that is changed to 918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // OddDblSpc depending on the lane number operand. 928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson enum NEONRegSpacing { 938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson SingleSpc, 948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson EvenDblSpc, 958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson OddDblSpc 968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Entries for NEON load/store information table. The table is sorted by 998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // PseudoOpc for fast binary-search lookups. 1008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson struct NEONLdStTableEntry { 101b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper uint16_t PseudoOpc; 102b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper uint16_t RealOpc; 1038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool IsLoad; 104f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach bool isUpdating; 105f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach bool hasWritebackOperand; 1068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpacing; 1078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char NumRegs; // D registers loaded or stored 1088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char RegElts; // elements per D register; used for lane ops 109280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // FIXME: Temporary flag to denote whether the real instruction takes 110280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // a single register (like the encoding) or all of the registers in 111280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // the list (like the asm syntax and the isel DAG). When all definitions 112280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // are converted to take only the single encoded register, this will 113280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // go away. 114280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach bool copyAllListRegs; 1158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Comparison methods for binary search of the table. 1178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool operator<(const NEONLdStTableEntry &TE) const { 1188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 1218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return TE.PseudoOpc < PseudoOpc; 1228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 123100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 124100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth const NEONLdStTableEntry &TE) { 1258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 1298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry NEONLdStTable[] = { 131f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 132f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 133f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 134f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 135f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 136f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 137f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 138f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 139f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 140f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 141f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 142f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 143f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 144f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 145f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 146f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 147f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 148f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 149f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 150f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 151f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 152f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 153a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 154a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 155f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 156a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 157a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 158f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 159a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 160a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 161f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 162f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 163f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 164f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 165f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 166f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 167f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 168f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 169f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 170f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 171f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 172f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 173f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 174f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 175f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 176f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 177f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 178f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 179f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 180f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 181f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 182f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 183f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 184f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 185f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 186f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 187f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 188f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 189f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 190f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 191f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 192f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 193f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 194f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 195f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 196f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 197f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 198f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 199f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 200f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 201f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 202f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 203f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 204f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 205f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 206f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 207f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 208f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 209f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 210f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 211f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 212f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 213f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 214f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 215f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 216f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 217f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 218f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 219f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 220f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 221f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 222f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 223f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 224f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 225f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 226f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 227f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 228f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 229f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 230f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 231f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 232f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 233f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 234f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 235f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 236f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 237f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 238f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 2394c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 2404c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 2414c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 242d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 243d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 244d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 245f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 246f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 247f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 248f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 249f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 250f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 251f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 252f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 253f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 254f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 255f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 256f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 257e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 258bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 259bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 260e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 261bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 262bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 263e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 264bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 265bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 266f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 267f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 268f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 269f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 270f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 271f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 272f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 273f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 274f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 275f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 276f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 277f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 278f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 279f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 280f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 281f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 282f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 283f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 284f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 285f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 286f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 287f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 288f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 289f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 290f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 291f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 292f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 293f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 294f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 295f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 296f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 297f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 298f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 299f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 300f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 301f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 302f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 303f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 304f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 305f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 306f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 307f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 308f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 309f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 310f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 311f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 312f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 313f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 314f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 315f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 316f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 317f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 318f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 319f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 320f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 321f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 3228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson}; 3238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 3258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// load or store pseudo instruction. 3268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 327b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper const unsigned NumEntries = array_lengthof(NEONLdStTable); 3288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#ifndef NDEBUG 3308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Make sure the table is sorted. 3318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson static bool TableChecked = false; 3328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableChecked) { 3338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson for (unsigned i = 0; i != NumEntries-1; ++i) 3348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(NEONLdStTable[i] < NEONLdStTable[i+1] && 3358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson "NEONLdStTable is not sorted!"); 3368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TableChecked = true; 3378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 3388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#endif 3398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *I = 3418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); 3428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) 3438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return I; 3448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return NULL; 3458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 3488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// corresponding to the specified register spacing. Not all of the results 3498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// are necessarily valid, e.g., a Q register only has 2 D subregisters. 3508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 3518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const TargetRegisterInfo *TRI, unsigned &D0, 3528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned &D1, unsigned &D2, unsigned &D3) { 3538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == SingleSpc) { 3548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_1); 3568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_2); 3578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_3); 3588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else if (RegSpc == EvenDblSpc) { 3598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_2); 3618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_4); 3628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_6); 3638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else { 3648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc == OddDblSpc && "unknown register spacing"); 3658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_1); 3668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_3); 3678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_5); 3688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_7); 369bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson } 3708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 37282a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 37382a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// operands to real VLD instructions with D register operands. 3748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 375ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineInstr &MI = *MBBI; 376ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 377ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 3788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 3798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 3808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 3818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 3828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 3848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 385ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned OpIdx = 0; 386ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 387ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 388ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 389ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned D0, D1, D2, D3; 3908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 391280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 392280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 1 && TableEntry->copyAllListRegs) 393280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 394280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 2 && TableEntry->copyAllListRegs) 395f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 396280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 3 && TableEntry->copyAllListRegs) 397f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 398ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 399f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 40063569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 402ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson // Copy the addrmode6 operands. 40363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 406f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 40763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 408ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 40919d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // For an instruction writing double-spaced subregs, the pseudo instruction 410823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // has an extra operand that is a use of the super-register. Record the 411823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // operand index and skip over it. 412823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcOpIdx = 0; 413823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 414823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson SrcOpIdx = OpIdx++; 415823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 416823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 417823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 418823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 419823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 420823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the super-register source operand used for double-spaced subregs over 42119d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // to the new instruction as an implicit operand. 422823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (SrcOpIdx != 0) { 423823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MachineOperand MO = MI.getOperand(SrcOpIdx); 42419d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MO.setImplicit(true); 42519d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MIB.addOperand(MO); 42619d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson } 427f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson // Add an implicit def for the super-register. 428f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 42919d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson TransferImpOps(MI, MIB, MIB); 430b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 431b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 432d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 433b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 434ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MI.eraseFromParent(); 435ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson} 436ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 43701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 43801ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// operands to real VST instructions with D register operands. 4398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 440709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineInstr &MI = *MBBI; 441709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 442709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 4458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 4468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 4498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 450709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned OpIdx = 0; 451f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 45263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 45363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 454709d59255a3100c7d440c93069efa1f726677a27Bob Wilson // Copy the addrmode6 operands. 45563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 45663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 45763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 458f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 45963569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 460709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 461709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 462d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 463823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 464709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned D0, D1, D2, D3; 4658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 466d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 4674334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 1 && TableEntry->copyAllListRegs) 468d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 4694334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 2 && TableEntry->copyAllListRegs) 470d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 4714334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 3 && TableEntry->copyAllListRegs) 472d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 473823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 474823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 475823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 476823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 477823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 478d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 479d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 480bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 481b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 482b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 483d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 484b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 485709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MI.eraseFromParent(); 486709d59255a3100c7d440c93069efa1f726677a27Bob Wilson} 487709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 4898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// register operands to real instructions with D register operands. 4908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 4918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstr &MI = *MBBI; 4928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 4938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && "NEONLdStTable lookup failed"); 4968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 4978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RegElts = TableEntry->RegElts; 4998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 5018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 5028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned OpIdx = 0; 5038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // The lane operand is always the 3rd from last operand, before the 2 5048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // predicate operands. 5058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 5068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Adjust the lane and spacing as needed for Q registers. 5088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 5098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == EvenDblSpc && Lane >= RegElts) { 5108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson RegSpc = OddDblSpc; 5118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson Lane -= RegElts; 5128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 5148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 515584520e8e2c1f8cc04bc8dd4dc4ea6c390627317Ted Kremenek unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 516fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned DstReg = 0; 517fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson bool DstIsDead = false; 5188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) { 5198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstIsDead = MI.getOperand(OpIdx).isDead(); 5208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstReg = MI.getOperand(OpIdx++).getReg(); 5218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 522b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 523b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 524b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 5258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 5278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 5298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 531f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 5328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the addrmode6 operands. 5358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the am6offset operand. 538f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 5398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Grab the super-register source. 5428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineOperand MO = MI.getOperand(OpIdx++); 5438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableEntry->IsLoad) 5448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 5458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the subregs as sources of the new instruction. 5478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 5488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson getKillRegState(MO.isKill())); 549b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, SrcFlags); 550b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 551b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, SrcFlags); 5528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, SrcFlags); 5548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, SrcFlags); 5568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the lane number operand. 5588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addImm(Lane); 559823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson OpIdx += 1; 560823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 561823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 562823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 563823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the super-register source to be an implicit source. 5668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MO.setImplicit(true); 5678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MO); 5688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) 5698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add an implicit def for the super-register. 5708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 5718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TransferImpOps(MI, MIB, MIB); 5722027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen // Transfer memoperands. 5732027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 5748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MI.eraseFromParent(); 5758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 5768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 577bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 578bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// register operands to real instructions with D register operands. 579bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilsonvoid ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 58060d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach unsigned Opc, bool IsExt) { 581bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstr &MI = *MBBI; 582bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 583bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 584bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 585bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned OpIdx = 0; 586bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 587bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Transfer the destination register operand. 588bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 589bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (IsExt) 590bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 591bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 592bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 593bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 594bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned D0, D1, D2, D3; 595bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 59660d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach MIB.addReg(D0); 597bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 598bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Copy the other source register operand. 599823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 600823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 601823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 602823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 603823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 604bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 605d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner if (SrcIsKill) // Add an implicit kill for the super-reg. 606d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 607bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 608bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MI.eraseFromParent(); 609bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson} 610bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 6119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengvoid ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 6129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI) { 6139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 6149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 6159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PredReg = 0; 616c89c744b69cecac576317a98322fd295e36e9886Craig Topper ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); 6179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 6189fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 6199fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 6209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 6219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder LO16, HI16; 6229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!STI->hasV6T2Ops() && 6249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 6259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Expand into a movi + orr. 6269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 6279fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 6289fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 6299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 6309fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6319fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 6329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned ImmVal = (unsigned)MO.getImm(); 6339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 6349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 6359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(SOImmValV1); 6369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(SOImmValV2); 637d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 638d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 6399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg).addReg(0); 6409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg).addReg(0); 6419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 6429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 6439fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return; 6449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 645b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 6469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LO16Opc = 0; 6479fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned HI16Opc = 0; 6489fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 6499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::t2MOVi16; 6509fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::t2MOVTi16; 6519fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else { 6529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::MOVi16; 6539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::MOVTi16; 6549fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 655b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 6569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 6579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 6589fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 6599fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 6609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MO.isImm()) { 6629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Imm = MO.getImm(); 6639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Lo16 = Imm & 0xffff; 6649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Hi16 = (Imm >> 16) & 0xffff; 6659fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(Lo16); 6669fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(Hi16); 6679fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else { 6689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO.getGlobal(); 6699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO.getTargetFlags(); 6709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 6719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 6729fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 673709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 674d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 675d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 6769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg); 6779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg); 6789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6799fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 6809fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 6819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 6829fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6839fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 6849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI) { 6859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 6869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 6879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng switch (Opcode) { 6889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng default: 6899fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 690f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVScc: 691f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVDcc: { 692f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; 693f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 694f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.getOperand(1).getReg()) 695f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addReg(MI.getOperand(2).getReg(), 696f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach getKillRegState(MI.getOperand(2).isKill())) 697f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 698f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addReg(MI.getOperand(4).getReg()); 699f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach 700f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.eraseFromParent(); 701f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach return true; 702f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach } 703efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach case ARM::t2MOVCCr: 704d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach case ARM::MOVCCr: { 705efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 706efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 707d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.getOperand(1).getReg()) 708d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(2).getReg(), 709d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach getKillRegState(MI.getOperand(2).isKill())) 710d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 711d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(4).getReg()) 712d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 713d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 714d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 715d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 716d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 717152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM::MOVCCsi: { 718152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 719152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson (MI.getOperand(1).getReg())) 720152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addReg(MI.getOperand(2).getReg(), 721152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson getKillRegState(MI.getOperand(2).isKill())) 722152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addImm(MI.getOperand(3).getImm()) 723152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addImm(MI.getOperand(4).getImm()) // 'pred' 724152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addReg(MI.getOperand(5).getReg()) 725152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addReg(0); // 's' bit 726152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 727152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson MI.eraseFromParent(); 728152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return true; 729152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson } 730152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 73192a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson case ARM::MOVCCsr: { 732152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 733d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach (MI.getOperand(1).getReg())) 734d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(2).getReg(), 735d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach getKillRegState(MI.getOperand(2).isKill())) 736d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(3).getReg(), 737d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach getKillRegState(MI.getOperand(3).isKill())) 738d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(4).getImm()) 739d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(5).getImm()) // 'pred' 740d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(6).getReg()) 741d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 7423906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach 7433906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 7443906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 7453906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 7463906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi16: { 7473906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16), 7483906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 7493906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 7503906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 7513906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(MI.getOperand(4).getReg()); 7523906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach 7533906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 7543906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 7553906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 756efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach case ARM::t2MOVCCi: 7573906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi: { 758efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 759efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 7603906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 7613906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 7623906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 7633906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(MI.getOperand(4).getReg()) 7643906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(0); // 's' bit 765e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach 766e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.eraseFromParent(); 767e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach return true; 768e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach } 769e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach case ARM::MVNCCi: { 770e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), 771e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.getOperand(1).getReg()) 772e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(2).getImm()) 773e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 774e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addReg(MI.getOperand(4).getReg()) 775e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addReg(0); // 's' bit 776d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 777d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 778d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 779d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 780f4aea8f34946d4d2b101b8e3c6db95c18be80173Bob Wilson case ARM::Int_eh_sjlj_dispatchsetup: 781f4aea8f34946d4d2b101b8e3c6db95c18be80173Bob Wilson case ARM::Int_eh_sjlj_dispatchsetup_nofp: 782f4aea8f34946d4d2b101b8e3c6db95c18be80173Bob Wilson case ARM::tInt_eh_sjlj_dispatchsetup: { 783e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MachineFunction &MF = *MI.getParent()->getParent(); 784e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *AII = 785e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach static_cast<const ARMBaseInstrInfo*>(TII); 786e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 787e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // For functions using a base pointer, we rematerialize it (via the frame 788e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 789e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // for us. Otherwise, expand to nothing. 790e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (RI.hasBasePointer(MF)) { 791e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int32_t NumBytes = AFI->getFramePtrSpillOffset(); 792e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned FramePtr = RI.getFrameRegister(MF); 79316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 7947920d96964d707a3af85332c98d95b2fabc3d5c9Benjamin Kramer "base pointer without frame pointer?"); 795e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 796e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (AFI->isThumb2Function()) { 797c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 798c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 799e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else if (AFI->isThumbFunction()) { 800c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 801c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, *TII, RI); 802e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else { 803c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 804c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, ARMCC::AL, 0, 805c89c744b69cecac576317a98322fd295e36e9886Craig Topper *TII); 806e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 8078b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // If there's dynamic realignment, adjust for it. 808b8e67fc92b0a508e3782b782baa98a6d56d5d7eaJim Grosbach if (RI.needsStackRealignment(MF)) { 8098b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 8108b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 8118b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 8128b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // Emit bic r6, r6, MaxAlign 8138b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned bicOpc = AFI->isThumbFunction() ? 8148b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach ARM::t2BICri : ARM::BICri; 8158b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 8168b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach TII->get(bicOpc), ARM::R6) 8178b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addReg(ARM::R6, RegState::Kill) 8188b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addImm(MaxAlign-1))); 8198b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach } 820e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 821e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 822e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MI.eraseFromParent(); 8239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 824e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 825e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 8267032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsrl_flag: 8277032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsra_flag: { 8287032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // These are just fancy MOVs insructions. 829152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 830dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands MI.getOperand(0).getReg()) 8319fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 832aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? 833aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach ARM_AM::lsr : ARM_AM::asr), 834aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach 1))) 8359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(ARM::CPSR, RegState::Define); 8367032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 8379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 8387032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 8397032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::RRX: { 8407032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // This encodes as "MOVs Rd, Rm, rrx 8417032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MachineInstrBuilder MIB = 8428e0c7697fd9b9354856074efc06eea9f6d80015cJim Grosbach AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi), 8437032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.getOperand(0).getReg()) 8449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 8459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 8467032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addReg(0); 8477032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach TransferImpOps(MI, MIB, MIB); 8487032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 8499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 8507032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 851ff97eb0cf4394090570feaa327d1237ba4b935e2Jim Grosbach case ARM::tTPsoft: 852a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim case ARM::TPsoft: { 853971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson MachineInstrBuilder MIB = 854a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim BuildMI(MBB, MBBI, MI.getDebugLoc(), 855ff97eb0cf4394090570feaa327d1237ba4b935e2Jim Grosbach TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL)) 856a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim .addExternalSymbol("__aeabi_read_tp", 0); 857a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim 858d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 859a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim TransferImpOps(MI, MIB, MIB); 860a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim MI.eraseFromParent(); 8619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 8622fe813af23e682b418ecd477144fe070be325419Bill Wendling } 863bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::tLDRpci_pic: 864b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng case ARM::t2LDRpci_pic: { 865b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 866971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson ? ARM::tLDRpci : ARM::t2LDRpci; 867b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 868431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 869431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB1 = 870971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 871971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson TII->get(NewLdOpc), DstReg) 872971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson .addOperand(MI.getOperand(1))); 873d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 874431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 875431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TII->get(ARM::tPICADD)) 87601b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 877431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg) 878431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addOperand(MI.getOperand(2)); 879431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, MIB1, MIB2); 880b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 8819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 882b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 883431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 88453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_dyn: 88553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel: 88653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel_ldr: 88753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOV_ga_dyn: 88853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOV_ga_pcrel: { 88953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 8909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LabelId = AFI->createPICLabelUId(); 891b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 892431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 8939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI.getOperand(1); 8949fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO1.getGlobal(); 8959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO1.getTargetFlags(); 896aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn); 89753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn); 89853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 899aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 90053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned LO16TF = isPIC 90153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY; 90253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned HI16TF = isPIC 90353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY; 9049fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PICAddOpc = isARM 90553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 9069fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng : ARM::tPICADD; 9079fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 9089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(LO16Opc), DstReg) 90953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 9109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 91153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 91253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TII->get(HI16Opc), DstReg) 9139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg) 91453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 9159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 91653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (!isPIC) { 91753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TransferImpOps(MI, MIB1, MIB2); 91853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MI.eraseFromParent(); 91953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng return true; 92053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng } 92153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng 92253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 9239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(PICAddOpc)) 92401b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 9259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg).addImm(LabelId); 9269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (isARM) { 92753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng AddDefaultPred(MIB3); 92853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_pcrel_ldr) 9296e6269a976baee45717265dbd12996367df6a201Jakob Stoklund Olesen MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 9305de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng } 93153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TransferImpOps(MI, MIB1, MIB3); 932b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 9339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 934d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng } 935d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng 9369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVi32imm: 9379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVCCi32imm: 9389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVi32imm: 9399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVCCi32imm: 9409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ExpandMOV32BitImm(MBB, MBBI); 9419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 943848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VLDMQIA: { 944848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VLDMDIA; 9459d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 94673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 9479d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 94873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9499d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register destination. 9509d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 9519d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 95273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 95373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the source register. 9549d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 95573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9569d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 9579d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 9589d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 95973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9609d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the destination operands (D subregs). 9619d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 9629d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 9639d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 9649d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 96573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9669d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add an implicit def for the super-register. 9679d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 9689d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 9692027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 9709d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 9719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9729d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 9739d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 974848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VSTMQIA: { 975848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VSTMDIA; 9769d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 97773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 9789d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 97973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9809d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register source. 9819d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 9829d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 98373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 98473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the destination register. 9859d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 98673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9879d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 9889d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 9899d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 99073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9919d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the source operands (D subregs). 9929d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 9939d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 9949d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0).addReg(D1); 99573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 996d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner if (SrcIsKill) // Add an implicit kill for the Q register. 997d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 99873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9999d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 10002027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 10019d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 10029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 10039d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 100465dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach case ARM::VDUPfqf: 100565dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach case ARM::VDUPfdf:{ 10068b8515c225c799e9df69bde8ffffa3c72cec9445Jim Grosbach unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : 10078b8515c225c799e9df69bde8ffffa3c72cec9445Jim Grosbach ARM::VDUPLN32d; 100865dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MachineInstrBuilder MIB = 100965dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 101065dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned OpIdx = 0; 101165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned SrcReg = MI.getOperand(1).getReg(); 1012df1c637ac4b6f6587c037be55cafed665c732d8fEric Christopher unsigned Lane = TRI->getEncodingValue(SrcReg) & 1; 101365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned DReg = TRI->getMatchingSuperReg(SrcReg, 1014b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3Jim Grosbach Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, 1015b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3Jim Grosbach &ARM::DPR_VFP2RegClass); 101665dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // The lane is [0,1] for the containing DReg superregister. 101765dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Copy the dst/src register operands. 101865dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 101965dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addReg(DReg); 102065dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach ++OpIdx; 102165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Add the lane select operand. 102265dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addImm(Lane); 102365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Add the predicate operands. 102465dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 102565dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 102665dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach 102765dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach TransferImpOps(MI, MIB, MIB); 102865dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MI.eraseFromParent(); 10299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 103065dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach } 10319d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 1032ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo: 1033ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo: 1034ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo: 1035a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 1036a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 1037a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 1038a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 1039a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 1040a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 1041f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo: 1042f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo: 1043f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo: 1044ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo: 1045f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo_UPD: 1046f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo_UPD: 1047f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo_UPD: 1048f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8Pseudo_UPD: 1049f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16Pseudo_UPD: 1050f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32Pseudo_UPD: 10517de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q8oddPseudo: 10527de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q16oddPseudo: 10537de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q32oddPseudo: 1054f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8oddPseudo_UPD: 1055f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16oddPseudo_UPD: 1056f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32oddPseudo_UPD: 1057f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo: 1058f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo: 1059f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo: 1060ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo: 1061f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo_UPD: 1062f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo_UPD: 1063f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo_UPD: 1064f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8Pseudo_UPD: 1065f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16Pseudo_UPD: 1066f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32Pseudo_UPD: 10677de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q8oddPseudo: 10687de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q16oddPseudo: 10697de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q32oddPseudo: 1070f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8oddPseudo_UPD: 1071f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16oddPseudo_UPD: 1072f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32oddPseudo_UPD: 107386c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo: 107486c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo: 107586c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo: 107686c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo_UPD: 107786c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo_UPD: 107886c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo_UPD: 10796c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo: 10806c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo: 10816c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo: 10826c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo_UPD: 10836c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo_UPD: 10846c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo_UPD: 10858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVLD(MBBI); 10869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1087ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 1088e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo: 1089e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo: 1090e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo: 1091bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q8PseudoWB_fixed: 1092bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q16PseudoWB_fixed: 1093bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q32PseudoWB_fixed: 1094bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q8PseudoWB_register: 1095bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q16PseudoWB_register: 1096bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q32PseudoWB_register: 109701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo: 109801ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo: 109901ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo: 110001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo: 110101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo_UPD: 110201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo_UPD: 110301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo_UPD: 1104d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach case ARM::VST1d64TPseudoWB_fixed: 1105d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach case ARM::VST1d64TPseudoWB_register: 110601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8Pseudo_UPD: 110701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16Pseudo_UPD: 110801ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32Pseudo_UPD: 11097de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q8oddPseudo: 11107de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q16oddPseudo: 11117de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q32oddPseudo: 111201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8oddPseudo_UPD: 111301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16oddPseudo_UPD: 111401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32oddPseudo_UPD: 1115709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo: 1116709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo: 1117709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo: 111870e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo: 1119709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo_UPD: 1120709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo_UPD: 1121709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo_UPD: 11224c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach case ARM::VST1d64QPseudoWB_fixed: 11234c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach case ARM::VST1d64QPseudoWB_register: 1124709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8Pseudo_UPD: 1125709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16Pseudo_UPD: 1126709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32Pseudo_UPD: 11277de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q8oddPseudo: 11287de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q16oddPseudo: 11297de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q32oddPseudo: 1130709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8oddPseudo_UPD: 1131709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16oddPseudo_UPD: 1132709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32oddPseudo_UPD: 11338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVST(MBBI); 11349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 11358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1136b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo: 1137b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo: 1138b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo: 1139b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo_UPD: 1140b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo_UPD: 1141b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo_UPD: 11428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo: 11438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo: 11448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo: 11458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo: 11468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo: 11478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo_UPD: 11488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo_UPD: 11498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo_UPD: 11508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo_UPD: 11518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo_UPD: 11528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo: 11538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo: 11548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo: 11558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo: 11568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo: 11578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo_UPD: 11588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo_UPD: 11598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo_UPD: 11608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo_UPD: 11618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo_UPD: 11628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo: 11638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo: 11648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo: 11658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo: 11668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo: 11678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo_UPD: 11688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo_UPD: 11698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo_UPD: 11708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo_UPD: 11718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo_UPD: 1172d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo: 1173d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo: 1174d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo: 1175d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo_UPD: 1176d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo_UPD: 1177d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo_UPD: 11788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo: 11798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo: 11808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo: 11818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo: 11828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo: 11838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo_UPD: 11848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo_UPD: 11858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo_UPD: 11868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo_UPD: 11878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo_UPD: 11888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo: 11898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo: 11908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo: 11918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo: 11928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo: 11938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo_UPD: 11948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo_UPD: 11958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo_UPD: 11968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo_UPD: 11978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo_UPD: 11988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo: 11998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo: 12008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo: 12018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo: 12028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo: 12038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo_UPD: 12048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo_UPD: 12058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo_UPD: 12068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo_UPD: 12078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo_UPD: 12088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandLaneOp(MBBI); 12099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 12109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 121160d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 121260d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 121360d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 121460d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 12159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 1217709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 12189fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 12199fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool Modified = false; 12209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 12229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng while (MBBI != E) { 12239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator NMBBI = llvm::next(MBBI); 12249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Modified |= ExpandMI(MBB, MBBI); 1225b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MBBI = NMBBI; 1226b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 1227b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1228b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1229b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1230b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1231b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 123253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng const TargetMachine &TM = MF.getTarget(); 123353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo()); 123453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TRI = TM.getRegisterInfo(); 123553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng STI = &TM.getSubtarget<ARMSubtarget>(); 12369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng AFI = MF.getInfo<ARMFunctionInfo>(); 1237b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1238b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 1239b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1240b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng ++MFI) 1241b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng Modified |= ExpandMBB(*MFI); 1242e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen if (VerifyARMPseudo) 1243e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen MF.verify(this, "After expanding ARM pseudo instructions."); 1244b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1245b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1246b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1247b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1248b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// expansion pass. 1249b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan ChengFunctionPass *llvm::createARMExpandPseudoPass() { 1250b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return new ARMExpandPseudo(); 1251b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1252