ARMExpandPseudoInsts.cpp revision e8d02539d7981c07d301d91a6a5b6ad34099b510 
1//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that expands pseudo instructions into target
11// instructions to allow proper scheduling, if-conversion, and other late
12// optimizations. This pass should be run after register allocation but before
13// the post-regalloc scheduling pass.
14//
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "arm-pseudo"
18#include "ARM.h"
19#include "ARMAddressingModes.h"
20#include "ARMBaseInstrInfo.h"
21#include "ARMBaseRegisterInfo.h"
22#include "ARMMachineFunctionInfo.h"
23#include "ARMRegisterInfo.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/Target/TargetFrameInfo.h"
28#include "llvm/Target/TargetRegisterInfo.h"
29#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
30using namespace llvm;
31
32namespace {
33  class ARMExpandPseudo : public MachineFunctionPass {
34  public:
35    static char ID;
36    ARMExpandPseudo() : MachineFunctionPass(ID) {}
37
38    const ARMBaseInstrInfo *TII;
39    const TargetRegisterInfo *TRI;
40    const ARMSubtarget *STI;
41
42    virtual bool runOnMachineFunction(MachineFunction &Fn);
43
44    virtual const char *getPassName() const {
45      return "ARM pseudo instruction expansion pass";
46    }
47
48  private:
49    void TransferImpOps(MachineInstr &OldMI,
50                        MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
51    bool ExpandMBB(MachineBasicBlock &MBB);
52    void ExpandVLD(MachineBasicBlock::iterator &MBBI);
53    void ExpandVST(MachineBasicBlock::iterator &MBBI);
54    void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
55    void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
56                    unsigned Opc, bool IsExt, unsigned NumRegs);
57  };
58  char ARMExpandPseudo::ID = 0;
59}
60
61/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
62/// the instructions created from the expansion.
63void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
64                                     MachineInstrBuilder &UseMI,
65                                     MachineInstrBuilder &DefMI) {
66  const TargetInstrDesc &Desc = OldMI.getDesc();
67  for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
68       i != e; ++i) {
69    const MachineOperand &MO = OldMI.getOperand(i);
70    assert(MO.isReg() && MO.getReg());
71    if (MO.isUse())
72      UseMI.addOperand(MO);
73    else
74      DefMI.addOperand(MO);
75  }
76}
77
78namespace {
79  // Constants for register spacing in NEON load/store instructions.
80  // For quad-register load-lane and store-lane pseudo instructors, the
81  // spacing is initially assumed to be EvenDblSpc, and that is changed to
82  // OddDblSpc depending on the lane number operand.
83  enum NEONRegSpacing {
84    SingleSpc,
85    EvenDblSpc,
86    OddDblSpc
87  };
88
89  // Entries for NEON load/store information table.  The table is sorted by
90  // PseudoOpc for fast binary-search lookups.
91  struct NEONLdStTableEntry {
92    unsigned PseudoOpc;
93    unsigned RealOpc;
94    bool IsLoad;
95    bool HasWriteBack;
96    NEONRegSpacing RegSpacing;
97    unsigned char NumRegs; // D registers loaded or stored
98    unsigned char RegElts; // elements per D register; used for lane ops
99
100    // Comparison methods for binary search of the table.
101    bool operator<(const NEONLdStTableEntry &TE) const {
102      return PseudoOpc < TE.PseudoOpc;
103    }
104    friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
105      return TE.PseudoOpc < PseudoOpc;
106    }
107    friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
108                                                const NEONLdStTableEntry &TE) {
109      return PseudoOpc < TE.PseudoOpc;
110    }
111  };
112}
113
114static const NEONLdStTableEntry NEONLdStTable[] = {
115{ ARM::VLD1DUPq16Pseudo,     ARM::VLD1DUPq16,     true, false, SingleSpc, 2, 4},
116{ ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true,  SingleSpc, 2, 4},
117{ ARM::VLD1DUPq32Pseudo,     ARM::VLD1DUPq32,     true, false, SingleSpc, 2, 2},
118{ ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true,  SingleSpc, 2, 2},
119{ ARM::VLD1DUPq8Pseudo,      ARM::VLD1DUPq8,      true, false, SingleSpc, 2, 8},
120{ ARM::VLD1DUPq8Pseudo_UPD,  ARM::VLD1DUPq8_UPD,  true, true,  SingleSpc, 2, 8},
121
122{ ARM::VLD1LNq16Pseudo,     ARM::VLD1LNd16,     true, false, EvenDblSpc, 1, 4 },
123{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true,  EvenDblSpc, 1, 4 },
124{ ARM::VLD1LNq32Pseudo,     ARM::VLD1LNd32,     true, false, EvenDblSpc, 1, 2 },
125{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true,  EvenDblSpc, 1, 2 },
126{ ARM::VLD1LNq8Pseudo,      ARM::VLD1LNd8,      true, false, EvenDblSpc, 1, 8 },
127{ ARM::VLD1LNq8Pseudo_UPD,  ARM::VLD1LNd8_UPD,  true, true,  EvenDblSpc, 1, 8 },
128
129{ ARM::VLD1d64QPseudo,      ARM::VLD1d64Q,     true,  false, SingleSpc,  4, 1 },
130{ ARM::VLD1d64QPseudo_UPD,  ARM::VLD1d64Q_UPD, true,  true,  SingleSpc,  4, 1 },
131{ ARM::VLD1d64TPseudo,      ARM::VLD1d64T,     true,  false, SingleSpc,  3, 1 },
132{ ARM::VLD1d64TPseudo_UPD,  ARM::VLD1d64T_UPD, true,  true,  SingleSpc,  3, 1 },
133
134{ ARM::VLD1q16Pseudo,       ARM::VLD1q16,      true,  false, SingleSpc,  2, 4 },
135{ ARM::VLD1q16Pseudo_UPD,   ARM::VLD1q16_UPD,  true,  true,  SingleSpc,  2, 4 },
136{ ARM::VLD1q32Pseudo,       ARM::VLD1q32,      true,  false, SingleSpc,  2, 2 },
137{ ARM::VLD1q32Pseudo_UPD,   ARM::VLD1q32_UPD,  true,  true,  SingleSpc,  2, 2 },
138{ ARM::VLD1q64Pseudo,       ARM::VLD1q64,      true,  false, SingleSpc,  2, 1 },
139{ ARM::VLD1q64Pseudo_UPD,   ARM::VLD1q64_UPD,  true,  true,  SingleSpc,  2, 1 },
140{ ARM::VLD1q8Pseudo,        ARM::VLD1q8,       true,  false, SingleSpc,  2, 8 },
141{ ARM::VLD1q8Pseudo_UPD,    ARM::VLD1q8_UPD,   true,  true,  SingleSpc,  2, 8 },
142
143{ ARM::VLD2DUPd16Pseudo,     ARM::VLD2DUPd16,     true, false, SingleSpc, 2, 4},
144{ ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true,  SingleSpc, 2, 4},
145{ ARM::VLD2DUPd32Pseudo,     ARM::VLD2DUPd32,     true, false, SingleSpc, 2, 2},
146{ ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true,  SingleSpc, 2, 2},
147{ ARM::VLD2DUPd8Pseudo,      ARM::VLD2DUPd8,      true, false, SingleSpc, 2, 8},
148{ ARM::VLD2DUPd8Pseudo_UPD,  ARM::VLD2DUPd8_UPD,  true, true,  SingleSpc, 2, 8},
149
150{ ARM::VLD2LNd16Pseudo,     ARM::VLD2LNd16,     true, false, SingleSpc,  2, 4 },
151{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true,  SingleSpc,  2, 4 },
152{ ARM::VLD2LNd32Pseudo,     ARM::VLD2LNd32,     true, false, SingleSpc,  2, 2 },
153{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true,  SingleSpc,  2, 2 },
154{ ARM::VLD2LNd8Pseudo,      ARM::VLD2LNd8,      true, false, SingleSpc,  2, 8 },
155{ ARM::VLD2LNd8Pseudo_UPD,  ARM::VLD2LNd8_UPD,  true, true,  SingleSpc,  2, 8 },
156{ ARM::VLD2LNq16Pseudo,     ARM::VLD2LNq16,     true, false, EvenDblSpc, 2, 4 },
157{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true,  EvenDblSpc, 2, 4 },
158{ ARM::VLD2LNq32Pseudo,     ARM::VLD2LNq32,     true, false, EvenDblSpc, 2, 2 },
159{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true,  EvenDblSpc, 2, 2 },
160
161{ ARM::VLD2d16Pseudo,       ARM::VLD2d16,      true,  false, SingleSpc,  2, 4 },
162{ ARM::VLD2d16Pseudo_UPD,   ARM::VLD2d16_UPD,  true,  true,  SingleSpc,  2, 4 },
163{ ARM::VLD2d32Pseudo,       ARM::VLD2d32,      true,  false, SingleSpc,  2, 2 },
164{ ARM::VLD2d32Pseudo_UPD,   ARM::VLD2d32_UPD,  true,  true,  SingleSpc,  2, 2 },
165{ ARM::VLD2d8Pseudo,        ARM::VLD2d8,       true,  false, SingleSpc,  2, 8 },
166{ ARM::VLD2d8Pseudo_UPD,    ARM::VLD2d8_UPD,   true,  true,  SingleSpc,  2, 8 },
167
168{ ARM::VLD2q16Pseudo,       ARM::VLD2q16,      true,  false, SingleSpc,  4, 4 },
169{ ARM::VLD2q16Pseudo_UPD,   ARM::VLD2q16_UPD,  true,  true,  SingleSpc,  4, 4 },
170{ ARM::VLD2q32Pseudo,       ARM::VLD2q32,      true,  false, SingleSpc,  4, 2 },
171{ ARM::VLD2q32Pseudo_UPD,   ARM::VLD2q32_UPD,  true,  true,  SingleSpc,  4, 2 },
172{ ARM::VLD2q8Pseudo,        ARM::VLD2q8,       true,  false, SingleSpc,  4, 8 },
173{ ARM::VLD2q8Pseudo_UPD,    ARM::VLD2q8_UPD,   true,  true,  SingleSpc,  4, 8 },
174
175{ ARM::VLD3DUPd16Pseudo,     ARM::VLD3DUPd16,     true, false, SingleSpc, 3, 4},
176{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true,  SingleSpc, 3, 4},
177{ ARM::VLD3DUPd32Pseudo,     ARM::VLD3DUPd32,     true, false, SingleSpc, 3, 2},
178{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true,  SingleSpc, 3, 2},
179{ ARM::VLD3DUPd8Pseudo,      ARM::VLD3DUPd8,      true, false, SingleSpc, 3, 8},
180{ ARM::VLD3DUPd8Pseudo_UPD,  ARM::VLD3DUPd8_UPD,  true, true,  SingleSpc, 3, 8},
181
182{ ARM::VLD3LNd16Pseudo,     ARM::VLD3LNd16,     true, false, SingleSpc,  3, 4 },
183{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true,  SingleSpc,  3, 4 },
184{ ARM::VLD3LNd32Pseudo,     ARM::VLD3LNd32,     true, false, SingleSpc,  3, 2 },
185{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true,  SingleSpc,  3, 2 },
186{ ARM::VLD3LNd8Pseudo,      ARM::VLD3LNd8,      true, false, SingleSpc,  3, 8 },
187{ ARM::VLD3LNd8Pseudo_UPD,  ARM::VLD3LNd8_UPD,  true, true,  SingleSpc,  3, 8 },
188{ ARM::VLD3LNq16Pseudo,     ARM::VLD3LNq16,     true, false, EvenDblSpc, 3, 4 },
189{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true,  EvenDblSpc, 3, 4 },
190{ ARM::VLD3LNq32Pseudo,     ARM::VLD3LNq32,     true, false, EvenDblSpc, 3, 2 },
191{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true,  EvenDblSpc, 3, 2 },
192
193{ ARM::VLD3d16Pseudo,       ARM::VLD3d16,      true,  false, SingleSpc,  3, 4 },
194{ ARM::VLD3d16Pseudo_UPD,   ARM::VLD3d16_UPD,  true,  true,  SingleSpc,  3, 4 },
195{ ARM::VLD3d32Pseudo,       ARM::VLD3d32,      true,  false, SingleSpc,  3, 2 },
196{ ARM::VLD3d32Pseudo_UPD,   ARM::VLD3d32_UPD,  true,  true,  SingleSpc,  3, 2 },
197{ ARM::VLD3d8Pseudo,        ARM::VLD3d8,       true,  false, SingleSpc,  3, 8 },
198{ ARM::VLD3d8Pseudo_UPD,    ARM::VLD3d8_UPD,   true,  true,  SingleSpc,  3, 8 },
199
200{ ARM::VLD3q16Pseudo_UPD,    ARM::VLD3q16_UPD, true,  true,  EvenDblSpc, 3, 4 },
201{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true,  true,  OddDblSpc,  3, 4 },
202{ ARM::VLD3q32Pseudo_UPD,    ARM::VLD3q32_UPD, true,  true,  EvenDblSpc, 3, 2 },
203{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true,  true,  OddDblSpc,  3, 2 },
204{ ARM::VLD3q8Pseudo_UPD,     ARM::VLD3q8_UPD,  true,  true,  EvenDblSpc, 3, 8 },
205{ ARM::VLD3q8oddPseudo_UPD,  ARM::VLD3q8_UPD,  true,  true,  OddDblSpc,  3, 8 },
206
207{ ARM::VLD4DUPd16Pseudo,     ARM::VLD4DUPd16,     true, false, SingleSpc, 4, 4},
208{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true,  SingleSpc, 4, 4},
209{ ARM::VLD4DUPd32Pseudo,     ARM::VLD4DUPd32,     true, false, SingleSpc, 4, 2},
210{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true,  SingleSpc, 4, 2},
211{ ARM::VLD4DUPd8Pseudo,      ARM::VLD4DUPd8,      true, false, SingleSpc, 4, 8},
212{ ARM::VLD4DUPd8Pseudo_UPD,  ARM::VLD4DUPd8_UPD,  true, true,  SingleSpc, 4, 8},
213
214{ ARM::VLD4LNd16Pseudo,     ARM::VLD4LNd16,     true, false, SingleSpc,  4, 4 },
215{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true,  SingleSpc,  4, 4 },
216{ ARM::VLD4LNd32Pseudo,     ARM::VLD4LNd32,     true, false, SingleSpc,  4, 2 },
217{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true,  SingleSpc,  4, 2 },
218{ ARM::VLD4LNd8Pseudo,      ARM::VLD4LNd8,      true, false, SingleSpc,  4, 8 },
219{ ARM::VLD4LNd8Pseudo_UPD,  ARM::VLD4LNd8_UPD,  true, true,  SingleSpc,  4, 8 },
220{ ARM::VLD4LNq16Pseudo,     ARM::VLD4LNq16,     true, false, EvenDblSpc, 4, 4 },
221{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true,  EvenDblSpc, 4, 4 },
222{ ARM::VLD4LNq32Pseudo,     ARM::VLD4LNq32,     true, false, EvenDblSpc, 4, 2 },
223{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true,  EvenDblSpc, 4, 2 },
224
225{ ARM::VLD4d16Pseudo,       ARM::VLD4d16,      true,  false, SingleSpc,  4, 4 },
226{ ARM::VLD4d16Pseudo_UPD,   ARM::VLD4d16_UPD,  true,  true,  SingleSpc,  4, 4 },
227{ ARM::VLD4d32Pseudo,       ARM::VLD4d32,      true,  false, SingleSpc,  4, 2 },
228{ ARM::VLD4d32Pseudo_UPD,   ARM::VLD4d32_UPD,  true,  true,  SingleSpc,  4, 2 },
229{ ARM::VLD4d8Pseudo,        ARM::VLD4d8,       true,  false, SingleSpc,  4, 8 },
230{ ARM::VLD4d8Pseudo_UPD,    ARM::VLD4d8_UPD,   true,  true,  SingleSpc,  4, 8 },
231
232{ ARM::VLD4q16Pseudo_UPD,    ARM::VLD4q16_UPD, true,  true,  EvenDblSpc, 4, 4 },
233{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true,  true,  OddDblSpc,  4, 4 },
234{ ARM::VLD4q32Pseudo_UPD,    ARM::VLD4q32_UPD, true,  true,  EvenDblSpc, 4, 2 },
235{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true,  true,  OddDblSpc,  4, 2 },
236{ ARM::VLD4q8Pseudo_UPD,     ARM::VLD4q8_UPD,  true,  true,  EvenDblSpc, 4, 8 },
237{ ARM::VLD4q8oddPseudo_UPD,  ARM::VLD4q8_UPD,  true,  true,  OddDblSpc,  4, 8 },
238
239{ ARM::VST1LNq16Pseudo,     ARM::VST1LNd16,    false, false, EvenDblSpc, 1, 4 },
240{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true,  EvenDblSpc, 1, 4 },
241{ ARM::VST1LNq32Pseudo,     ARM::VST1LNd32,    false, false, EvenDblSpc, 1, 2 },
242{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true,  EvenDblSpc, 1, 2 },
243{ ARM::VST1LNq8Pseudo,      ARM::VST1LNd8,     false, false, EvenDblSpc, 1, 8 },
244{ ARM::VST1LNq8Pseudo_UPD,  ARM::VST1LNd8_UPD, false, true,  EvenDblSpc, 1, 8 },
245
246{ ARM::VST1d64QPseudo,      ARM::VST1d64Q,     false, false, SingleSpc,  4, 1 },
247{ ARM::VST1d64QPseudo_UPD,  ARM::VST1d64Q_UPD, false, true,  SingleSpc,  4, 1 },
248{ ARM::VST1d64TPseudo,      ARM::VST1d64T,     false, false, SingleSpc,  3, 1 },
249{ ARM::VST1d64TPseudo_UPD,  ARM::VST1d64T_UPD, false, true,  SingleSpc,  3, 1 },
250
251{ ARM::VST1q16Pseudo,       ARM::VST1q16,      false, false, SingleSpc,  2, 4 },
252{ ARM::VST1q16Pseudo_UPD,   ARM::VST1q16_UPD,  false, true,  SingleSpc,  2, 4 },
253{ ARM::VST1q32Pseudo,       ARM::VST1q32,      false, false, SingleSpc,  2, 2 },
254{ ARM::VST1q32Pseudo_UPD,   ARM::VST1q32_UPD,  false, true,  SingleSpc,  2, 2 },
255{ ARM::VST1q64Pseudo,       ARM::VST1q64,      false, false, SingleSpc,  2, 1 },
256{ ARM::VST1q64Pseudo_UPD,   ARM::VST1q64_UPD,  false, true,  SingleSpc,  2, 1 },
257{ ARM::VST1q8Pseudo,        ARM::VST1q8,       false, false, SingleSpc,  2, 8 },
258{ ARM::VST1q8Pseudo_UPD,    ARM::VST1q8_UPD,   false, true,  SingleSpc,  2, 8 },
259
260{ ARM::VST2LNd16Pseudo,     ARM::VST2LNd16,     false, false, SingleSpc, 2, 4 },
261{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true,  SingleSpc, 2, 4 },
262{ ARM::VST2LNd32Pseudo,     ARM::VST2LNd32,     false, false, SingleSpc, 2, 2 },
263{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true,  SingleSpc, 2, 2 },
264{ ARM::VST2LNd8Pseudo,      ARM::VST2LNd8,      false, false, SingleSpc, 2, 8 },
265{ ARM::VST2LNd8Pseudo_UPD,  ARM::VST2LNd8_UPD,  false, true,  SingleSpc, 2, 8 },
266{ ARM::VST2LNq16Pseudo,     ARM::VST2LNq16,     false, false, EvenDblSpc, 2, 4},
267{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true,  EvenDblSpc, 2, 4},
268{ ARM::VST2LNq32Pseudo,     ARM::VST2LNq32,     false, false, EvenDblSpc, 2, 2},
269{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true,  EvenDblSpc, 2, 2},
270
271{ ARM::VST2d16Pseudo,       ARM::VST2d16,      false, false, SingleSpc,  2, 4 },
272{ ARM::VST2d16Pseudo_UPD,   ARM::VST2d16_UPD,  false, true,  SingleSpc,  2, 4 },
273{ ARM::VST2d32Pseudo,       ARM::VST2d32,      false, false, SingleSpc,  2, 2 },
274{ ARM::VST2d32Pseudo_UPD,   ARM::VST2d32_UPD,  false, true,  SingleSpc,  2, 2 },
275{ ARM::VST2d8Pseudo,        ARM::VST2d8,       false, false, SingleSpc,  2, 8 },
276{ ARM::VST2d8Pseudo_UPD,    ARM::VST2d8_UPD,   false, true,  SingleSpc,  2, 8 },
277
278{ ARM::VST2q16Pseudo,       ARM::VST2q16,      false, false, SingleSpc,  4, 4 },
279{ ARM::VST2q16Pseudo_UPD,   ARM::VST2q16_UPD,  false, true,  SingleSpc,  4, 4 },
280{ ARM::VST2q32Pseudo,       ARM::VST2q32,      false, false, SingleSpc,  4, 2 },
281{ ARM::VST2q32Pseudo_UPD,   ARM::VST2q32_UPD,  false, true,  SingleSpc,  4, 2 },
282{ ARM::VST2q8Pseudo,        ARM::VST2q8,       false, false, SingleSpc,  4, 8 },
283{ ARM::VST2q8Pseudo_UPD,    ARM::VST2q8_UPD,   false, true,  SingleSpc,  4, 8 },
284
285{ ARM::VST3LNd16Pseudo,     ARM::VST3LNd16,     false, false, SingleSpc, 3, 4 },
286{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true,  SingleSpc, 3, 4 },
287{ ARM::VST3LNd32Pseudo,     ARM::VST3LNd32,     false, false, SingleSpc, 3, 2 },
288{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true,  SingleSpc, 3, 2 },
289{ ARM::VST3LNd8Pseudo,      ARM::VST3LNd8,      false, false, SingleSpc, 3, 8 },
290{ ARM::VST3LNd8Pseudo_UPD,  ARM::VST3LNd8_UPD,  false, true,  SingleSpc, 3, 8 },
291{ ARM::VST3LNq16Pseudo,     ARM::VST3LNq16,     false, false, EvenDblSpc, 3, 4},
292{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true,  EvenDblSpc, 3, 4},
293{ ARM::VST3LNq32Pseudo,     ARM::VST3LNq32,     false, false, EvenDblSpc, 3, 2},
294{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true,  EvenDblSpc, 3, 2},
295
296{ ARM::VST3d16Pseudo,       ARM::VST3d16,      false, false, SingleSpc,  3, 4 },
297{ ARM::VST3d16Pseudo_UPD,   ARM::VST3d16_UPD,  false, true,  SingleSpc,  3, 4 },
298{ ARM::VST3d32Pseudo,       ARM::VST3d32,      false, false, SingleSpc,  3, 2 },
299{ ARM::VST3d32Pseudo_UPD,   ARM::VST3d32_UPD,  false, true,  SingleSpc,  3, 2 },
300{ ARM::VST3d8Pseudo,        ARM::VST3d8,       false, false, SingleSpc,  3, 8 },
301{ ARM::VST3d8Pseudo_UPD,    ARM::VST3d8_UPD,   false, true,  SingleSpc,  3, 8 },
302
303{ ARM::VST3q16Pseudo_UPD,    ARM::VST3q16_UPD, false, true,  EvenDblSpc, 3, 4 },
304{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true,  OddDblSpc,  3, 4 },
305{ ARM::VST3q32Pseudo_UPD,    ARM::VST3q32_UPD, false, true,  EvenDblSpc, 3, 2 },
306{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true,  OddDblSpc,  3, 2 },
307{ ARM::VST3q8Pseudo_UPD,     ARM::VST3q8_UPD,  false, true,  EvenDblSpc, 3, 8 },
308{ ARM::VST3q8oddPseudo_UPD,  ARM::VST3q8_UPD,  false, true,  OddDblSpc,  3, 8 },
309
310{ ARM::VST4LNd16Pseudo,     ARM::VST4LNd16,     false, false, SingleSpc, 4, 4 },
311{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true,  SingleSpc, 4, 4 },
312{ ARM::VST4LNd32Pseudo,     ARM::VST4LNd32,     false, false, SingleSpc, 4, 2 },
313{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true,  SingleSpc, 4, 2 },
314{ ARM::VST4LNd8Pseudo,      ARM::VST4LNd8,      false, false, SingleSpc, 4, 8 },
315{ ARM::VST4LNd8Pseudo_UPD,  ARM::VST4LNd8_UPD,  false, true,  SingleSpc, 4, 8 },
316{ ARM::VST4LNq16Pseudo,     ARM::VST4LNq16,     false, false, EvenDblSpc, 4, 4},
317{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true,  EvenDblSpc, 4, 4},
318{ ARM::VST4LNq32Pseudo,     ARM::VST4LNq32,     false, false, EvenDblSpc, 4, 2},
319{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true,  EvenDblSpc, 4, 2},
320
321{ ARM::VST4d16Pseudo,       ARM::VST4d16,      false, false, SingleSpc,  4, 4 },
322{ ARM::VST4d16Pseudo_UPD,   ARM::VST4d16_UPD,  false, true,  SingleSpc,  4, 4 },
323{ ARM::VST4d32Pseudo,       ARM::VST4d32,      false, false, SingleSpc,  4, 2 },
324{ ARM::VST4d32Pseudo_UPD,   ARM::VST4d32_UPD,  false, true,  SingleSpc,  4, 2 },
325{ ARM::VST4d8Pseudo,        ARM::VST4d8,       false, false, SingleSpc,  4, 8 },
326{ ARM::VST4d8Pseudo_UPD,    ARM::VST4d8_UPD,   false, true,  SingleSpc,  4, 8 },
327
328{ ARM::VST4q16Pseudo_UPD,    ARM::VST4q16_UPD, false, true,  EvenDblSpc, 4, 4 },
329{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true,  OddDblSpc,  4, 4 },
330{ ARM::VST4q32Pseudo_UPD,    ARM::VST4q32_UPD, false, true,  EvenDblSpc, 4, 2 },
331{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true,  OddDblSpc,  4, 2 },
332{ ARM::VST4q8Pseudo_UPD,     ARM::VST4q8_UPD,  false, true,  EvenDblSpc, 4, 8 },
333{ ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD,  false, true,  OddDblSpc,  4, 8 }
334};
335
336/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
337/// load or store pseudo instruction.
338static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
339  unsigned NumEntries = array_lengthof(NEONLdStTable);
340
341#ifndef NDEBUG
342  // Make sure the table is sorted.
343  static bool TableChecked = false;
344  if (!TableChecked) {
345    for (unsigned i = 0; i != NumEntries-1; ++i)
346      assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
347             "NEONLdStTable is not sorted!");
348    TableChecked = true;
349  }
350#endif
351
352  const NEONLdStTableEntry *I =
353    std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
354  if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
355    return I;
356  return NULL;
357}
358
359/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
360/// corresponding to the specified register spacing.  Not all of the results
361/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
362static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
363                        const TargetRegisterInfo *TRI, unsigned &D0,
364                        unsigned &D1, unsigned &D2, unsigned &D3) {
365  if (RegSpc == SingleSpc) {
366    D0 = TRI->getSubReg(Reg, ARM::dsub_0);
367    D1 = TRI->getSubReg(Reg, ARM::dsub_1);
368    D2 = TRI->getSubReg(Reg, ARM::dsub_2);
369    D3 = TRI->getSubReg(Reg, ARM::dsub_3);
370  } else if (RegSpc == EvenDblSpc) {
371    D0 = TRI->getSubReg(Reg, ARM::dsub_0);
372    D1 = TRI->getSubReg(Reg, ARM::dsub_2);
373    D2 = TRI->getSubReg(Reg, ARM::dsub_4);
374    D3 = TRI->getSubReg(Reg, ARM::dsub_6);
375  } else {
376    assert(RegSpc == OddDblSpc && "unknown register spacing");
377    D0 = TRI->getSubReg(Reg, ARM::dsub_1);
378    D1 = TRI->getSubReg(Reg, ARM::dsub_3);
379    D2 = TRI->getSubReg(Reg, ARM::dsub_5);
380    D3 = TRI->getSubReg(Reg, ARM::dsub_7);
381  }
382}
383
384/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
385/// operands to real VLD instructions with D register operands.
386void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
387  MachineInstr &MI = *MBBI;
388  MachineBasicBlock &MBB = *MI.getParent();
389
390  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
391  assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
392  NEONRegSpacing RegSpc = TableEntry->RegSpacing;
393  unsigned NumRegs = TableEntry->NumRegs;
394
395  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
396                                    TII->get(TableEntry->RealOpc));
397  unsigned OpIdx = 0;
398
399  bool DstIsDead = MI.getOperand(OpIdx).isDead();
400  unsigned DstReg = MI.getOperand(OpIdx++).getReg();
401  unsigned D0, D1, D2, D3;
402  GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
403  MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
404    .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
405  if (NumRegs > 2)
406    MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
407  if (NumRegs > 3)
408    MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
409
410  if (TableEntry->HasWriteBack)
411    MIB.addOperand(MI.getOperand(OpIdx++));
412
413  // Copy the addrmode6 operands.
414  MIB.addOperand(MI.getOperand(OpIdx++));
415  MIB.addOperand(MI.getOperand(OpIdx++));
416  // Copy the am6offset operand.
417  if (TableEntry->HasWriteBack)
418    MIB.addOperand(MI.getOperand(OpIdx++));
419
420  // For an instruction writing double-spaced subregs, the pseudo instruction
421  // has an extra operand that is a use of the super-register.  Record the
422  // operand index and skip over it.
423  unsigned SrcOpIdx = 0;
424  if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
425    SrcOpIdx = OpIdx++;
426
427  // Copy the predicate operands.
428  MIB.addOperand(MI.getOperand(OpIdx++));
429  MIB.addOperand(MI.getOperand(OpIdx++));
430
431  // Copy the super-register source operand used for double-spaced subregs over
432  // to the new instruction as an implicit operand.
433  if (SrcOpIdx != 0) {
434    MachineOperand MO = MI.getOperand(SrcOpIdx);
435    MO.setImplicit(true);
436    MIB.addOperand(MO);
437  }
438  // Add an implicit def for the super-register.
439  MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
440  TransferImpOps(MI, MIB, MIB);
441  MI.eraseFromParent();
442}
443
444/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
445/// operands to real VST instructions with D register operands.
446void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
447  MachineInstr &MI = *MBBI;
448  MachineBasicBlock &MBB = *MI.getParent();
449
450  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
451  assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
452  NEONRegSpacing RegSpc = TableEntry->RegSpacing;
453  unsigned NumRegs = TableEntry->NumRegs;
454
455  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
456                                    TII->get(TableEntry->RealOpc));
457  unsigned OpIdx = 0;
458  if (TableEntry->HasWriteBack)
459    MIB.addOperand(MI.getOperand(OpIdx++));
460
461  // Copy the addrmode6 operands.
462  MIB.addOperand(MI.getOperand(OpIdx++));
463  MIB.addOperand(MI.getOperand(OpIdx++));
464  // Copy the am6offset operand.
465  if (TableEntry->HasWriteBack)
466    MIB.addOperand(MI.getOperand(OpIdx++));
467
468  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
469  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
470  unsigned D0, D1, D2, D3;
471  GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
472  MIB.addReg(D0).addReg(D1);
473  if (NumRegs > 2)
474    MIB.addReg(D2);
475  if (NumRegs > 3)
476    MIB.addReg(D3);
477
478  // Copy the predicate operands.
479  MIB.addOperand(MI.getOperand(OpIdx++));
480  MIB.addOperand(MI.getOperand(OpIdx++));
481
482  if (SrcIsKill)
483    // Add an implicit kill for the super-reg.
484    (*MIB).addRegisterKilled(SrcReg, TRI, true);
485  TransferImpOps(MI, MIB, MIB);
486  MI.eraseFromParent();
487}
488
489/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
490/// register operands to real instructions with D register operands.
491void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
492  MachineInstr &MI = *MBBI;
493  MachineBasicBlock &MBB = *MI.getParent();
494
495  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
496  assert(TableEntry && "NEONLdStTable lookup failed");
497  NEONRegSpacing RegSpc = TableEntry->RegSpacing;
498  unsigned NumRegs = TableEntry->NumRegs;
499  unsigned RegElts = TableEntry->RegElts;
500
501  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
502                                    TII->get(TableEntry->RealOpc));
503  unsigned OpIdx = 0;
504  // The lane operand is always the 3rd from last operand, before the 2
505  // predicate operands.
506  unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
507
508  // Adjust the lane and spacing as needed for Q registers.
509  assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
510  if (RegSpc == EvenDblSpc && Lane >= RegElts) {
511    RegSpc = OddDblSpc;
512    Lane -= RegElts;
513  }
514  assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
515
516  unsigned D0, D1, D2, D3;
517  unsigned DstReg = 0;
518  bool DstIsDead = false;
519  if (TableEntry->IsLoad) {
520    DstIsDead = MI.getOperand(OpIdx).isDead();
521    DstReg = MI.getOperand(OpIdx++).getReg();
522    GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
523    MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
524    if (NumRegs > 1)
525      MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
526    if (NumRegs > 2)
527      MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
528    if (NumRegs > 3)
529      MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
530  }
531
532  if (TableEntry->HasWriteBack)
533    MIB.addOperand(MI.getOperand(OpIdx++));
534
535  // Copy the addrmode6 operands.
536  MIB.addOperand(MI.getOperand(OpIdx++));
537  MIB.addOperand(MI.getOperand(OpIdx++));
538  // Copy the am6offset operand.
539  if (TableEntry->HasWriteBack)
540    MIB.addOperand(MI.getOperand(OpIdx++));
541
542  // Grab the super-register source.
543  MachineOperand MO = MI.getOperand(OpIdx++);
544  if (!TableEntry->IsLoad)
545    GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
546
547  // Add the subregs as sources of the new instruction.
548  unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
549                       getKillRegState(MO.isKill()));
550  MIB.addReg(D0, SrcFlags);
551  if (NumRegs > 1)
552    MIB.addReg(D1, SrcFlags);
553  if (NumRegs > 2)
554    MIB.addReg(D2, SrcFlags);
555  if (NumRegs > 3)
556    MIB.addReg(D3, SrcFlags);
557
558  // Add the lane number operand.
559  MIB.addImm(Lane);
560  OpIdx += 1;
561
562  // Copy the predicate operands.
563  MIB.addOperand(MI.getOperand(OpIdx++));
564  MIB.addOperand(MI.getOperand(OpIdx++));
565
566  // Copy the super-register source to be an implicit source.
567  MO.setImplicit(true);
568  MIB.addOperand(MO);
569  if (TableEntry->IsLoad)
570    // Add an implicit def for the super-register.
571    MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
572  TransferImpOps(MI, MIB, MIB);
573  MI.eraseFromParent();
574}
575
576/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
577/// register operands to real instructions with D register operands.
578void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
579                                 unsigned Opc, bool IsExt, unsigned NumRegs) {
580  MachineInstr &MI = *MBBI;
581  MachineBasicBlock &MBB = *MI.getParent();
582
583  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
584  unsigned OpIdx = 0;
585
586  // Transfer the destination register operand.
587  MIB.addOperand(MI.getOperand(OpIdx++));
588  if (IsExt)
589    MIB.addOperand(MI.getOperand(OpIdx++));
590
591  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
592  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
593  unsigned D0, D1, D2, D3;
594  GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
595  MIB.addReg(D0).addReg(D1);
596  if (NumRegs > 2)
597    MIB.addReg(D2);
598  if (NumRegs > 3)
599    MIB.addReg(D3);
600
601  // Copy the other source register operand.
602  MIB.addOperand(MI.getOperand(OpIdx++));
603
604  // Copy the predicate operands.
605  MIB.addOperand(MI.getOperand(OpIdx++));
606  MIB.addOperand(MI.getOperand(OpIdx++));
607
608  if (SrcIsKill)
609    // Add an implicit kill for the super-reg.
610    (*MIB).addRegisterKilled(SrcReg, TRI, true);
611  TransferImpOps(MI, MIB, MIB);
612  MI.eraseFromParent();
613}
614
615bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
616  bool Modified = false;
617
618  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
619  while (MBBI != E) {
620    MachineInstr &MI = *MBBI;
621    MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
622
623    bool ModifiedOp = true;
624    unsigned Opcode = MI.getOpcode();
625    switch (Opcode) {
626    default:
627      ModifiedOp = false;
628      break;
629
630    case ARM::Int_eh_sjlj_dispatchsetup: {
631      MachineFunction &MF = *MI.getParent()->getParent();
632      const ARMBaseInstrInfo *AII =
633        static_cast<const ARMBaseInstrInfo*>(TII);
634      const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
635      // For functions using a base pointer, we rematerialize it (via the frame
636      // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
637      // for us. Otherwise, expand to nothing.
638      if (RI.hasBasePointer(MF)) {
639        ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
640        int32_t NumBytes = AFI->getFramePtrSpillOffset();
641        unsigned FramePtr = RI.getFrameRegister(MF);
642        assert(MF.getTarget().getFrameInfo()->hasFP(MF) &&
643               "base pointer without frame pointer?");
644
645        if (AFI->isThumb2Function()) {
646          llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
647                                       FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
648        } else if (AFI->isThumbFunction()) {
649          llvm::emitThumbRegPlusImmediate(MBB, MBBI, ARM::R6,
650                                          FramePtr, -NumBytes,
651                                          *TII, RI, MI.getDebugLoc());
652        } else {
653          llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
654                                        FramePtr, -NumBytes, ARMCC::AL, 0,
655                                        *TII);
656        }
657        // If there's dynamic realignment, adjust for it.
658        if (RI.needsStackRealignment(MF)) {
659          MachineFrameInfo  *MFI = MF.getFrameInfo();
660          unsigned MaxAlign = MFI->getMaxAlignment();
661          assert (!AFI->isThumb1OnlyFunction());
662          // Emit bic r6, r6, MaxAlign
663          unsigned bicOpc = AFI->isThumbFunction() ?
664            ARM::t2BICri : ARM::BICri;
665          AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
666                                              TII->get(bicOpc), ARM::R6)
667                                      .addReg(ARM::R6, RegState::Kill)
668                                      .addImm(MaxAlign-1)));
669        }
670
671      }
672      MI.eraseFromParent();
673      break;
674    }
675
676    case ARM::MOVsrl_flag:
677    case ARM::MOVsra_flag: {
678      // These are just fancy MOVs insructions.
679      AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
680                             MI.getOperand(0).getReg())
681      .addOperand(MI.getOperand(1))
682      .addReg(0)
683      .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
684                                   : ARM_AM::asr), 1)))
685      .addReg(ARM::CPSR, RegState::Define);
686      MI.eraseFromParent();
687      break;
688    }
689    case ARM::RRX: {
690      // This encodes as "MOVs Rd, Rm, rrx
691      MachineInstrBuilder MIB =
692        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
693                               MI.getOperand(0).getReg())
694        .addOperand(MI.getOperand(1))
695        .addOperand(MI.getOperand(1))
696        .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
697        .addReg(0);
698      TransferImpOps(MI, MIB, MIB);
699      MI.eraseFromParent();
700      break;
701    }
702    case ARM::TPsoft: {
703      MachineInstrBuilder MIB =
704        BuildMI(MBB, MBBI, MI.getDebugLoc(),
705                TII->get(ARM::BL))
706        .addExternalSymbol("__aeabi_read_tp", 0);
707
708      (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
709      TransferImpOps(MI, MIB, MIB);
710      MI.eraseFromParent();
711      break;
712    }
713    case ARM::t2LDRHpci:
714    case ARM::t2LDRBpci:
715    case ARM::t2LDRSHpci:
716    case ARM::t2LDRSBpci:
717    case ARM::t2LDRpci: {
718      unsigned NewLdOpc;
719      if (Opcode == ARM::t2LDRpci)
720        NewLdOpc = ARM::t2LDRi12;
721      else if (Opcode == ARM::t2LDRHpci)
722        NewLdOpc = ARM::t2LDRHi12;
723      else if (Opcode == ARM::t2LDRBpci)
724        NewLdOpc = ARM::t2LDRBi12;
725      else if (Opcode == ARM::t2LDRSHpci)
726        NewLdOpc = ARM::t2LDRSHi12;
727      else if (Opcode == ARM::t2LDRSBpci)
728        NewLdOpc = ARM::t2LDRSBi12;
729      else
730        llvm_unreachable("Not a known opcode?");
731
732      unsigned DstReg = MI.getOperand(0).getReg();
733      MachineInstrBuilder MIB =
734        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
735                               TII->get(NewLdOpc), DstReg)
736                .addReg(ARM::PC)
737                .addOperand(MI.getOperand(1)));
738      (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
739      TransferImpOps(MI, MIB, MIB);
740      MI.eraseFromParent();
741      break;
742    }
743    case ARM::tLDRpci_pic:
744    case ARM::t2LDRpci_pic: {
745      unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
746        ? ARM::tLDRpci : ARM::t2LDRi12;
747      unsigned DstReg = MI.getOperand(0).getReg();
748      bool DstIsDead = MI.getOperand(0).isDead();
749      MachineInstrBuilder MIB1 =
750        BuildMI(MBB, MBBI, MI.getDebugLoc(),
751        TII->get(NewLdOpc), DstReg);
752      if (Opcode == ARM::t2LDRpci_pic) MIB1.addReg(ARM::PC);
753      MIB1.addOperand(MI.getOperand(1));
754      AddDefaultPred(MIB1);
755      (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
756      MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
757                                         TII->get(ARM::tPICADD))
758        .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
759        .addReg(DstReg)
760        .addOperand(MI.getOperand(2));
761      TransferImpOps(MI, MIB1, MIB2);
762      MI.eraseFromParent();
763      break;
764    }
765
766    case ARM::t2LEApcrel:
767    case ARM::t2LEApcrelJT: {
768      bool DstIsDead = MI.getOperand(0).isDead();
769      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
770                                TII->get(ARM::t2ADR))
771        .addReg(MI.getOperand(0).getReg(),
772                RegState::Define | getDeadRegState(DstIsDead)) // Dst reg
773        .addOperand(MI.getOperand(1))      // Label
774        .addOperand(MI.getOperand(2))      // Pred
775        .addOperand(MI.getOperand(3));
776      TransferImpOps(MI, MIB, MIB);
777      MI.eraseFromParent();
778      return MIB;
779    }
780
781    case ARM::MOVi32imm:
782    case ARM::MOVCCi32imm:
783    case ARM::t2MOVi32imm:
784    case ARM::t2MOVCCi32imm: {
785      unsigned PredReg = 0;
786      ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
787      unsigned DstReg = MI.getOperand(0).getReg();
788      bool DstIsDead = MI.getOperand(0).isDead();
789      bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
790      const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
791      MachineInstrBuilder LO16, HI16;
792
793      if (!STI->hasV6T2Ops() &&
794          (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
795        // Expand into a movi + orr.
796        LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
797        HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
798          .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
799          .addReg(DstReg);
800
801        assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
802        unsigned ImmVal = (unsigned)MO.getImm();
803        unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
804        unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
805        LO16 = LO16.addImm(SOImmValV1);
806        HI16 = HI16.addImm(SOImmValV2);
807        (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
808        (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
809        LO16.addImm(Pred).addReg(PredReg).addReg(0);
810        HI16.addImm(Pred).addReg(PredReg).addReg(0);
811        TransferImpOps(MI, LO16, HI16);
812        MI.eraseFromParent();
813        break;
814      }
815
816      bool isThumb =
817        (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm);
818
819      LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
820                     TII->get(isThumb ? ARM::t2MOVi16 : ARM::MOVi16),
821                     DstReg);
822      HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
823                     TII->get(isThumb ? ARM::t2MOVTi16 : ARM::MOVTi16))
824        .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
825        .addReg(DstReg);
826
827      if (MO.isImm()) {
828        unsigned Imm = MO.getImm();
829        unsigned Lo16 = Imm & 0xffff;
830        unsigned Hi16 = (Imm >> 16) & 0xffff;
831        LO16 = LO16.addImm(Lo16);
832        HI16 = HI16.addImm(Hi16);
833      } else {
834        const GlobalValue *GV = MO.getGlobal();
835        unsigned TF = MO.getTargetFlags();
836        LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
837        HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
838      }
839      (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
840      (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
841      LO16.addImm(Pred).addReg(PredReg);
842      HI16.addImm(Pred).addReg(PredReg);
843      TransferImpOps(MI, LO16, HI16);
844      MI.eraseFromParent();
845      break;
846    }
847
848    case ARM::VMOVQQ: {
849      unsigned DstReg = MI.getOperand(0).getReg();
850      bool DstIsDead = MI.getOperand(0).isDead();
851      unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
852      unsigned OddDst  = TRI->getSubReg(DstReg, ARM::qsub_1);
853      unsigned SrcReg = MI.getOperand(1).getReg();
854      bool SrcIsKill = MI.getOperand(1).isKill();
855      unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
856      unsigned OddSrc  = TRI->getSubReg(SrcReg, ARM::qsub_1);
857      MachineInstrBuilder Even =
858        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
859                               TII->get(ARM::VMOVQ))
860                     .addReg(EvenDst,
861                             RegState::Define | getDeadRegState(DstIsDead))
862                     .addReg(EvenSrc, getKillRegState(SrcIsKill)));
863      MachineInstrBuilder Odd =
864        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
865                               TII->get(ARM::VMOVQ))
866                     .addReg(OddDst,
867                             RegState::Define | getDeadRegState(DstIsDead))
868                     .addReg(OddSrc, getKillRegState(SrcIsKill)));
869      TransferImpOps(MI, Even, Odd);
870      MI.eraseFromParent();
871      break;
872    }
873
874    case ARM::VLDMQIA:
875    case ARM::VLDMQDB: {
876      unsigned NewOpc = (Opcode == ARM::VLDMQIA) ? ARM::VLDMDIA : ARM::VLDMDDB;
877      MachineInstrBuilder MIB =
878        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
879      unsigned OpIdx = 0;
880
881      // Grab the Q register destination.
882      bool DstIsDead = MI.getOperand(OpIdx).isDead();
883      unsigned DstReg = MI.getOperand(OpIdx++).getReg();
884
885      // Copy the source register.
886      MIB.addOperand(MI.getOperand(OpIdx++));
887
888      // Copy the predicate operands.
889      MIB.addOperand(MI.getOperand(OpIdx++));
890      MIB.addOperand(MI.getOperand(OpIdx++));
891
892      // Add the destination operands (D subregs).
893      unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
894      unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
895      MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
896        .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
897
898      // Add an implicit def for the super-register.
899      MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
900      TransferImpOps(MI, MIB, MIB);
901      MI.eraseFromParent();
902      break;
903    }
904
905    case ARM::VSTMQIA:
906    case ARM::VSTMQDB: {
907      unsigned NewOpc = (Opcode == ARM::VSTMQIA) ? ARM::VSTMDIA : ARM::VSTMDDB;
908      MachineInstrBuilder MIB =
909        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
910      unsigned OpIdx = 0;
911
912      // Grab the Q register source.
913      bool SrcIsKill = MI.getOperand(OpIdx).isKill();
914      unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
915
916      // Copy the destination register.
917      MIB.addOperand(MI.getOperand(OpIdx++));
918
919      // Copy the predicate operands.
920      MIB.addOperand(MI.getOperand(OpIdx++));
921      MIB.addOperand(MI.getOperand(OpIdx++));
922
923      // Add the source operands (D subregs).
924      unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
925      unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
926      MIB.addReg(D0).addReg(D1);
927
928      if (SrcIsKill)
929        // Add an implicit kill for the Q register.
930        (*MIB).addRegisterKilled(SrcReg, TRI, true);
931
932      TransferImpOps(MI, MIB, MIB);
933      MI.eraseFromParent();
934      break;
935    }
936    case ARM::VDUPfqf:
937    case ARM::VDUPfdf:{
938      unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd;
939      MachineInstrBuilder MIB =
940        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
941      unsigned OpIdx = 0;
942      unsigned SrcReg = MI.getOperand(1).getReg();
943      unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
944      unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
945          Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
946      // The lane is [0,1] for the containing DReg superregister.
947      // Copy the dst/src register operands.
948      MIB.addOperand(MI.getOperand(OpIdx++));
949      MIB.addReg(DReg);
950      ++OpIdx;
951      // Add the lane select operand.
952      MIB.addImm(Lane);
953      // Add the predicate operands.
954      MIB.addOperand(MI.getOperand(OpIdx++));
955      MIB.addOperand(MI.getOperand(OpIdx++));
956
957      TransferImpOps(MI, MIB, MIB);
958      MI.eraseFromParent();
959      break;
960    }
961
962    case ARM::VLD1q8Pseudo:
963    case ARM::VLD1q16Pseudo:
964    case ARM::VLD1q32Pseudo:
965    case ARM::VLD1q64Pseudo:
966    case ARM::VLD1q8Pseudo_UPD:
967    case ARM::VLD1q16Pseudo_UPD:
968    case ARM::VLD1q32Pseudo_UPD:
969    case ARM::VLD1q64Pseudo_UPD:
970    case ARM::VLD2d8Pseudo:
971    case ARM::VLD2d16Pseudo:
972    case ARM::VLD2d32Pseudo:
973    case ARM::VLD2q8Pseudo:
974    case ARM::VLD2q16Pseudo:
975    case ARM::VLD2q32Pseudo:
976    case ARM::VLD2d8Pseudo_UPD:
977    case ARM::VLD2d16Pseudo_UPD:
978    case ARM::VLD2d32Pseudo_UPD:
979    case ARM::VLD2q8Pseudo_UPD:
980    case ARM::VLD2q16Pseudo_UPD:
981    case ARM::VLD2q32Pseudo_UPD:
982    case ARM::VLD3d8Pseudo:
983    case ARM::VLD3d16Pseudo:
984    case ARM::VLD3d32Pseudo:
985    case ARM::VLD1d64TPseudo:
986    case ARM::VLD3d8Pseudo_UPD:
987    case ARM::VLD3d16Pseudo_UPD:
988    case ARM::VLD3d32Pseudo_UPD:
989    case ARM::VLD1d64TPseudo_UPD:
990    case ARM::VLD3q8Pseudo_UPD:
991    case ARM::VLD3q16Pseudo_UPD:
992    case ARM::VLD3q32Pseudo_UPD:
993    case ARM::VLD3q8oddPseudo_UPD:
994    case ARM::VLD3q16oddPseudo_UPD:
995    case ARM::VLD3q32oddPseudo_UPD:
996    case ARM::VLD4d8Pseudo:
997    case ARM::VLD4d16Pseudo:
998    case ARM::VLD4d32Pseudo:
999    case ARM::VLD1d64QPseudo:
1000    case ARM::VLD4d8Pseudo_UPD:
1001    case ARM::VLD4d16Pseudo_UPD:
1002    case ARM::VLD4d32Pseudo_UPD:
1003    case ARM::VLD1d64QPseudo_UPD:
1004    case ARM::VLD4q8Pseudo_UPD:
1005    case ARM::VLD4q16Pseudo_UPD:
1006    case ARM::VLD4q32Pseudo_UPD:
1007    case ARM::VLD4q8oddPseudo_UPD:
1008    case ARM::VLD4q16oddPseudo_UPD:
1009    case ARM::VLD4q32oddPseudo_UPD:
1010    case ARM::VLD1DUPq8Pseudo:
1011    case ARM::VLD1DUPq16Pseudo:
1012    case ARM::VLD1DUPq32Pseudo:
1013    case ARM::VLD1DUPq8Pseudo_UPD:
1014    case ARM::VLD1DUPq16Pseudo_UPD:
1015    case ARM::VLD1DUPq32Pseudo_UPD:
1016    case ARM::VLD2DUPd8Pseudo:
1017    case ARM::VLD2DUPd16Pseudo:
1018    case ARM::VLD2DUPd32Pseudo:
1019    case ARM::VLD2DUPd8Pseudo_UPD:
1020    case ARM::VLD2DUPd16Pseudo_UPD:
1021    case ARM::VLD2DUPd32Pseudo_UPD:
1022    case ARM::VLD3DUPd8Pseudo:
1023    case ARM::VLD3DUPd16Pseudo:
1024    case ARM::VLD3DUPd32Pseudo:
1025    case ARM::VLD3DUPd8Pseudo_UPD:
1026    case ARM::VLD3DUPd16Pseudo_UPD:
1027    case ARM::VLD3DUPd32Pseudo_UPD:
1028    case ARM::VLD4DUPd8Pseudo:
1029    case ARM::VLD4DUPd16Pseudo:
1030    case ARM::VLD4DUPd32Pseudo:
1031    case ARM::VLD4DUPd8Pseudo_UPD:
1032    case ARM::VLD4DUPd16Pseudo_UPD:
1033    case ARM::VLD4DUPd32Pseudo_UPD:
1034      ExpandVLD(MBBI);
1035      break;
1036
1037    case ARM::VST1q8Pseudo:
1038    case ARM::VST1q16Pseudo:
1039    case ARM::VST1q32Pseudo:
1040    case ARM::VST1q64Pseudo:
1041    case ARM::VST1q8Pseudo_UPD:
1042    case ARM::VST1q16Pseudo_UPD:
1043    case ARM::VST1q32Pseudo_UPD:
1044    case ARM::VST1q64Pseudo_UPD:
1045    case ARM::VST2d8Pseudo:
1046    case ARM::VST2d16Pseudo:
1047    case ARM::VST2d32Pseudo:
1048    case ARM::VST2q8Pseudo:
1049    case ARM::VST2q16Pseudo:
1050    case ARM::VST2q32Pseudo:
1051    case ARM::VST2d8Pseudo_UPD:
1052    case ARM::VST2d16Pseudo_UPD:
1053    case ARM::VST2d32Pseudo_UPD:
1054    case ARM::VST2q8Pseudo_UPD:
1055    case ARM::VST2q16Pseudo_UPD:
1056    case ARM::VST2q32Pseudo_UPD:
1057    case ARM::VST3d8Pseudo:
1058    case ARM::VST3d16Pseudo:
1059    case ARM::VST3d32Pseudo:
1060    case ARM::VST1d64TPseudo:
1061    case ARM::VST3d8Pseudo_UPD:
1062    case ARM::VST3d16Pseudo_UPD:
1063    case ARM::VST3d32Pseudo_UPD:
1064    case ARM::VST1d64TPseudo_UPD:
1065    case ARM::VST3q8Pseudo_UPD:
1066    case ARM::VST3q16Pseudo_UPD:
1067    case ARM::VST3q32Pseudo_UPD:
1068    case ARM::VST3q8oddPseudo_UPD:
1069    case ARM::VST3q16oddPseudo_UPD:
1070    case ARM::VST3q32oddPseudo_UPD:
1071    case ARM::VST4d8Pseudo:
1072    case ARM::VST4d16Pseudo:
1073    case ARM::VST4d32Pseudo:
1074    case ARM::VST1d64QPseudo:
1075    case ARM::VST4d8Pseudo_UPD:
1076    case ARM::VST4d16Pseudo_UPD:
1077    case ARM::VST4d32Pseudo_UPD:
1078    case ARM::VST1d64QPseudo_UPD:
1079    case ARM::VST4q8Pseudo_UPD:
1080    case ARM::VST4q16Pseudo_UPD:
1081    case ARM::VST4q32Pseudo_UPD:
1082    case ARM::VST4q8oddPseudo_UPD:
1083    case ARM::VST4q16oddPseudo_UPD:
1084    case ARM::VST4q32oddPseudo_UPD:
1085      ExpandVST(MBBI);
1086      break;
1087
1088    case ARM::VLD1LNq8Pseudo:
1089    case ARM::VLD1LNq16Pseudo:
1090    case ARM::VLD1LNq32Pseudo:
1091    case ARM::VLD1LNq8Pseudo_UPD:
1092    case ARM::VLD1LNq16Pseudo_UPD:
1093    case ARM::VLD1LNq32Pseudo_UPD:
1094    case ARM::VLD2LNd8Pseudo:
1095    case ARM::VLD2LNd16Pseudo:
1096    case ARM::VLD2LNd32Pseudo:
1097    case ARM::VLD2LNq16Pseudo:
1098    case ARM::VLD2LNq32Pseudo:
1099    case ARM::VLD2LNd8Pseudo_UPD:
1100    case ARM::VLD2LNd16Pseudo_UPD:
1101    case ARM::VLD2LNd32Pseudo_UPD:
1102    case ARM::VLD2LNq16Pseudo_UPD:
1103    case ARM::VLD2LNq32Pseudo_UPD:
1104    case ARM::VLD3LNd8Pseudo:
1105    case ARM::VLD3LNd16Pseudo:
1106    case ARM::VLD3LNd32Pseudo:
1107    case ARM::VLD3LNq16Pseudo:
1108    case ARM::VLD3LNq32Pseudo:
1109    case ARM::VLD3LNd8Pseudo_UPD:
1110    case ARM::VLD3LNd16Pseudo_UPD:
1111    case ARM::VLD3LNd32Pseudo_UPD:
1112    case ARM::VLD3LNq16Pseudo_UPD:
1113    case ARM::VLD3LNq32Pseudo_UPD:
1114    case ARM::VLD4LNd8Pseudo:
1115    case ARM::VLD4LNd16Pseudo:
1116    case ARM::VLD4LNd32Pseudo:
1117    case ARM::VLD4LNq16Pseudo:
1118    case ARM::VLD4LNq32Pseudo:
1119    case ARM::VLD4LNd8Pseudo_UPD:
1120    case ARM::VLD4LNd16Pseudo_UPD:
1121    case ARM::VLD4LNd32Pseudo_UPD:
1122    case ARM::VLD4LNq16Pseudo_UPD:
1123    case ARM::VLD4LNq32Pseudo_UPD:
1124    case ARM::VST1LNq8Pseudo:
1125    case ARM::VST1LNq16Pseudo:
1126    case ARM::VST1LNq32Pseudo:
1127    case ARM::VST1LNq8Pseudo_UPD:
1128    case ARM::VST1LNq16Pseudo_UPD:
1129    case ARM::VST1LNq32Pseudo_UPD:
1130    case ARM::VST2LNd8Pseudo:
1131    case ARM::VST2LNd16Pseudo:
1132    case ARM::VST2LNd32Pseudo:
1133    case ARM::VST2LNq16Pseudo:
1134    case ARM::VST2LNq32Pseudo:
1135    case ARM::VST2LNd8Pseudo_UPD:
1136    case ARM::VST2LNd16Pseudo_UPD:
1137    case ARM::VST2LNd32Pseudo_UPD:
1138    case ARM::VST2LNq16Pseudo_UPD:
1139    case ARM::VST2LNq32Pseudo_UPD:
1140    case ARM::VST3LNd8Pseudo:
1141    case ARM::VST3LNd16Pseudo:
1142    case ARM::VST3LNd32Pseudo:
1143    case ARM::VST3LNq16Pseudo:
1144    case ARM::VST3LNq32Pseudo:
1145    case ARM::VST3LNd8Pseudo_UPD:
1146    case ARM::VST3LNd16Pseudo_UPD:
1147    case ARM::VST3LNd32Pseudo_UPD:
1148    case ARM::VST3LNq16Pseudo_UPD:
1149    case ARM::VST3LNq32Pseudo_UPD:
1150    case ARM::VST4LNd8Pseudo:
1151    case ARM::VST4LNd16Pseudo:
1152    case ARM::VST4LNd32Pseudo:
1153    case ARM::VST4LNq16Pseudo:
1154    case ARM::VST4LNq32Pseudo:
1155    case ARM::VST4LNd8Pseudo_UPD:
1156    case ARM::VST4LNd16Pseudo_UPD:
1157    case ARM::VST4LNd32Pseudo_UPD:
1158    case ARM::VST4LNq16Pseudo_UPD:
1159    case ARM::VST4LNq32Pseudo_UPD:
1160      ExpandLaneOp(MBBI);
1161      break;
1162
1163    case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
1164    case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
1165    case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
1166    case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
1167    case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
1168    case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
1169    }
1170
1171    if (ModifiedOp)
1172      Modified = true;
1173    MBBI = NMBBI;
1174  }
1175
1176  return Modified;
1177}
1178
1179bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1180  TII = static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1181  TRI = MF.getTarget().getRegisterInfo();
1182  STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
1183
1184  bool Modified = false;
1185  for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1186       ++MFI)
1187    Modified |= ExpandMBB(*MFI);
1188  return Modified;
1189}
1190
1191/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1192/// expansion pass.
1193FunctionPass *llvm::createARMExpandPseudoPass() {
1194  return new ARMExpandPseudo();
1195}
1196