1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the ARM target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "arm-isel" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMTargetMachine.h" 18#include "MCTargetDesc/ARMAddressingModes.h" 19#include "llvm/CallingConv.h" 20#include "llvm/Constants.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/Intrinsics.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/SelectionDAG.h" 29#include "llvm/CodeGen/SelectionDAGISel.h" 30#include "llvm/Target/TargetLowering.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Compiler.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37 38using namespace llvm; 39 40static cl::opt<bool> 41DisableShifterOp("disable-shifter-op", cl::Hidden, 42 cl::desc("Disable isel of shifter-op"), 43 cl::init(false)); 44 45static cl::opt<bool> 46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden, 47 cl::desc("Check fp vmla / vmls hazard at isel time"), 48 cl::init(true)); 49 50//===--------------------------------------------------------------------===// 51/// ARMDAGToDAGISel - ARM specific code to select ARM machine 52/// instructions for SelectionDAG operations. 53/// 54namespace { 55 56enum AddrMode2Type { 57 AM2_BASE, // Simple AM2 (+-imm12) 58 AM2_SHOP // Shifter-op AM2 59}; 60 61class ARMDAGToDAGISel : public SelectionDAGISel { 62 ARMBaseTargetMachine &TM; 63 const ARMBaseInstrInfo *TII; 64 65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 66 /// make the right decision when generating code for different targets. 67 const ARMSubtarget *Subtarget; 68 69public: 70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, 71 CodeGenOpt::Level OptLevel) 72 : SelectionDAGISel(tm, OptLevel), TM(tm), 73 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())), 74 Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 75 } 76 77 virtual const char *getPassName() const { 78 return "ARM Instruction Selection"; 79 } 80 81 /// getI32Imm - Return a target constant of type i32 with the specified 82 /// value. 83 inline SDValue getI32Imm(unsigned Imm) { 84 return CurDAG->getTargetConstant(Imm, MVT::i32); 85 } 86 87 SDNode *Select(SDNode *N); 88 89 90 bool hasNoVMLxHazardUse(SDNode *N) const; 91 bool isShifterOpProfitable(const SDValue &Shift, 92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt); 93 bool SelectRegShifterOperand(SDValue N, SDValue &A, 94 SDValue &B, SDValue &C, 95 bool CheckProfitability = true); 96 bool SelectImmShifterOperand(SDValue N, SDValue &A, 97 SDValue &B, bool CheckProfitability = true); 98 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A, 99 SDValue &B, SDValue &C) { 100 // Don't apply the profitability check 101 return SelectRegShifterOperand(N, A, B, C, false); 102 } 103 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A, 104 SDValue &B) { 105 // Don't apply the profitability check 106 return SelectImmShifterOperand(N, A, B, false); 107 } 108 109 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm); 110 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); 111 112 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base, 113 SDValue &Offset, SDValue &Opc); 114 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset, 115 SDValue &Opc) { 116 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; 117 } 118 119 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset, 120 SDValue &Opc) { 121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; 122 } 123 124 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset, 125 SDValue &Opc) { 126 SelectAddrMode2Worker(N, Base, Offset, Opc); 127// return SelectAddrMode2ShOp(N, Base, Offset, Opc); 128 // This always matches one way or another. 129 return true; 130 } 131 132 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, 133 SDValue &Offset, SDValue &Opc); 134 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, 135 SDValue &Offset, SDValue &Opc); 136 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, 137 SDValue &Offset, SDValue &Opc); 138 bool SelectAddrOffsetNone(SDValue N, SDValue &Base); 139 bool SelectAddrMode3(SDValue N, SDValue &Base, 140 SDValue &Offset, SDValue &Opc); 141 bool SelectAddrMode3Offset(SDNode *Op, SDValue N, 142 SDValue &Offset, SDValue &Opc); 143 bool SelectAddrMode5(SDValue N, SDValue &Base, 144 SDValue &Offset); 145 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align); 146 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset); 147 148 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label); 149 150 // Thumb Addressing Modes: 151 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset); 152 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset, 153 unsigned Scale); 154 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset); 155 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset); 156 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset); 157 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base, 158 SDValue &OffImm); 159 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base, 160 SDValue &OffImm); 161 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base, 162 SDValue &OffImm); 163 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base, 164 SDValue &OffImm); 165 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm); 166 167 // Thumb 2 Addressing Modes: 168 bool SelectT2ShifterOperandReg(SDValue N, 169 SDValue &BaseReg, SDValue &Opc); 170 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm); 171 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base, 172 SDValue &OffImm); 173 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 174 SDValue &OffImm); 175 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base, 176 SDValue &OffReg, SDValue &ShImm); 177 178 inline bool is_so_imm(unsigned Imm) const { 179 return ARM_AM::getSOImmVal(Imm) != -1; 180 } 181 182 inline bool is_so_imm_not(unsigned Imm) const { 183 return ARM_AM::getSOImmVal(~Imm) != -1; 184 } 185 186 inline bool is_t2_so_imm(unsigned Imm) const { 187 return ARM_AM::getT2SOImmVal(Imm) != -1; 188 } 189 190 inline bool is_t2_so_imm_not(unsigned Imm) const { 191 return ARM_AM::getT2SOImmVal(~Imm) != -1; 192 } 193 194 // Include the pieces autogenerated from the target description. 195#include "ARMGenDAGISel.inc" 196 197private: 198 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for 199 /// ARM. 200 SDNode *SelectARMIndexedLoad(SDNode *N); 201 SDNode *SelectT2IndexedLoad(SDNode *N); 202 203 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 204 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for 205 /// loads of D registers and even subregs and odd subregs of Q registers. 206 /// For NumVecs <= 2, QOpcodes1 is not used. 207 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, 208 const uint16_t *DOpcodes, 209 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1); 210 211 /// SelectVST - Select NEON store intrinsics. NumVecs should 212 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for 213 /// stores of D registers and even subregs and odd subregs of Q registers. 214 /// For NumVecs <= 2, QOpcodes1 is not used. 215 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, 216 const uint16_t *DOpcodes, 217 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1); 218 219 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 220 /// be 2, 3 or 4. The opcode arrays specify the instructions used for 221 /// load/store of D registers and Q registers. 222 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, 223 bool isUpdating, unsigned NumVecs, 224 const uint16_t *DOpcodes, const uint16_t *QOpcodes); 225 226 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs 227 /// should be 2, 3 or 4. The opcode array specifies the instructions used 228 /// for loading D registers. (Q registers are not supported.) 229 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, 230 const uint16_t *Opcodes); 231 232 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2, 233 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be 234 /// generated to force the table registers to be consecutive. 235 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc); 236 237 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM. 238 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned); 239 240 /// SelectCMOVOp - Select CMOV instructions for ARM. 241 SDNode *SelectCMOVOp(SDNode *N); 242 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 243 ARMCC::CondCodes CCVal, SDValue CCR, 244 SDValue InFlag); 245 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 246 ARMCC::CondCodes CCVal, SDValue CCR, 247 SDValue InFlag); 248 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 249 ARMCC::CondCodes CCVal, SDValue CCR, 250 SDValue InFlag); 251 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 252 ARMCC::CondCodes CCVal, SDValue CCR, 253 SDValue InFlag); 254 255 // Select special operations if node forms integer ABS pattern 256 SDNode *SelectABSOp(SDNode *N); 257 258 SDNode *SelectConcatVector(SDNode *N); 259 260 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 261 262 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 263 /// inline asm expressions. 264 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 265 char ConstraintCode, 266 std::vector<SDValue> &OutOps); 267 268 // Form pairs of consecutive S, D, or Q registers. 269 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1); 270 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1); 271 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1); 272 273 // Form sequences of 4 consecutive S, D, or Q registers. 274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 277 278 // Get the alignment operand for a NEON VLD or VST instruction. 279 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector); 280}; 281} 282 283/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 284/// operand. If so Imm will receive the 32-bit value. 285static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 286 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 287 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 288 return true; 289 } 290 return false; 291} 292 293// isInt32Immediate - This method tests to see if a constant operand. 294// If so Imm will receive the 32 bit value. 295static bool isInt32Immediate(SDValue N, unsigned &Imm) { 296 return isInt32Immediate(N.getNode(), Imm); 297} 298 299// isOpcWithIntImmediate - This method tests to see if the node is a specific 300// opcode and that it has a immediate integer right operand. 301// If so Imm will receive the 32 bit value. 302static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 303 return N->getOpcode() == Opc && 304 isInt32Immediate(N->getOperand(1).getNode(), Imm); 305} 306 307/// \brief Check whether a particular node is a constant value representable as 308/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax). 309/// 310/// \param ScaledConstant [out] - On success, the pre-scaled constant value. 311static bool isScaledConstantInRange(SDValue Node, int Scale, 312 int RangeMin, int RangeMax, 313 int &ScaledConstant) { 314 assert(Scale > 0 && "Invalid scale!"); 315 316 // Check that this is a constant. 317 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node); 318 if (!C) 319 return false; 320 321 ScaledConstant = (int) C->getZExtValue(); 322 if ((ScaledConstant % Scale) != 0) 323 return false; 324 325 ScaledConstant /= Scale; 326 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax; 327} 328 329/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS 330/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at 331/// least on current ARM implementations) which should be avoidded. 332bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const { 333 if (OptLevel == CodeGenOpt::None) 334 return true; 335 336 if (!CheckVMLxHazard) 337 return true; 338 339 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9()) 340 return true; 341 342 if (!N->hasOneUse()) 343 return false; 344 345 SDNode *Use = *N->use_begin(); 346 if (Use->getOpcode() == ISD::CopyToReg) 347 return true; 348 if (Use->isMachineOpcode()) { 349 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode()); 350 if (MCID.mayStore()) 351 return true; 352 unsigned Opcode = MCID.getOpcode(); 353 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) 354 return true; 355 // vmlx feeding into another vmlx. We actually want to unfold 356 // the use later in the MLxExpansion pass. e.g. 357 // vmla 358 // vmla (stall 8 cycles) 359 // 360 // vmul (5 cycles) 361 // vadd (5 cycles) 362 // vmla 363 // This adds up to about 18 - 19 cycles. 364 // 365 // vmla 366 // vmul (stall 4 cycles) 367 // vadd adds up to about 14 cycles. 368 return TII->isFpMLxInstruction(Opcode); 369 } 370 371 return false; 372} 373 374bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift, 375 ARM_AM::ShiftOpc ShOpcVal, 376 unsigned ShAmt) { 377 if (!Subtarget->isCortexA9()) 378 return true; 379 if (Shift.hasOneUse()) 380 return true; 381 // R << 2 is free. 382 return ShOpcVal == ARM_AM::lsl && ShAmt == 2; 383} 384 385bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N, 386 SDValue &BaseReg, 387 SDValue &Opc, 388 bool CheckProfitability) { 389 if (DisableShifterOp) 390 return false; 391 392 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); 393 394 // Don't match base register only case. That is matched to a separate 395 // lower complexity pattern with explicit register operand. 396 if (ShOpcVal == ARM_AM::no_shift) return false; 397 398 BaseReg = N.getOperand(0); 399 unsigned ShImmVal = 0; 400 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)); 401 if (!RHS) return false; 402 ShImmVal = RHS->getZExtValue() & 31; 403 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), 404 MVT::i32); 405 return true; 406} 407 408bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N, 409 SDValue &BaseReg, 410 SDValue &ShReg, 411 SDValue &Opc, 412 bool CheckProfitability) { 413 if (DisableShifterOp) 414 return false; 415 416 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); 417 418 // Don't match base register only case. That is matched to a separate 419 // lower complexity pattern with explicit register operand. 420 if (ShOpcVal == ARM_AM::no_shift) return false; 421 422 BaseReg = N.getOperand(0); 423 unsigned ShImmVal = 0; 424 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)); 425 if (RHS) return false; 426 427 ShReg = N.getOperand(1); 428 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal)) 429 return false; 430 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), 431 MVT::i32); 432 return true; 433} 434 435 436bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N, 437 SDValue &Base, 438 SDValue &OffImm) { 439 // Match simple R + imm12 operands. 440 441 // Base only. 442 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 443 !CurDAG->isBaseWithConstantOffset(N)) { 444 if (N.getOpcode() == ISD::FrameIndex) { 445 // Match frame index. 446 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 447 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 448 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 449 return true; 450 } 451 452 if (N.getOpcode() == ARMISD::Wrapper && 453 !(Subtarget->useMovt() && 454 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 455 Base = N.getOperand(0); 456 } else 457 Base = N; 458 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 459 return true; 460 } 461 462 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 463 int RHSC = (int)RHS->getZExtValue(); 464 if (N.getOpcode() == ISD::SUB) 465 RHSC = -RHSC; 466 467 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned) 468 Base = N.getOperand(0); 469 if (Base.getOpcode() == ISD::FrameIndex) { 470 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 471 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 472 } 473 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 474 return true; 475 } 476 } 477 478 // Base only. 479 Base = N; 480 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 481 return true; 482} 483 484 485 486bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, 487 SDValue &Opc) { 488 if (N.getOpcode() == ISD::MUL && 489 (!Subtarget->isCortexA9() || N.hasOneUse())) { 490 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 491 // X * [3,5,9] -> X + X * [2,4,8] etc. 492 int RHSC = (int)RHS->getZExtValue(); 493 if (RHSC & 1) { 494 RHSC = RHSC & ~1; 495 ARM_AM::AddrOpc AddSub = ARM_AM::add; 496 if (RHSC < 0) { 497 AddSub = ARM_AM::sub; 498 RHSC = - RHSC; 499 } 500 if (isPowerOf2_32(RHSC)) { 501 unsigned ShAmt = Log2_32(RHSC); 502 Base = Offset = N.getOperand(0); 503 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, 504 ARM_AM::lsl), 505 MVT::i32); 506 return true; 507 } 508 } 509 } 510 } 511 512 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 513 // ISD::OR that is equivalent to an ISD::ADD. 514 !CurDAG->isBaseWithConstantOffset(N)) 515 return false; 516 517 // Leave simple R +/- imm12 operands for LDRi12 518 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) { 519 int RHSC; 520 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1, 521 -0x1000+1, 0x1000, RHSC)) // 12 bits. 522 return false; 523 } 524 525 // Otherwise this is R +/- [possibly shifted] R. 526 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add; 527 ARM_AM::ShiftOpc ShOpcVal = 528 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode()); 529 unsigned ShAmt = 0; 530 531 Base = N.getOperand(0); 532 Offset = N.getOperand(1); 533 534 if (ShOpcVal != ARM_AM::no_shift) { 535 // Check to see if the RHS of the shift is a constant, if not, we can't fold 536 // it. 537 if (ConstantSDNode *Sh = 538 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) { 539 ShAmt = Sh->getZExtValue(); 540 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt)) 541 Offset = N.getOperand(1).getOperand(0); 542 else { 543 ShAmt = 0; 544 ShOpcVal = ARM_AM::no_shift; 545 } 546 } else { 547 ShOpcVal = ARM_AM::no_shift; 548 } 549 } 550 551 // Try matching (R shl C) + (R). 552 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && 553 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) { 554 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode()); 555 if (ShOpcVal != ARM_AM::no_shift) { 556 // Check to see if the RHS of the shift is a constant, if not, we can't 557 // fold it. 558 if (ConstantSDNode *Sh = 559 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) { 560 ShAmt = Sh->getZExtValue(); 561 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) { 562 Offset = N.getOperand(0).getOperand(0); 563 Base = N.getOperand(1); 564 } else { 565 ShAmt = 0; 566 ShOpcVal = ARM_AM::no_shift; 567 } 568 } else { 569 ShOpcVal = ARM_AM::no_shift; 570 } 571 } 572 } 573 574 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 575 MVT::i32); 576 return true; 577} 578 579 580//----- 581 582AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N, 583 SDValue &Base, 584 SDValue &Offset, 585 SDValue &Opc) { 586 if (N.getOpcode() == ISD::MUL && 587 (!Subtarget->isCortexA9() || N.hasOneUse())) { 588 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 589 // X * [3,5,9] -> X + X * [2,4,8] etc. 590 int RHSC = (int)RHS->getZExtValue(); 591 if (RHSC & 1) { 592 RHSC = RHSC & ~1; 593 ARM_AM::AddrOpc AddSub = ARM_AM::add; 594 if (RHSC < 0) { 595 AddSub = ARM_AM::sub; 596 RHSC = - RHSC; 597 } 598 if (isPowerOf2_32(RHSC)) { 599 unsigned ShAmt = Log2_32(RHSC); 600 Base = Offset = N.getOperand(0); 601 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, 602 ARM_AM::lsl), 603 MVT::i32); 604 return AM2_SHOP; 605 } 606 } 607 } 608 } 609 610 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 611 // ISD::OR that is equivalent to an ADD. 612 !CurDAG->isBaseWithConstantOffset(N)) { 613 Base = N; 614 if (N.getOpcode() == ISD::FrameIndex) { 615 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 616 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 617 } else if (N.getOpcode() == ARMISD::Wrapper && 618 !(Subtarget->useMovt() && 619 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 620 Base = N.getOperand(0); 621 } 622 Offset = CurDAG->getRegister(0, MVT::i32); 623 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, 624 ARM_AM::no_shift), 625 MVT::i32); 626 return AM2_BASE; 627 } 628 629 // Match simple R +/- imm12 operands. 630 if (N.getOpcode() != ISD::SUB) { 631 int RHSC; 632 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1, 633 -0x1000+1, 0x1000, RHSC)) { // 12 bits. 634 Base = N.getOperand(0); 635 if (Base.getOpcode() == ISD::FrameIndex) { 636 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 637 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 638 } 639 Offset = CurDAG->getRegister(0, MVT::i32); 640 641 ARM_AM::AddrOpc AddSub = ARM_AM::add; 642 if (RHSC < 0) { 643 AddSub = ARM_AM::sub; 644 RHSC = - RHSC; 645 } 646 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, 647 ARM_AM::no_shift), 648 MVT::i32); 649 return AM2_BASE; 650 } 651 } 652 653 if (Subtarget->isCortexA9() && !N.hasOneUse()) { 654 // Compute R +/- (R << N) and reuse it. 655 Base = N; 656 Offset = CurDAG->getRegister(0, MVT::i32); 657 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, 658 ARM_AM::no_shift), 659 MVT::i32); 660 return AM2_BASE; 661 } 662 663 // Otherwise this is R +/- [possibly shifted] R. 664 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub; 665 ARM_AM::ShiftOpc ShOpcVal = 666 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode()); 667 unsigned ShAmt = 0; 668 669 Base = N.getOperand(0); 670 Offset = N.getOperand(1); 671 672 if (ShOpcVal != ARM_AM::no_shift) { 673 // Check to see if the RHS of the shift is a constant, if not, we can't fold 674 // it. 675 if (ConstantSDNode *Sh = 676 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) { 677 ShAmt = Sh->getZExtValue(); 678 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt)) 679 Offset = N.getOperand(1).getOperand(0); 680 else { 681 ShAmt = 0; 682 ShOpcVal = ARM_AM::no_shift; 683 } 684 } else { 685 ShOpcVal = ARM_AM::no_shift; 686 } 687 } 688 689 // Try matching (R shl C) + (R). 690 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && 691 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) { 692 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode()); 693 if (ShOpcVal != ARM_AM::no_shift) { 694 // Check to see if the RHS of the shift is a constant, if not, we can't 695 // fold it. 696 if (ConstantSDNode *Sh = 697 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) { 698 ShAmt = Sh->getZExtValue(); 699 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) { 700 Offset = N.getOperand(0).getOperand(0); 701 Base = N.getOperand(1); 702 } else { 703 ShAmt = 0; 704 ShOpcVal = ARM_AM::no_shift; 705 } 706 } else { 707 ShOpcVal = ARM_AM::no_shift; 708 } 709 } 710 } 711 712 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 713 MVT::i32); 714 return AM2_SHOP; 715} 716 717bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, 718 SDValue &Offset, SDValue &Opc) { 719 unsigned Opcode = Op->getOpcode(); 720 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 721 ? cast<LoadSDNode>(Op)->getAddressingMode() 722 : cast<StoreSDNode>(Op)->getAddressingMode(); 723 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 724 ? ARM_AM::add : ARM_AM::sub; 725 int Val; 726 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) 727 return false; 728 729 Offset = N; 730 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); 731 unsigned ShAmt = 0; 732 if (ShOpcVal != ARM_AM::no_shift) { 733 // Check to see if the RHS of the shift is a constant, if not, we can't fold 734 // it. 735 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 736 ShAmt = Sh->getZExtValue(); 737 if (isShifterOpProfitable(N, ShOpcVal, ShAmt)) 738 Offset = N.getOperand(0); 739 else { 740 ShAmt = 0; 741 ShOpcVal = ARM_AM::no_shift; 742 } 743 } else { 744 ShOpcVal = ARM_AM::no_shift; 745 } 746 } 747 748 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 749 MVT::i32); 750 return true; 751} 752 753bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, 754 SDValue &Offset, SDValue &Opc) { 755 unsigned Opcode = Op->getOpcode(); 756 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 757 ? cast<LoadSDNode>(Op)->getAddressingMode() 758 : cast<StoreSDNode>(Op)->getAddressingMode(); 759 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 760 ? ARM_AM::add : ARM_AM::sub; 761 int Val; 762 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits. 763 if (AddSub == ARM_AM::sub) Val *= -1; 764 Offset = CurDAG->getRegister(0, MVT::i32); 765 Opc = CurDAG->getTargetConstant(Val, MVT::i32); 766 return true; 767 } 768 769 return false; 770} 771 772 773bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, 774 SDValue &Offset, SDValue &Opc) { 775 unsigned Opcode = Op->getOpcode(); 776 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 777 ? cast<LoadSDNode>(Op)->getAddressingMode() 778 : cast<StoreSDNode>(Op)->getAddressingMode(); 779 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 780 ? ARM_AM::add : ARM_AM::sub; 781 int Val; 782 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits. 783 Offset = CurDAG->getRegister(0, MVT::i32); 784 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, 785 ARM_AM::no_shift), 786 MVT::i32); 787 return true; 788 } 789 790 return false; 791} 792 793bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) { 794 Base = N; 795 return true; 796} 797 798bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N, 799 SDValue &Base, SDValue &Offset, 800 SDValue &Opc) { 801 if (N.getOpcode() == ISD::SUB) { 802 // X - C is canonicalize to X + -C, no need to handle it here. 803 Base = N.getOperand(0); 804 Offset = N.getOperand(1); 805 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32); 806 return true; 807 } 808 809 if (!CurDAG->isBaseWithConstantOffset(N)) { 810 Base = N; 811 if (N.getOpcode() == ISD::FrameIndex) { 812 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 813 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 814 } 815 Offset = CurDAG->getRegister(0, MVT::i32); 816 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32); 817 return true; 818 } 819 820 // If the RHS is +/- imm8, fold into addr mode. 821 int RHSC; 822 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1, 823 -256 + 1, 256, RHSC)) { // 8 bits. 824 Base = N.getOperand(0); 825 if (Base.getOpcode() == ISD::FrameIndex) { 826 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 827 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 828 } 829 Offset = CurDAG->getRegister(0, MVT::i32); 830 831 ARM_AM::AddrOpc AddSub = ARM_AM::add; 832 if (RHSC < 0) { 833 AddSub = ARM_AM::sub; 834 RHSC = -RHSC; 835 } 836 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32); 837 return true; 838 } 839 840 Base = N.getOperand(0); 841 Offset = N.getOperand(1); 842 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32); 843 return true; 844} 845 846bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N, 847 SDValue &Offset, SDValue &Opc) { 848 unsigned Opcode = Op->getOpcode(); 849 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 850 ? cast<LoadSDNode>(Op)->getAddressingMode() 851 : cast<StoreSDNode>(Op)->getAddressingMode(); 852 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 853 ? ARM_AM::add : ARM_AM::sub; 854 int Val; 855 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits. 856 Offset = CurDAG->getRegister(0, MVT::i32); 857 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32); 858 return true; 859 } 860 861 Offset = N; 862 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32); 863 return true; 864} 865 866bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N, 867 SDValue &Base, SDValue &Offset) { 868 if (!CurDAG->isBaseWithConstantOffset(N)) { 869 Base = N; 870 if (N.getOpcode() == ISD::FrameIndex) { 871 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 872 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 873 } else if (N.getOpcode() == ARMISD::Wrapper && 874 !(Subtarget->useMovt() && 875 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 876 Base = N.getOperand(0); 877 } 878 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 879 MVT::i32); 880 return true; 881 } 882 883 // If the RHS is +/- imm8, fold into addr mode. 884 int RHSC; 885 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 886 -256 + 1, 256, RHSC)) { 887 Base = N.getOperand(0); 888 if (Base.getOpcode() == ISD::FrameIndex) { 889 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 890 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 891 } 892 893 ARM_AM::AddrOpc AddSub = ARM_AM::add; 894 if (RHSC < 0) { 895 AddSub = ARM_AM::sub; 896 RHSC = -RHSC; 897 } 898 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC), 899 MVT::i32); 900 return true; 901 } 902 903 Base = N; 904 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 905 MVT::i32); 906 return true; 907} 908 909bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr, 910 SDValue &Align) { 911 Addr = N; 912 913 unsigned Alignment = 0; 914 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) { 915 // This case occurs only for VLD1-lane/dup and VST1-lane instructions. 916 // The maximum alignment is equal to the memory size being referenced. 917 unsigned LSNAlign = LSN->getAlignment(); 918 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8; 919 if (LSNAlign >= MemSize && MemSize > 1) 920 Alignment = MemSize; 921 } else { 922 // All other uses of addrmode6 are for intrinsics. For now just record 923 // the raw alignment value; it will be refined later based on the legal 924 // alignment operands for the intrinsic. 925 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment(); 926 } 927 928 Align = CurDAG->getTargetConstant(Alignment, MVT::i32); 929 return true; 930} 931 932bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N, 933 SDValue &Offset) { 934 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); 935 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); 936 if (AM != ISD::POST_INC) 937 return false; 938 Offset = N; 939 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) { 940 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits()) 941 Offset = CurDAG->getRegister(0, MVT::i32); 942 } 943 return true; 944} 945 946bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N, 947 SDValue &Offset, SDValue &Label) { 948 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) { 949 Offset = N.getOperand(0); 950 SDValue N1 = N.getOperand(1); 951 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(), 952 MVT::i32); 953 return true; 954 } 955 956 return false; 957} 958 959 960//===----------------------------------------------------------------------===// 961// Thumb Addressing Modes 962//===----------------------------------------------------------------------===// 963 964bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N, 965 SDValue &Base, SDValue &Offset){ 966 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) { 967 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N); 968 if (!NC || !NC->isNullValue()) 969 return false; 970 971 Base = Offset = N; 972 return true; 973 } 974 975 Base = N.getOperand(0); 976 Offset = N.getOperand(1); 977 return true; 978} 979 980bool 981ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base, 982 SDValue &Offset, unsigned Scale) { 983 if (Scale == 4) { 984 SDValue TmpBase, TmpOffImm; 985 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm)) 986 return false; // We want to select tLDRspi / tSTRspi instead. 987 988 if (N.getOpcode() == ARMISD::Wrapper && 989 N.getOperand(0).getOpcode() == ISD::TargetConstantPool) 990 return false; // We want to select tLDRpci instead. 991 } 992 993 if (!CurDAG->isBaseWithConstantOffset(N)) 994 return false; 995 996 // Thumb does not have [sp, r] address mode. 997 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 998 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); 999 if ((LHSR && LHSR->getReg() == ARM::SP) || 1000 (RHSR && RHSR->getReg() == ARM::SP)) 1001 return false; 1002 1003 // FIXME: Why do we explicitly check for a match here and then return false? 1004 // Presumably to allow something else to match, but shouldn't this be 1005 // documented? 1006 int RHSC; 1007 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) 1008 return false; 1009 1010 Base = N.getOperand(0); 1011 Offset = N.getOperand(1); 1012 return true; 1013} 1014 1015bool 1016ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N, 1017 SDValue &Base, 1018 SDValue &Offset) { 1019 return SelectThumbAddrModeRI(N, Base, Offset, 1); 1020} 1021 1022bool 1023ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N, 1024 SDValue &Base, 1025 SDValue &Offset) { 1026 return SelectThumbAddrModeRI(N, Base, Offset, 2); 1027} 1028 1029bool 1030ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N, 1031 SDValue &Base, 1032 SDValue &Offset) { 1033 return SelectThumbAddrModeRI(N, Base, Offset, 4); 1034} 1035 1036bool 1037ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, 1038 SDValue &Base, SDValue &OffImm) { 1039 if (Scale == 4) { 1040 SDValue TmpBase, TmpOffImm; 1041 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm)) 1042 return false; // We want to select tLDRspi / tSTRspi instead. 1043 1044 if (N.getOpcode() == ARMISD::Wrapper && 1045 N.getOperand(0).getOpcode() == ISD::TargetConstantPool) 1046 return false; // We want to select tLDRpci instead. 1047 } 1048 1049 if (!CurDAG->isBaseWithConstantOffset(N)) { 1050 if (N.getOpcode() == ARMISD::Wrapper && 1051 !(Subtarget->useMovt() && 1052 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 1053 Base = N.getOperand(0); 1054 } else { 1055 Base = N; 1056 } 1057 1058 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 1059 return true; 1060 } 1061 1062 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 1063 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); 1064 if ((LHSR && LHSR->getReg() == ARM::SP) || 1065 (RHSR && RHSR->getReg() == ARM::SP)) { 1066 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0)); 1067 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)); 1068 unsigned LHSC = LHS ? LHS->getZExtValue() : 0; 1069 unsigned RHSC = RHS ? RHS->getZExtValue() : 0; 1070 1071 // Thumb does not have [sp, #imm5] address mode for non-zero imm5. 1072 if (LHSC != 0 || RHSC != 0) return false; 1073 1074 Base = N; 1075 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 1076 return true; 1077 } 1078 1079 // If the RHS is + imm5 * scale, fold into addr mode. 1080 int RHSC; 1081 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) { 1082 Base = N.getOperand(0); 1083 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 1084 return true; 1085 } 1086 1087 Base = N.getOperand(0); 1088 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 1089 return true; 1090} 1091 1092bool 1093ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base, 1094 SDValue &OffImm) { 1095 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm); 1096} 1097 1098bool 1099ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base, 1100 SDValue &OffImm) { 1101 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm); 1102} 1103 1104bool 1105ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base, 1106 SDValue &OffImm) { 1107 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm); 1108} 1109 1110bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N, 1111 SDValue &Base, SDValue &OffImm) { 1112 if (N.getOpcode() == ISD::FrameIndex) { 1113 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 1114 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1115 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 1116 return true; 1117 } 1118 1119 if (!CurDAG->isBaseWithConstantOffset(N)) 1120 return false; 1121 1122 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 1123 if (N.getOperand(0).getOpcode() == ISD::FrameIndex || 1124 (LHSR && LHSR->getReg() == ARM::SP)) { 1125 // If the RHS is + imm8 * scale, fold into addr mode. 1126 int RHSC; 1127 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) { 1128 Base = N.getOperand(0); 1129 if (Base.getOpcode() == ISD::FrameIndex) { 1130 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 1131 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1132 } 1133 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 1134 return true; 1135 } 1136 } 1137 1138 return false; 1139} 1140 1141 1142//===----------------------------------------------------------------------===// 1143// Thumb 2 Addressing Modes 1144//===----------------------------------------------------------------------===// 1145 1146 1147bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, 1148 SDValue &Opc) { 1149 if (DisableShifterOp) 1150 return false; 1151 1152 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); 1153 1154 // Don't match base register only case. That is matched to a separate 1155 // lower complexity pattern with explicit register operand. 1156 if (ShOpcVal == ARM_AM::no_shift) return false; 1157 1158 BaseReg = N.getOperand(0); 1159 unsigned ShImmVal = 0; 1160 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 1161 ShImmVal = RHS->getZExtValue() & 31; 1162 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal)); 1163 return true; 1164 } 1165 1166 return false; 1167} 1168 1169bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N, 1170 SDValue &Base, SDValue &OffImm) { 1171 // Match simple R + imm12 operands. 1172 1173 // Base only. 1174 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 1175 !CurDAG->isBaseWithConstantOffset(N)) { 1176 if (N.getOpcode() == ISD::FrameIndex) { 1177 // Match frame index. 1178 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 1179 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1180 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 1181 return true; 1182 } 1183 1184 if (N.getOpcode() == ARMISD::Wrapper && 1185 !(Subtarget->useMovt() && 1186 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 1187 Base = N.getOperand(0); 1188 if (Base.getOpcode() == ISD::TargetConstantPool) 1189 return false; // We want to select t2LDRpci instead. 1190 } else 1191 Base = N; 1192 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 1193 return true; 1194 } 1195 1196 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 1197 if (SelectT2AddrModeImm8(N, Base, OffImm)) 1198 // Let t2LDRi8 handle (R - imm8). 1199 return false; 1200 1201 int RHSC = (int)RHS->getZExtValue(); 1202 if (N.getOpcode() == ISD::SUB) 1203 RHSC = -RHSC; 1204 1205 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned) 1206 Base = N.getOperand(0); 1207 if (Base.getOpcode() == ISD::FrameIndex) { 1208 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 1209 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1210 } 1211 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 1212 return true; 1213 } 1214 } 1215 1216 // Base only. 1217 Base = N; 1218 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 1219 return true; 1220} 1221 1222bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N, 1223 SDValue &Base, SDValue &OffImm) { 1224 // Match simple R - imm8 operands. 1225 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 1226 !CurDAG->isBaseWithConstantOffset(N)) 1227 return false; 1228 1229 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 1230 int RHSC = (int)RHS->getSExtValue(); 1231 if (N.getOpcode() == ISD::SUB) 1232 RHSC = -RHSC; 1233 1234 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative) 1235 Base = N.getOperand(0); 1236 if (Base.getOpcode() == ISD::FrameIndex) { 1237 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 1238 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1239 } 1240 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 1241 return true; 1242 } 1243 } 1244 1245 return false; 1246} 1247 1248bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 1249 SDValue &OffImm){ 1250 unsigned Opcode = Op->getOpcode(); 1251 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 1252 ? cast<LoadSDNode>(Op)->getAddressingMode() 1253 : cast<StoreSDNode>(Op)->getAddressingMode(); 1254 int RHSC; 1255 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits. 1256 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) 1257 ? CurDAG->getTargetConstant(RHSC, MVT::i32) 1258 : CurDAG->getTargetConstant(-RHSC, MVT::i32); 1259 return true; 1260 } 1261 1262 return false; 1263} 1264 1265bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N, 1266 SDValue &Base, 1267 SDValue &OffReg, SDValue &ShImm) { 1268 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12. 1269 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) 1270 return false; 1271 1272 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8. 1273 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 1274 int RHSC = (int)RHS->getZExtValue(); 1275 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned) 1276 return false; 1277 else if (RHSC < 0 && RHSC >= -255) // 8 bits 1278 return false; 1279 } 1280 1281 // Look for (R + R) or (R + (R << [1,2,3])). 1282 unsigned ShAmt = 0; 1283 Base = N.getOperand(0); 1284 OffReg = N.getOperand(1); 1285 1286 // Swap if it is ((R << c) + R). 1287 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); 1288 if (ShOpcVal != ARM_AM::lsl) { 1289 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode()); 1290 if (ShOpcVal == ARM_AM::lsl) 1291 std::swap(Base, OffReg); 1292 } 1293 1294 if (ShOpcVal == ARM_AM::lsl) { 1295 // Check to see if the RHS of the shift is a constant, if not, we can't fold 1296 // it. 1297 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) { 1298 ShAmt = Sh->getZExtValue(); 1299 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt)) 1300 OffReg = OffReg.getOperand(0); 1301 else { 1302 ShAmt = 0; 1303 ShOpcVal = ARM_AM::no_shift; 1304 } 1305 } else { 1306 ShOpcVal = ARM_AM::no_shift; 1307 } 1308 } 1309 1310 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32); 1311 1312 return true; 1313} 1314 1315//===--------------------------------------------------------------------===// 1316 1317/// getAL - Returns a ARMCC::AL immediate node. 1318static inline SDValue getAL(SelectionDAG *CurDAG) { 1319 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); 1320} 1321 1322SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) { 1323 LoadSDNode *LD = cast<LoadSDNode>(N); 1324 ISD::MemIndexedMode AM = LD->getAddressingMode(); 1325 if (AM == ISD::UNINDEXED) 1326 return NULL; 1327 1328 EVT LoadedVT = LD->getMemoryVT(); 1329 SDValue Offset, AMOpc; 1330 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 1331 unsigned Opcode = 0; 1332 bool Match = false; 1333 if (LoadedVT == MVT::i32 && isPre && 1334 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) { 1335 Opcode = ARM::LDR_PRE_IMM; 1336 Match = true; 1337 } else if (LoadedVT == MVT::i32 && !isPre && 1338 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) { 1339 Opcode = ARM::LDR_POST_IMM; 1340 Match = true; 1341 } else if (LoadedVT == MVT::i32 && 1342 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) { 1343 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; 1344 Match = true; 1345 1346 } else if (LoadedVT == MVT::i16 && 1347 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 1348 Match = true; 1349 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) 1350 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) 1351 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); 1352 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { 1353 if (LD->getExtensionType() == ISD::SEXTLOAD) { 1354 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 1355 Match = true; 1356 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; 1357 } 1358 } else { 1359 if (isPre && 1360 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) { 1361 Match = true; 1362 Opcode = ARM::LDRB_PRE_IMM; 1363 } else if (!isPre && 1364 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) { 1365 Match = true; 1366 Opcode = ARM::LDRB_POST_IMM; 1367 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) { 1368 Match = true; 1369 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; 1370 } 1371 } 1372 } 1373 1374 if (Match) { 1375 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) { 1376 SDValue Chain = LD->getChain(); 1377 SDValue Base = LD->getBasePtr(); 1378 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG), 1379 CurDAG->getRegister(0, MVT::i32), Chain }; 1380 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, 1381 MVT::i32, MVT::Other, Ops, 5); 1382 } else { 1383 SDValue Chain = LD->getChain(); 1384 SDValue Base = LD->getBasePtr(); 1385 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), 1386 CurDAG->getRegister(0, MVT::i32), Chain }; 1387 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, 1388 MVT::i32, MVT::Other, Ops, 6); 1389 } 1390 } 1391 1392 return NULL; 1393} 1394 1395SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) { 1396 LoadSDNode *LD = cast<LoadSDNode>(N); 1397 ISD::MemIndexedMode AM = LD->getAddressingMode(); 1398 if (AM == ISD::UNINDEXED) 1399 return NULL; 1400 1401 EVT LoadedVT = LD->getMemoryVT(); 1402 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; 1403 SDValue Offset; 1404 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 1405 unsigned Opcode = 0; 1406 bool Match = false; 1407 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) { 1408 switch (LoadedVT.getSimpleVT().SimpleTy) { 1409 case MVT::i32: 1410 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; 1411 break; 1412 case MVT::i16: 1413 if (isSExtLd) 1414 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; 1415 else 1416 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; 1417 break; 1418 case MVT::i8: 1419 case MVT::i1: 1420 if (isSExtLd) 1421 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; 1422 else 1423 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; 1424 break; 1425 default: 1426 return NULL; 1427 } 1428 Match = true; 1429 } 1430 1431 if (Match) { 1432 SDValue Chain = LD->getChain(); 1433 SDValue Base = LD->getBasePtr(); 1434 SDValue Ops[]= { Base, Offset, getAL(CurDAG), 1435 CurDAG->getRegister(0, MVT::i32), Chain }; 1436 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, 1437 MVT::Other, Ops, 5); 1438 } 1439 1440 return NULL; 1441} 1442 1443/// PairSRegs - Form a D register from a pair of S registers. 1444/// 1445SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) { 1446 DebugLoc dl = V0.getNode()->getDebugLoc(); 1447 SDValue RegClass = 1448 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32); 1449 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); 1450 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); 1451 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1452 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); 1453} 1454 1455/// PairDRegs - Form a quad register from a pair of D registers. 1456/// 1457SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) { 1458 DebugLoc dl = V0.getNode()->getDebugLoc(); 1459 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); 1460 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1461 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1462 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1463 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); 1464} 1465 1466/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers. 1467/// 1468SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) { 1469 DebugLoc dl = V0.getNode()->getDebugLoc(); 1470 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); 1471 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 1472 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 1473 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1474 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5); 1475} 1476 1477/// QuadSRegs - Form 4 consecutive S registers. 1478/// 1479SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1, 1480 SDValue V2, SDValue V3) { 1481 DebugLoc dl = V0.getNode()->getDebugLoc(); 1482 SDValue RegClass = 1483 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32); 1484 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); 1485 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); 1486 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32); 1487 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32); 1488 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, 1489 V2, SubReg2, V3, SubReg3 }; 1490 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); 1491} 1492 1493/// QuadDRegs - Form 4 consecutive D registers. 1494/// 1495SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1, 1496 SDValue V2, SDValue V3) { 1497 DebugLoc dl = V0.getNode()->getDebugLoc(); 1498 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); 1499 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1500 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1501 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); 1502 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); 1503 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, 1504 V2, SubReg2, V3, SubReg3 }; 1505 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); 1506} 1507 1508/// QuadQRegs - Form 4 consecutive Q registers. 1509/// 1510SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1, 1511 SDValue V2, SDValue V3) { 1512 DebugLoc dl = V0.getNode()->getDebugLoc(); 1513 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); 1514 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 1515 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 1516 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32); 1517 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32); 1518 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, 1519 V2, SubReg2, V3, SubReg3 }; 1520 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9); 1521} 1522 1523/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand 1524/// of a NEON VLD or VST instruction. The supported values depend on the 1525/// number of registers being loaded. 1526SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs, 1527 bool is64BitVector) { 1528 unsigned NumRegs = NumVecs; 1529 if (!is64BitVector && NumVecs < 3) 1530 NumRegs *= 2; 1531 1532 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue(); 1533 if (Alignment >= 32 && NumRegs == 4) 1534 Alignment = 32; 1535 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4)) 1536 Alignment = 16; 1537 else if (Alignment >= 8) 1538 Alignment = 8; 1539 else 1540 Alignment = 0; 1541 1542 return CurDAG->getTargetConstant(Alignment, MVT::i32); 1543} 1544 1545// Get the register stride update opcode of a VLD/VST instruction that 1546// is otherwise equivalent to the given fixed stride updating instruction. 1547static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) { 1548 switch (Opc) { 1549 default: break; 1550 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register; 1551 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register; 1552 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register; 1553 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register; 1554 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register; 1555 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register; 1556 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register; 1557 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register; 1558 1559 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register; 1560 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register; 1561 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register; 1562 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register; 1563 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register; 1564 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register; 1565 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register; 1566 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register; 1567 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register; 1568 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register; 1569 1570 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register; 1571 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register; 1572 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register; 1573 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register; 1574 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register; 1575 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register; 1576 1577 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register; 1578 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register; 1579 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register; 1580 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register; 1581 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register; 1582 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register; 1583 1584 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register; 1585 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register; 1586 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register; 1587 } 1588 return Opc; // If not one we handle, return it unchanged. 1589} 1590 1591SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, 1592 const uint16_t *DOpcodes, 1593 const uint16_t *QOpcodes0, 1594 const uint16_t *QOpcodes1) { 1595 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); 1596 DebugLoc dl = N->getDebugLoc(); 1597 1598 SDValue MemAddr, Align; 1599 unsigned AddrOpIdx = isUpdating ? 1 : 2; 1600 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align)) 1601 return NULL; 1602 1603 SDValue Chain = N->getOperand(0); 1604 EVT VT = N->getValueType(0); 1605 bool is64BitVector = VT.is64BitVector(); 1606 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); 1607 1608 unsigned OpcodeIndex; 1609 switch (VT.getSimpleVT().SimpleTy) { 1610 default: llvm_unreachable("unhandled vld type"); 1611 // Double-register operations: 1612 case MVT::v8i8: OpcodeIndex = 0; break; 1613 case MVT::v4i16: OpcodeIndex = 1; break; 1614 case MVT::v2f32: 1615 case MVT::v2i32: OpcodeIndex = 2; break; 1616 case MVT::v1i64: OpcodeIndex = 3; break; 1617 // Quad-register operations: 1618 case MVT::v16i8: OpcodeIndex = 0; break; 1619 case MVT::v8i16: OpcodeIndex = 1; break; 1620 case MVT::v4f32: 1621 case MVT::v4i32: OpcodeIndex = 2; break; 1622 case MVT::v2i64: OpcodeIndex = 3; 1623 assert(NumVecs == 1 && "v2i64 type only supported for VLD1"); 1624 break; 1625 } 1626 1627 EVT ResTy; 1628 if (NumVecs == 1) 1629 ResTy = VT; 1630 else { 1631 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; 1632 if (!is64BitVector) 1633 ResTyElts *= 2; 1634 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts); 1635 } 1636 std::vector<EVT> ResTys; 1637 ResTys.push_back(ResTy); 1638 if (isUpdating) 1639 ResTys.push_back(MVT::i32); 1640 ResTys.push_back(MVT::Other); 1641 1642 SDValue Pred = getAL(CurDAG); 1643 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1644 SDNode *VLd; 1645 SmallVector<SDValue, 7> Ops; 1646 1647 // Double registers and VLD1/VLD2 quad registers are directly supported. 1648 if (is64BitVector || NumVecs <= 2) { 1649 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : 1650 QOpcodes0[OpcodeIndex]); 1651 Ops.push_back(MemAddr); 1652 Ops.push_back(Align); 1653 if (isUpdating) { 1654 SDValue Inc = N->getOperand(AddrOpIdx + 1); 1655 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0 1656 // case entirely when the rest are updated to that form, too. 1657 if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode())) 1658 Opc = getVLDSTRegisterUpdateOpcode(Opc); 1659 // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so 1660 // check for that explicitly too. Horribly hacky, but temporary. 1661 if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) || 1662 !isa<ConstantSDNode>(Inc.getNode())) 1663 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); 1664 } 1665 Ops.push_back(Pred); 1666 Ops.push_back(Reg0); 1667 Ops.push_back(Chain); 1668 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size()); 1669 1670 } else { 1671 // Otherwise, quad registers are loaded with two separate instructions, 1672 // where one loads the even registers and the other loads the odd registers. 1673 EVT AddrTy = MemAddr.getValueType(); 1674 1675 // Load the even subregs. This is always an updating load, so that it 1676 // provides the address to the second load for the odd subregs. 1677 SDValue ImplDef = 1678 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); 1679 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; 1680 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl, 1681 ResTy, AddrTy, MVT::Other, OpsA, 7); 1682 Chain = SDValue(VLdA, 2); 1683 1684 // Load the odd subregs. 1685 Ops.push_back(SDValue(VLdA, 1)); 1686 Ops.push_back(Align); 1687 if (isUpdating) { 1688 SDValue Inc = N->getOperand(AddrOpIdx + 1); 1689 assert(isa<ConstantSDNode>(Inc.getNode()) && 1690 "only constant post-increment update allowed for VLD3/4"); 1691 (void)Inc; 1692 Ops.push_back(Reg0); 1693 } 1694 Ops.push_back(SDValue(VLdA, 0)); 1695 Ops.push_back(Pred); 1696 Ops.push_back(Reg0); 1697 Ops.push_back(Chain); 1698 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, 1699 Ops.data(), Ops.size()); 1700 } 1701 1702 // Transfer memoperands. 1703 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1704 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); 1705 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1); 1706 1707 if (NumVecs == 1) 1708 return VLd; 1709 1710 // Extract out the subregisters. 1711 SDValue SuperReg = SDValue(VLd, 0); 1712 assert(ARM::dsub_7 == ARM::dsub_0+7 && 1713 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1714 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); 1715 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1716 ReplaceUses(SDValue(N, Vec), 1717 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 1718 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1)); 1719 if (isUpdating) 1720 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2)); 1721 return NULL; 1722} 1723 1724SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, 1725 const uint16_t *DOpcodes, 1726 const uint16_t *QOpcodes0, 1727 const uint16_t *QOpcodes1) { 1728 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); 1729 DebugLoc dl = N->getDebugLoc(); 1730 1731 SDValue MemAddr, Align; 1732 unsigned AddrOpIdx = isUpdating ? 1 : 2; 1733 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1) 1734 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align)) 1735 return NULL; 1736 1737 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1738 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); 1739 1740 SDValue Chain = N->getOperand(0); 1741 EVT VT = N->getOperand(Vec0Idx).getValueType(); 1742 bool is64BitVector = VT.is64BitVector(); 1743 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); 1744 1745 unsigned OpcodeIndex; 1746 switch (VT.getSimpleVT().SimpleTy) { 1747 default: llvm_unreachable("unhandled vst type"); 1748 // Double-register operations: 1749 case MVT::v8i8: OpcodeIndex = 0; break; 1750 case MVT::v4i16: OpcodeIndex = 1; break; 1751 case MVT::v2f32: 1752 case MVT::v2i32: OpcodeIndex = 2; break; 1753 case MVT::v1i64: OpcodeIndex = 3; break; 1754 // Quad-register operations: 1755 case MVT::v16i8: OpcodeIndex = 0; break; 1756 case MVT::v8i16: OpcodeIndex = 1; break; 1757 case MVT::v4f32: 1758 case MVT::v4i32: OpcodeIndex = 2; break; 1759 case MVT::v2i64: OpcodeIndex = 3; 1760 assert(NumVecs == 1 && "v2i64 type only supported for VST1"); 1761 break; 1762 } 1763 1764 std::vector<EVT> ResTys; 1765 if (isUpdating) 1766 ResTys.push_back(MVT::i32); 1767 ResTys.push_back(MVT::Other); 1768 1769 SDValue Pred = getAL(CurDAG); 1770 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1771 SmallVector<SDValue, 7> Ops; 1772 1773 // Double registers and VST1/VST2 quad registers are directly supported. 1774 if (is64BitVector || NumVecs <= 2) { 1775 SDValue SrcReg; 1776 if (NumVecs == 1) { 1777 SrcReg = N->getOperand(Vec0Idx); 1778 } else if (is64BitVector) { 1779 // Form a REG_SEQUENCE to force register allocation. 1780 SDValue V0 = N->getOperand(Vec0Idx + 0); 1781 SDValue V1 = N->getOperand(Vec0Idx + 1); 1782 if (NumVecs == 2) 1783 SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1784 else { 1785 SDValue V2 = N->getOperand(Vec0Idx + 2); 1786 // If it's a vst3, form a quad D-register and leave the last part as 1787 // an undef. 1788 SDValue V3 = (NumVecs == 3) 1789 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1790 : N->getOperand(Vec0Idx + 3); 1791 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1792 } 1793 } else { 1794 // Form a QQ register. 1795 SDValue Q0 = N->getOperand(Vec0Idx); 1796 SDValue Q1 = N->getOperand(Vec0Idx + 1); 1797 SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0); 1798 } 1799 1800 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : 1801 QOpcodes0[OpcodeIndex]); 1802 Ops.push_back(MemAddr); 1803 Ops.push_back(Align); 1804 if (isUpdating) { 1805 SDValue Inc = N->getOperand(AddrOpIdx + 1); 1806 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0 1807 // case entirely when the rest are updated to that form, too. 1808 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode())) 1809 Opc = getVLDSTRegisterUpdateOpcode(Opc); 1810 // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so 1811 // check for that explicitly too. Horribly hacky, but temporary. 1812 if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) || 1813 !isa<ConstantSDNode>(Inc.getNode())) 1814 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); 1815 } 1816 Ops.push_back(SrcReg); 1817 Ops.push_back(Pred); 1818 Ops.push_back(Reg0); 1819 Ops.push_back(Chain); 1820 SDNode *VSt = 1821 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size()); 1822 1823 // Transfer memoperands. 1824 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1); 1825 1826 return VSt; 1827 } 1828 1829 // Otherwise, quad registers are stored with two separate instructions, 1830 // where one stores the even registers and the other stores the odd registers. 1831 1832 // Form the QQQQ REG_SEQUENCE. 1833 SDValue V0 = N->getOperand(Vec0Idx + 0); 1834 SDValue V1 = N->getOperand(Vec0Idx + 1); 1835 SDValue V2 = N->getOperand(Vec0Idx + 2); 1836 SDValue V3 = (NumVecs == 3) 1837 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 1838 : N->getOperand(Vec0Idx + 3); 1839 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1840 1841 // Store the even D registers. This is always an updating store, so that it 1842 // provides the address to the second store for the odd subregs. 1843 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; 1844 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl, 1845 MemAddr.getValueType(), 1846 MVT::Other, OpsA, 7); 1847 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1); 1848 Chain = SDValue(VStA, 1); 1849 1850 // Store the odd D registers. 1851 Ops.push_back(SDValue(VStA, 0)); 1852 Ops.push_back(Align); 1853 if (isUpdating) { 1854 SDValue Inc = N->getOperand(AddrOpIdx + 1); 1855 assert(isa<ConstantSDNode>(Inc.getNode()) && 1856 "only constant post-increment update allowed for VST3/4"); 1857 (void)Inc; 1858 Ops.push_back(Reg0); 1859 } 1860 Ops.push_back(RegSeq); 1861 Ops.push_back(Pred); 1862 Ops.push_back(Reg0); 1863 Ops.push_back(Chain); 1864 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, 1865 Ops.data(), Ops.size()); 1866 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1); 1867 return VStB; 1868} 1869 1870SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, 1871 bool isUpdating, unsigned NumVecs, 1872 const uint16_t *DOpcodes, 1873 const uint16_t *QOpcodes) { 1874 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range"); 1875 DebugLoc dl = N->getDebugLoc(); 1876 1877 SDValue MemAddr, Align; 1878 unsigned AddrOpIdx = isUpdating ? 1 : 2; 1879 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1) 1880 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align)) 1881 return NULL; 1882 1883 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1884 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); 1885 1886 SDValue Chain = N->getOperand(0); 1887 unsigned Lane = 1888 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue(); 1889 EVT VT = N->getOperand(Vec0Idx).getValueType(); 1890 bool is64BitVector = VT.is64BitVector(); 1891 1892 unsigned Alignment = 0; 1893 if (NumVecs != 3) { 1894 Alignment = cast<ConstantSDNode>(Align)->getZExtValue(); 1895 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8; 1896 if (Alignment > NumBytes) 1897 Alignment = NumBytes; 1898 if (Alignment < 8 && Alignment < NumBytes) 1899 Alignment = 0; 1900 // Alignment must be a power of two; make sure of that. 1901 Alignment = (Alignment & -Alignment); 1902 if (Alignment == 1) 1903 Alignment = 0; 1904 } 1905 Align = CurDAG->getTargetConstant(Alignment, MVT::i32); 1906 1907 unsigned OpcodeIndex; 1908 switch (VT.getSimpleVT().SimpleTy) { 1909 default: llvm_unreachable("unhandled vld/vst lane type"); 1910 // Double-register operations: 1911 case MVT::v8i8: OpcodeIndex = 0; break; 1912 case MVT::v4i16: OpcodeIndex = 1; break; 1913 case MVT::v2f32: 1914 case MVT::v2i32: OpcodeIndex = 2; break; 1915 // Quad-register operations: 1916 case MVT::v8i16: OpcodeIndex = 0; break; 1917 case MVT::v4f32: 1918 case MVT::v4i32: OpcodeIndex = 1; break; 1919 } 1920 1921 std::vector<EVT> ResTys; 1922 if (IsLoad) { 1923 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; 1924 if (!is64BitVector) 1925 ResTyElts *= 2; 1926 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), 1927 MVT::i64, ResTyElts)); 1928 } 1929 if (isUpdating) 1930 ResTys.push_back(MVT::i32); 1931 ResTys.push_back(MVT::Other); 1932 1933 SDValue Pred = getAL(CurDAG); 1934 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1935 1936 SmallVector<SDValue, 8> Ops; 1937 Ops.push_back(MemAddr); 1938 Ops.push_back(Align); 1939 if (isUpdating) { 1940 SDValue Inc = N->getOperand(AddrOpIdx + 1); 1941 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); 1942 } 1943 1944 SDValue SuperReg; 1945 SDValue V0 = N->getOperand(Vec0Idx + 0); 1946 SDValue V1 = N->getOperand(Vec0Idx + 1); 1947 if (NumVecs == 2) { 1948 if (is64BitVector) 1949 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1950 else 1951 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); 1952 } else { 1953 SDValue V2 = N->getOperand(Vec0Idx + 2); 1954 SDValue V3 = (NumVecs == 3) 1955 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 1956 : N->getOperand(Vec0Idx + 3); 1957 if (is64BitVector) 1958 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1959 else 1960 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1961 } 1962 Ops.push_back(SuperReg); 1963 Ops.push_back(getI32Imm(Lane)); 1964 Ops.push_back(Pred); 1965 Ops.push_back(Reg0); 1966 Ops.push_back(Chain); 1967 1968 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : 1969 QOpcodes[OpcodeIndex]); 1970 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, 1971 Ops.data(), Ops.size()); 1972 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1); 1973 if (!IsLoad) 1974 return VLdLn; 1975 1976 // Extract the subregisters. 1977 SuperReg = SDValue(VLdLn, 0); 1978 assert(ARM::dsub_7 == ARM::dsub_0+7 && 1979 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1980 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; 1981 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1982 ReplaceUses(SDValue(N, Vec), 1983 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 1984 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1)); 1985 if (isUpdating) 1986 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2)); 1987 return NULL; 1988} 1989 1990SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, 1991 unsigned NumVecs, 1992 const uint16_t *Opcodes) { 1993 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); 1994 DebugLoc dl = N->getDebugLoc(); 1995 1996 SDValue MemAddr, Align; 1997 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align)) 1998 return NULL; 1999 2000 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 2001 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); 2002 2003 SDValue Chain = N->getOperand(0); 2004 EVT VT = N->getValueType(0); 2005 2006 unsigned Alignment = 0; 2007 if (NumVecs != 3) { 2008 Alignment = cast<ConstantSDNode>(Align)->getZExtValue(); 2009 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8; 2010 if (Alignment > NumBytes) 2011 Alignment = NumBytes; 2012 if (Alignment < 8 && Alignment < NumBytes) 2013 Alignment = 0; 2014 // Alignment must be a power of two; make sure of that. 2015 Alignment = (Alignment & -Alignment); 2016 if (Alignment == 1) 2017 Alignment = 0; 2018 } 2019 Align = CurDAG->getTargetConstant(Alignment, MVT::i32); 2020 2021 unsigned OpcodeIndex; 2022 switch (VT.getSimpleVT().SimpleTy) { 2023 default: llvm_unreachable("unhandled vld-dup type"); 2024 case MVT::v8i8: OpcodeIndex = 0; break; 2025 case MVT::v4i16: OpcodeIndex = 1; break; 2026 case MVT::v2f32: 2027 case MVT::v2i32: OpcodeIndex = 2; break; 2028 } 2029 2030 SDValue Pred = getAL(CurDAG); 2031 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 2032 SDValue SuperReg; 2033 unsigned Opc = Opcodes[OpcodeIndex]; 2034 SmallVector<SDValue, 6> Ops; 2035 Ops.push_back(MemAddr); 2036 Ops.push_back(Align); 2037 if (isUpdating) { 2038 // fixed-stride update instructions don't have an explicit writeback 2039 // operand. It's implicit in the opcode itself. 2040 SDValue Inc = N->getOperand(2); 2041 if (!isa<ConstantSDNode>(Inc.getNode())) 2042 Ops.push_back(Inc); 2043 // FIXME: VLD3 and VLD4 haven't been updated to that form yet. 2044 else if (NumVecs > 2) 2045 Ops.push_back(Reg0); 2046 } 2047 Ops.push_back(Pred); 2048 Ops.push_back(Reg0); 2049 Ops.push_back(Chain); 2050 2051 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; 2052 std::vector<EVT> ResTys; 2053 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts)); 2054 if (isUpdating) 2055 ResTys.push_back(MVT::i32); 2056 ResTys.push_back(MVT::Other); 2057 SDNode *VLdDup = 2058 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size()); 2059 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1); 2060 SuperReg = SDValue(VLdDup, 0); 2061 2062 // Extract the subregisters. 2063 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 2064 unsigned SubIdx = ARM::dsub_0; 2065 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 2066 ReplaceUses(SDValue(N, Vec), 2067 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); 2068 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1)); 2069 if (isUpdating) 2070 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2)); 2071 return NULL; 2072} 2073 2074SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, 2075 unsigned Opc) { 2076 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range"); 2077 DebugLoc dl = N->getDebugLoc(); 2078 EVT VT = N->getValueType(0); 2079 unsigned FirstTblReg = IsExt ? 2 : 1; 2080 2081 // Form a REG_SEQUENCE to force register allocation. 2082 SDValue RegSeq; 2083 SDValue V0 = N->getOperand(FirstTblReg + 0); 2084 SDValue V1 = N->getOperand(FirstTblReg + 1); 2085 if (NumVecs == 2) 2086 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0); 2087 else { 2088 SDValue V2 = N->getOperand(FirstTblReg + 2); 2089 // If it's a vtbl3, form a quad D-register and leave the last part as 2090 // an undef. 2091 SDValue V3 = (NumVecs == 3) 2092 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 2093 : N->getOperand(FirstTblReg + 3); 2094 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 2095 } 2096 2097 SmallVector<SDValue, 6> Ops; 2098 if (IsExt) 2099 Ops.push_back(N->getOperand(1)); 2100 Ops.push_back(RegSeq); 2101 Ops.push_back(N->getOperand(FirstTblReg + NumVecs)); 2102 Ops.push_back(getAL(CurDAG)); // predicate 2103 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register 2104 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size()); 2105} 2106 2107SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N, 2108 bool isSigned) { 2109 if (!Subtarget->hasV6T2Ops()) 2110 return NULL; 2111 2112 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) 2113 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); 2114 2115 2116 // For unsigned extracts, check for a shift right and mask 2117 unsigned And_imm = 0; 2118 if (N->getOpcode() == ISD::AND) { 2119 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) { 2120 2121 // The immediate is a mask of the low bits iff imm & (imm+1) == 0 2122 if (And_imm & (And_imm + 1)) 2123 return NULL; 2124 2125 unsigned Srl_imm = 0; 2126 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, 2127 Srl_imm)) { 2128 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 2129 2130 // Note: The width operand is encoded as width-1. 2131 unsigned Width = CountTrailingOnes_32(And_imm) - 1; 2132 unsigned LSB = Srl_imm; 2133 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 2134 SDValue Ops[] = { N->getOperand(0).getOperand(0), 2135 CurDAG->getTargetConstant(LSB, MVT::i32), 2136 CurDAG->getTargetConstant(Width, MVT::i32), 2137 getAL(CurDAG), Reg0 }; 2138 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 2139 } 2140 } 2141 return NULL; 2142 } 2143 2144 // Otherwise, we're looking for a shift of a shift 2145 unsigned Shl_imm = 0; 2146 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) { 2147 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!"); 2148 unsigned Srl_imm = 0; 2149 if (isInt32Immediate(N->getOperand(1), Srl_imm)) { 2150 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 2151 // Note: The width operand is encoded as width-1. 2152 unsigned Width = 32 - Srl_imm - 1; 2153 int LSB = Srl_imm - Shl_imm; 2154 if (LSB < 0) 2155 return NULL; 2156 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 2157 SDValue Ops[] = { N->getOperand(0).getOperand(0), 2158 CurDAG->getTargetConstant(LSB, MVT::i32), 2159 CurDAG->getTargetConstant(Width, MVT::i32), 2160 getAL(CurDAG), Reg0 }; 2161 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 2162 } 2163 } 2164 return NULL; 2165} 2166 2167SDNode *ARMDAGToDAGISel:: 2168SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 2169 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 2170 SDValue CPTmp0; 2171 SDValue CPTmp1; 2172 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) { 2173 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue(); 2174 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); 2175 unsigned Opc = 0; 2176 switch (SOShOp) { 2177 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; 2178 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; 2179 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; 2180 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; 2181 default: 2182 llvm_unreachable("Unknown so_reg opcode!"); 2183 } 2184 SDValue SOShImm = 2185 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); 2186 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 2187 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag }; 2188 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6); 2189 } 2190 return 0; 2191} 2192 2193SDNode *ARMDAGToDAGISel:: 2194SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 2195 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 2196 SDValue CPTmp0; 2197 SDValue CPTmp1; 2198 SDValue CPTmp2; 2199 if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) { 2200 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 2201 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag }; 2202 return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6); 2203 } 2204 2205 if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) { 2206 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 2207 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag }; 2208 return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7); 2209 } 2210 return 0; 2211} 2212 2213SDNode *ARMDAGToDAGISel:: 2214SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 2215 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 2216 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 2217 if (!T) 2218 return 0; 2219 2220 unsigned Opc = 0; 2221 unsigned TrueImm = T->getZExtValue(); 2222 if (is_t2_so_imm(TrueImm)) { 2223 Opc = ARM::t2MOVCCi; 2224 } else if (TrueImm <= 0xffff) { 2225 Opc = ARM::t2MOVCCi16; 2226 } else if (is_t2_so_imm_not(TrueImm)) { 2227 TrueImm = ~TrueImm; 2228 Opc = ARM::t2MVNCCi; 2229 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) { 2230 // Large immediate. 2231 Opc = ARM::t2MOVCCi32imm; 2232 } 2233 2234 if (Opc) { 2235 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32); 2236 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 2237 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 2238 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 2239 } 2240 2241 return 0; 2242} 2243 2244SDNode *ARMDAGToDAGISel:: 2245SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 2246 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 2247 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 2248 if (!T) 2249 return 0; 2250 2251 unsigned Opc = 0; 2252 unsigned TrueImm = T->getZExtValue(); 2253 bool isSoImm = is_so_imm(TrueImm); 2254 if (isSoImm) { 2255 Opc = ARM::MOVCCi; 2256 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) { 2257 Opc = ARM::MOVCCi16; 2258 } else if (is_so_imm_not(TrueImm)) { 2259 TrueImm = ~TrueImm; 2260 Opc = ARM::MVNCCi; 2261 } else if (TrueVal.getNode()->hasOneUse() && 2262 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) { 2263 // Large immediate. 2264 Opc = ARM::MOVCCi32imm; 2265 } 2266 2267 if (Opc) { 2268 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32); 2269 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 2270 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 2271 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 2272 } 2273 2274 return 0; 2275} 2276 2277SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) { 2278 EVT VT = N->getValueType(0); 2279 SDValue FalseVal = N->getOperand(0); 2280 SDValue TrueVal = N->getOperand(1); 2281 SDValue CC = N->getOperand(2); 2282 SDValue CCR = N->getOperand(3); 2283 SDValue InFlag = N->getOperand(4); 2284 assert(CC.getOpcode() == ISD::Constant); 2285 assert(CCR.getOpcode() == ISD::Register); 2286 ARMCC::CondCodes CCVal = 2287 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue(); 2288 2289 if (!Subtarget->isThumb1Only() && VT == MVT::i32) { 2290 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 2291 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 2292 // Pattern complexity = 18 cost = 1 size = 0 2293 if (Subtarget->isThumb()) { 2294 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal, 2295 CCVal, CCR, InFlag); 2296 if (!Res) 2297 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal, 2298 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 2299 if (Res) 2300 return Res; 2301 } else { 2302 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal, 2303 CCVal, CCR, InFlag); 2304 if (!Res) 2305 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal, 2306 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 2307 if (Res) 2308 return Res; 2309 } 2310 2311 // Pattern: (ARMcmov:i32 GPR:i32:$false, 2312 // (imm:i32)<<P:Pred_so_imm>>:$true, 2313 // (imm:i32):$cc) 2314 // Emits: (MOVCCi:i32 GPR:i32:$false, 2315 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc) 2316 // Pattern complexity = 10 cost = 1 size = 0 2317 if (Subtarget->isThumb()) { 2318 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal, 2319 CCVal, CCR, InFlag); 2320 if (!Res) 2321 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal, 2322 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 2323 if (Res) 2324 return Res; 2325 } else { 2326 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal, 2327 CCVal, CCR, InFlag); 2328 if (!Res) 2329 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal, 2330 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 2331 if (Res) 2332 return Res; 2333 } 2334 } 2335 2336 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 2337 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 2338 // Pattern complexity = 6 cost = 1 size = 0 2339 // 2340 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 2341 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 2342 // Pattern complexity = 6 cost = 11 size = 0 2343 // 2344 // Also VMOVScc and VMOVDcc. 2345 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32); 2346 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag }; 2347 unsigned Opc = 0; 2348 switch (VT.getSimpleVT().SimpleTy) { 2349 default: llvm_unreachable("Illegal conditional move type!"); 2350 case MVT::i32: 2351 Opc = Subtarget->isThumb() 2352 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo) 2353 : ARM::MOVCCr; 2354 break; 2355 case MVT::f32: 2356 Opc = ARM::VMOVScc; 2357 break; 2358 case MVT::f64: 2359 Opc = ARM::VMOVDcc; 2360 break; 2361 } 2362 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); 2363} 2364 2365/// Target-specific DAG combining for ISD::XOR. 2366/// Target-independent combining lowers SELECT_CC nodes of the form 2367/// select_cc setg[ge] X, 0, X, -X 2368/// select_cc setgt X, -1, X, -X 2369/// select_cc setl[te] X, 0, -X, X 2370/// select_cc setlt X, 1, -X, X 2371/// which represent Integer ABS into: 2372/// Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2373/// ARM instruction selection detects the latter and matches it to 2374/// ARM::ABS or ARM::t2ABS machine node. 2375SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){ 2376 SDValue XORSrc0 = N->getOperand(0); 2377 SDValue XORSrc1 = N->getOperand(1); 2378 EVT VT = N->getValueType(0); 2379 2380 if (Subtarget->isThumb1Only()) 2381 return NULL; 2382 2383 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA) 2384 return NULL; 2385 2386 SDValue ADDSrc0 = XORSrc0.getOperand(0); 2387 SDValue ADDSrc1 = XORSrc0.getOperand(1); 2388 SDValue SRASrc0 = XORSrc1.getOperand(0); 2389 SDValue SRASrc1 = XORSrc1.getOperand(1); 2390 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1); 2391 EVT XType = SRASrc0.getValueType(); 2392 unsigned Size = XType.getSizeInBits() - 1; 2393 2394 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && 2395 XType.isInteger() && SRAConstant != NULL && 2396 Size == SRAConstant->getZExtValue()) { 2397 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; 2398 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0); 2399 } 2400 2401 return NULL; 2402} 2403 2404SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) { 2405 // The only time a CONCAT_VECTORS operation can have legal types is when 2406 // two 64-bit vectors are concatenated to a 128-bit vector. 2407 EVT VT = N->getValueType(0); 2408 if (!VT.is128BitVector() || N->getNumOperands() != 2) 2409 llvm_unreachable("unexpected CONCAT_VECTORS"); 2410 return PairDRegs(VT, N->getOperand(0), N->getOperand(1)); 2411} 2412 2413SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { 2414 SmallVector<SDValue, 6> Ops; 2415 Ops.push_back(Node->getOperand(1)); // Ptr 2416 Ops.push_back(Node->getOperand(2)); // Low part of Val1 2417 Ops.push_back(Node->getOperand(3)); // High part of Val1 2418 if (Opc == ARM::ATOMCMPXCHG6432) { 2419 Ops.push_back(Node->getOperand(4)); // Low part of Val2 2420 Ops.push_back(Node->getOperand(5)); // High part of Val2 2421 } 2422 Ops.push_back(Node->getOperand(0)); // Chain 2423 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 2424 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 2425 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), 2426 MVT::i32, MVT::i32, MVT::Other, 2427 Ops.data() ,Ops.size()); 2428 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1); 2429 return ResNode; 2430} 2431 2432SDNode *ARMDAGToDAGISel::Select(SDNode *N) { 2433 DebugLoc dl = N->getDebugLoc(); 2434 2435 if (N->isMachineOpcode()) 2436 return NULL; // Already selected. 2437 2438 switch (N->getOpcode()) { 2439 default: break; 2440 case ISD::XOR: { 2441 // Select special operations if XOR node forms integer ABS pattern 2442 SDNode *ResNode = SelectABSOp(N); 2443 if (ResNode) 2444 return ResNode; 2445 // Other cases are autogenerated. 2446 break; 2447 } 2448 case ISD::Constant: { 2449 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue(); 2450 bool UseCP = true; 2451 if (Subtarget->hasThumb2()) 2452 // Thumb2-aware targets have the MOVT instruction, so all immediates can 2453 // be done with MOV + MOVT, at worst. 2454 UseCP = 0; 2455 else { 2456 if (Subtarget->isThumb()) { 2457 UseCP = (Val > 255 && // MOV 2458 ~Val > 255 && // MOV + MVN 2459 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL 2460 } else 2461 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV 2462 ARM_AM::getSOImmVal(~Val) == -1 && // MVN 2463 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. 2464 } 2465 2466 if (UseCP) { 2467 SDValue CPIdx = 2468 CurDAG->getTargetConstantPool(ConstantInt::get( 2469 Type::getInt32Ty(*CurDAG->getContext()), Val), 2470 TLI.getPointerTy()); 2471 2472 SDNode *ResNode; 2473 if (Subtarget->isThumb1Only()) { 2474 SDValue Pred = getAL(CurDAG); 2475 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2476 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 2477 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other, 2478 Ops, 4); 2479 } else { 2480 SDValue Ops[] = { 2481 CPIdx, 2482 CurDAG->getTargetConstant(0, MVT::i32), 2483 getAL(CurDAG), 2484 CurDAG->getRegister(0, MVT::i32), 2485 CurDAG->getEntryNode() 2486 }; 2487 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, 2488 Ops, 5); 2489 } 2490 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0)); 2491 return NULL; 2492 } 2493 2494 // Other cases are autogenerated. 2495 break; 2496 } 2497 case ISD::FrameIndex: { 2498 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm. 2499 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 2500 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 2501 if (Subtarget->isThumb1Only()) { 2502 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), 2503 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 2504 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4); 2505 } else { 2506 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? 2507 ARM::t2ADDri : ARM::ADDri); 2508 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), 2509 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 2510 CurDAG->getRegister(0, MVT::i32) }; 2511 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 2512 } 2513 } 2514 case ISD::SRL: 2515 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 2516 return I; 2517 break; 2518 case ISD::SRA: 2519 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true)) 2520 return I; 2521 break; 2522 case ISD::MUL: 2523 if (Subtarget->isThumb1Only()) 2524 break; 2525 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 2526 unsigned RHSV = C->getZExtValue(); 2527 if (!RHSV) break; 2528 if (isPowerOf2_32(RHSV-1)) { // 2^n+1? 2529 unsigned ShImm = Log2_32(RHSV-1); 2530 if (ShImm >= 32) 2531 break; 2532 SDValue V = N->getOperand(0); 2533 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 2534 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 2535 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 2536 if (Subtarget->isThumb()) { 2537 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 2538 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6); 2539 } else { 2540 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 2541 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7); 2542 } 2543 } 2544 if (isPowerOf2_32(RHSV+1)) { // 2^n-1? 2545 unsigned ShImm = Log2_32(RHSV+1); 2546 if (ShImm >= 32) 2547 break; 2548 SDValue V = N->getOperand(0); 2549 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 2550 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 2551 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 2552 if (Subtarget->isThumb()) { 2553 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 2554 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6); 2555 } else { 2556 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 2557 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7); 2558 } 2559 } 2560 } 2561 break; 2562 case ISD::AND: { 2563 // Check for unsigned bitfield extract 2564 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 2565 return I; 2566 2567 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits 2568 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits 2569 // are entirely contributed by c2 and lower 16-bits are entirely contributed 2570 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)). 2571 // Select it to: "movt x, ((c1 & 0xffff) >> 16) 2572 EVT VT = N->getValueType(0); 2573 if (VT != MVT::i32) 2574 break; 2575 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) 2576 ? ARM::t2MOVTi16 2577 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); 2578 if (!Opc) 2579 break; 2580 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2582 if (!N1C) 2583 break; 2584 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) { 2585 SDValue N2 = N0.getOperand(1); 2586 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2587 if (!N2C) 2588 break; 2589 unsigned N1CVal = N1C->getZExtValue(); 2590 unsigned N2CVal = N2C->getZExtValue(); 2591 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) && 2592 (N1CVal & 0xffffU) == 0xffffU && 2593 (N2CVal & 0xffffU) == 0x0U) { 2594 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16, 2595 MVT::i32); 2596 SDValue Ops[] = { N0.getOperand(0), Imm16, 2597 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 2598 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4); 2599 } 2600 } 2601 break; 2602 } 2603 case ARMISD::VMOVRRD: 2604 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, 2605 N->getOperand(0), getAL(CurDAG), 2606 CurDAG->getRegister(0, MVT::i32)); 2607 case ISD::UMUL_LOHI: { 2608 if (Subtarget->isThumb1Only()) 2609 break; 2610 if (Subtarget->isThumb()) { 2611 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2612 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 2613 CurDAG->getRegister(0, MVT::i32) }; 2614 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4); 2615 } else { 2616 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2617 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 2618 CurDAG->getRegister(0, MVT::i32) }; 2619 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? 2620 ARM::UMULL : ARM::UMULLv5, 2621 dl, MVT::i32, MVT::i32, Ops, 5); 2622 } 2623 } 2624 case ISD::SMUL_LOHI: { 2625 if (Subtarget->isThumb1Only()) 2626 break; 2627 if (Subtarget->isThumb()) { 2628 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2629 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 2630 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4); 2631 } else { 2632 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 2633 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 2634 CurDAG->getRegister(0, MVT::i32) }; 2635 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? 2636 ARM::SMULL : ARM::SMULLv5, 2637 dl, MVT::i32, MVT::i32, Ops, 5); 2638 } 2639 } 2640 case ARMISD::UMLAL:{ 2641 if (Subtarget->isThumb()) { 2642 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), 2643 N->getOperand(3), getAL(CurDAG), 2644 CurDAG->getRegister(0, MVT::i32)}; 2645 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops, 6); 2646 }else{ 2647 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), 2648 N->getOperand(3), getAL(CurDAG), 2649 CurDAG->getRegister(0, MVT::i32), 2650 CurDAG->getRegister(0, MVT::i32) }; 2651 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? 2652 ARM::UMLAL : ARM::UMLALv5, 2653 dl, MVT::i32, MVT::i32, Ops, 7); 2654 } 2655 } 2656 case ARMISD::SMLAL:{ 2657 if (Subtarget->isThumb()) { 2658 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), 2659 N->getOperand(3), getAL(CurDAG), 2660 CurDAG->getRegister(0, MVT::i32)}; 2661 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops, 6); 2662 }else{ 2663 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), 2664 N->getOperand(3), getAL(CurDAG), 2665 CurDAG->getRegister(0, MVT::i32), 2666 CurDAG->getRegister(0, MVT::i32) }; 2667 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? 2668 ARM::SMLAL : ARM::SMLALv5, 2669 dl, MVT::i32, MVT::i32, Ops, 7); 2670 } 2671 } 2672 case ISD::LOAD: { 2673 SDNode *ResNode = 0; 2674 if (Subtarget->isThumb() && Subtarget->hasThumb2()) 2675 ResNode = SelectT2IndexedLoad(N); 2676 else 2677 ResNode = SelectARMIndexedLoad(N); 2678 if (ResNode) 2679 return ResNode; 2680 // Other cases are autogenerated. 2681 break; 2682 } 2683 case ARMISD::BRCOND: { 2684 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2685 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc) 2686 // Pattern complexity = 6 cost = 1 size = 0 2687 2688 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2689 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc) 2690 // Pattern complexity = 6 cost = 1 size = 0 2691 2692 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2693 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc) 2694 // Pattern complexity = 6 cost = 1 size = 0 2695 2696 unsigned Opc = Subtarget->isThumb() ? 2697 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; 2698 SDValue Chain = N->getOperand(0); 2699 SDValue N1 = N->getOperand(1); 2700 SDValue N2 = N->getOperand(2); 2701 SDValue N3 = N->getOperand(3); 2702 SDValue InFlag = N->getOperand(4); 2703 assert(N1.getOpcode() == ISD::BasicBlock); 2704 assert(N2.getOpcode() == ISD::Constant); 2705 assert(N3.getOpcode() == ISD::Register); 2706 2707 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 2708 cast<ConstantSDNode>(N2)->getZExtValue()), 2709 MVT::i32); 2710 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; 2711 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, 2712 MVT::Glue, Ops, 5); 2713 Chain = SDValue(ResNode, 0); 2714 if (N->getNumValues() == 2) { 2715 InFlag = SDValue(ResNode, 1); 2716 ReplaceUses(SDValue(N, 1), InFlag); 2717 } 2718 ReplaceUses(SDValue(N, 0), 2719 SDValue(Chain.getNode(), Chain.getResNo())); 2720 return NULL; 2721 } 2722 case ARMISD::CMOV: 2723 return SelectCMOVOp(N); 2724 case ARMISD::VZIP: { 2725 unsigned Opc = 0; 2726 EVT VT = N->getValueType(0); 2727 switch (VT.getSimpleVT().SimpleTy) { 2728 default: return NULL; 2729 case MVT::v8i8: Opc = ARM::VZIPd8; break; 2730 case MVT::v4i16: Opc = ARM::VZIPd16; break; 2731 case MVT::v2f32: 2732 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm. 2733 case MVT::v2i32: Opc = ARM::VTRNd32; break; 2734 case MVT::v16i8: Opc = ARM::VZIPq8; break; 2735 case MVT::v8i16: Opc = ARM::VZIPq16; break; 2736 case MVT::v4f32: 2737 case MVT::v4i32: Opc = ARM::VZIPq32; break; 2738 } 2739 SDValue Pred = getAL(CurDAG); 2740 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2741 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2742 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2743 } 2744 case ARMISD::VUZP: { 2745 unsigned Opc = 0; 2746 EVT VT = N->getValueType(0); 2747 switch (VT.getSimpleVT().SimpleTy) { 2748 default: return NULL; 2749 case MVT::v8i8: Opc = ARM::VUZPd8; break; 2750 case MVT::v4i16: Opc = ARM::VUZPd16; break; 2751 case MVT::v2f32: 2752 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm. 2753 case MVT::v2i32: Opc = ARM::VTRNd32; break; 2754 case MVT::v16i8: Opc = ARM::VUZPq8; break; 2755 case MVT::v8i16: Opc = ARM::VUZPq16; break; 2756 case MVT::v4f32: 2757 case MVT::v4i32: Opc = ARM::VUZPq32; break; 2758 } 2759 SDValue Pred = getAL(CurDAG); 2760 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2761 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2762 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2763 } 2764 case ARMISD::VTRN: { 2765 unsigned Opc = 0; 2766 EVT VT = N->getValueType(0); 2767 switch (VT.getSimpleVT().SimpleTy) { 2768 default: return NULL; 2769 case MVT::v8i8: Opc = ARM::VTRNd8; break; 2770 case MVT::v4i16: Opc = ARM::VTRNd16; break; 2771 case MVT::v2f32: 2772 case MVT::v2i32: Opc = ARM::VTRNd32; break; 2773 case MVT::v16i8: Opc = ARM::VTRNq8; break; 2774 case MVT::v8i16: Opc = ARM::VTRNq16; break; 2775 case MVT::v4f32: 2776 case MVT::v4i32: Opc = ARM::VTRNq32; break; 2777 } 2778 SDValue Pred = getAL(CurDAG); 2779 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2780 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2781 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2782 } 2783 case ARMISD::BUILD_VECTOR: { 2784 EVT VecVT = N->getValueType(0); 2785 EVT EltVT = VecVT.getVectorElementType(); 2786 unsigned NumElts = VecVT.getVectorNumElements(); 2787 if (EltVT == MVT::f64) { 2788 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR"); 2789 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1)); 2790 } 2791 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR"); 2792 if (NumElts == 2) 2793 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1)); 2794 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR"); 2795 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1), 2796 N->getOperand(2), N->getOperand(3)); 2797 } 2798 2799 case ARMISD::VLD2DUP: { 2800 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, 2801 ARM::VLD2DUPd32 }; 2802 return SelectVLDDup(N, false, 2, Opcodes); 2803 } 2804 2805 case ARMISD::VLD3DUP: { 2806 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo, 2807 ARM::VLD3DUPd16Pseudo, 2808 ARM::VLD3DUPd32Pseudo }; 2809 return SelectVLDDup(N, false, 3, Opcodes); 2810 } 2811 2812 case ARMISD::VLD4DUP: { 2813 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo, 2814 ARM::VLD4DUPd16Pseudo, 2815 ARM::VLD4DUPd32Pseudo }; 2816 return SelectVLDDup(N, false, 4, Opcodes); 2817 } 2818 2819 case ARMISD::VLD2DUP_UPD: { 2820 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed, 2821 ARM::VLD2DUPd16wb_fixed, 2822 ARM::VLD2DUPd32wb_fixed }; 2823 return SelectVLDDup(N, true, 2, Opcodes); 2824 } 2825 2826 case ARMISD::VLD3DUP_UPD: { 2827 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, 2828 ARM::VLD3DUPd16Pseudo_UPD, 2829 ARM::VLD3DUPd32Pseudo_UPD }; 2830 return SelectVLDDup(N, true, 3, Opcodes); 2831 } 2832 2833 case ARMISD::VLD4DUP_UPD: { 2834 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, 2835 ARM::VLD4DUPd16Pseudo_UPD, 2836 ARM::VLD4DUPd32Pseudo_UPD }; 2837 return SelectVLDDup(N, true, 4, Opcodes); 2838 } 2839 2840 case ARMISD::VLD1_UPD: { 2841 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed, 2842 ARM::VLD1d16wb_fixed, 2843 ARM::VLD1d32wb_fixed, 2844 ARM::VLD1d64wb_fixed }; 2845 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed, 2846 ARM::VLD1q16wb_fixed, 2847 ARM::VLD1q32wb_fixed, 2848 ARM::VLD1q64wb_fixed }; 2849 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0); 2850 } 2851 2852 case ARMISD::VLD2_UPD: { 2853 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed, 2854 ARM::VLD2d16wb_fixed, 2855 ARM::VLD2d32wb_fixed, 2856 ARM::VLD1q64wb_fixed}; 2857 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed, 2858 ARM::VLD2q16PseudoWB_fixed, 2859 ARM::VLD2q32PseudoWB_fixed }; 2860 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0); 2861 } 2862 2863 case ARMISD::VLD3_UPD: { 2864 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, 2865 ARM::VLD3d16Pseudo_UPD, 2866 ARM::VLD3d32Pseudo_UPD, 2867 ARM::VLD1q64wb_fixed}; 2868 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, 2869 ARM::VLD3q16Pseudo_UPD, 2870 ARM::VLD3q32Pseudo_UPD }; 2871 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD, 2872 ARM::VLD3q16oddPseudo_UPD, 2873 ARM::VLD3q32oddPseudo_UPD }; 2874 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1); 2875 } 2876 2877 case ARMISD::VLD4_UPD: { 2878 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, 2879 ARM::VLD4d16Pseudo_UPD, 2880 ARM::VLD4d32Pseudo_UPD, 2881 ARM::VLD1q64wb_fixed}; 2882 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, 2883 ARM::VLD4q16Pseudo_UPD, 2884 ARM::VLD4q32Pseudo_UPD }; 2885 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD, 2886 ARM::VLD4q16oddPseudo_UPD, 2887 ARM::VLD4q32oddPseudo_UPD }; 2888 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1); 2889 } 2890 2891 case ARMISD::VLD2LN_UPD: { 2892 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, 2893 ARM::VLD2LNd16Pseudo_UPD, 2894 ARM::VLD2LNd32Pseudo_UPD }; 2895 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD, 2896 ARM::VLD2LNq32Pseudo_UPD }; 2897 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes); 2898 } 2899 2900 case ARMISD::VLD3LN_UPD: { 2901 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, 2902 ARM::VLD3LNd16Pseudo_UPD, 2903 ARM::VLD3LNd32Pseudo_UPD }; 2904 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD, 2905 ARM::VLD3LNq32Pseudo_UPD }; 2906 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes); 2907 } 2908 2909 case ARMISD::VLD4LN_UPD: { 2910 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, 2911 ARM::VLD4LNd16Pseudo_UPD, 2912 ARM::VLD4LNd32Pseudo_UPD }; 2913 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD, 2914 ARM::VLD4LNq32Pseudo_UPD }; 2915 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes); 2916 } 2917 2918 case ARMISD::VST1_UPD: { 2919 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed, 2920 ARM::VST1d16wb_fixed, 2921 ARM::VST1d32wb_fixed, 2922 ARM::VST1d64wb_fixed }; 2923 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed, 2924 ARM::VST1q16wb_fixed, 2925 ARM::VST1q32wb_fixed, 2926 ARM::VST1q64wb_fixed }; 2927 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0); 2928 } 2929 2930 case ARMISD::VST2_UPD: { 2931 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed, 2932 ARM::VST2d16wb_fixed, 2933 ARM::VST2d32wb_fixed, 2934 ARM::VST1q64wb_fixed}; 2935 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed, 2936 ARM::VST2q16PseudoWB_fixed, 2937 ARM::VST2q32PseudoWB_fixed }; 2938 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0); 2939 } 2940 2941 case ARMISD::VST3_UPD: { 2942 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD, 2943 ARM::VST3d16Pseudo_UPD, 2944 ARM::VST3d32Pseudo_UPD, 2945 ARM::VST1d64TPseudoWB_fixed}; 2946 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, 2947 ARM::VST3q16Pseudo_UPD, 2948 ARM::VST3q32Pseudo_UPD }; 2949 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD, 2950 ARM::VST3q16oddPseudo_UPD, 2951 ARM::VST3q32oddPseudo_UPD }; 2952 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1); 2953 } 2954 2955 case ARMISD::VST4_UPD: { 2956 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD, 2957 ARM::VST4d16Pseudo_UPD, 2958 ARM::VST4d32Pseudo_UPD, 2959 ARM::VST1d64QPseudoWB_fixed}; 2960 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, 2961 ARM::VST4q16Pseudo_UPD, 2962 ARM::VST4q32Pseudo_UPD }; 2963 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD, 2964 ARM::VST4q16oddPseudo_UPD, 2965 ARM::VST4q32oddPseudo_UPD }; 2966 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1); 2967 } 2968 2969 case ARMISD::VST2LN_UPD: { 2970 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, 2971 ARM::VST2LNd16Pseudo_UPD, 2972 ARM::VST2LNd32Pseudo_UPD }; 2973 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD, 2974 ARM::VST2LNq32Pseudo_UPD }; 2975 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes); 2976 } 2977 2978 case ARMISD::VST3LN_UPD: { 2979 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, 2980 ARM::VST3LNd16Pseudo_UPD, 2981 ARM::VST3LNd32Pseudo_UPD }; 2982 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD, 2983 ARM::VST3LNq32Pseudo_UPD }; 2984 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes); 2985 } 2986 2987 case ARMISD::VST4LN_UPD: { 2988 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, 2989 ARM::VST4LNd16Pseudo_UPD, 2990 ARM::VST4LNd32Pseudo_UPD }; 2991 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD, 2992 ARM::VST4LNq32Pseudo_UPD }; 2993 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes); 2994 } 2995 2996 case ISD::INTRINSIC_VOID: 2997 case ISD::INTRINSIC_W_CHAIN: { 2998 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2999 switch (IntNo) { 3000 default: 3001 break; 3002 3003 case Intrinsic::arm_ldrexd: { 3004 SDValue MemAddr = N->getOperand(2); 3005 DebugLoc dl = N->getDebugLoc(); 3006 SDValue Chain = N->getOperand(0); 3007 3008 unsigned NewOpc = ARM::LDREXD; 3009 if (Subtarget->isThumb() && Subtarget->hasThumb2()) 3010 NewOpc = ARM::t2LDREXD; 3011 3012 // arm_ldrexd returns a i64 value in {i32, i32} 3013 std::vector<EVT> ResTys; 3014 ResTys.push_back(MVT::i32); 3015 ResTys.push_back(MVT::i32); 3016 ResTys.push_back(MVT::Other); 3017 3018 // place arguments in the right order 3019 SmallVector<SDValue, 7> Ops; 3020 Ops.push_back(MemAddr); 3021 Ops.push_back(getAL(CurDAG)); 3022 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); 3023 Ops.push_back(Chain); 3024 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), 3025 Ops.size()); 3026 // Transfer memoperands. 3027 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 3028 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); 3029 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1); 3030 3031 // Until there's support for specifing explicit register constraints 3032 // like the use of even/odd register pair, hardcode ldrexd to always 3033 // use the pair [R0, R1] to hold the load result. 3034 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0, 3035 SDValue(Ld, 0), SDValue(0,0)); 3036 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1, 3037 SDValue(Ld, 1), Chain.getValue(1)); 3038 3039 // Remap uses. 3040 SDValue Glue = Chain.getValue(1); 3041 if (!SDValue(N, 0).use_empty()) { 3042 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 3043 ARM::R0, MVT::i32, Glue); 3044 Glue = Result.getValue(2); 3045 ReplaceUses(SDValue(N, 0), Result); 3046 } 3047 if (!SDValue(N, 1).use_empty()) { 3048 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 3049 ARM::R1, MVT::i32, Glue); 3050 Glue = Result.getValue(2); 3051 ReplaceUses(SDValue(N, 1), Result); 3052 } 3053 3054 ReplaceUses(SDValue(N, 2), SDValue(Ld, 2)); 3055 return NULL; 3056 } 3057 3058 case Intrinsic::arm_strexd: { 3059 DebugLoc dl = N->getDebugLoc(); 3060 SDValue Chain = N->getOperand(0); 3061 SDValue Val0 = N->getOperand(2); 3062 SDValue Val1 = N->getOperand(3); 3063 SDValue MemAddr = N->getOperand(4); 3064 3065 // Until there's support for specifing explicit register constraints 3066 // like the use of even/odd register pair, hardcode strexd to always 3067 // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored. 3068 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0, 3069 SDValue(0, 0)); 3070 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1)); 3071 3072 SDValue Glue = Chain.getValue(1); 3073 Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 3074 ARM::R2, MVT::i32, Glue); 3075 Glue = Val0.getValue(1); 3076 Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 3077 ARM::R3, MVT::i32, Glue); 3078 3079 // Store exclusive double return a i32 value which is the return status 3080 // of the issued store. 3081 std::vector<EVT> ResTys; 3082 ResTys.push_back(MVT::i32); 3083 ResTys.push_back(MVT::Other); 3084 3085 // place arguments in the right order 3086 SmallVector<SDValue, 7> Ops; 3087 Ops.push_back(Val0); 3088 Ops.push_back(Val1); 3089 Ops.push_back(MemAddr); 3090 Ops.push_back(getAL(CurDAG)); 3091 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); 3092 Ops.push_back(Chain); 3093 3094 unsigned NewOpc = ARM::STREXD; 3095 if (Subtarget->isThumb() && Subtarget->hasThumb2()) 3096 NewOpc = ARM::t2STREXD; 3097 3098 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), 3099 Ops.size()); 3100 // Transfer memoperands. 3101 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 3102 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); 3103 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); 3104 3105 return St; 3106 } 3107 3108 case Intrinsic::arm_neon_vld1: { 3109 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, 3110 ARM::VLD1d32, ARM::VLD1d64 }; 3111 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, 3112 ARM::VLD1q32, ARM::VLD1q64}; 3113 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0); 3114 } 3115 3116 case Intrinsic::arm_neon_vld2: { 3117 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16, 3118 ARM::VLD2d32, ARM::VLD1q64 }; 3119 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, 3120 ARM::VLD2q32Pseudo }; 3121 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0); 3122 } 3123 3124 case Intrinsic::arm_neon_vld3: { 3125 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo, 3126 ARM::VLD3d16Pseudo, 3127 ARM::VLD3d32Pseudo, 3128 ARM::VLD1d64TPseudo }; 3129 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, 3130 ARM::VLD3q16Pseudo_UPD, 3131 ARM::VLD3q32Pseudo_UPD }; 3132 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo, 3133 ARM::VLD3q16oddPseudo, 3134 ARM::VLD3q32oddPseudo }; 3135 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1); 3136 } 3137 3138 case Intrinsic::arm_neon_vld4: { 3139 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo, 3140 ARM::VLD4d16Pseudo, 3141 ARM::VLD4d32Pseudo, 3142 ARM::VLD1d64QPseudo }; 3143 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, 3144 ARM::VLD4q16Pseudo_UPD, 3145 ARM::VLD4q32Pseudo_UPD }; 3146 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo, 3147 ARM::VLD4q16oddPseudo, 3148 ARM::VLD4q32oddPseudo }; 3149 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1); 3150 } 3151 3152 case Intrinsic::arm_neon_vld2lane: { 3153 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo, 3154 ARM::VLD2LNd16Pseudo, 3155 ARM::VLD2LNd32Pseudo }; 3156 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo, 3157 ARM::VLD2LNq32Pseudo }; 3158 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes); 3159 } 3160 3161 case Intrinsic::arm_neon_vld3lane: { 3162 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo, 3163 ARM::VLD3LNd16Pseudo, 3164 ARM::VLD3LNd32Pseudo }; 3165 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo, 3166 ARM::VLD3LNq32Pseudo }; 3167 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes); 3168 } 3169 3170 case Intrinsic::arm_neon_vld4lane: { 3171 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo, 3172 ARM::VLD4LNd16Pseudo, 3173 ARM::VLD4LNd32Pseudo }; 3174 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo, 3175 ARM::VLD4LNq32Pseudo }; 3176 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes); 3177 } 3178 3179 case Intrinsic::arm_neon_vst1: { 3180 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, 3181 ARM::VST1d32, ARM::VST1d64 }; 3182 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16, 3183 ARM::VST1q32, ARM::VST1q64 }; 3184 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0); 3185 } 3186 3187 case Intrinsic::arm_neon_vst2: { 3188 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16, 3189 ARM::VST2d32, ARM::VST1q64 }; 3190 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo, 3191 ARM::VST2q32Pseudo }; 3192 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0); 3193 } 3194 3195 case Intrinsic::arm_neon_vst3: { 3196 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo, 3197 ARM::VST3d16Pseudo, 3198 ARM::VST3d32Pseudo, 3199 ARM::VST1d64TPseudo }; 3200 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, 3201 ARM::VST3q16Pseudo_UPD, 3202 ARM::VST3q32Pseudo_UPD }; 3203 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo, 3204 ARM::VST3q16oddPseudo, 3205 ARM::VST3q32oddPseudo }; 3206 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1); 3207 } 3208 3209 case Intrinsic::arm_neon_vst4: { 3210 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo, 3211 ARM::VST4d16Pseudo, 3212 ARM::VST4d32Pseudo, 3213 ARM::VST1d64QPseudo }; 3214 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, 3215 ARM::VST4q16Pseudo_UPD, 3216 ARM::VST4q32Pseudo_UPD }; 3217 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo, 3218 ARM::VST4q16oddPseudo, 3219 ARM::VST4q32oddPseudo }; 3220 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1); 3221 } 3222 3223 case Intrinsic::arm_neon_vst2lane: { 3224 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo, 3225 ARM::VST2LNd16Pseudo, 3226 ARM::VST2LNd32Pseudo }; 3227 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo, 3228 ARM::VST2LNq32Pseudo }; 3229 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes); 3230 } 3231 3232 case Intrinsic::arm_neon_vst3lane: { 3233 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo, 3234 ARM::VST3LNd16Pseudo, 3235 ARM::VST3LNd32Pseudo }; 3236 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo, 3237 ARM::VST3LNq32Pseudo }; 3238 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes); 3239 } 3240 3241 case Intrinsic::arm_neon_vst4lane: { 3242 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo, 3243 ARM::VST4LNd16Pseudo, 3244 ARM::VST4LNd32Pseudo }; 3245 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo, 3246 ARM::VST4LNq32Pseudo }; 3247 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes); 3248 } 3249 } 3250 break; 3251 } 3252 3253 case ISD::INTRINSIC_WO_CHAIN: { 3254 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 3255 switch (IntNo) { 3256 default: 3257 break; 3258 3259 case Intrinsic::arm_neon_vtbl2: 3260 return SelectVTBL(N, false, 2, ARM::VTBL2); 3261 case Intrinsic::arm_neon_vtbl3: 3262 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo); 3263 case Intrinsic::arm_neon_vtbl4: 3264 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo); 3265 3266 case Intrinsic::arm_neon_vtbx2: 3267 return SelectVTBL(N, true, 2, ARM::VTBX2); 3268 case Intrinsic::arm_neon_vtbx3: 3269 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo); 3270 case Intrinsic::arm_neon_vtbx4: 3271 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo); 3272 } 3273 break; 3274 } 3275 3276 case ARMISD::VTBL1: { 3277 DebugLoc dl = N->getDebugLoc(); 3278 EVT VT = N->getValueType(0); 3279 SmallVector<SDValue, 6> Ops; 3280 3281 Ops.push_back(N->getOperand(0)); 3282 Ops.push_back(N->getOperand(1)); 3283 Ops.push_back(getAL(CurDAG)); // Predicate 3284 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register 3285 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size()); 3286 } 3287 case ARMISD::VTBL2: { 3288 DebugLoc dl = N->getDebugLoc(); 3289 EVT VT = N->getValueType(0); 3290 3291 // Form a REG_SEQUENCE to force register allocation. 3292 SDValue V0 = N->getOperand(0); 3293 SDValue V1 = N->getOperand(1); 3294 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0); 3295 3296 SmallVector<SDValue, 6> Ops; 3297 Ops.push_back(RegSeq); 3298 Ops.push_back(N->getOperand(2)); 3299 Ops.push_back(getAL(CurDAG)); // Predicate 3300 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register 3301 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, 3302 Ops.data(), Ops.size()); 3303 } 3304 3305 case ISD::CONCAT_VECTORS: 3306 return SelectConcatVector(N); 3307 3308 case ARMISD::ATOMOR64_DAG: 3309 return SelectAtomic64(N, ARM::ATOMOR6432); 3310 case ARMISD::ATOMXOR64_DAG: 3311 return SelectAtomic64(N, ARM::ATOMXOR6432); 3312 case ARMISD::ATOMADD64_DAG: 3313 return SelectAtomic64(N, ARM::ATOMADD6432); 3314 case ARMISD::ATOMSUB64_DAG: 3315 return SelectAtomic64(N, ARM::ATOMSUB6432); 3316 case ARMISD::ATOMNAND64_DAG: 3317 return SelectAtomic64(N, ARM::ATOMNAND6432); 3318 case ARMISD::ATOMAND64_DAG: 3319 return SelectAtomic64(N, ARM::ATOMAND6432); 3320 case ARMISD::ATOMSWAP64_DAG: 3321 return SelectAtomic64(N, ARM::ATOMSWAP6432); 3322 case ARMISD::ATOMCMPXCHG64_DAG: 3323 return SelectAtomic64(N, ARM::ATOMCMPXCHG6432); 3324 } 3325 3326 return SelectCode(N); 3327} 3328 3329bool ARMDAGToDAGISel:: 3330SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 3331 std::vector<SDValue> &OutOps) { 3332 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 3333 // Require the address to be in a register. That is safe for all ARM 3334 // variants and it is hard to do anything much smarter without knowing 3335 // how the operand is used. 3336 OutOps.push_back(Op); 3337 return false; 3338} 3339 3340/// createARMISelDag - This pass converts a legalized DAG into a 3341/// ARM-specific DAG, ready for instruction scheduling. 3342/// 3343FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, 3344 CodeGenOpt::Level OptLevel) { 3345 return new ARMDAGToDAGISel(TM, OptLevel); 3346} 3347