ARMISelDAGToDAG.cpp revision 226f8bc38c7d1916518602126c7091812265bf6b
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the ARM target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMTargetMachine.h" 16#include "llvm/CallingConv.h" 17#include "llvm/DerivedTypes.h" 18#include "llvm/Function.h" 19#include "llvm/Constants.h" 20#include "llvm/Intrinsics.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/SelectionDAGISel.h" 26#include "llvm/CodeGen/SSARegMap.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Support/Debug.h" 29#include <iostream> 30#include <vector> 31using namespace llvm; 32 33namespace { 34 class ARMTargetLowering : public TargetLowering { 35 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 36 public: 37 ARMTargetLowering(TargetMachine &TM); 38 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 39 virtual const char *getTargetNodeName(unsigned Opcode) const; 40 }; 41 42} 43 44ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 45 : TargetLowering(TM) { 46 addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass); 47 addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass); 48 addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass); 49 50 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 51 52 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 53 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 54 55 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 56 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 57 58 setOperationAction(ISD::RET, MVT::Other, Custom); 59 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 60 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 61 62 setOperationAction(ISD::SELECT, MVT::i32, Expand); 63 64 setOperationAction(ISD::SETCC, MVT::i32, Expand); 65 setOperationAction(ISD::SETCC, MVT::f32, Expand); 66 setOperationAction(ISD::SETCC, MVT::f64, Expand); 67 68 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 69 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 70 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 71 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 72 73 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 74 75 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 76 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 77 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 78 setOperationAction(ISD::SDIV, MVT::i32, Expand); 79 setOperationAction(ISD::UDIV, MVT::i32, Expand); 80 setOperationAction(ISD::SREM, MVT::i32, Expand); 81 setOperationAction(ISD::UREM, MVT::i32, Expand); 82 83 setOperationAction(ISD::VASTART, MVT::Other, Custom); 84 setOperationAction(ISD::VAEND, MVT::Other, Expand); 85 86 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 87 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 88 89 setSchedulingPreference(SchedulingForRegPressure); 90 computeRegisterProperties(); 91} 92 93namespace llvm { 94 namespace ARMISD { 95 enum NodeType { 96 // Start the numbering where the builting ops and target ops leave off. 97 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END, 98 /// CALL - A direct function call. 99 CALL, 100 101 /// Return with a flag operand. 102 RET_FLAG, 103 104 CMP, 105 106 SELECT, 107 108 BR, 109 110 FSITOS, 111 FTOSIS, 112 113 FSITOD, 114 FTOSID, 115 116 FUITOS, 117 FTOUIS, 118 119 FUITOD, 120 FTOUID, 121 122 FMRRD, 123 124 FMDRR, 125 126 FMSTAT 127 }; 128 } 129} 130 131/// DAGFPCCToARMCC - Convert a DAG fp condition code to an ARM CC 132// Unordered = !N & !Z & C & V = V 133// Ordered = N | Z | !C | !V = N | Z | !V 134static ARMCC::CondCodes DAGFPCCToARMCC(ISD::CondCode CC) { 135 switch (CC) { 136 default: 137 assert(0 && "Unknown fp condition code!"); 138// SETOEQ = (N | Z | !V) & Z = Z = EQ 139 case ISD::SETEQ: 140 case ISD::SETOEQ: return ARMCC::EQ; 141// SETOGT = (N | Z | !V) & !N & !Z = !V &!N &!Z = (N = V) & !Z = GT 142 case ISD::SETGT: 143 case ISD::SETOGT: return ARMCC::GT; 144// SETOGE = (N | Z | !V) & !N = (Z | !V) & !N = !V & !N = GE 145 case ISD::SETGE: 146 case ISD::SETOGE: return ARMCC::GE; 147// SETOLT = (N | Z | !V) & N = N = MI 148 case ISD::SETLT: 149 case ISD::SETOLT: return ARMCC::MI; 150// SETOLE = (N | Z | !V) & (N | Z) = N | Z = !C | Z = LS 151 case ISD::SETLE: 152 case ISD::SETOLE: return ARMCC::LS; 153// SETONE = (N | Z | !V) & !Z = (N | !V) & Z = !V & Z = Z = NE 154 case ISD::SETNE: 155 case ISD::SETONE: return ARMCC::NE; 156// SETO = N | Z | !V = Z | !V = !V = VC 157 case ISD::SETO: return ARMCC::VC; 158// SETUO = V = VS 159 case ISD::SETUO: return ARMCC::VS; 160// SETUEQ = V | Z = ?? 161// SETUGT = V | (!Z & !N) = !Z & !N = !Z & C = HI 162 case ISD::SETUGT: return ARMCC::HI; 163// SETUGE = V | !N = !N = PL 164 case ISD::SETUGE: return ARMCC::PL; 165// SETULT = V | N = ?? 166// SETULE = V | Z | N = ?? 167// SETUNE = V | !Z = !Z = NE 168 case ISD::SETUNE: return ARMCC::NE; 169 } 170} 171 172/// DAGIntCCToARMCC - Convert a DAG integer condition code to an ARM CC 173static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) { 174 switch (CC) { 175 default: 176 assert(0 && "Unknown integer condition code!"); 177 case ISD::SETEQ: return ARMCC::EQ; 178 case ISD::SETNE: return ARMCC::NE; 179 case ISD::SETLT: return ARMCC::LT; 180 case ISD::SETLE: return ARMCC::LE; 181 case ISD::SETGT: return ARMCC::GT; 182 case ISD::SETGE: return ARMCC::GE; 183 case ISD::SETULT: return ARMCC::CC; 184 case ISD::SETULE: return ARMCC::LS; 185 case ISD::SETUGT: return ARMCC::HI; 186 case ISD::SETUGE: return ARMCC::CS; 187 } 188} 189 190const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 191 switch (Opcode) { 192 default: return 0; 193 case ARMISD::CALL: return "ARMISD::CALL"; 194 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 195 case ARMISD::SELECT: return "ARMISD::SELECT"; 196 case ARMISD::CMP: return "ARMISD::CMP"; 197 case ARMISD::BR: return "ARMISD::BR"; 198 case ARMISD::FSITOS: return "ARMISD::FSITOS"; 199 case ARMISD::FTOSIS: return "ARMISD::FTOSIS"; 200 case ARMISD::FSITOD: return "ARMISD::FSITOD"; 201 case ARMISD::FTOSID: return "ARMISD::FTOSID"; 202 case ARMISD::FUITOS: return "ARMISD::FUITOS"; 203 case ARMISD::FTOUIS: return "ARMISD::FTOUIS"; 204 case ARMISD::FUITOD: return "ARMISD::FUITOD"; 205 case ARMISD::FTOUID: return "ARMISD::FTOUID"; 206 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 207 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 208 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 209 } 210} 211 212class ArgumentLayout { 213 std::vector<bool> is_reg; 214 std::vector<unsigned> pos; 215 std::vector<MVT::ValueType> types; 216public: 217 ArgumentLayout(const std::vector<MVT::ValueType> &Types) { 218 types = Types; 219 220 unsigned RegNum = 0; 221 unsigned StackOffset = 0; 222 for(std::vector<MVT::ValueType>::const_iterator I = Types.begin(); 223 I != Types.end(); 224 ++I) { 225 MVT::ValueType VT = *I; 226 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 227 unsigned size = MVT::getSizeInBits(VT)/32; 228 229 RegNum = ((RegNum + size - 1) / size) * size; 230 if (RegNum < 4) { 231 pos.push_back(RegNum); 232 is_reg.push_back(true); 233 RegNum += size; 234 } else { 235 unsigned bytes = size * 32/8; 236 StackOffset = ((StackOffset + bytes - 1) / bytes) * bytes; 237 pos.push_back(StackOffset); 238 is_reg.push_back(false); 239 StackOffset += bytes; 240 } 241 } 242 } 243 unsigned getRegisterNum(unsigned argNum) { 244 assert(isRegister(argNum)); 245 return pos[argNum]; 246 } 247 unsigned getOffset(unsigned argNum) { 248 assert(isOffset(argNum)); 249 return pos[argNum]; 250 } 251 unsigned isRegister(unsigned argNum) { 252 assert(argNum < is_reg.size()); 253 return is_reg[argNum]; 254 } 255 unsigned isOffset(unsigned argNum) { 256 return !isRegister(argNum); 257 } 258 MVT::ValueType getType(unsigned argNum) { 259 assert(argNum < types.size()); 260 return types[argNum]; 261 } 262 unsigned getStackSize(void) { 263 int last = is_reg.size() - 1; 264 if (last < 0) 265 return 0; 266 if (isRegister(last)) 267 return 0; 268 return getOffset(last) + MVT::getSizeInBits(getType(last))/8; 269 } 270 int lastRegArg(void) { 271 int size = is_reg.size(); 272 int last = 0; 273 while(last < size && isRegister(last)) 274 last++; 275 last--; 276 return last; 277 } 278 int lastRegNum(void) { 279 int l = lastRegArg(); 280 if (l < 0) 281 return -1; 282 unsigned r = getRegisterNum(l); 283 MVT::ValueType t = getType(l); 284 assert(t == MVT::i32 || t == MVT::f32 || t == MVT::f64); 285 if (t == MVT::f64) 286 return r + 1; 287 return r; 288 } 289}; 290 291// This transforms a ISD::CALL node into a 292// callseq_star <- ARMISD:CALL <- callseq_end 293// chain 294static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { 295 SDOperand Chain = Op.getOperand(0); 296 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 297 assert(CallConv == CallingConv::C && "unknown calling convention"); 298 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 299 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 300 SDOperand Callee = Op.getOperand(4); 301 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 302 SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32); 303 static const unsigned regs[] = { 304 ARM::R0, ARM::R1, ARM::R2, ARM::R3 305 }; 306 307 std::vector<MVT::ValueType> Types; 308 for (unsigned i = 0; i < NumOps; ++i) { 309 MVT::ValueType VT = Op.getOperand(5+2*i).getValueType(); 310 Types.push_back(VT); 311 } 312 ArgumentLayout Layout(Types); 313 314 unsigned NumBytes = Layout.getStackSize(); 315 316 Chain = DAG.getCALLSEQ_START(Chain, 317 DAG.getConstant(NumBytes, MVT::i32)); 318 319 //Build a sequence of stores 320 std::vector<SDOperand> MemOpChains; 321 for (unsigned i = Layout.lastRegArg() + 1; i < NumOps; ++i) { 322 SDOperand Arg = Op.getOperand(5+2*i); 323 unsigned ArgOffset = Layout.getOffset(i); 324 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 325 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 326 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 327 } 328 if (!MemOpChains.empty()) 329 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 330 &MemOpChains[0], MemOpChains.size()); 331 332 // If the callee is a GlobalAddress node (quite common, every direct call is) 333 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 334 // Likewise ExternalSymbol -> TargetExternalSymbol. 335 assert(Callee.getValueType() == MVT::i32); 336 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 337 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 338 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 339 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 340 341 // If this is a direct call, pass the chain and the callee. 342 assert (Callee.Val); 343 std::vector<SDOperand> Ops; 344 Ops.push_back(Chain); 345 Ops.push_back(Callee); 346 347 // Build a sequence of copy-to-reg nodes chained together with token chain 348 // and flag operands which copy the outgoing args into the appropriate regs. 349 SDOperand InFlag; 350 for (int i = 0, e = Layout.lastRegArg(); i <= e; ++i) { 351 SDOperand Arg = Op.getOperand(5+2*i); 352 unsigned RegNum = Layout.getRegisterNum(i); 353 unsigned Reg1 = regs[RegNum]; 354 MVT::ValueType VT = Layout.getType(i); 355 assert(VT == Arg.getValueType()); 356 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 357 358 // Add argument register to the end of the list so that it is known live 359 // into the call. 360 Ops.push_back(DAG.getRegister(Reg1, MVT::i32)); 361 if (VT == MVT::f64) { 362 unsigned Reg2 = regs[RegNum + 1]; 363 SDOperand SDReg1 = DAG.getRegister(Reg1, MVT::i32); 364 SDOperand SDReg2 = DAG.getRegister(Reg2, MVT::i32); 365 366 Ops.push_back(DAG.getRegister(Reg2, MVT::i32)); 367 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 368 SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg, InFlag}; 369 Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, InFlag.Val ? 5 : 4); 370 } else { 371 if (VT == MVT::f32) 372 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg); 373 Chain = DAG.getCopyToReg(Chain, Reg1, Arg, InFlag); 374 } 375 InFlag = Chain.getValue(1); 376 } 377 378 std::vector<MVT::ValueType> NodeTys; 379 NodeTys.push_back(MVT::Other); // Returns a chain 380 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 381 382 unsigned CallOpc = ARMISD::CALL; 383 if (InFlag.Val) 384 Ops.push_back(InFlag); 385 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 386 InFlag = Chain.getValue(1); 387 388 std::vector<SDOperand> ResultVals; 389 NodeTys.clear(); 390 391 // If the call has results, copy the values out of the ret val registers. 392 MVT::ValueType VT = Op.Val->getValueType(0); 393 if (VT != MVT::Other) { 394 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 395 396 SDOperand Value1 = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 397 Chain = Value1.getValue(1); 398 InFlag = Value1.getValue(2); 399 NodeTys.push_back(VT); 400 if (VT == MVT::i32) { 401 ResultVals.push_back(Value1); 402 if (Op.Val->getValueType(1) == MVT::i32) { 403 SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag); 404 Chain = Value2.getValue(1); 405 ResultVals.push_back(Value2); 406 NodeTys.push_back(VT); 407 } 408 } 409 if (VT == MVT::f32) { 410 SDOperand Value = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Value1); 411 ResultVals.push_back(Value); 412 } 413 if (VT == MVT::f64) { 414 SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag); 415 Chain = Value2.getValue(1); 416 SDOperand Value = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2); 417 ResultVals.push_back(Value); 418 } 419 } 420 421 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 422 DAG.getConstant(NumBytes, MVT::i32)); 423 NodeTys.push_back(MVT::Other); 424 425 if (ResultVals.empty()) 426 return Chain; 427 428 ResultVals.push_back(Chain); 429 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], 430 ResultVals.size()); 431 return Res.getValue(Op.ResNo); 432} 433 434static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 435 SDOperand Copy; 436 SDOperand Chain = Op.getOperand(0); 437 SDOperand R0 = DAG.getRegister(ARM::R0, MVT::i32); 438 SDOperand R1 = DAG.getRegister(ARM::R1, MVT::i32); 439 440 switch(Op.getNumOperands()) { 441 default: 442 assert(0 && "Do not know how to return this many arguments!"); 443 abort(); 444 case 1: { 445 SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32); 446 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 447 } 448 case 3: { 449 SDOperand Val = Op.getOperand(1); 450 assert(Val.getValueType() == MVT::i32 || 451 Val.getValueType() == MVT::f32 || 452 Val.getValueType() == MVT::f64); 453 454 if (Val.getValueType() == MVT::f64) { 455 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 456 SDOperand Ops[] = {Chain, R0, R1, Val}; 457 Copy = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4); 458 } else { 459 if (Val.getValueType() == MVT::f32) 460 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 461 Copy = DAG.getCopyToReg(Chain, R0, Val, SDOperand()); 462 } 463 464 if (DAG.getMachineFunction().liveout_empty()) { 465 DAG.getMachineFunction().addLiveOut(ARM::R0); 466 if (Val.getValueType() == MVT::f64) 467 DAG.getMachineFunction().addLiveOut(ARM::R1); 468 } 469 break; 470 } 471 case 5: 472 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); 473 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 474 // If we haven't noted the R0+R1 are live out, do so now. 475 if (DAG.getMachineFunction().liveout_empty()) { 476 DAG.getMachineFunction().addLiveOut(ARM::R0); 477 DAG.getMachineFunction().addLiveOut(ARM::R1); 478 } 479 break; 480 } 481 482 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 483 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 484} 485 486static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 487 MVT::ValueType PtrVT = Op.getValueType(); 488 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 489 Constant *C = CP->getConstVal(); 490 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 491 492 return CPI; 493} 494 495static SDOperand LowerGlobalAddress(SDOperand Op, 496 SelectionDAG &DAG) { 497 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 498 int alignment = 2; 499 SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment); 500 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr, NULL, 0); 501} 502 503static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 504 unsigned VarArgsFrameIndex) { 505 // vastart just stores the address of the VarArgsFrameIndex slot into the 506 // memory location argument. 507 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 508 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 509 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 510 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 511 SV->getOffset()); 512} 513 514static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 515 int &VarArgsFrameIndex) { 516 MachineFunction &MF = DAG.getMachineFunction(); 517 MachineFrameInfo *MFI = MF.getFrameInfo(); 518 SSARegMap *RegMap = MF.getSSARegMap(); 519 unsigned NumArgs = Op.Val->getNumValues()-1; 520 SDOperand Root = Op.getOperand(0); 521 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 522 static const unsigned REGS[] = { 523 ARM::R0, ARM::R1, ARM::R2, ARM::R3 524 }; 525 526 std::vector<MVT::ValueType> Types(Op.Val->value_begin(), Op.Val->value_end() - 1); 527 ArgumentLayout Layout(Types); 528 529 std::vector<SDOperand> ArgValues; 530 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) { 531 MVT::ValueType VT = Types[ArgNo]; 532 533 SDOperand Value; 534 if (Layout.isRegister(ArgNo)) { 535 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64); 536 unsigned RegNum = Layout.getRegisterNum(ArgNo); 537 unsigned Reg1 = REGS[RegNum]; 538 unsigned VReg1 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass); 539 SDOperand Value1 = DAG.getCopyFromReg(Root, VReg1, MVT::i32); 540 MF.addLiveIn(Reg1, VReg1); 541 if (VT == MVT::f64) { 542 unsigned Reg2 = REGS[RegNum + 1]; 543 unsigned VReg2 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass); 544 SDOperand Value2 = DAG.getCopyFromReg(Root, VReg2, MVT::i32); 545 MF.addLiveIn(Reg2, VReg2); 546 Value = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2); 547 } else { 548 Value = Value1; 549 if (VT == MVT::f32) 550 Value = DAG.getNode(ISD::BIT_CONVERT, VT, Value); 551 } 552 } else { 553 // If the argument is actually used, emit a load from the right stack 554 // slot. 555 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 556 unsigned Offset = Layout.getOffset(ArgNo); 557 unsigned Size = MVT::getSizeInBits(VT)/8; 558 int FI = MFI->CreateFixedObject(Size, Offset); 559 SDOperand FIN = DAG.getFrameIndex(FI, VT); 560 Value = DAG.getLoad(VT, Root, FIN, NULL, 0); 561 } else { 562 Value = DAG.getNode(ISD::UNDEF, VT); 563 } 564 } 565 ArgValues.push_back(Value); 566 } 567 568 unsigned NextRegNum = Layout.lastRegNum() + 1; 569 570 if (isVarArg) { 571 //If this function is vararg we must store the remaing 572 //registers so that they can be acessed with va_start 573 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8, 574 -16 + NextRegNum * 4); 575 576 SmallVector<SDOperand, 4> MemOps; 577 for (unsigned RegNo = NextRegNum; RegNo < 4; ++RegNo) { 578 int RegOffset = - (4 - RegNo) * 4; 579 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8, 580 RegOffset); 581 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 582 583 unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass); 584 MF.addLiveIn(REGS[RegNo], VReg); 585 586 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 587 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 588 MemOps.push_back(Store); 589 } 590 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 591 } 592 593 ArgValues.push_back(Root); 594 595 // Return the new list of results. 596 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 597 Op.Val->value_end()); 598 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 599} 600 601static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS, 602 SelectionDAG &DAG) { 603 MVT::ValueType vt = LHS.getValueType(); 604 assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64); 605 606 SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS); 607 608 if (vt != MVT::i32) 609 Cmp = DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 610 return Cmp; 611} 612 613static SDOperand GetARMCC(ISD::CondCode CC, MVT::ValueType vt, 614 SelectionDAG &DAG) { 615 assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64); 616 if (vt == MVT::i32) 617 return DAG.getConstant(DAGIntCCToARMCC(CC), MVT::i32); 618 else 619 return DAG.getConstant(DAGFPCCToARMCC(CC), MVT::i32); 620} 621 622static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 623 SDOperand LHS = Op.getOperand(0); 624 SDOperand RHS = Op.getOperand(1); 625 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 626 SDOperand TrueVal = Op.getOperand(2); 627 SDOperand FalseVal = Op.getOperand(3); 628 SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG); 629 SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG); 630 return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp); 631} 632 633static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { 634 SDOperand Chain = Op.getOperand(0); 635 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 636 SDOperand LHS = Op.getOperand(2); 637 SDOperand RHS = Op.getOperand(3); 638 SDOperand Dest = Op.getOperand(4); 639 SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG); 640 SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG); 641 return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp); 642} 643 644static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 645 SDOperand IntVal = Op.getOperand(0); 646 assert(IntVal.getValueType() == MVT::i32); 647 MVT::ValueType vt = Op.getValueType(); 648 assert(vt == MVT::f32 || 649 vt == MVT::f64); 650 651 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal); 652 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FSITOS : ARMISD::FSITOD; 653 return DAG.getNode(op, vt, Tmp); 654} 655 656static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 657 assert(Op.getValueType() == MVT::i32); 658 SDOperand FloatVal = Op.getOperand(0); 659 MVT::ValueType vt = FloatVal.getValueType(); 660 assert(vt == MVT::f32 || vt == MVT::f64); 661 662 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOSIS : ARMISD::FTOSID; 663 SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal); 664 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp); 665} 666 667static SDOperand LowerUINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 668 SDOperand IntVal = Op.getOperand(0); 669 assert(IntVal.getValueType() == MVT::i32); 670 MVT::ValueType vt = Op.getValueType(); 671 assert(vt == MVT::f32 || 672 vt == MVT::f64); 673 674 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal); 675 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FUITOS : ARMISD::FUITOD; 676 return DAG.getNode(op, vt, Tmp); 677} 678 679static SDOperand LowerFP_TO_UINT(SDOperand Op, SelectionDAG &DAG) { 680 assert(Op.getValueType() == MVT::i32); 681 SDOperand FloatVal = Op.getOperand(0); 682 MVT::ValueType vt = FloatVal.getValueType(); 683 assert(vt == MVT::f32 || vt == MVT::f64); 684 685 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOUIS : ARMISD::FTOUID; 686 SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal); 687 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp); 688} 689 690SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 691 switch (Op.getOpcode()) { 692 default: 693 assert(0 && "Should not custom lower this!"); 694 abort(); 695 case ISD::ConstantPool: 696 return LowerConstantPool(Op, DAG); 697 case ISD::GlobalAddress: 698 return LowerGlobalAddress(Op, DAG); 699 case ISD::FP_TO_SINT: 700 return LowerFP_TO_SINT(Op, DAG); 701 case ISD::SINT_TO_FP: 702 return LowerSINT_TO_FP(Op, DAG); 703 case ISD::FP_TO_UINT: 704 return LowerFP_TO_UINT(Op, DAG); 705 case ISD::UINT_TO_FP: 706 return LowerUINT_TO_FP(Op, DAG); 707 case ISD::FORMAL_ARGUMENTS: 708 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex); 709 case ISD::CALL: 710 return LowerCALL(Op, DAG); 711 case ISD::RET: 712 return LowerRET(Op, DAG); 713 case ISD::SELECT_CC: 714 return LowerSELECT_CC(Op, DAG); 715 case ISD::BR_CC: 716 return LowerBR_CC(Op, DAG); 717 case ISD::VASTART: 718 return LowerVASTART(Op, DAG, VarArgsFrameIndex); 719 } 720} 721 722//===----------------------------------------------------------------------===// 723// Instruction Selector Implementation 724//===----------------------------------------------------------------------===// 725 726//===--------------------------------------------------------------------===// 727/// ARMDAGToDAGISel - ARM specific code to select ARM machine 728/// instructions for SelectionDAG operations. 729/// 730namespace { 731class ARMDAGToDAGISel : public SelectionDAGISel { 732 ARMTargetLowering Lowering; 733 734public: 735 ARMDAGToDAGISel(TargetMachine &TM) 736 : SelectionDAGISel(Lowering), Lowering(TM) { 737 } 738 739 SDNode *Select(SDOperand Op); 740 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 741 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base); 742 bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift, 743 SDOperand &ShiftType); 744 bool SelectAddrMode5(SDOperand N, SDOperand &Arg, SDOperand &Offset); 745 746 // Include the pieces autogenerated from the target description. 747#include "ARMGenDAGISel.inc" 748}; 749 750void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 751 DEBUG(BB->dump()); 752 753 DAG.setRoot(SelectRoot(DAG.getRoot())); 754 DAG.RemoveDeadNodes(); 755 756 ScheduleAndEmitDAG(DAG); 757} 758 759static bool isInt12Immediate(SDNode *N, short &Imm) { 760 if (N->getOpcode() != ISD::Constant) 761 return false; 762 763 int32_t t = cast<ConstantSDNode>(N)->getValue(); 764 int max = 1<<12; 765 int min = -max; 766 if (t > min && t < max) { 767 Imm = t; 768 return true; 769 } 770 else 771 return false; 772} 773 774static bool isInt12Immediate(SDOperand Op, short &Imm) { 775 return isInt12Immediate(Op.Val, Imm); 776} 777 778static uint32_t rotateL(uint32_t x) { 779 uint32_t bit31 = (x & (1 << 31)) >> 31; 780 uint32_t t = x << 1; 781 return t | bit31; 782} 783 784static bool isUInt8Immediate(uint32_t x) { 785 return x < (1 << 8); 786} 787 788static bool isRotInt8Immediate(uint32_t x) { 789 int r; 790 for (r = 0; r < 16; r++) { 791 if (isUInt8Immediate(x)) 792 return true; 793 x = rotateL(rotateL(x)); 794 } 795 return false; 796} 797 798bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N, 799 SDOperand &Arg, 800 SDOperand &Shift, 801 SDOperand &ShiftType) { 802 switch(N.getOpcode()) { 803 case ISD::Constant: { 804 uint32_t val = cast<ConstantSDNode>(N)->getValue(); 805 if(!isRotInt8Immediate(val)) { 806 const Type *t = MVT::getTypeForValueType(MVT::i32); 807 Constant *C = ConstantUInt::get(t, val); 808 int alignment = 2; 809 SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment); 810 SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32); 811 SDNode *n = CurDAG->getTargetNode(ARM::ldr, MVT::i32, Z, Addr); 812 Arg = SDOperand(n, 0); 813 } else 814 Arg = CurDAG->getTargetConstant(val, MVT::i32); 815 816 Shift = CurDAG->getTargetConstant(0, MVT::i32); 817 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32); 818 return true; 819 } 820 case ISD::SRA: 821 Arg = N.getOperand(0); 822 Shift = N.getOperand(1); 823 ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32); 824 return true; 825 case ISD::SRL: 826 Arg = N.getOperand(0); 827 Shift = N.getOperand(1); 828 ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32); 829 return true; 830 case ISD::SHL: 831 Arg = N.getOperand(0); 832 Shift = N.getOperand(1); 833 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32); 834 return true; 835 } 836 837 Arg = N; 838 Shift = CurDAG->getTargetConstant(0, MVT::i32); 839 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32); 840 return true; 841} 842 843bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg, 844 SDOperand &Offset) { 845 //TODO: detect offset 846 Offset = CurDAG->getTargetConstant(0, MVT::i32); 847 Arg = N; 848 return true; 849} 850 851//register plus/minus 12 bit offset 852bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset, 853 SDOperand &Base) { 854 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) { 855 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 856 Offset = CurDAG->getTargetConstant(0, MVT::i32); 857 return true; 858 } 859 if (N.getOpcode() == ISD::ADD) { 860 short imm = 0; 861 if (isInt12Immediate(N.getOperand(1), imm)) { 862 Offset = CurDAG->getTargetConstant(imm, MVT::i32); 863 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 864 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); 865 } else { 866 Base = N.getOperand(0); 867 } 868 return true; // [r+i] 869 } 870 } 871 872 Offset = CurDAG->getTargetConstant(0, MVT::i32); 873 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) { 874 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); 875 } 876 else 877 Base = N; 878 return true; //any address fits in a register 879} 880 881SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { 882 SDNode *N = Op.Val; 883 884 switch (N->getOpcode()) { 885 default: 886 return SelectCode(Op); 887 break; 888 } 889 return NULL; 890} 891 892} // end anonymous namespace 893 894/// createARMISelDag - This pass converts a legalized DAG into a 895/// ARM-specific DAG, ready for instruction scheduling. 896/// 897FunctionPass *llvm::createARMISelDag(TargetMachine &TM) { 898 return new ARMDAGToDAGISel(TM); 899} 900