ARMTargetMachine.cpp revision 6c50119ba33bf22885d2229726c809539a85c247 
1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMTargetMachine.h"
14#include "ARMMCAsmInfo.h"
15#include "ARMFrameInfo.h"
16#include "ARM.h"
17#include "llvm/PassManager.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/Support/FormattedStream.h"
20#include "llvm/Target/TargetOptions.h"
21#include "llvm/Target/TargetRegistry.h"
22using namespace llvm;
23
24static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
25  Triple TheTriple(TT);
26  switch (TheTriple.getOS()) {
27  case Triple::Darwin:
28    return new ARMMCAsmInfoDarwin();
29  default:
30    return new ARMELFMCAsmInfo();
31  }
32}
33
34// This is duplicated code. Refactor this.
35static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
36                                    MCContext &Ctx, TargetAsmBackend &TAB,
37                                    raw_ostream &_OS,
38                                    MCCodeEmitter *_Emitter,
39                                    bool RelaxAll) {
40  Triple TheTriple(TT);
41  switch (TheTriple.getOS()) {
42  case Triple::Darwin:
43    return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
44  case Triple::MinGW32:
45  case Triple::MinGW64:
46  case Triple::Cygwin:
47  case Triple::Win32:
48    llvm_unreachable("ARM does not support Windows COFF format");
49    return NULL;
50  default:
51    return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
52  }
53}
54
55extern "C" void LLVMInitializeARMTarget() {
56  // Register the target.
57  RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
58  RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
59
60  // Register the target asm info.
61  RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
62  RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
63
64  // Register the MC Code Emitter
65  TargetRegistry::RegisterCodeEmitter(TheARMTarget,
66                                      createARMMCCodeEmitter);
67  TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
68                                      createARMMCCodeEmitter);
69
70  // Register the asm backend.
71  TargetRegistry::RegisterAsmBackend(TheARMTarget,
72                                     createARMAsmBackend);
73  TargetRegistry::RegisterAsmBackend(TheThumbTarget,
74                                     createARMAsmBackend);
75
76  // Register the object streamer.
77  TargetRegistry::RegisterObjectStreamer(TheARMTarget,
78                                         createMCStreamer);
79  TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
80                                         createMCStreamer);
81
82}
83
84/// TargetMachine ctor - Create an ARM architecture model.
85///
86ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
87                                           const std::string &TT,
88                                           const std::string &FS,
89                                           bool isThumb)
90  : LLVMTargetMachine(T, TT),
91    Subtarget(TT, FS, isThumb),
92    FrameInfo(Subtarget),
93    JITInfo(),
94    InstrItins(Subtarget.getInstrItineraryData())
95{
96  DefRelocModel = getRelocationModel();
97}
98
99ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
100                                   const std::string &FS)
101  : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
102    DataLayout(Subtarget.isAPCS_ABI() ?
103               std::string("e-p:32:32-f64:32:64-i64:32:64-"
104                           "v128:32:128-v64:32:64-n32") :
105               std::string("e-p:32:32-f64:64:64-i64:64:64-"
106                           "v128:64:128-v64:64:64-n32")),
107    ELFWriterInfo(*this),
108    TLInfo(*this),
109    TSInfo(*this) {
110  if (!Subtarget.hasARMOps())
111    report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
112                       "support ARM mode execution!");
113}
114
115ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
116                                       const std::string &FS)
117  : ARMBaseTargetMachine(T, TT, FS, true),
118    InstrInfo(Subtarget.hasThumb2()
119              ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
120              : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
121    DataLayout(Subtarget.isAPCS_ABI() ?
122               std::string("e-p:32:32-f64:32:64-i64:32:64-"
123                           "i16:16:32-i8:8:32-i1:8:32-"
124                           "v128:32:128-v64:32:64-a:0:32-n32") :
125               std::string("e-p:32:32-f64:64:64-i64:64:64-"
126                           "i16:16:32-i8:8:32-i1:8:32-"
127                           "v128:64:128-v64:64:64-a:0:32-n32")),
128    ELFWriterInfo(*this),
129    TLInfo(*this),
130    TSInfo(*this) {
131}
132
133// Pass Pipeline Configuration
134bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
135                                      CodeGenOpt::Level OptLevel) {
136  if (OptLevel != CodeGenOpt::None)
137    PM.add(createARMGlobalMergePass(getTargetLowering()));
138
139  return false;
140}
141
142bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
143                                           CodeGenOpt::Level OptLevel) {
144  PM.add(createARMISelDag(*this, OptLevel));
145  return false;
146}
147
148bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
149                                          CodeGenOpt::Level OptLevel) {
150  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
151  if (!Subtarget.isThumb1Only())
152    PM.add(createARMLoadStoreOptimizationPass(true));
153
154  return true;
155}
156
157bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
158                                        CodeGenOpt::Level OptLevel) {
159  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
160  if (!Subtarget.isThumb1Only())
161    PM.add(createARMLoadStoreOptimizationPass());
162
163  if (OptLevel != CodeGenOpt::None && Subtarget.hasNEON())
164    PM.add(createNEONMoveFixPass());
165
166  // Expand some pseudo instructions into multiple instructions to allow
167  // proper scheduling.
168  PM.add(createARMExpandPseudoPass());
169
170  if (OptLevel != CodeGenOpt::None) {
171    if (!Subtarget.isThumb1Only())
172      PM.add(createIfConverterPass());
173  }
174  if (Subtarget.isThumb2())
175    PM.add(createThumb2ITBlockPass());
176
177  return true;
178}
179
180bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
181                                          CodeGenOpt::Level OptLevel) {
182  if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
183    PM.add(createThumb2SizeReductionPass());
184
185  PM.add(createARMConstantIslandPass());
186  return true;
187}
188
189bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
190                                          CodeGenOpt::Level OptLevel,
191                                          JITCodeEmitter &JCE) {
192  // FIXME: Move this to TargetJITInfo!
193  if (DefRelocModel == Reloc::Default)
194    setRelocationModel(Reloc::Static);
195
196  // Machine code emitter pass for ARM.
197  PM.add(createARMJITCodeEmitterPass(*this, JCE));
198  return false;
199}
200