ARMTargetMachine.cpp revision d4d4f4f488d46a9743a0c494b42b22a1b15e0e7d 
1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMTargetMachine.h"
14#include "ARMMCAsmInfo.h"
15#include "ARMFrameInfo.h"
16#include "ARM.h"
17#include "llvm/PassManager.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/Support/FormattedStream.h"
20#include "llvm/Target/TargetOptions.h"
21#include "llvm/Target/TargetRegistry.h"
22using namespace llvm;
23
24static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
25  Triple TheTriple(TT);
26  switch (TheTriple.getOS()) {
27  case Triple::Darwin:
28    return new ARMMCAsmInfoDarwin();
29  default:
30    return new ARMELFMCAsmInfo();
31  }
32}
33
34// This is duplicated code. Refactor this.
35static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
36                                    MCContext &Ctx, TargetAsmBackend &TAB,
37                                    raw_ostream &_OS,
38                                    MCCodeEmitter *_Emitter,
39                                    bool RelaxAll) {
40  Triple TheTriple(TT);
41  switch (TheTriple.getOS()) {
42  case Triple::Darwin:
43    return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
44  case Triple::MinGW32:
45  case Triple::MinGW64:
46  case Triple::Cygwin:
47  case Triple::Win32:
48    llvm_unreachable("ARM does not support Windows COFF format");
49    return NULL;
50  default:
51    return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
52  }
53}
54
55extern "C" void LLVMInitializeARMTarget() {
56  // Register the target.
57  RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
58  RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
59
60  // Register the target asm info.
61  RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
62  RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
63
64  // Register the MC Code Emitter
65  TargetRegistry::RegisterCodeEmitter(TheARMTarget,
66                                      createARMMCCodeEmitter);
67  TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
68                                      createARMMCCodeEmitter);
69
70  // Register the asm backend.
71  TargetRegistry::RegisterAsmBackend(TheARMTarget,
72                                     createARMAsmBackend);
73  TargetRegistry::RegisterAsmBackend(TheThumbTarget,
74                                     createARMAsmBackend);
75
76  // Register the object streamer.
77  TargetRegistry::RegisterObjectStreamer(TheARMTarget,
78                                         createMCStreamer);
79  TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
80                                         createMCStreamer);
81
82}
83
84/// TargetMachine ctor - Create an ARM architecture model.
85///
86ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
87                                           const std::string &TT,
88                                           const std::string &FS,
89                                           bool isThumb)
90  : LLVMTargetMachine(T, TT),
91    Subtarget(TT, FS, isThumb),
92    FrameInfo(Subtarget),
93    JITInfo(),
94    InstrItins(Subtarget.getInstrItineraryData()),
95    DataLayout(Subtarget.getDataLayout()),
96    ELFWriterInfo(*this)
97{
98  DefRelocModel = getRelocationModel();
99}
100
101ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
102                                   const std::string &FS)
103  : ARMBaseTargetMachine(T, TT, FS, false),
104    InstrInfo(Subtarget),
105    TLInfo(*this),
106    TSInfo(*this) {
107  if (!Subtarget.hasARMOps())
108    report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
109                       "support ARM mode execution!");
110}
111
112ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
113                                       const std::string &FS)
114  : ARMBaseTargetMachine(T, TT, FS, true),
115    InstrInfo(Subtarget.hasThumb2()
116              ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
117              : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
118    TLInfo(*this),
119    TSInfo(*this) {
120}
121
122// Pass Pipeline Configuration
123bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
124                                      CodeGenOpt::Level OptLevel) {
125  if (OptLevel != CodeGenOpt::None)
126    PM.add(createARMGlobalMergePass(getTargetLowering()));
127
128  return false;
129}
130
131bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
132                                           CodeGenOpt::Level OptLevel) {
133  PM.add(createARMISelDag(*this, OptLevel));
134  return false;
135}
136
137bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
138                                          CodeGenOpt::Level OptLevel) {
139  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
140  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
141    PM.add(createARMLoadStoreOptimizationPass(true));
142
143  return true;
144}
145
146bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
147                                        CodeGenOpt::Level OptLevel) {
148  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
149  if (OptLevel != CodeGenOpt::None) {
150    if (!Subtarget.isThumb1Only())
151      PM.add(createARMLoadStoreOptimizationPass());
152    if (Subtarget.hasNEON())
153      PM.add(createNEONMoveFixPass());
154  }
155
156  // Expand some pseudo instructions into multiple instructions to allow
157  // proper scheduling.
158  PM.add(createARMExpandPseudoPass());
159
160  if (OptLevel != CodeGenOpt::None) {
161    if (!Subtarget.isThumb1Only())
162      PM.add(createIfConverterPass());
163  }
164  if (Subtarget.isThumb2())
165    PM.add(createThumb2ITBlockPass());
166
167  return true;
168}
169
170bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
171                                          CodeGenOpt::Level OptLevel) {
172  if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
173    PM.add(createThumb2SizeReductionPass());
174
175  PM.add(createARMConstantIslandPass());
176  return true;
177}
178
179bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
180                                          CodeGenOpt::Level OptLevel,
181                                          JITCodeEmitter &JCE) {
182  // FIXME: Move this to TargetJITInfo!
183  if (DefRelocModel == Reloc::Default)
184    setRelocationModel(Reloc::Static);
185
186  // Machine code emitter pass for ARM.
187  PM.add(createARMJITCodeEmitterPass(*this, JCE));
188  return false;
189}
190