ARMAsmParser.cpp revision 0b4c6738868e11ba06047a406f79489cb1db8c5a
1ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 3ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// The LLVM Compiler Infrastructure 4ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 5ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// This file is distributed under the University of Illinois Open Source 6ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// License. See LICENSE.TXT for details. 7ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 8ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===----------------------------------------------------------------------===// 9ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 1094b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "MCTargetDesc/ARMBaseInfo.h" 11ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 12ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMMCExpr.h" 13c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmLexer.h" 14c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmParser.h" 15c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 166469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola#include "llvm/MC/MCAsmInfo.h" 17642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach#include "llvm/MC/MCContext.h" 18ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCStreamer.h" 19ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCExpr.h" 20ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCInst.h" 217801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng#include "llvm/MC/MCInstrDesc.h" 2294b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCRegisterInfo.h" 23ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng#include "llvm/MC/MCSubtargetInfo.h" 2494b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCTargetAsmParser.h" 2589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach#include "llvm/Support/MathExtras.h" 26c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/Support/SourceMgr.h" 273e74d6fdd248e20a280f1dff3da9a6c689c2c4c3Evan Cheng#include "llvm/Support/TargetRegistry.h" 28fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar#include "llvm/Support/raw_ostream.h" 2911e03e7c2d0c163e54b911ad1e665616dc0bcc8cJim Grosbach#include "llvm/ADT/BitVector.h" 3075ca4b94bd9dcd3952fdc237429342a2154ba142Benjamin Kramer#include "llvm/ADT/OwningPtr.h" 3194b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/ADT/STLExtras.h" 32c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/SmallVector.h" 33345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar#include "llvm/ADT/StringSwitch.h" 34c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/Twine.h" 35ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 36ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyusing namespace llvm; 37ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 383a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 39146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 40146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand; 4116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 427636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbachenum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 4398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 4494b9550a32d189704a8eae55505edf62662c0534Evan Chengclass ARMAsmParser : public MCTargetAsmParser { 45ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng MCSubtargetInfo &STI; 46ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &Parser; 47ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 48a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Map of register aliases registers via the .req directive. 49a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StringMap<unsigned> RegisterReqs; 50a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 51f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach struct { 52f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes Cond; // Condition for IT block. 53f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Mask:4; // Condition mask for instructions. 54f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Starting at first 1 (from lsb). 55f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '1' condition as indicated in IT. 56f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '0' inverse of condition (else). 57f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Count of instructions in IT block is 58f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // 4 - trailingzeroes(mask) 59f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 60f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool FirstCond; // Explicit flag for when we're parsing the 61f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // First instruction in the IT block. It's 62f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // implied in the mask, so needs special 63f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // handling. 64f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 65f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned CurPosition; // Current position in parsing of IT 66f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // block. In range [0,3]. Initialized 67f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // according to count of instructions in block. 68f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // ~0U if no active IT block. 69f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } ITState; 70f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool inITBlock() { return ITState.CurPosition != ~0U;} 71a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach void forwardITPosition() { 72a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (!inITBlock()) return; 73a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Move to the next instruction in the IT block, if there is one. If not, 74a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // mark the block as done. 75a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach unsigned TZ = CountTrailingZeros_32(ITState.Mask); 76a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (++ITState.CurPosition == 5 - TZ) 77a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach ITState.CurPosition = ~0U; // Done with the IT block after this. 78a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 79f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 80f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 81ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &getParser() const { return Parser; } 82ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmLexer &getLexer() const { return Parser.getLexer(); } 83ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 84ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 85ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 86ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 871355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int tryParseRegister(); 881355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 890d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 901355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 921355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 931355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &ShiftAmount); 961355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveWord(unsigned Size, SMLoc L); 971355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumb(SMLoc L); 989a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach bool parseDirectiveARM(SMLoc L); 991355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumbFunc(SMLoc L); 1001355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveCode(SMLoc L); 1011355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveSyntax(SMLoc L); 102a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveReq(StringRef Name, SMLoc L); 103a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveUnreq(SMLoc L); 104d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveArch(SMLoc L); 105d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveEabiAttr(SMLoc L); 106515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 1071355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 10889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach bool &CarrySetting, unsigned &ProcessorIMod, 10989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask); 1101355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 111fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode); 11216c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 113ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumb() const { 114ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // FIXME: Can tablegen auto-generate this? 115ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 116ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 117ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumbOne() const { 118ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 119ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 12047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach bool isThumbTwo() const { 12147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 12247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 123194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach bool hasV6Ops() const { 124194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return STI.getFeatureBits() & ARM::HasV6Ops; 125194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach } 126acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool hasV7Ops() const { 127acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::HasV7Ops; 128acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 12932869205052430f45d598fba25ab878d8b29da2dEvan Cheng void SwitchMode() { 130ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 131ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(FB); 13232869205052430f45d598fba25ab878d8b29da2dEvan Cheng } 133acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool isMClass() const { 134acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::FeatureMClass; 135acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 136ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 137a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// @name Auto-generated Match Functions 138a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// { 1393483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 1400692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_ASSEMBLER_HEADER 1410692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#include "ARMGenAsmMatcher.inc" 142a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 143a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// } 144a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 14589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 14643904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocNumOperand( 147f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 14843904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocRegOperand( 149f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 1509b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OperandMatchResultTy parseCoprocOptionOperand( 1519b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 15243904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMemBarrierOptOperand( 1538bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 15443904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseProcIFlagsOperand( 1558bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 15643904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMSRMaskOperand( 1578bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 158f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 159f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef Op, int Low, int High); 160f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 161f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "lsl", 0, 31); 162f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 163f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 164f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "asr", 1, 32); 165f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 166c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 167580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 1687e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 169293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 1707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 171251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 1729d39036f62674606565217a10db28171b9594bc7Jim Grosbach OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 173862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 1747636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 175ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 176ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Asm Match Converter Methods 177a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 178a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 179a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 180a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 181eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 182eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 183ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 184ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1851355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 186ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 1879ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 1889ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &); 189548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 190548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1911355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 192ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 1937b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 1947b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 1967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 1987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2032fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2042fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 20514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 20614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 207623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 208623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 20988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 21088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21112431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 21212431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21312431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 21412431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2154334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 2164334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2174334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 2184334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 219189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 220189610f9466686a91fb7d847b572e1645c785323Jim Grosbach bool validateInstruction(MCInst &Inst, 221189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 22283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach bool processInstruction(MCInst &Inst, 223f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 224d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach bool shouldOmitCCOutOperand(StringRef Mnemonic, 225d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 226189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 227ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbypublic: 22847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach enum ARMMatchResultTy { 229194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 230f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Match_RequiresNotITBlock, 231194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresV6, 232194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresThumb2 23347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach }; 23447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 235ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 23694b9550a32d189704a8eae55505edf62662c0534Evan Cheng : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 237ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng MCAsmParserExtension::Initialize(_Parser); 23832869205052430f45d598fba25ab878d8b29da2dEvan Cheng 239ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // Initialize the set of available features. 240ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 241f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 242f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Not in an ITBlock to start with. 243f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = ~0U; 244ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 245ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 2461355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach // Implementation of the MCTargetAsmParser interface: 2471355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 2481355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseInstruction(StringRef Name, SMLoc NameLoc, 249189610f9466686a91fb7d847b572e1645c785323Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 2501355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseDirective(AsmToken DirectiveID); 2511355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach 25247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned checkTargetMatchPredicate(MCInst &Inst); 25347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 2541355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool MatchAndEmitInstruction(SMLoc IDLoc, 2551355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2561355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach MCStreamer &Out); 257ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby}; 25816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach} // end anonymous namespace 25916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2603a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 2613a69756e392942bc522193f38d7f33958ed3b131Chris Lattner 262a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ARMOperand - Instances of this class represent a parsed ARM machine 263a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// instruction. 264146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand : public MCParsedAsmOperand { 265762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan enum KindTy { 26621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CondCode, 26721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CCOut, 26821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ITCondMask, 26921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocNum, 27021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocReg, 2719b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach k_CoprocOption, 27221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Immediate, 27321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_FPImmediate, 27421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MemBarrierOpt, 27521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Memory, 27621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_PostIndexRegister, 27721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MSRMask, 27821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ProcIFlags, 279460a90540b045c102012da2492999557e6840526Jim Grosbach k_VectorIndex, 28021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Register, 28121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RegisterList, 28221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_DPRRegisterList, 28321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_SPRRegisterList, 284862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach k_VectorList, 28598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach k_VectorListAllLanes, 2867636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach k_VectorListIndexed, 28721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedRegister, 28821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedImmediate, 28921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShifterImmediate, 29021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RotateImmediate, 29121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_BitfieldDescriptor, 29221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Token 293a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Kind; 294a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 295762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc StartLoc, EndLoc; 29624d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling SmallVector<unsigned, 8> Registers; 297a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 298a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby union { 299a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 3008462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes Val; 3018462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } CC; 3028462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 3038462b30548fb5969250858036638c73c16b65b43Daniel Dunbar struct { 304fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned Val; 305fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } Cop; 306fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 307fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes struct { 3089b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach unsigned Val; 3099b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } CoprocOption; 3109b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 3119b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach struct { 31289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask:4; 31389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } ITMask; 31489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 31589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 31689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ARM_MB::MemBOpt Val; 31789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } MBOpt; 31889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 31989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 320a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags Val; 321a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } IFlags; 322a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 323a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes struct { 324584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Val; 325584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } MMask; 326584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 327584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes struct { 328a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby const char *Data; 329a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned Length; 330a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Tok; 331a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 332a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 333a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned RegNum; 334a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Reg; 335a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 336862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // A vector register list is a sequential list of 1 to 4 registers. 337862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach struct { 338862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned RegNum; 339862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count; 3407636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 3410aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced; 342862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } VectorList; 343862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3448155e5b753aca42973cf317727f3805faddcaf90Bill Wendling struct { 345460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned Val; 346460a90540b045c102012da2492999557e6840526Jim Grosbach } VectorIndex; 347460a90540b045c102012da2492999557e6840526Jim Grosbach 348460a90540b045c102012da2492999557e6840526Jim Grosbach struct { 349cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *Val; 350cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } Imm; 35116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 3529d39036f62674606565217a10db28171b9594bc7Jim Grosbach struct { 3539d39036f62674606565217a10db28171b9594bc7Jim Grosbach unsigned Val; // encoded 8-bit representation 3549d39036f62674606565217a10db28171b9594bc7Jim Grosbach } FPImm; 3559d39036f62674606565217a10db28171b9594bc7Jim Grosbach 3566a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar /// Combined record for all forms of ARM address expressions. 357a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 358a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned BaseRegNum; 3597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 3607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // was specified. 3617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm; // Offset immediate value 3627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 3637ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 36457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned ShiftImm; // shift for OffsetReg. 36557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment; // 0 = no alignment specified 366eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach // n = alignment in bytes (2, 4, 8, 16, or 32) 3677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 368e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach } Memory; 3690082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 3700082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson struct { 3717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned RegNum; 372f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isAdd; 373f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 374f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm; 3757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } PostIdxReg; 3767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach struct { 378580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 379e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned Imm; 380580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } ShifterImm; 381e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach struct { 382e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ARM_AM::ShiftOpc ShiftTy; 383e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg; 384e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg; 385e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm; 386af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedReg; 38792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson struct { 38892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson ARM_AM::ShiftOpc ShiftTy; 38992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg; 39092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm; 391af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedImm; 3927e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach struct { 3937e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach unsigned Imm; 3947e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } RotImm; 395293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach struct { 396293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned LSB; 397293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned Width; 398293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } Bitfield; 399a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby }; 40016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 401146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 402146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingpublic: 403762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 404762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Kind = o.Kind; 405762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan StartLoc = o.StartLoc; 406762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan EndLoc = o.EndLoc; 407762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan switch (Kind) { 40821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 4098462b30548fb5969250858036638c73c16b65b43Daniel Dunbar CC = o.CC; 4108462b30548fb5969250858036638c73c16b65b43Daniel Dunbar break; 41121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: 41289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = o.ITMask; 41389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 41421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 4158462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Tok = o.Tok; 416762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 41721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 41821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 419762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Reg = o.Reg; 420762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 42121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 42221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 42321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: 42424d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Registers = o.Registers; 4258d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 426862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 42798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 4287636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 429862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach VectorList = o.VectorList; 430862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 43121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 43221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 433fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Cop = o.Cop; 434fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 4359b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 4369b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach CoprocOption = o.CoprocOption; 4379b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 43821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 439762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Imm = o.Imm; 440762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 44121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_FPImmediate: 4429d39036f62674606565217a10db28171b9594bc7Jim Grosbach FPImm = o.FPImm; 4439d39036f62674606565217a10db28171b9594bc7Jim Grosbach break; 44421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 445706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes MBOpt = o.MBOpt; 446706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 44721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 448e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory = o.Memory; 449762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 45021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 4517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach PostIdxReg = o.PostIdxReg; 4527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 45321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 454584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes MMask = o.MMask; 455584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 45621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: 457a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes IFlags = o.IFlags; 4580082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 45921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 460580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm = o.ShifterImm; 4610082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 46221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 463af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedReg = o.RegShiftedReg; 464e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 46521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 466af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedImm = o.RegShiftedImm; 46792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 46821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 4697e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach RotImm = o.RotImm; 4707e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 47121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 472293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Bitfield = o.Bitfield; 473293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 474460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 475460a90540b045c102012da2492999557e6840526Jim Grosbach VectorIndex = o.VectorIndex; 476460a90540b045c102012da2492999557e6840526Jim Grosbach break; 477762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 478762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 47916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 480762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getStartLoc - Get the location of the first token of this operand. 481762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getStartLoc() const { return StartLoc; } 482762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getEndLoc - Get the location of the last token of this operand. 483762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getEndLoc() const { return EndLoc; } 484a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4858462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes getCondCode() const { 48621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_CondCode && "Invalid access!"); 4878462b30548fb5969250858036638c73c16b65b43Daniel Dunbar return CC.Val; 4888462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 4898462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 490fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned getCoproc() const { 49121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 492fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Cop.Val; 493fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 494fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 495a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby StringRef getToken() const { 49621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_Token && "Invalid access!"); 497a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return StringRef(Tok.Data, Tok.Length); 498a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 499a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 500a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned getReg() const { 50121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 5027729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling return Reg.RegNum; 503a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 504a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 5055fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &getRegList() const { 50621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 50721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind == k_SPRRegisterList) && "Invalid access!"); 50824d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling return Registers; 5098d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 5108d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 511cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *getImm() const { 51221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach assert(isImm() && "Invalid access!"); 513cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby return Imm.Val; 514cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 515cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 5169d39036f62674606565217a10db28171b9594bc7Jim Grosbach unsigned getFPImm() const { 51721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_FPImmediate && "Invalid access!"); 5189d39036f62674606565217a10db28171b9594bc7Jim Grosbach return FPImm.Val; 5199d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 5209d39036f62674606565217a10db28171b9594bc7Jim Grosbach 521460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned getVectorIndex() const { 522460a90540b045c102012da2492999557e6840526Jim Grosbach assert(Kind == k_VectorIndex && "Invalid access!"); 523460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val; 524460a90540b045c102012da2492999557e6840526Jim Grosbach } 525460a90540b045c102012da2492999557e6840526Jim Grosbach 526706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes ARM_MB::MemBOpt getMemBarrierOpt() const { 52721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MemBarrierOpt && "Invalid access!"); 528706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return MBOpt.Val; 529706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 530706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 531a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags getProcIFlags() const { 53221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_ProcIFlags && "Invalid access!"); 533a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return IFlags.Val; 534a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 535a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 536584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned getMSRMask() const { 53721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MSRMask && "Invalid access!"); 538584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MMask.Val; 539584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 540584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 54121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocNum() const { return Kind == k_CoprocNum; } 54221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocReg() const { return Kind == k_CoprocReg; } 5439b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach bool isCoprocOption() const { return Kind == k_CoprocOption; } 54421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCondCode() const { return Kind == k_CondCode; } 54521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCCOut() const { return Kind == k_CCOut; } 54621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITMask() const { return Kind == k_ITCondMask; } 54721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITCondCode() const { return Kind == k_CondCode; } 54821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isImm() const { return Kind == k_Immediate; } 54921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isFPImm() const { return Kind == k_FPImmediate; } 5504050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits16() const { 5514050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5524050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5534050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5544050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5554050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 0 && Value <= 16; 5564050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 5574050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits32() const { 5584050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5594050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5604050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5614050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5624050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 1 && Value <= 32; 5634050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 564a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isImm8s4() const { 56521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 566a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 567a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach if (!CE) return false; 568a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach int64_t Value = CE->getValue(); 569a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 570a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 57172f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_1020s4() const { 57221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 57372f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 57472f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 57572f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 57672f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 57772f39f8436848885176943b0ba985a7171145423Jim Grosbach } 57872f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_508s4() const { 57921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 58072f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 58172f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 58272f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 58372f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 58472f39f8436848885176943b0ba985a7171145423Jim Grosbach } 5856b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isImm0_255() const { 58621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 5876b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5886b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 5896b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 5906b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return Value >= 0 && Value < 256; 5916b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 592587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_1() const { 59321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 594587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 595587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 596587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 597587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 2; 598587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 599587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_3() const { 60021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 601587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 602587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 603587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 604587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 4; 605587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 60683ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_7() const { 60721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 60883ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 60983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 61083ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 61183ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 8; 61283ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 61383ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_15() const { 61421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 61583ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 61683ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 61783ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 61883ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 16; 61983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 6207c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach bool isImm0_31() const { 62121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6227c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6237c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach if (!CE) return false; 6247c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach int64_t Value = CE->getValue(); 6257c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach return Value >= 0 && Value < 32; 6267c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach } 627730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach bool isImm0_63() const { 62821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 629730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 630730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach if (!CE) return false; 631730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach int64_t Value = CE->getValue(); 632730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach return Value >= 0 && Value < 64; 633730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach } 6343b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm8() const { 63521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6363b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6373b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6383b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6393b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 8; 6403b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6413b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm16() const { 64221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6433b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6443b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6453b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6463b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 16; 6473b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6483b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm32() const { 64921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6503b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6513b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6523b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6533b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 32; 6543b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6556b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm8() const { 65621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6576b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6586b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6596b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6606b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 8; 6616b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6626b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm16() const { 66321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6646b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6656b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6666b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6676b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 16; 6686b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6696b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm32() const { 67021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6716b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6726b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6736b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6746b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 32; 6756b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6766b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm64() const { 67721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6786b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6796b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6806b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6816b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 64; 6826b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6833b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_7() const { 68421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6853b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6863b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6873b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6883b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 8; 6893b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6903b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_15() const { 69121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6923b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6933b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6943b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6953b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 16; 6963b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6973b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_31() const { 69821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6993b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7003b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 7013b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 7023b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 32; 7033b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 704f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach bool isImm1_16() const { 70521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 706f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 707f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach if (!CE) return false; 708f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach int64_t Value = CE->getValue(); 709f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach return Value > 0 && Value < 17; 710f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 7114a5ffb399f841783c201c599b88d576757f1922eJim Grosbach bool isImm1_32() const { 71221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7134a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7144a5ffb399f841783c201c599b88d576757f1922eJim Grosbach if (!CE) return false; 7154a5ffb399f841783c201c599b88d576757f1922eJim Grosbach int64_t Value = CE->getValue(); 7164a5ffb399f841783c201c599b88d576757f1922eJim Grosbach return Value > 0 && Value < 33; 7174a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 718ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach bool isImm0_32() const { 71921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 720ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 721ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (!CE) return false; 722ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach int64_t Value = CE->getValue(); 723ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach return Value >= 0 && Value < 33; 724ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 725fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach bool isImm0_65535() const { 72621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 727fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 728fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach if (!CE) return false; 729fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach int64_t Value = CE->getValue(); 730fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach return Value >= 0 && Value < 65536; 731fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach } 732ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach bool isImm0_65535Expr() const { 73321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 734ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 735ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // If it's not a constant expression, it'll generate a fixup and be 736ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // handled later. 737ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach if (!CE) return true; 738ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach int64_t Value = CE->getValue(); 739ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Value >= 0 && Value < 65536; 740ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 741ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach bool isImm24bit() const { 74221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 743ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 744ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach if (!CE) return false; 745ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach int64_t Value = CE->getValue(); 746ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach return Value >= 0 && Value <= 0xffffff; 747ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach } 74870939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach bool isImmThumbSR() const { 74921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 75070939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 75170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach if (!CE) return false; 75270939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach int64_t Value = CE->getValue(); 75370939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach return Value > 0 && Value < 33; 75470939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach } 755f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHLSLImm() const { 75621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 757f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 758f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 759f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 760f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value >= 0 && Value < 32; 761f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 762f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHASRImm() const { 76321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 764f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 765f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 766f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 767f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value > 0 && Value <= 32; 768f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 7696bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach bool isARMSOImm() const { 77021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7716bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7726bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach if (!CE) return false; 7736bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach int64_t Value = CE->getValue(); 7746bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach return ARM_AM::getSOImmVal(Value) != -1; 7756bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach } 776e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach bool isARMSOImmNot() const { 77721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 778e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 779e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach if (!CE) return false; 780e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach int64_t Value = CE->getValue(); 781e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach return ARM_AM::getSOImmVal(~Value) != -1; 782e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 7833bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isARMSOImmNeg() const { 78421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7853bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7863bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 7873bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 7883bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach return ARM_AM::getSOImmVal(-Value) != -1; 7893bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 7906b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isT2SOImm() const { 79121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7926b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7936b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 7946b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 7956b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return ARM_AM::getT2SOImmVal(Value) != -1; 7966b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 79789a633708542de5847e807f98f86edfefc9fc019Jim Grosbach bool isT2SOImmNot() const { 79821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 79989a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 80089a633708542de5847e807f98f86edfefc9fc019Jim Grosbach if (!CE) return false; 80189a633708542de5847e807f98f86edfefc9fc019Jim Grosbach int64_t Value = CE->getValue(); 80289a633708542de5847e807f98f86edfefc9fc019Jim Grosbach return ARM_AM::getT2SOImmVal(~Value) != -1; 80389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 8043bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isT2SOImmNeg() const { 80521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 8063bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8073bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 8083bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 8093bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach return ARM_AM::getT2SOImmVal(-Value) != -1; 8103bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 811c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach bool isSetEndImm() const { 81221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 813c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 814c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CE) return false; 815c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int64_t Value = CE->getValue(); 816c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Value == 1 || Value == 0; 817c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 81821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isReg() const { return Kind == k_Register; } 81921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegList() const { return Kind == k_RegisterList; } 82021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 82121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 82221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isToken() const { return Kind == k_Token; } 82321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 82421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemory() const { return Kind == k_Memory; } 82521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isShifterImm() const { return Kind == k_ShifterImmediate; } 82621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 82721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 82821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRotImm() const { return Kind == k_RotateImmediate; } 82921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 83021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 831f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isPostIdxReg() const { 832430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 833f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 83457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isMemNoOffset(bool alignOK = false) const { 835f6c35c59f515505fa2e9b74b3d0f4ab06f8266d8Jim Grosbach if (!isMemory()) 836ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return false; 8377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // No offset of any kind. 83857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 83957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach (alignOK || Memory.Alignment == 0); 84057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 8410b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach bool isMemPCRelImm12() const { 8420b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 8430b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return false; 8440b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base register must be PC. 8450b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum != ARM::PC) 8460b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return false; 8470b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Immediate offset in range [-4095, 4095]. 8480b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (!Memory.OffsetImm) return true; 8490b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8500b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 8510b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach } 85257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isAlignedMemory() const { 85357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return isMemNoOffset(true); 854ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 8557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode2() const { 85657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 858e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 8597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 860e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 861e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Val > -4096 && Val < 4096; 8637ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 864039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach bool isAM2OffsetImm() const { 86521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 866039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Immediate offset in range [-4095, 4095]. 867039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 868039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (!CE) return false; 869039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int64_t Val = CE->getValue(); 870039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach return Val > -4096 && Val < 4096; 871039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 8722fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAddrMode3() const { 8732f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 8742f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 8752f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 87621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 8772f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 87857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8792fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // No shifts are legal for AM3. 880e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::no_shift) return false; 8812fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Check for register offset. 882e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 8832fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 884e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 885e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8862fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return Val > -256 && Val < 256; 8872fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 8882fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAM3Offset() const { 88921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind != k_Immediate && Kind != k_PostIndexRegister) 8902fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return false; 89121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) 8922fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return PostIdxReg.ShiftTy == ARM_AM::no_shift; 8932fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 8942fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8952fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (!CE) return false; 8962fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int64_t Val = CE->getValue(); 897251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Special case, #-0 is INT32_MIN. 898251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return (Val > -256 && Val < 256) || Val == INT32_MIN; 8992fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 9007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode5() const { 901681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 902681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 903681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 90421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 905681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return true; 90657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 9077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 908e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return false; 9097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-1020, 1020] and a multiple of 4. 910e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 911e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 9120da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 913681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Val == INT32_MIN; 9147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 9157f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBB() const { 916e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 91757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 9187f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9197f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9207f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9217f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBH() const { 922e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 92357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 92457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0 ) 9257f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9267f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9277f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemRegOffset() const { 92957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 930ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return false; 931ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 932ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 933ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach bool isT2MemRegOffset() const { 93457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 93557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0) 936ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 937ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach // Only lsl #{0, 1, 2, 3} allowed. 938e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType == ARM_AM::no_shift) 939ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 940e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 941ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 942ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 943ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 9447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemThumbRR() const { 9457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Thumb reg+reg addressing is simple. Just two registers, a base and 9467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // an offset. No shifts, negations or any other complicating factors. 947e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 94857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 94987f4f9a946549ad93046990a364ac5190333a7ebBill Wendling return false; 950e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach return isARMLowRegister(Memory.BaseRegNum) && 951e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 95260f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 95360f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach bool isMemThumbRIs4() const { 954e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 95557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 95660f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach return false; 95760f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach // Immediate offset, multiple of 4 in range [0, 124]. 958e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 959e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 960ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 124 && (Val % 4) == 0; 961ecd858968384be029574d845eb098d357049e02eJim Grosbach } 96238466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach bool isMemThumbRIs2() const { 963e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 96457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 96538466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return false; 96638466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach // Immediate offset, multiple of 4 in range [0, 62]. 967e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 968e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 96938466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return Val >= 0 && Val <= 62 && (Val % 2) == 0; 97038466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 97148ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach bool isMemThumbRIs1() const { 972e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 97357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 97448ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return false; 97548ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach // Immediate offset in range [0, 31]. 976e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 977e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 97848ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return Val >= 0 && Val <= 31; 97948ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 980ecd858968384be029574d845eb098d357049e02eJim Grosbach bool isMemThumbSPI() const { 98157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 98257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 983ecd858968384be029574d845eb098d357049e02eJim Grosbach return false; 984ecd858968384be029574d845eb098d357049e02eJim Grosbach // Immediate offset, multiple of 4 in range [0, 1020]. 985e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 986e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 987ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 988505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 989a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isMemImm8s4Offset() const { 9902f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 9912f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 9922f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 99321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 9942f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 99557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 996a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return false; 997a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Immediate offset a multiple of 4 in range [-1020, 1020]. 998e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 999e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1000a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 1001a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1002b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach bool isMemImm0_1020s4Offset() const { 100357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1004b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return false; 1005b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // Immediate offset a multiple of 4 in range [0, 1020]. 1006e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1007e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1008b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1009b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 10107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm8Offset() const { 101157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1012f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling return false; 10130b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base reg of PC isn't allowed for these encodings. 10140b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum == ARM::PC) return false; 10157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-255, 255]. 1016e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1017e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10184d2a00147d19b17d382644de0d6a1f0d3230e0e4Owen Anderson return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1019f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1020f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach bool isMemPosImm8Offset() const { 102157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1022f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return false; 1023f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach // Immediate offset in range [0, 255]. 1024e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1025e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1026f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return Val >= 0 && Val < 256; 1027f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1028a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemNegImm8Offset() const { 102957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1030a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 10310b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base reg of PC isn't allowed for these encodings. 10320b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum == ARM::PC) return false; 1033a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [-255, -1]. 1034df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach if (!Memory.OffsetImm) return false; 1035e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1036df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1037a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1038a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemUImm12Offset() const { 103957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1040a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 1041a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [0, 4095]. 1042e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1043e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1044a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return (Val >= 0 && Val < 4096); 1045a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 10467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm12Offset() const { 104709176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 104809176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 104909176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // and we reject it. 105021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 105109176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return true; 105209176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 105357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1054ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling return false; 10557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 1056e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1057e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10580da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 10597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 10607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isPostIdxImm8() const { 106121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 10627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1063ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling if (!CE) return false; 10647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Val = CE->getValue(); 106563553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1066ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 10672bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isPostIdxImm8s4() const { 106821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 10692bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 10702bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (!CE) return false; 10712bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int64_t Val = CE->getValue(); 10722bd0118472de352745a2e038245fab4974f7c87eJim Grosbach return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 10732bd0118472de352745a2e038245fab4974f7c87eJim Grosbach (Val == INT32_MIN); 10742bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 10757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 107621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMSRMask() const { return Kind == k_MSRMask; } 107721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isProcIFlags() const { return Kind == k_ProcIFlags; } 10783483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 10790e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // NEON operands. 10800aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isSingleSpacedVectorList() const { 10810aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && !VectorList.isDoubleSpaced; 10820aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 10830aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpacedVectorList() const { 10840aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && VectorList.isDoubleSpaced; 10850aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 1086862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach bool isVecListOneD() const { 10870aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1088862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return VectorList.Count == 1; 1089862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1090862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 1091280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach bool isVecListTwoD() const { 10920aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1093280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach return VectorList.Count == 2; 1094280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach } 1095280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach 1096cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach bool isVecListThreeD() const { 10970aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1098cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach return VectorList.Count == 3; 1099cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach } 1100cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach 1101b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach bool isVecListFourD() const { 11020aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1103b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach return VectorList.Count == 4; 1104b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach } 1105b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach 11064661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach bool isVecListTwoQ() const { 11070aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isDoubleSpacedVectorList()) return false; 11080aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return VectorList.Count == 2; 11094661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach } 11104661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach 11113471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isSingleSpacedVectorAllLanes() const { 11123471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 11133471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 11143471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpacedVectorAllLanes() const { 11153471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 11163471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 111798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach bool isVecListOneDAllLanes() const { 11183471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 111998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return VectorList.Count == 1; 112098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 112198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 112213af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach bool isVecListTwoDAllLanes() const { 11233471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 11243471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return VectorList.Count == 2; 11253471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 11263471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach 11273471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isVecListTwoQAllLanes() const { 11283471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isDoubleSpacedVectorAllLanes()) return false; 112913af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach return VectorList.Count == 2; 113013af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach } 113113af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach 113295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isSingleSpacedVectorIndexed() const { 113395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 113495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 113595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpacedVectorIndexed() const { 113695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 113795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 11387636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach bool isVecListOneDByteIndexed() const { 113995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11407636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 11417636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 11427636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1143799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDHWordIndexed() const { 114495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1145799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1146799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1147799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1148799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDWordIndexed() const { 114995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1150799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1151799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1152799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 11539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach bool isVecListTwoDByteIndexed() const { 115495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 11569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 11579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 1158799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDHWordIndexed() const { 115995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 116095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 116195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 116295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 116395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQWordIndexed() const { 116495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 116595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 116695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 116795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 116895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQHWordIndexed() const { 116995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 1170799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1171799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1172799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1173799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDWordIndexed() const { 117495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1175799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1176799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1177799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1178460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex8() const { 1179460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1180460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 8; 1181460a90540b045c102012da2492999557e6840526Jim Grosbach } 1182460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex16() const { 1183460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1184460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 4; 1185460a90540b045c102012da2492999557e6840526Jim Grosbach } 1186460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex32() const { 1187460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1188460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 2; 1189460a90540b045c102012da2492999557e6840526Jim Grosbach } 1190460a90540b045c102012da2492999557e6840526Jim Grosbach 11910e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach bool isNEONi8splat() const { 119221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 11930e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 11940e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Must be a constant. 11950e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!CE) return false; 11960e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach int64_t Value = CE->getValue(); 11970e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // i8 value splatted across 8 bytes. The immediate is just the 8 byte 11980e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // value. 11990e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return Value >= 0 && Value < 256; 12000e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 1201460a90540b045c102012da2492999557e6840526Jim Grosbach 1202ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach bool isNEONi16splat() const { 120321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1204ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1205ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // Must be a constant. 1206ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (!CE) return false; 1207ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach int64_t Value = CE->getValue(); 1208ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // i16 value in the range [0,255] or [0x0100, 0xff00] 1209ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1210ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1211ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 12126248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32splat() const { 121321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12146248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12156248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 12166248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 12176248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 12186248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 12196248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 12206248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12216248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12226248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000); 12236248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 12246248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 12256248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32vmov() const { 122621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12276248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12286248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 12296248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 12306248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 12316248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 12326248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 12336248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 12346248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12356248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12366248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 12376248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 12386248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 12396248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 12409b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach bool isNEONi32vmovNeg() const { 124121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12429b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12439b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // Must be a constant. 12449b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (!CE) return false; 12459b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach int64_t Value = ~CE->getValue(); 12469b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 12479b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 12489b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach return (Value >= 0 && Value < 256) || 12499b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12509b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12519b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 12529b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 12539b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 12549b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 12556248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 1256f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach bool isNEONi64splat() const { 125721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1258f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1259f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // Must be a constant. 1260f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if (!CE) return false; 1261f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 1262f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // i64 value with each byte being either 0 or 0xff. 1263f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i) 1264f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1265f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach return true; 1266f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1267f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 12683483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addExpr(MCInst &Inst, const MCExpr *Expr) const { 126914b93851cc7611ae6c2000f1c162592ead954420Chris Lattner // Add as immediates when possible. Null MCExpr = 0. 127014b93851cc7611ae6c2000f1c162592ead954420Chris Lattner if (Expr == 0) 127114b93851cc7611ae6c2000f1c162592ead954420Chris Lattner Inst.addOperand(MCOperand::CreateImm(0)); 127214b93851cc7611ae6c2000f1c162592ead954420Chris Lattner else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 12733483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 12743483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar else 12753483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateExpr(Expr)); 12763483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar } 12773483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 12788462b30548fb5969250858036638c73c16b65b43Daniel Dunbar void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1279345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar assert(N == 2 && "Invalid number of operands!"); 12808462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 128104f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 128204f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegNum)); 12838462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 12848462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 1285fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1286fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1287fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1288fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1289fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 12909b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 12919b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 12929b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(getCoproc())); 12939b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 12949b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 12959b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 12969b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 12979b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 12989b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 12999b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 130089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITMaskOperands(MCInst &Inst, unsigned N) const { 130189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 130289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 130389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 130489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 130589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 130689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 130789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 130889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 130989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 1310d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach void addCCOutOperands(MCInst &Inst, unsigned N) const { 1311d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1312d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Inst.addOperand(MCOperand::CreateReg(getReg())); 1313d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 1314d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 1315a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby void addRegOperands(MCInst &Inst, unsigned N) const { 1316a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby assert(N == 1 && "Invalid number of operands!"); 1317a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby Inst.addOperand(MCOperand::CreateReg(getReg())); 1318a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1319a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 1320af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1321e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1322430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedReg() && 1323430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedRegOperands() on non RegShiftedReg!"); 1324af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1325af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1326e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Inst.addOperand(MCOperand::CreateImm( 1327af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1328e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 1329e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 1330af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1331152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(N == 2 && "Invalid number of operands!"); 1332430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedImm() && 1333430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedImmOperands() on non RegShiftedImm!"); 1334af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 133592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Inst.addOperand(MCOperand::CreateImm( 1336af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 133792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 133892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 1339580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach void addShifterImmOperands(MCInst &Inst, unsigned N) const { 13400082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(N == 1 && "Invalid number of operands!"); 1341580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1342580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm.Imm)); 13430082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 13440082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 134587f4f9a946549ad93046990a364ac5190333a7ebBill Wendling void addRegListOperands(MCInst &Inst, unsigned N) const { 13467729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling assert(N == 1 && "Invalid number of operands!"); 13475fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 13485fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 13497729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ++I) 13507729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling Inst.addOperand(MCOperand::CreateReg(*I)); 135187f4f9a946549ad93046990a364ac5190333a7ebBill Wendling } 135287f4f9a946549ad93046990a364ac5190333a7ebBill Wendling 13530f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 13540f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 13550f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 13560f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 13570f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 13580f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 13590f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 13600f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 13617e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach void addRotImmOperands(MCInst &Inst, unsigned N) const { 13627e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13637e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Encoded as val>>3. The printer handles display as 8, 16, 24. 13647e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 13657e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 13667e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 1367293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1368293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1369293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Munge the lsb/width into a bitfield mask. 1370293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned lsb = Bitfield.LSB; 1371293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned width = Bitfield.Width; 1372293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1373293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1374293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach (32 - (lsb + width))); 1375293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Mask)); 1376293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 1377293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 13783483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addImmOperands(MCInst &Inst, unsigned N) const { 13796b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13806b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach addExpr(Inst, getImm()); 13816b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 13826b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach 13834050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits16Operands(MCInst &Inst, unsigned N) const { 13844050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13854050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13864050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 13874050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 13884050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 13894050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits32Operands(MCInst &Inst, unsigned N) const { 13904050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13914050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13924050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 13934050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 13944050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 13959d39036f62674606565217a10db28171b9594bc7Jim Grosbach void addFPImmOperands(MCInst &Inst, unsigned N) const { 13969d39036f62674606565217a10db28171b9594bc7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13979d39036f62674606565217a10db28171b9594bc7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getFPImm())); 13989d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 13999d39036f62674606565217a10db28171b9594bc7Jim Grosbach 1400a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1401a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1402a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // FIXME: We really want to scale the value here, but the LDRD/STRD 1403a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // instruction don't encode operands that way yet. 1404a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1405a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1406a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1407a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 140872f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 140972f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 141072f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 141172f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 141272f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 141372f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 141472f39f8436848885176943b0ba985a7171145423Jim Grosbach } 141572f39f8436848885176943b0ba985a7171145423Jim Grosbach 141672f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 141772f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 141872f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 141972f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 142072f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 142172f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 142272f39f8436848885176943b0ba985a7171145423Jim Grosbach } 142372f39f8436848885176943b0ba985a7171145423Jim Grosbach 1424f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1425f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1426f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 1427f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // the bits as encoded, so subtract off one here. 1428f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1429f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1430f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 1431f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach 14324a5ffb399f841783c201c599b88d576757f1922eJim Grosbach void addImm1_32Operands(MCInst &Inst, unsigned N) const { 14334a5ffb399f841783c201c599b88d576757f1922eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14344a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 14354a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // the bits as encoded, so subtract off one here. 14364a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14374a5ffb399f841783c201c599b88d576757f1922eJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 14384a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 14394a5ffb399f841783c201c599b88d576757f1922eJim Grosbach 144070939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 144170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 144270939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // The constant encodes as the immediate, except for 32, which encodes as 144370939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // zero. 144470939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 144570939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach unsigned Imm = CE->getValue(); 144670939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1447ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 1448ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 1449f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1450f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1451f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // An ASR value of 32 encodes as 0, so that's how we want to add it to 1452f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // the instruction as well. 1453f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1454f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 1455f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1456f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 1457f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 145889a633708542de5847e807f98f86edfefc9fc019Jim Grosbach void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 145989a633708542de5847e807f98f86edfefc9fc019Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 146089a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // The operand is actually a t2_so_imm, but we have its bitwise 146189a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // negation in the assembly source, so twiddle it here. 146289a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 146389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 146489a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 146589a633708542de5847e807f98f86edfefc9fc019Jim Grosbach 14663bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 14673bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14683bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a t2_so_imm, but we have its 14693bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 14703bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14713bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 14723bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 14733bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 1474e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1475e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1476e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // The operand is actually a so_imm, but we have its bitwise 1477e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // negation in the assembly source, so twiddle it here. 1478e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1479e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1480e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 1481e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach 14823bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 14833bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14843bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a so_imm, but we have its 14853bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 14863bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14873bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 14883bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 14893bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 1490706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1491706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1492706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1493706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 1494706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 14957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 14967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1497e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1498505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 1499505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes 15000b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 15010b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 15020b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach int32_t Imm = Memory.OffsetImm->getValue(); 15030b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // FIXME: Handle #-0 15040b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Imm == INT32_MIN) Imm = 0; 15050b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 15060b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach } 15070b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach 150857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 150957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 151057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 151157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 151257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 151357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 15147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 15157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1516e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1517e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 15187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 15207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 15217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 15227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 15237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else { 15247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // For register offset, we encode the shift type and negation flag 15257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // here. 1526e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1527e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory.ShiftImm, Memory.ShiftType); 1528ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1529e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1530e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 15317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1532ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1533ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 1534039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1535039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1536039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1537039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(CE && "non-constant AM2OffsetImm operand!"); 1538039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int32_t Val = CE->getValue(); 1539039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1540039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Special case for #-0 1541039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val == INT32_MIN) Val = 0; 1542039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val < 0) Val = -Val; 1543039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1544039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 1545039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1546039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 1547039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach 15482fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 15492fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 15502f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 15512f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 15522f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 15532f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 15542f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 15552f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 15562f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 15572f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 15582f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 15592f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1560e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1561e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 15622fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15632fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 15642fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 15652fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 15662fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 15672fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } else { 15682fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // For register offset, we encode the shift type and negation flag 15692fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // here. 1570e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 15712fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 1572e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1573e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 15742fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 15752fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 15762fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 15772fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 15782fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 157921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) { 15802fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = 15812fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 15822fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 15832fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1584251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return; 15852fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 15862fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 15872fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Constant offset. 15882fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 15892fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = CE->getValue(); 15902fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15912fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 15922fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 15932fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 1594251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 15952fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 15962fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 15972fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 15982fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 15997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 16007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1601681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 1602681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 1603681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 1604681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach if (isImm()) { 1605681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 1606681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1607681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return; 1608681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach } 1609681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach 16107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1611e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 16127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 16137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 16147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 16157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 16167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM5Opc(AddSub, Val); 1617e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 16187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 16197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 16207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 1621a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1622a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 16232f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 16242f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 16252f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 16262f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 16272f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 16282f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 16292f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 16302f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 16312f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1632e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1633e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1634a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1635a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1636a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 1637b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1638b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1639b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1640e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1641e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1642b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1643b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 1644b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 16457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 16467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1647e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1648e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 16497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1650ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 1651ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 1652f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1653f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1654f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1655f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach 1656a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1657f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1658a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1659a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1660a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1661a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1662a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // If this is an immediate, it's a label reference. 166321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 1664a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach addExpr(Inst, getImm()); 1665a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1666a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return; 1667a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1668a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1669a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1670e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1671e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1672a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1673a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1674a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 16757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 16767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 167709176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If this is an immediate, it's a label reference. 167821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 167909176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach addExpr(Inst, getImm()); 168009176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 168109176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return; 168209176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach } 168309176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 168409176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1685e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1686e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 16877ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 16887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 168992b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 16907f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBBOperands(MCInst &Inst, unsigned N) const { 16917f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1692e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1693e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 16947f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 16957f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 16967f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBHOperands(MCInst &Inst, unsigned N) const { 16977f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1698e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1699e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 17007f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 17017f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 17027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 17037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1704430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach unsigned Val = 1705430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1706430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach Memory.ShiftImm, Memory.ShiftType); 1707e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1708e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 17097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 17107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 1711d3df5f32c059b3ac111f1c08571d5493aa1d48c6Daniel Dunbar 1712ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1713ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1714e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1715e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1716e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1717ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 1718ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach 17197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 17207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1721e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1722e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 172314b93851cc7611ae6c2000f1c162592ead954420Chris Lattner } 17243483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 172560f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 172660f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1727e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1728e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 172960f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 173048ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 173148ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach 173238466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 173338466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1734e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1735e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 173638466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 173738466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 173838466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach 173948ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 174048ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1741e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1742e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 174348ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 174460f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 174560f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach 1746ecd858968384be029574d845eb098d357049e02eJim Grosbach void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1747ecd858968384be029574d845eb098d357049e02eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1748e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1749e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1750ecd858968384be029574d845eb098d357049e02eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1751ecd858968384be029574d845eb098d357049e02eJim Grosbach } 1752ecd858968384be029574d845eb098d357049e02eJim Grosbach 17537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 17547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 17557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 17567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(CE && "non-constant post-idx-imm8 operand!"); 17577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Imm = CE->getValue(); 17587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAdd = Imm >= 0; 175963553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson if (Imm == INT32_MIN) Imm = 0; 17607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 17617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1762f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1763ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 17642bd0118472de352745a2e038245fab4974f7c87eJim Grosbach void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 17652bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 17662bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 17672bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(CE && "non-constant post-idx-imm8s4 operand!"); 17682bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int Imm = CE->getValue(); 17692bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isAdd = Imm >= 0; 17702bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (Imm == INT32_MIN) Imm = 0; 17712bd0118472de352745a2e038245fab4974f7c87eJim Grosbach // Immediate is scaled by 4. 17722bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 17732bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 17742bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 17752bd0118472de352745a2e038245fab4974f7c87eJim Grosbach 17767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 17777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 17787ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1779f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1780f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 1781f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 1782f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1783f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1784f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1785f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // The sign, shift type, and shift amount are encoded in a single operand 1786f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // using the AM2 encoding helpers. 1787f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1788f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1789f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach PostIdxReg.ShiftTy); 1790f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1791ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 1792ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 1793584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1794584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1795584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1796584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 1797584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 1798a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1799a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1800a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1801a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 1802a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 18036029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach void addVecListOperands(MCInst &Inst, unsigned N) const { 1804862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1805862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1806862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1807862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 18087636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 18097636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 18107636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 18117636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 18127636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 18137636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1814460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1815460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1816460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1817460a90540b045c102012da2492999557e6840526Jim Grosbach } 1818460a90540b045c102012da2492999557e6840526Jim Grosbach 1819460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1820460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1821460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1822460a90540b045c102012da2492999557e6840526Jim Grosbach } 1823460a90540b045c102012da2492999557e6840526Jim Grosbach 1824460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1825460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1826460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1827460a90540b045c102012da2492999557e6840526Jim Grosbach } 1828460a90540b045c102012da2492999557e6840526Jim Grosbach 18290e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 18300e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18310e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // The immediate encodes the type of constant as well as the value. 18320e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Mask in that this is an i8 splat. 18330e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18340e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 18350e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 18360e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 1837ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1838ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1839ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // The immediate encodes the type of constant as well as the value. 1840ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1841ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach unsigned Value = CE->getValue(); 1842ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (Value >= 256) 1843ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value = (Value >> 8) | 0xa00; 1844ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach else 1845ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value |= 0x800; 1846ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 1847ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1848ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 18496248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 18506248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18516248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 18526248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18536248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 18546248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xff00) 18556248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | 0x200; 18566248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xff0000) 18576248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | 0x400; 18586248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 18596248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 18606248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 18616248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 18626248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 18636248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 18646248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18656248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 18666248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18676248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 18686248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xffff) 18696248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 18706248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 18716248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 18726248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 18736248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 18749b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 18759b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 18769b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach 18779b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 18789b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18799b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // The immediate encodes the type of constant as well as the value. 18809b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18819b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach unsigned Value = ~CE->getValue(); 18829b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (Value >= 256 && Value <= 0xffff) 18839b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 18849b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 18859b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 18869b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffffff) 18879b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 24) | 0x600; 18886248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 18896248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 18906248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 1891f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 1892f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1893f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // The immediate encodes the type of constant as well as the value. 1894f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1895f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 1896f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach unsigned Imm = 0; 1897f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 1898f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Imm |= (Value & 1) << i; 1899f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1900f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 1901f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1902f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 1903b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbach virtual void print(raw_ostream &OS) const; 1904b3cb6967949493a2e1b10d015ac08b746736764eDaniel Dunbar 190589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 190621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ITCondMask); 190789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->ITMask.Mask = Mask; 190889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->StartLoc = S; 190989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->EndLoc = S; 191089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return Op; 191189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 191289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 19133a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 191421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CondCode); 1915345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->CC.Val = CC; 1916345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->StartLoc = S; 1917345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->EndLoc = S; 19183a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1919345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar } 1920345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 1921fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 192221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocNum); 1923fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 1924fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 1925fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 1926fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 1927fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1928fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 1929fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 193021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocReg); 1931fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 1932fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 1933fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 1934fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 1935fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1936fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 19379b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 19389b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocOption); 19399b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->Cop.Val = Val; 19409b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->StartLoc = S; 19419b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->EndLoc = E; 19429b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return Op; 19439b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 19449b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 1945d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 194621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CCOut); 1947d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->Reg.RegNum = RegNum; 1948d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->StartLoc = S; 1949d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->EndLoc = S; 1950d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach return Op; 1951d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 1952d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 19533a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 195421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Token); 1955762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Data = Str.data(); 1956762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Length = Str.size(); 1957762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 1958762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = S; 19593a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1960a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1961a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 196250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 196321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Register); 1964762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Reg.RegNum = RegNum; 1965762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 1966762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 19673a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1968a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1969a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 1970e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1971e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg, 1972e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg, 1973e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm, 1974e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc S, SMLoc E) { 197521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 1976af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftTy = ShTy; 1977af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.SrcReg = SrcReg; 1978af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftReg = ShiftReg; 1979af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftImm = ShiftImm; 1980e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->StartLoc = S; 1981e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->EndLoc = E; 1982e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Op; 1983e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 1984e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 198592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 198692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg, 198792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm, 198892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson SMLoc S, SMLoc E) { 198921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 1990af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftTy = ShTy; 1991af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.SrcReg = SrcReg; 1992af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftImm = ShiftImm; 199392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->StartLoc = S; 199492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->EndLoc = E; 199592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson return Op; 199692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 199792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 1998580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 19990082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S, SMLoc E) { 200021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2001580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.isASR = isASR; 2002580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.Imm = Imm; 20030082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->StartLoc = S; 20040082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->EndLoc = E; 20050082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return Op; 20060082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 20070082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 20087e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 200921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_RotateImmediate); 20107e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->RotImm.Imm = Imm; 20117e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->StartLoc = S; 20127e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->EndLoc = E; 20137e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return Op; 20147e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 20157e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 2016293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2017293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S, SMLoc E) { 201821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2019293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.LSB = LSB; 2020293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.Width = Width; 2021293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->StartLoc = S; 2022293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->EndLoc = E; 2023293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return Op; 2024293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 2025293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 20267729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling static ARMOperand * 20275fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2028cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay SMLoc StartLoc, SMLoc EndLoc) { 202921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach KindTy Kind = k_RegisterList; 20300f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 2031d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 203221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_DPRRegisterList; 2033d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2034275944afb55086d0b4b20d4d831de7c1c7507925Evan Cheng contains(Regs.front().first)) 203521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_SPRRegisterList; 20360f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 20370f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling ARMOperand *Op = new ARMOperand(Kind); 20385fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 20397729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = Regs.begin(), E = Regs.end(); I != E; ++I) 204024d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Op->Registers.push_back(I->first); 2041cb21d1c9fd1cf53f063183f7eb28af7fa4052ef0Bill Wendling array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2042cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->StartLoc = StartLoc; 2043cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->EndLoc = EndLoc; 20448d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling return Op; 20458d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 20468d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 2047862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 20480aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced, SMLoc S, SMLoc E) { 2049862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorList); 2050862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.RegNum = RegNum; 2051862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.Count = Count; 20520aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2053862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->StartLoc = S; 2054862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->EndLoc = E; 2055862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return Op; 2056862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 2057862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 205898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 20593471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpaced, 206098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc S, SMLoc E) { 206198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 206298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.RegNum = RegNum; 206398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.Count = Count; 20643471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 206598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->StartLoc = S; 206698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->EndLoc = E; 206798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Op; 206898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 206998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 20707636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 207195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Index, 207295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpaced, 207395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach SMLoc S, SMLoc E) { 20747636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 20757636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.RegNum = RegNum; 20767636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.Count = Count; 20777636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.LaneIndex = Index; 207895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 20797636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->StartLoc = S; 20807636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->EndLoc = E; 20817636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return Op; 20827636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 20837636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 2084460a90540b045c102012da2492999557e6840526Jim Grosbach static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2085460a90540b045c102012da2492999557e6840526Jim Grosbach MCContext &Ctx) { 2086460a90540b045c102012da2492999557e6840526Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorIndex); 2087460a90540b045c102012da2492999557e6840526Jim Grosbach Op->VectorIndex.Val = Idx; 2088460a90540b045c102012da2492999557e6840526Jim Grosbach Op->StartLoc = S; 2089460a90540b045c102012da2492999557e6840526Jim Grosbach Op->EndLoc = E; 2090460a90540b045c102012da2492999557e6840526Jim Grosbach return Op; 2091460a90540b045c102012da2492999557e6840526Jim Grosbach } 2092460a90540b045c102012da2492999557e6840526Jim Grosbach 20933a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 209421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Immediate); 2095762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Imm.Val = Val; 2096762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2097762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 20983a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2099cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 2100cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 21019d39036f62674606565217a10db28171b9594bc7Jim Grosbach static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) { 210221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_FPImmediate); 21039d39036f62674606565217a10db28171b9594bc7Jim Grosbach Op->FPImm.Val = Val; 21049d39036f62674606565217a10db28171b9594bc7Jim Grosbach Op->StartLoc = S; 21059d39036f62674606565217a10db28171b9594bc7Jim Grosbach Op->EndLoc = S; 21069d39036f62674606565217a10db28171b9594bc7Jim Grosbach return Op; 21079d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 21089d39036f62674606565217a10db28171b9594bc7Jim Grosbach 21097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach static ARMOperand *CreateMem(unsigned BaseRegNum, 21107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm, 21117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum, 21127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType, 21130d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm, 211457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment, 21157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative, 21163a69756e392942bc522193f38d7f33958ed3b131Chris Lattner SMLoc S, SMLoc E) { 211721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Memory); 2118e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.BaseRegNum = BaseRegNum; 2119e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetImm = OffsetImm; 2120e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetRegNum = OffsetRegNum; 2121e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftType = ShiftType; 2122e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftImm = ShiftImm; 212357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Op->Memory.Alignment = Alignment; 2124e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.isNegative = isNegative; 21257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->StartLoc = S; 21267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->EndLoc = E; 21277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Op; 21287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 212916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2130f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2131f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy, 2132f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm, 21337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S, SMLoc E) { 213421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 21357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->PostIdxReg.RegNum = RegNum; 2136f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.isAdd = isAdd; 2137f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftTy = ShiftTy; 2138f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftImm = ShiftImm; 2139762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2140762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 21413a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2142a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 2143706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 2144706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 214521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2146706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->MBOpt.Val = Opt; 2147706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->StartLoc = S; 2148706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->EndLoc = S; 2149706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return Op; 2150706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 2151a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 2152a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 215321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2154a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->IFlags.Val = IFlags; 2155a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->StartLoc = S; 2156a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->EndLoc = S; 2157a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return Op; 2158a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 2159584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 2160584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 216121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MSRMask); 2162584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->MMask.Val = MMask; 2163584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->StartLoc = S; 2164584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->EndLoc = S; 2165584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return Op; 2166584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 2167a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby}; 2168a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2169a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} // end anonymous namespace. 2170a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2171b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbachvoid ARMOperand::print(raw_ostream &OS) const { 2172fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar switch (Kind) { 217321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_FPImmediate: 21749d39036f62674606565217a10db28171b9594bc7Jim Grosbach OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm()) 21759d39036f62674606565217a10db28171b9594bc7Jim Grosbach << ") >"; 21769d39036f62674606565217a10db28171b9594bc7Jim Grosbach break; 217721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 21786a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2179fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 218021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 2181d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach OS << "<ccout " << getReg() << ">"; 2182d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach break; 218321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: { 21841a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer static const char *MaskStr[] = { 21851a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 21861a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 21871a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer }; 218889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert((ITMask.Mask & 0xf) == ITMask.Mask); 218989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 219089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 219189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 219221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 2193fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor number: " << getCoproc() << ">"; 2194fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 219521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 2196fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor register: " << getCoproc() << ">"; 2197fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 21989b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 21999b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OS << "<coprocessor option: " << CoprocOption.Val << ">"; 22009b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 220121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 2202584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes OS << "<mask: " << getMSRMask() << ">"; 2203584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 220421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 2205fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar getImm()->print(OS); 2206fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 220721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 2208706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2209706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 221021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 22116ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << "<memory " 2212e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach << " base:" << Memory.BaseRegNum; 22136ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << ">"; 2214fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 221521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 2216f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2217f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.RegNum; 2218f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2219f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2220f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.ShiftImm; 2221f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ">"; 22227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 222321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: { 2224a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << "<ARM_PROC::"; 2225a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = getProcIFlags(); 2226a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes for (int i=2; i >= 0; --i) 2227a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IFlags & (1 << i)) 2228a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ARM_PROC::IFlagsToString(1 << i); 2229a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ">"; 2230a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes break; 2231a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 223221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 223350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling OS << "<register " << getReg() << ">"; 2234fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 223521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 2236580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2237580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach << " #" << ShifterImm.Imm << ">"; 2238e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 223921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 224092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_reg " 2241efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedReg.SrcReg << " " 2242efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2243efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " " << RegShiftedReg.ShiftReg << ">"; 22440082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 224521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 224692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_imm " 2247efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedImm.SrcReg << " " 2248efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2249efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " #" << RegShiftedImm.ShiftImm << ">"; 225092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 225121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 22527e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 22537e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 225421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 2255293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OS << "<bitfield " << "lsb: " << Bitfield.LSB 2256293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach << ", width: " << Bitfield.Width << ">"; 2257293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 225821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 225921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 226021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: { 22618d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << "<register_list "; 22628d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 22635fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 22645fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 22657729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ) { 22667729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling OS << *I; 22677729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling if (++I < E) OS << ", "; 22688d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 22698d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 22708d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << ">"; 22718d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 22728d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 2273862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 2274862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OS << "<vector_list " << VectorList.Count << " * " 2275862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach << VectorList.RegNum << ">"; 2276862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 227798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 227898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach OS << "<vector_list(all lanes) " << VectorList.Count << " * " 227998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach << VectorList.RegNum << ">"; 228098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 22817636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 22827636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 22837636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach << VectorList.Count << " * " << VectorList.RegNum << ">"; 22847636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 228521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 2286fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar OS << "'" << getToken() << "'"; 2287fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 2288460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 2289460a90540b045c102012da2492999557e6840526Jim Grosbach OS << "<vectorindex " << getVectorIndex() << ">"; 2290460a90540b045c102012da2492999557e6840526Jim Grosbach break; 2291fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar } 2292fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar} 22933483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 22943483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// @name Auto-generated Match Functions 22953483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// { 22963483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 22973483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbarstatic unsigned MatchRegisterName(StringRef Name); 22983483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 22993483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// } 23003483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 230169df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilsonbool ARMAsmParser::ParseRegister(unsigned &RegNo, 230269df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson SMLoc &StartLoc, SMLoc &EndLoc) { 2303a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StartLoc = Parser.getTok().getLoc(); 23041355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach RegNo = tryParseRegister(); 2305a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach EndLoc = Parser.getTok().getLoc(); 2306bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 2307bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky return (RegNo == (unsigned)-1); 2308bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky} 2309bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 23109c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Try to parse a register name. The token must be an Identifier when called, 2311e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// and if it is a register name the token is eaten and the register number is 2312e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// returned. Otherwise return -1. 23133a69756e392942bc522193f38d7f33958ed3b131Chris Lattner/// 23141355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachint ARMAsmParser::tryParseRegister() { 231518b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 23167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) return -1; 2317d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 2318590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 23190c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson unsigned RegNum = MatchRegisterName(lowerCase); 23200c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson if (!RegNum) { 23210c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson RegNum = StringSwitch<unsigned>(lowerCase) 23220c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r13", ARM::SP) 23230c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r14", ARM::LR) 23240c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r15", ARM::PC) 23250c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("ip", ARM::R12) 232640e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach // Additional register name aliases for 'gas' compatibility. 232740e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a1", ARM::R0) 232840e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a2", ARM::R1) 232940e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a3", ARM::R2) 233040e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a4", ARM::R3) 233140e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v1", ARM::R4) 233240e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v2", ARM::R5) 233340e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v3", ARM::R6) 233440e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v4", ARM::R7) 233540e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v5", ARM::R8) 233640e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v6", ARM::R9) 233740e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v7", ARM::R10) 233840e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v8", ARM::R11) 233940e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sb", ARM::R9) 234040e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sl", ARM::R10) 234140e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("fp", ARM::R11) 23420c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Default(0); 23430c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson } 2344a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (!RegNum) { 2345aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // Check for aliases registered via .req. Canonicalize to lower case. 2346aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // That's more consistent since register names are case insensitive, and 2347aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // it's how the original entry was passed in from MC/MCParser/AsmParser. 2348aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2349a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // If no match, return failure. 2350a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Entry == RegisterReqs.end()) 2351a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return -1; 2352a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat identifier token. 2353a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Entry->getValue(); 2354a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 235569df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson 2356b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat identifier token. 2357460a90540b045c102012da2492999557e6840526Jim Grosbach 2358e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner return RegNum; 2359e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner} 2360d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 236119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 236219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// If a recoverable error occurs, return 1. If an irrecoverable error 236319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// occurs, return -1. An irrecoverable error is one where tokens have been 236419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// consumed in the process of trying to parse the shifter (i.e., when it is 236519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// indeed a shifter operand, but malformed). 23660d87ec21d79c8622733b8367aa41067169602480Jim Grosbachint ARMAsmParser::tryParseShiftRegister( 23670082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 23680082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 23690082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson const AsmToken &Tok = Parser.getTok(); 23700082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 23710082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2372590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 23730082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2374af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach .Case("asl", ARM_AM::lsl) 23750082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsl", ARM_AM::lsl) 23760082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsr", ARM_AM::lsr) 23770082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("asr", ARM_AM::asr) 23780082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("ror", ARM_AM::ror) 23790082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("rrx", ARM_AM::rrx) 23800082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Default(ARM_AM::no_shift); 23810082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 23820082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson if (ShiftTy == ARM_AM::no_shift) 238319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 1; 23840082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2385e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat the operator. 2386e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 2387e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The source register for the shift has already been added to the 2388e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // operand list, so we need to pop it off and combine it into the shifted 2389e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // register operand instead. 2390eac0796542d098caa371856d545faa6cdab5aad3Benjamin Kramer OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2391e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (!PrevOp->isReg()) 2392e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2393e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int SrcReg = PrevOp->getReg(); 2394e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int64_t Imm = 0; 2395e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int ShiftReg = 0; 2396e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (ShiftTy == ARM_AM::rrx) { 2397e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // RRX Doesn't have an explicit shift amount. The encoder expects 2398e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // the shift register to be the same as the source register. Seems odd, 2399e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // but OK. 2400e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ShiftReg = SrcReg; 2401e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else { 2402e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Figure out if this is shifted by a constant or a register (for non-RRX). 24038a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 24048a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 2405e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat hash. 2406e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc ImmLoc = Parser.getTok().getLoc(); 2407e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCExpr *ShiftExpr = 0; 240819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (getParser().ParseExpression(ShiftExpr)) { 240919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 241019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 241119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2412e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The expression must be evaluatable as an immediate. 2413e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 241419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (!CE) { 241519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 241619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 241719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2418e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Range check the immediate. 2419e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsl, ror: 0 <= imm <= 31 2420e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsr, asr: 0 <= imm <= 32 2421e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Imm = CE->getValue(); 2422e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (Imm < 0 || 2423e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2424e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 242519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "immediate shift value out of range"); 242619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 2427e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2428de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // shift by zero is a nop. Always send it through as lsl. 2429de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // ('as' compatibility) 2430de626ad8726677328e10dbdc15011254214437d7Jim Grosbach if (Imm == 0) 2431de626ad8726677328e10dbdc15011254214437d7Jim Grosbach ShiftTy = ARM_AM::lsl; 2432e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else if (Parser.getTok().is(AsmToken::Identifier)) { 24331355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach ShiftReg = tryParseRegister(); 2434e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc L = Parser.getTok().getLoc(); 243519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (ShiftReg == -1) { 243619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (L, "expected immediate or register in shift operand"); 243719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 243819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 243919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } else { 244019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (Parser.getTok().getLoc(), 2441e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach "expected immediate or register in shift operand"); 244219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 244319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2444e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2445e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 244692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson if (ShiftReg && ShiftTy != ARM_AM::rrx) 244792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2448af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ShiftReg, Imm, 24490082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson S, Parser.getTok().getLoc())); 245092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson else 245192a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 245292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson S, Parser.getTok().getLoc())); 24530082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 245419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 0; 24550082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson} 24560082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 24570082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 245850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// Try to parse a register name. The token must be an Identifier when called. 245950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// If it's a register, an AsmOperand is created. Another AsmOperand is created 246050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// if there is a "writeback". 'true' if it's not a register. 2461e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// 2462e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// TODO this is likely to change to allow different register types and or to 2463e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// parse for a specific register type. 246450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 24651355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachtryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2466e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner SMLoc S = Parser.getTok().getLoc(); 24671355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int RegNo = tryParseRegister(); 2468e717610f53e0465cde198536561a3c00ce29d59fBill Wendling if (RegNo == -1) 246950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 2470d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 247150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2472a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2473e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner const AsmToken &ExclaimTok = Parser.getTok(); 2474e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner if (ExclaimTok.is(AsmToken::Exclaim)) { 247550d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 247650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling ExclaimTok.getLoc())); 2477e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner Parser.Lex(); // Eat exclaim token 2478460a90540b045c102012da2492999557e6840526Jim Grosbach return false; 2479460a90540b045c102012da2492999557e6840526Jim Grosbach } 2480460a90540b045c102012da2492999557e6840526Jim Grosbach 2481460a90540b045c102012da2492999557e6840526Jim Grosbach // Also check for an index operand. This is only legal for vector registers, 2482460a90540b045c102012da2492999557e6840526Jim Grosbach // but that'll get caught OK in operand matching, so we don't need to 2483460a90540b045c102012da2492999557e6840526Jim Grosbach // explicitly filter everything else out here. 2484460a90540b045c102012da2492999557e6840526Jim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 2485460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc SIdx = Parser.getTok().getLoc(); 2486460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat left bracket token. 2487460a90540b045c102012da2492999557e6840526Jim Grosbach 2488460a90540b045c102012da2492999557e6840526Jim Grosbach const MCExpr *ImmVal; 2489460a90540b045c102012da2492999557e6840526Jim Grosbach if (getParser().ParseExpression(ImmVal)) 2490460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2491460a90540b045c102012da2492999557e6840526Jim Grosbach const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2492460a90540b045c102012da2492999557e6840526Jim Grosbach if (!MCE) { 2493460a90540b045c102012da2492999557e6840526Jim Grosbach TokError("immediate value expected for vector index"); 2494460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2495460a90540b045c102012da2492999557e6840526Jim Grosbach } 2496460a90540b045c102012da2492999557e6840526Jim Grosbach 2497460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2498460a90540b045c102012da2492999557e6840526Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) { 2499460a90540b045c102012da2492999557e6840526Jim Grosbach Error(E, "']' expected"); 2500460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2501460a90540b045c102012da2492999557e6840526Jim Grosbach } 2502460a90540b045c102012da2492999557e6840526Jim Grosbach 2503460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat right bracket token. 2504460a90540b045c102012da2492999557e6840526Jim Grosbach 2505460a90540b045c102012da2492999557e6840526Jim Grosbach Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2506460a90540b045c102012da2492999557e6840526Jim Grosbach SIdx, E, 2507460a90540b045c102012da2492999557e6840526Jim Grosbach getContext())); 250899e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby } 250999e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby 251050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2511a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 2512a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2513fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2514fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2515fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// "c5", ... 2516fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopesstatic int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2517e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Use the same layout as the tablegen'erated register name matcher. Ugly, 2518e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // but efficient. 2519e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name.size()) { 2520e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: break; 2521e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 2: 2522fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp) 2523e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2524e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[1]) { 2525e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2526e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 0; 2527e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 1; 2528e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 2; 2529e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 3; 2530e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 4; 2531e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 5; 2532e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '6': return 6; 2533e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '7': return 7; 2534e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '8': return 8; 2535e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '9': return 9; 2536e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2537e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson break; 2538e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 3: 2539fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp || Name[1] != '1') 2540e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2541e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[2]) { 2542e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2543e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 10; 2544e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 11; 2545e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 12; 2546e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 13; 2547e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 14; 2548e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 15; 2549e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2550e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson break; 2551e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2552e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2553e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2554e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2555e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 255689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach/// parseITCondCode - Try to parse a condition code for an IT instruction. 255789df996ab20609676ecc8823f58414d598b09b46Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 255889df996ab20609676ecc8823f58414d598b09b46Jim GrosbachparseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 255989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 256089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach const AsmToken &Tok = Parser.getTok(); 256189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (!Tok.is(AsmToken::Identifier)) 256289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 256389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned CC = StringSwitch<unsigned>(Tok.getString()) 256489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("eq", ARMCC::EQ) 256589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ne", ARMCC::NE) 256689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hs", ARMCC::HS) 256789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cs", ARMCC::HS) 256889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lo", ARMCC::LO) 256989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cc", ARMCC::LO) 257089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("mi", ARMCC::MI) 257189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("pl", ARMCC::PL) 257289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vs", ARMCC::VS) 257389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vc", ARMCC::VC) 257489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hi", ARMCC::HI) 257589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ls", ARMCC::LS) 257689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ge", ARMCC::GE) 257789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lt", ARMCC::LT) 257889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("gt", ARMCC::GT) 257989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("le", ARMCC::LE) 258089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("al", ARMCC::AL) 258189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Default(~0U); 258289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (CC == ~0U) 258389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 258489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.Lex(); // Eat the token. 258589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 258689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 258789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 258889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_Success; 258989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach} 259089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 259143904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2592fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2593fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2594f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 259543904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2596e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 2597e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson const AsmToken &Tok = Parser.getTok(); 2598c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2599c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2600e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2601fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2602e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson if (Num == -1) 2603f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2604e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2605e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson Parser.Lex(); // Eat identifier token. 2606fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2607f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2608fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes} 2609fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 261043904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2611fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2612fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2613f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 261443904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2615fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 2616fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 2617c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2618c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2619fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2620fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2621fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Reg == -1) 2622f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2623fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2624fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 2625fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2626f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2627e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2628e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 26299b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 26309b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// coproc_option : '{' imm0_255 '}' 26319b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 26329b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachparseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 26339b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc S = Parser.getTok().getLoc(); 26349b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26359b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // If this isn't a '{', this isn't a coprocessor immediate operand. 26369b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 26379b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_NoMatch; 26389b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '{' 26399b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26409b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCExpr *Expr; 26419b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 26429b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (getParser().ParseExpression(Expr)) { 26439b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "illegal expression"); 26449b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26459b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 26469b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 26479b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 26489b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 26499b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26509b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 26519b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach int Val = CE->getValue(); 26529b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26539b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // Check for and consume the closing '}' 26549b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 26559b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26569b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc E = Parser.getTok().getLoc(); 26579b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '}' 26589b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26599b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 26609b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_Success; 26619b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach} 26629b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 2663d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// For register list parsing, we need to map from raw GPR register numbering 2664d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// to the enumeration values. The enumeration values aren't sorted by 2665d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// register number due to our using "sp", "lr" and "pc" as canonical names. 2666d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbachstatic unsigned getNextRegister(unsigned Reg) { 2667d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If this is a GPR, we need to do it manually, otherwise we can rely 2668d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // on the sort ordering of the enumeration since the other reg-classes 2669d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // are sane. 2670d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2671d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Reg + 1; 2672d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach switch(Reg) { 2673d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach default: assert(0 && "Invalid GPR number!"); 2674d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2675d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2676d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2677d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2678d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2679d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2680d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2681d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2682d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2683d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach} 2684d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2685ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach// Return the low-subreg of a given Q register. 2686ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbachstatic unsigned getDRegFromQReg(unsigned QReg) { 2687ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach switch (QReg) { 2688ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach default: llvm_unreachable("expected a Q register!"); 2689ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q0: return ARM::D0; 2690ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q1: return ARM::D2; 2691ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q2: return ARM::D4; 2692ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q3: return ARM::D6; 2693ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q4: return ARM::D8; 2694ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q5: return ARM::D10; 2695ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q6: return ARM::D12; 2696ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q7: return ARM::D14; 2697ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q8: return ARM::D16; 269825e0a87e9190cdca62aee5ac95cfc8ef44f35e92Jim Grosbach case ARM::Q9: return ARM::D18; 2699ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q10: return ARM::D20; 2700ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q11: return ARM::D22; 2701ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q12: return ARM::D24; 2702ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q13: return ARM::D26; 2703ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q14: return ARM::D28; 2704ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q15: return ARM::D30; 2705ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2706ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach} 2707ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2708d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach/// Parse a register list. 270950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 27101355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachparseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 271118b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LCurly) && 2712a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Curly Brace"); 2713e717610f53e0465cde198536561a3c00ce29d59fBill Wendling SMLoc S = Parser.getTok().getLoc(); 2714d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '{' token. 2715d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 271616c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2717d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Check the first register in the list to see what register class 2718d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // this is a list of. 2719d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int Reg = tryParseRegister(); 2720d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 2721d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "register expected"); 2722d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2723ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // The reglist instructions have at most 16 registers, so reserve 2724ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // space for that many. 2725ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2726ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2727ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2728ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2729ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2730ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2731ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach ++Reg; 2732ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 27331a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCRegisterClass *RC; 2734d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2735d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2736d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2737d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2738d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2739d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2740d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else 2741d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2742e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 2743ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Store the register. 2744d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2745d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2746d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // This starts immediately after the first register token in the list, 2747d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // so we can see either a comma or a minus (range separator) as a legal 2748d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // next token. 2749d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 2750d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 2751d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 2752e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 2753d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 2754d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int EndReg = tryParseRegister(); 2755d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (EndReg == -1) 2756d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "register expected"); 2757ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2758ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2759ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 2760d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If the register is the same as the start reg, there's nothing 2761d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // more to do. 2762d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == EndReg) 2763d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2764d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2765d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(EndReg)) 2766d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "invalid register in register list"); 2767d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Ranges must go from low to high. 2768d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2769d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "bad range in register list"); 2770d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2771d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Add all the registers in the range to the register list. 2772d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Reg != EndReg) { 2773d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = getNextRegister(Reg); 2774d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2775d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2776d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2777d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2778d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat the comma. 2779d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RegLoc = Parser.getTok().getLoc(); 2780d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int OldReg = Reg; 2781a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach const AsmToken RegTok = Parser.getTok(); 2782d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = tryParseRegister(); 2783d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 27842d539691a1e4b9d61853aa99d1a5580dc88595dbJim Grosbach return Error(RegLoc, "register expected"); 2785ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2786ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach bool isQReg = false; 2787ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2788ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2789ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach isQReg = true; 2790ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2791d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2792d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(Reg)) 2793d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2794d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // List must be monotonically increasing. 2795a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) 2796d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "register list not in ascending order"); 2797a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) { 2798a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2799a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach ") in register list"); 2800a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach continue; 2801a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach } 2802d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register lists must also be contiguous. 2803d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // It's OK to use the enumeration values directly here rather, as the 2804d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register classes have the enum sorted properly. 2805d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2806d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg != OldReg + 1) 2807d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "non-contiguous register range"); 2808d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2809ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (isQReg) 2810ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2811d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2812d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2813d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2814d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 2815d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(E, "'}' expected"); 2816d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '}' token. 2817e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 281827debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // Push the register list operand. 281950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 282027debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 282127debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // The ARM system instruction variants for LDM/STM have a '^' token here. 282227debd60a152d39e421c57bce511f16d8439a670Jim Grosbach if (Parser.getTok().is(AsmToken::Caret)) { 282327debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 282427debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Parser.Lex(); // Eat '^' token. 282527debd60a152d39e421c57bce511f16d8439a670Jim Grosbach } 282627debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 282750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2828d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby} 2829d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby 283098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach// Helper function to parse the lane index for vector lists. 283198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 28327636bf6530fd83bf7356ae3894246a4e558741a4Jim GrosbachparseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 28337636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Index = 0; // Always return a defined index value. 283498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 283598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the '['. 283698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::RBrac)) { 283798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // "Dn[]" is the 'all lanes' syntax. 283898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = AllLanes; 283998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the ']'. 284098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 284198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 2842c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCExpr *LaneIndex; 2843c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 2844c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (getParser().ParseExpression(LaneIndex)) { 2845c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "illegal expression"); 2846c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 28477636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 2848c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 2849c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (!CE) { 2850c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "lane index must be empty or an integer"); 2851c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2852c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2853c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) { 2854c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "']' expected"); 2855c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2856c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2857c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Parser.Lex(); // Eat the ']'. 2858c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach int64_t Val = CE->getValue(); 2859c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach 2860c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach // FIXME: Make this range check context sensitive for .8, .16, .32. 2861c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Val < 0 || Val > 7) { 2862c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "lane index out of range"); 2863c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2864c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2865c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Index = Val; 2866c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach LaneKind = IndexedLane; 2867c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_Success; 286898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 286998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = NoLanes; 287098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 287198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach} 287298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 2873862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach// parse a vector register list 2874862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2875862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachparseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 287698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy LaneKind; 28777636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 28785c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc S = Parser.getTok().getLoc(); 28795c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // As an extension (to match gas), support a plain D register or Q register 28805c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // (without encosing curly braces) as a single or double entry list, 28815c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // respectively. 28825c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) { 28835c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach int Reg = tryParseRegister(); 28845c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Reg == -1) 28855c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_NoMatch; 28865c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 28875c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 28887636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 288998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 289098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 289198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 289298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 289398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 28940aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 289598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 289698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 289798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 28983471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 28993471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 290098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 29017636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 29027636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 290395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 290495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 29057636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 290698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 29075c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 29085c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29095c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 29105c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Reg = getDRegFromQReg(Reg); 29117636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 291298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 291398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 291498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 291598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 291698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 29170aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 291898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 291998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 292098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 29213471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 29223471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 292398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 29247636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 29257636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 292695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 292795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 29287636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 292998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 29305c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 29315c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29325c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Error(S, "vector register expected"); 29335c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_ParseFail; 29345c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29355c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach 29365c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 2937862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_NoMatch; 2938862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 2939862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '{' token. 2940862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 2941862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 2942862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int Reg = tryParseRegister(); 2943862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 2944862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 2945862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 2946862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 2947862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count = 1; 2948276ed0344c05822617934fa4a6a9920d864193a5Jim Grosbach int Spacing = 0; 2949c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach unsigned FirstReg = Reg; 2950c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 2951c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 2952c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2953c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach FirstReg = Reg = getDRegFromQReg(Reg); 29540aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // double-spacing requires explicit D registers, otherwise 29550aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // it's ambiguous with four-register single spaced. 2956c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 2957c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Count; 2958c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 29597636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 296098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 2961c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach 2962e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 2963e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 2964e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 29650aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 29660aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 29670aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 29680aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(Parser.getTok().getLoc(), 29690aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "sequential registers in double spaced list"); 29700aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 29710aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 2972e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 2973e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 2974e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach int EndReg = tryParseRegister(); 2975e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (EndReg == -1) { 2976e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "register expected"); 2977e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2978e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 2979e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2980e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2981e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 2982e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // If the register is the same as the start reg, there's nothing 2983e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // more to do. 2984e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg == EndReg) 2985e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 2986e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // The register must be in the same register class as the first. 2987e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 2988e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "invalid register in register list"); 2989e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2990e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 2991e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Ranges must go from low to high. 2992e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg > EndReg) { 2993e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "bad range in register list"); 2994e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2995e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 299698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 299798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 29987636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 29997636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 300098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30017636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 300298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 300398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 300498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 300598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach EndLoc = Parser.getTok().getLoc(); 3006e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach 3007e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Add all the registers in the range to the register list. 3008e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Count += EndReg - Reg; 3009e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Reg = EndReg; 3010e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 3011e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 3012862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat the comma. 3013862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach RegLoc = Parser.getTok().getLoc(); 3014862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int OldReg = Reg; 3015862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Reg = tryParseRegister(); 3016862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 3017862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 3018862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3019862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3020c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // vector register lists must be contiguous. 3021862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // It's OK to use the enumeration values directly here rather, as the 3022862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // VFP register classes have the enum sorted properly. 3023c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // 3024c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 3025c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 3026c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 30270aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 30280aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 30290aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 30300aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(RegLoc, 30310aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "invalid register in double-spaced list (must be 'D' register')"); 30320aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 30330aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 3034c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Reg = getDRegFromQReg(Reg); 3035c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (Reg != OldReg + 1) { 3036c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Error(RegLoc, "non-contiguous register range"); 3037c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach return MatchOperand_ParseFail; 3038c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 3039c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 3040c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Count += 2; 304198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 304298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 30437636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 304498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 30457636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 304698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30477636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 304898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 304998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 305098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3051c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach continue; 3052c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 30530aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Normal D register. 30540aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Figure out the register spacing (single or double) of the list if 30550aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // we don't know it already. 30560aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 30570aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1 + (Reg == OldReg + 2); 30580aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach 30590aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Just check that it's contiguous and keep going. 30600aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (Reg != OldReg + Spacing) { 3061862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "non-contiguous register range"); 3062862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3063862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3064862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ++Count; 306598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 306698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 30677636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 306898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 30697636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 307098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30717636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 307298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 307398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 307498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3075862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3076862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3077862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3078862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) { 3079862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(E, "'}' expected"); 3080862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3081862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3082862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '}' token. 3083862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 308498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 308598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 30860aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 30870aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach (Spacing == 2), S, E)); 308898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 308998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 309098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 30913471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach (Spacing == 2), 309298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach S, E)); 309398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 30947636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 30957636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 309695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 309795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach (Spacing == 2), 309895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach S, E)); 30997636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 310098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3101862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_Success; 3102862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach} 3103862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 310443904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3105f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 310643904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3107706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3108706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3109706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3110706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes StringRef OptStr = Tok.getString(); 3111706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3112706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 3113706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("sy", ARM_MB::SY) 3114706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("st", ARM_MB::ST) 3115032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("sh", ARM_MB::ISH) 3116706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ish", ARM_MB::ISH) 3117032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("shst", ARM_MB::ISHST) 3118706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ishst", ARM_MB::ISHST) 3119706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nsh", ARM_MB::NSH) 3120032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("un", ARM_MB::NSH) 3121706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nshst", ARM_MB::NSHST) 3122032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("unst", ARM_MB::NSHST) 3123706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("osh", ARM_MB::OSH) 3124706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("oshst", ARM_MB::OSHST) 3125706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Default(~0U); 3126706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3127706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes if (Opt == ~0U) 3128f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 3129706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3130706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3131706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3132f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 3133706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes} 3134706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 313543904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3136a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 313743904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3138a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3139a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3140a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3141a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef IFlagsStr = Tok.getString(); 3142a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 31432dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // An iflags string of "none" is interpreted to mean that none of the AIF 31442dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // bits are set. Not a terribly useful instruction, but a valid encoding. 3145a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = 0; 31462dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (IFlagsStr != "none") { 31472dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 31482dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 31492dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("a", ARM_PROC::A) 31502dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("i", ARM_PROC::I) 31512dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("f", ARM_PROC::F) 31522dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Default(~0U); 31532dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 31542dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // If some specific iflag is already set, it means that some letter is 31552dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // present more than once, this is not acceptable. 31562dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (Flag == ~0U || (IFlags & Flag)) 31572dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson return MatchOperand_NoMatch; 31582dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 31592dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson IFlags |= Flag; 31602dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson } 3161a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 3162a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3163a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3164a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3165a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return MatchOperand_Success; 3166584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes} 3167584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 316843904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3169584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 317043904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3171584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3172584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3173584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3174584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Mask = Tok.getString(); 3175584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3176acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (isMClass()) { 3177acad68da50581de905a994ed3c6b9c197bcea687James Molloy // See ARMv6-M 10.1.1 3178acad68da50581de905a994ed3c6b9c197bcea687James Molloy unsigned FlagsVal = StringSwitch<unsigned>(Mask) 3179acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("apsr", 0) 3180acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("iapsr", 1) 3181acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("eapsr", 2) 3182acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("xpsr", 3) 3183acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("ipsr", 5) 3184acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("epsr", 6) 3185acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("iepsr", 7) 3186acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("msp", 8) 3187acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("psp", 9) 3188acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("primask", 16) 3189acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("basepri", 17) 3190acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("basepri_max", 18) 3191acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("faultmask", 19) 3192acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("control", 20) 3193acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Default(~0U); 319418c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3195acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (FlagsVal == ~0U) 3196acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 3197acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3198acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) 3199acad68da50581de905a994ed3c6b9c197bcea687James Molloy // basepri, basepri_max and faultmask only valid for V7m. 3200acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 320118c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3202acad68da50581de905a994ed3c6b9c197bcea687James Molloy Parser.Lex(); // Eat identifier token. 3203acad68da50581de905a994ed3c6b9c197bcea687James Molloy Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3204acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_Success; 3205acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 3206acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3207584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3208584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes size_t Start = 0, Next = Mask.find('_'); 3209584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Flags = ""; 3210590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string SpecReg = Mask.slice(Start, Next).lower(); 3211584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (Next != StringRef::npos) 3212584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Flags = Mask.slice(Next+1, Mask.size()); 3213584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3214584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // FlagsVal contains the complete mask: 3215584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 3-0: Mask 3216584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3217584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned FlagsVal = 0; 3218584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3219584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "apsr") { 3220584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal = StringSwitch<unsigned>(Flags) 3221b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach .Case("nzcvq", 0x8) // same as CPSR_f 3222584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("g", 0x4) // same as CPSR_s 3223584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("nzcvqg", 0xc) // same as CPSR_fs 3224584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3225584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 32264b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger if (FlagsVal == ~0U) { 3227584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (!Flags.empty()) 3228584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3229584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes else 3230bf841cf3360558d2939c9f1a244a7a7296f846dfJim Grosbach FlagsVal = 8; // No flag 32314b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger } 3232584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 323356926a39619bd644c83c4128f0b55189e52707d7Bruno Cardoso Lopes if (Flags == "all") // cpsr_all is an alias for cpsr_fc 323456926a39619bd644c83c4128f0b55189e52707d7Bruno Cardoso Lopes Flags = "fc"; 3235584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes for (int i = 0, e = Flags.size(); i != e; ++i) { 3236584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3237584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("c", 1) 3238584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("x", 2) 3239584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("s", 4) 3240584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("f", 8) 3241584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3242584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3243584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // If some specific flag is already set, it means that some letter is 3244584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // present more than once, this is not acceptable. 3245584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (FlagsVal == ~0U || (FlagsVal & Flag)) 3246584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3247584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= Flag; 3248584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 3249584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else // No match for special register. 3250584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3251584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 32527784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // Special register without flags is NOT equivalent to "fc" flags. 32537784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // NOTE: This is a divergence from gas' behavior. Uncommenting the following 32547784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // two lines would enable gas compatibility at the expense of breaking 32557784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // round-tripping. 32567784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // 32577784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // if (!FlagsVal) 32587784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // FlagsVal = 0x9; 3259584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3260584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3261584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "spsr") 3262584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= 16; 3263584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3264584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3265584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3266584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_Success; 3267a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes} 3268a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3269f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3270f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachparsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3271f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Low, int High) { 3272f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3273f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3274f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3275f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3276f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3277f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef ShiftName = Tok.getString(); 3278590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string LowerOp = Op.lower(); 3279590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string UpperOp = Op.upper(); 3280f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (ShiftName != LowerOp && ShiftName != UpperOp) { 3281f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3282f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3283f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3284f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat shift type token. 3285f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3286f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // There must be a '#' and a shift amount. 32878a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 32888a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3289f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3290f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3291f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3292f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat hash token. 3293f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3294f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCExpr *ShiftAmount; 3295f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 3296f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3297f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "illegal expression"); 3298f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3299f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3300f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3301f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) { 3302f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "constant expression expected"); 3303f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3304f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3305f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 3306f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Val < Low || Val > High) { 3307f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "immediate value out of range"); 3308f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3309f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3310f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3311f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3312f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3313f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_Success; 3314f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach} 3315f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3316c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3317c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachparseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3318c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3319c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach SMLoc S = Tok.getLoc(); 3320c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3321c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3322c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3323c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3324c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int Val = StringSwitch<int>(Tok.getString()) 3325c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("be", 1) 3326c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("le", 0) 3327c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Default(-1); 3328c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.Lex(); // Eat the token. 3329c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3330c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Val == -1) { 3331c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3332c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3333c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3334c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3335c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach getContext()), 3336c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach S, Parser.getTok().getLoc())); 3337c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_Success; 3338c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach} 3339c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3340580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3341580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// instructions. Legal values are: 3342580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// lsl #n 'n' in [0,31] 3343580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// asr #n 'n' in [1,32] 3344580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// n == 32 encoded as n == 0. 3345580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3346580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachparseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3347580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const AsmToken &Tok = Parser.getTok(); 3348580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc S = Tok.getLoc(); 3349580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3350580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3351580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3352580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3353580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach StringRef ShiftName = Tok.getString(); 3354580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 3355580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL") 3356580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = false; 3357580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else if (ShiftName == "asr" || ShiftName == "ASR") 3358580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = true; 3359580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else { 3360580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3361580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3362580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3363580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat the operator. 3364580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3365580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // A '#' and a shift amount. 33668a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 33678a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3368580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3369580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3370580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3371580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat hash token. 3372580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3373580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCExpr *ShiftAmount; 3374580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3375580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3376580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "malformed shift expression"); 3377580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3378580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3379580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3380580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (!CE) { 3381580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "shift amount must be an immediate"); 3382580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3383580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3384580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3385580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach int64_t Val = CE->getValue(); 3386580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (isASR) { 3387580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3388580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 1 || Val > 32) { 3389580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'asr' shift amount must be in range [1,32]"); 3390580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3391580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 33920afa0094afdfe589f407feb76948f273b414b278Owen Anderson // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 33930afa0094afdfe589f407feb76948f273b414b278Owen Anderson if (isThumb() && Val == 32) { 33940afa0094afdfe589f407feb76948f273b414b278Owen Anderson Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 33950afa0094afdfe589f407feb76948f273b414b278Owen Anderson return MatchOperand_ParseFail; 33960afa0094afdfe589f407feb76948f273b414b278Owen Anderson } 3397580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val == 32) Val = 0; 3398580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } else { 3399580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3400580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 0 || Val > 31) { 3401580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'lsr' shift amount must be in range [0,31]"); 3402580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3403580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3404580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3405580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3406580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach E = Parser.getTok().getLoc(); 3407580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3408580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3409580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_Success; 3410580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach} 3411580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 34127e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 34137e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// of instructions. Legal values are: 34147e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// ror #n 'n' in {0, 8, 16, 24} 34157e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 34167e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachparseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 34177e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const AsmToken &Tok = Parser.getTok(); 34187e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc S = Tok.getLoc(); 3419326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) 3420326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 34217e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach StringRef ShiftName = Tok.getString(); 3422326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (ShiftName != "ror" && ShiftName != "ROR") 3423326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 34247e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat the operator. 34257e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34267e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // A '#' and a rotate amount. 34278a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34288a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 34297e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 34307e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34317e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34327e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat hash token. 34337e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34347e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCExpr *ShiftAmount; 34357e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 34367e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 34377e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "malformed rotate expression"); 34387e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34397e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34407e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 34417e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (!CE) { 34427e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "rotate amount must be an immediate"); 34437e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34447e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34457e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34467e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach int64_t Val = CE->getValue(); 34477e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 34487e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // normally, zero is represented in asm by omitting the rotate operand 34497e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // entirely. 34507e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 34517e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "'ror' rotate amount must be 8, 16, or 24"); 34527e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34537e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34547e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34557e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach E = Parser.getTok().getLoc(); 34567e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 34577e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34587e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_Success; 34597e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach} 34607e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 3461293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3462293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachparseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3463293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 3464293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The bitfield descriptor is really two operands, the LSB and the width. 34658a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34668a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3467293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3468293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3469293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3470293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3471293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3472293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *LSBExpr; 3473293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3474293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(LSBExpr)) { 3475293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3476293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3477293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3478293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3479293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3480293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be an immediate"); 3481293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3482293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3483293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3484293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t LSB = CE->getValue(); 3485293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [0,31] 3486293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (LSB < 0 || LSB > 31) { 3487293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be in the range [0,31]"); 3488293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3489293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3490293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3491293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3492293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Expect another immediate operand. 3493293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Parser.getTok().isNot(AsmToken::Comma)) { 3494293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "too few operands"); 3495293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3496293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3497293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 34988a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34998a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3500293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3501293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3502293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3503293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3504293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3505293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *WidthExpr; 3506293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(WidthExpr)) { 3507293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3508293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3509293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3510293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach CE = dyn_cast<MCConstantExpr>(WidthExpr); 3511293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3512293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be an immediate"); 3513293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3514293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3515293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3516293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t Width = CE->getValue(); 3517293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [1,32-lsb] 3518293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Width < 1 || Width > 32 - LSB) { 3519293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be in the range [1,32-lsb]"); 3520293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3521293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3522293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3523293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3524293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3525293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3526293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_Success; 3527293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach} 3528293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 35297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 35307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 35317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3532f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // postidx_reg := '+' register {, shift} 3533f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | '-' register {, shift} 3534f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | register {, shift} 35357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 35367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 35377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // in the case where there is no match, as other alternatives take other 35387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // parse methods. 35397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach AsmToken Tok = Parser.getTok(); 35407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S = Tok.getLoc(); 35417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool haveEaten = false; 354216578b50889329eb62774148091ba0f38b681a09Jim Grosbach bool isAdd = true; 35437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Reg = -1; 35447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::Plus)) { 35457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+' token. 35467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 35477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 35487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-' token. 354916578b50889329eb62774148091ba0f38b681a09Jim Grosbach isAdd = false; 35507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 35517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 35527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 35537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Reg = tryParseRegister(); 35547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Reg == -1) { 35557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!haveEaten) 35567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_NoMatch; 35577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 35587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_ParseFail; 35597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 35607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 35617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3562f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3563f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm = 0; 35640d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 35650d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach Parser.Lex(); // Eat the ','. 35660d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 35670d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach return MatchOperand_ParseFail; 35680d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach } 3569f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 3570f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3571f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ShiftImm, S, E)); 35727ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 35737ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_Success; 35747ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 35757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3576251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3577251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachparseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3578251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3579251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // am3offset := '+' register 3580251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | '-' register 3581251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | register 3582251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # imm 3583251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # + imm 3584251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # - imm 3585251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3586251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 3587251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // in the case where there is no match, as other alternatives take other 3588251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // parse methods. 3589251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach AsmToken Tok = Parser.getTok(); 3590251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc S = Tok.getLoc(); 3591251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3592251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Do immediates first, as we always parse those if we have a '#'. 35938a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 35948a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 3595251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '#'. 3596251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Explicitly look for a '-', as we need to encode negative zero 3597251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // differently. 3598251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isNegative = Parser.getTok().is(AsmToken::Minus); 3599251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCExpr *Offset; 3600251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (getParser().ParseExpression(Offset)) 3601251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3602251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3603251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!CE) { 3604251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(S, "constant expression expected"); 3605251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3606251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3607251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Tok.getLoc(); 3608251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Negative zero is encoded as the flag value INT32_MIN. 3609251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int32_t Val = CE->getValue(); 3610251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (isNegative && Val == 0) 3611251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = INT32_MIN; 3612251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3613251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back( 3614251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3615251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3616251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3617251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3618251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3619251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3620251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool haveEaten = false; 3621251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isAdd = true; 3622251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int Reg = -1; 3623251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Tok.is(AsmToken::Plus)) { 3624251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '+' token. 3625251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3626251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 3627251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '-' token. 3628251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach isAdd = false; 3629251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3630251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3631251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 3632251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Reg = tryParseRegister(); 3633251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Reg == -1) { 3634251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!haveEaten) 3635251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_NoMatch; 3636251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 3637251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3638251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3639251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3640251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3641251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3642251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 0, S, E)); 3643251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3644251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3645251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach} 3646251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3647a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2LdrdPre - Convert parsed operands to MCInst. 3648a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3649a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3650a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3651a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3652a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3653a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3654a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3655a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3656a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3657a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3658a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3659a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3660a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3661a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3662a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3663a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3664a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3665a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2StrdPre - Convert parsed operands to MCInst. 3666a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3667a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3668a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3669a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3670a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3671a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3672a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3673a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3674a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3675a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3676a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3677a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3678a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3679a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3680a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3681a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3682a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3683eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3684eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3685eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3686eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbachbool ARMAsmParser:: 3687eeec025cf5a2236ee9527a3312496a6ea42100c6Jim GrosbachcvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3688eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3689eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3690eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3691eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach // Create a writeback register dummy placeholder. 3692eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3693eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3694eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3695eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3696eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach return true; 3697eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach} 3698eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3699ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3700ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3701ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3702ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbachbool ARMAsmParser:: 3703ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim GrosbachcvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3704ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3705ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach // Create a writeback register dummy placeholder. 3706ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3707ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3708ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3709ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3710ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach return true; 3711ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach} 3712ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach 37131355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3714ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3715ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3716ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 37171355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3718ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3719ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3720ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 3721ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3722ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3723ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 37247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3725ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3726ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3727ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3728ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 37299ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 37309ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37319ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// when they refer multiple MIOperands inside a single one. 37329ab0f25fc194b4315db1b87d38d4024054120bf6Owen Andersonbool ARMAsmParser:: 37339ab0f25fc194b4315db1b87d38d4024054120bf6Owen AndersoncvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 37349ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37359ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37369ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37379ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson // Create a writeback register dummy placeholder. 37389ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson Inst.addOperand(MCOperand::CreateImm(0)); 37399ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37409ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 37419ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37429ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson return true; 37439ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson} 37449ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37459ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 3746548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3747548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3748548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3749548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbachbool ARMAsmParser:: 3750548340c4bfa596b602f286dfd3a8782817859d95Jim GrosbachcvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3751548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3752548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach // Create a writeback register dummy placeholder. 3753548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3754548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3755548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3756548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3757548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach return true; 3758548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach} 3759548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach 37601355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3761ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3762ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3763ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 37641355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3765ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3766ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3767ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3768548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3769548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3770548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 37727ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 37737ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 37747b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 37757b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37767b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// when they refer multiple MIOperands inside a single one. 37777b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbachbool ARMAsmParser:: 37787b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim GrosbachcvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 37797b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37807b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach // Create a writeback register dummy placeholder. 37817b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 37827b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37837b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 37847b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37857b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach return true; 37867b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach} 37877b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach 37887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 37897ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37907ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 37917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 37927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 37937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3795ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 37977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 37987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 37997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 38027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3803ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3804ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3805ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3806ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 38077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 3808ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3809ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3810ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 38117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 38127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3814aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3815ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 3816ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 38177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 38217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 38227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 38237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 38247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 3825aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson 38267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 38277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 38287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 38297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 38307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 38317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 38337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 38347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 38357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 38407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3841ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3842ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 3843ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 3844ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 38457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 3846ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3847ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3848ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 38497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 38507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3851ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 3852ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 38537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3854ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 38597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3860ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3861ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 3862ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 3863ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 38642fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// cvtLdrdPre - Convert parsed operands to MCInst. 38652fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 38662fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// when they refer multiple MIOperands inside a single one. 38672fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbachbool ARMAsmParser:: 38682fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim GrosbachcvtLdrdPre(MCInst &Inst, unsigned Opcode, 38692fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38702fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Rt, Rt2 38712fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38722fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 38732fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Create a writeback register dummy placeholder. 38742fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 38752fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // addr 38762fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 38772fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // pred 38782fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 38792fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return true; 38802fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach} 38812fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 388214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// cvtStrdPre - Convert parsed operands to MCInst. 388314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 388414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// when they refer multiple MIOperands inside a single one. 388514605d1a679d55ff25875656e100ff455194ee17Jim Grosbachbool ARMAsmParser:: 388614605d1a679d55ff25875656e100ff455194ee17Jim GrosbachcvtStrdPre(MCInst &Inst, unsigned Opcode, 388714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 388814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Create a writeback register dummy placeholder. 388914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 389014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt, Rt2 389114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 389214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 389314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // addr 389414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 389514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // pred 389614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 389714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return true; 389814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach} 389914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach 3900623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3901623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3902623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3903623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbachbool ARMAsmParser:: 3904623a454b0f5c300e69a19984d7855a1e976c3d09Jim GrosbachcvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3905623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3906623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3907623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach // Create a writeback register dummy placeholder. 3908623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3909623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3910623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3911623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach return true; 3912623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach} 3913623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 391488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// cvtThumbMultiple- Convert parsed operands to MCInst. 391588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 391688ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// when they refer multiple MIOperands inside a single one. 391788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbachbool ARMAsmParser:: 391888ae2bc6d53bbf58422ff74729da18a53e155b4aJim GrosbachcvtThumbMultiply(MCInst &Inst, unsigned Opcode, 391988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 392088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // The second source operand must be the same register as the destination 392188ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // operand. 392288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach if (Operands.size() == 6 && 39237a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 39247a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[5])->getReg()) && 39257a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 39267a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[4])->getReg())) { 392788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach Error(Operands[3]->getStartLoc(), 39287a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach "destination register must match source register"); 392988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return false; 393088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach } 393188ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 393288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 39331b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // If we have a three-operand form, make sure to set Rn to be the operand 39341b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // that isn't the same as Rd. 39351b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach unsigned RegOp = 4; 39361b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach if (Operands.size() == 6 && 39371b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[4])->getReg() == 39381b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[3])->getReg()) 39391b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach RegOp = 5; 39401b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 39411b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach Inst.addOperand(Inst.getOperand(0)); 394288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 394388ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach 394488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 394588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach} 3946623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 394712431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 394812431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 394912431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 395012431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 39516029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 395212431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 395312431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 395412431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 395512431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 395612431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 395712431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 395812431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 395912431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 396012431329d617064d6e72dd040a58c1635cc261abJim Grosbach 396112431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 396212431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 396312431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 396412431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 39656029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 396612431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 396712431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 396812431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 396912431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 397012431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vm 397112431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 397212431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 397312431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 397412431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 397512431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 397612431329d617064d6e72dd040a58c1635cc261abJim Grosbach 39774334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 39784334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 39794334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39804334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 39814334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 39824334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 39834334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 39844334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 39856029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 39864334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 39874334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 39884334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 39894334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 39904334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 39914334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 39924334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 39934334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39944334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 39954334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 39964334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 39974334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 39984334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vm 39994334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 40004334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 40016029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 40024334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 40034334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 40044334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 40054334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 40064334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 4007e717610f53e0465cde198536561a3c00ce29d59fBill Wendling/// Parse an ARM memory expression, return false if successful else return true 40089c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// or an error. The first token must be a '[' when called. 400950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 40107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4011762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 401218b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LBrac) && 4013a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Bracket"); 4014762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4015b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat left bracket token. 4016a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 401718b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &BaseRegTok = Parser.getTok(); 40181355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int BaseRegNum = tryParseRegister(); 40197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (BaseRegNum == -1) 40207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(BaseRegTok.getLoc(), "register expected"); 4021a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 40220571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar // The next token must either be a comma or a closing bracket. 40230571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar const AsmToken &Tok = Parser.getTok(); 40240571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 40257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Tok.getLoc(), "malformed memory operand"); 40260571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar 40277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::RBrac)) { 4028762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = Tok.getLoc(); 4029b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat right bracket token. 4030a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 40317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 403257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 0, 0, false, S, E)); 403303f44a04e63ff77af12df33e10ffdc473609dfe2Jim Grosbach 4034fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4035fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // operand. It's rather odd, but syntactically valid. 4036fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4037fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4038fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Parser.Lex(); // Eat the '!'. 4039fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach } 4040fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach 40417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 40427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 404350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 40447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 40457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the comma. 404650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 404757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a ':', it's an alignment specifier. 404857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Colon)) { 404957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the ':'. 405057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 405157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 405257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCExpr *Expr; 405357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (getParser().ParseExpression(Expr)) 405457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return true; 405557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 405657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // The expression has to be a constant. Memory references with relocations 405757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // don't come through here, as they use the <label> forms of the relevant 405857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // instructions. 405957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 406057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!CE) 406157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error (E, "constant expression expected"); 406257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 406357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Align = 0; 406457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach switch (CE->getValue()) { 406557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach default: 4066eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach return Error(E, 4067eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4068eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 16: Align = 2; break; 4069eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 32: Align = 4; break; 407057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 64: Align = 8; break; 407157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 128: Align = 16; break; 407257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 256: Align = 32; break; 407357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 407457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 407557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Now we should have the closing ']' 407657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 407757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 407857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error(E, "']' expected"); 407957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat right bracket token. 408057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 408157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Don't worry about range checking the value here. That's handled by 408257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // the is*() predicates. 408357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 408457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, Align, 408557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 408657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 408757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 408857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // operand. 408957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 409057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 409157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the '!'. 409257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 409357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 409457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return false; 409557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 409657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 409757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a '#', it's an immediate offset, else assume it's a register 40986cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // offset. Be friendly and also accept a plain integer (without a leading 40996cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // hash) for gas compatibility. 41006cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 41018a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar) || 41026cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.getTok().is(AsmToken::Integer)) { 41038a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Integer)) 41046cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.Lex(); // Eat the '#'. 41057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 410650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 41070da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson bool isNegative = getParser().getTok().is(AsmToken::Minus); 41087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Offset; 41097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Offset)) 41107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 411105d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 41127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The expression has to be a constant. Memory references with relocations 41137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // don't come through here, as they use the <label> forms of the relevant 41147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // instructions. 41157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 41167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 41177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error (E, "constant expression expected"); 41187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41190da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson // If the constant was #-0, represent it as INT32_MIN. 41200da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson int32_t Val = CE->getValue(); 41210da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson if (isNegative && Val == 0) 41220da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson CE = MCConstantExpr::Create(INT32_MIN, getContext()); 41230da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson 41247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 41257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 41277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 41287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 412905d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 41307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Don't worry about range checking the value here. That's handled by 41317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // the is*() predicates. 41327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 413357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, 0, 413457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 4135a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 41367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 41377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // operand. 41387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 41397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 41407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '!'. 4141762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 41427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 41449c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 4145d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 41467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The register offset is optionally preceded by a '+' or '-' 41477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative = false; 41487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 41497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach isNegative = true; 41507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-'. 41517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Parser.getTok().is(AsmToken::Plus)) { 41527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Nothing to do. 41537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+'. 41547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 41559c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int OffsetRegNum = tryParseRegister(); 41587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (OffsetRegNum == -1) 41597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "register expected"); 41607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a shift operator, handle it. 41627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 41630d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm = 0; 41647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 41657ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the ','. 41660d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 41677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 41689c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 416916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 41707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 41717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41727ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 41737ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 41747ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 41757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 417757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ShiftType, ShiftImm, 0, isNegative, 41787ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach S, E)); 41797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 4180f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4181f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // operand. 4182f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4183f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4184f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Parser.Lex(); // Eat the '!'. 4185f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 41869c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41879c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby return false; 41889c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby} 41899c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41907ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// parseMemRegOffsetShift - one of these two: 4191a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ( lsl | lsr | asr | ror ) , # shift_amount 4192a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// rrx 41937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// return true if it parses a shift otherwise it returns false. 41947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 41957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &Amount) { 41967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 419718b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 4198a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby if (Tok.isNot(AsmToken::Identifier)) 4199a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return true; 420038e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef ShiftName = Tok.getString(); 4201af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL" || 4202af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach ShiftName == "asl" || ShiftName == "ASL") 42030082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsl; 4204a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "lsr" || ShiftName == "LSR") 42050082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsr; 4206a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "asr" || ShiftName == "ASR") 42070082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::asr; 4208a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "ror" || ShiftName == "ROR") 42090082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::ror; 4210a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "rrx" || ShiftName == "RRX") 42110082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::rrx; 4212a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else 42137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "illegal shift operator"); 4214b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat shift type token. 4215a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 42167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // rrx stands alone. 42177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = 0; 42187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (St != ARM_AM::rrx) { 42197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Loc = Parser.getTok().getLoc(); 42207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // A '#' and a shift amount. 42217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const AsmToken &HashTok = Parser.getTok(); 42228a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (HashTok.isNot(AsmToken::Hash) && 42238a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach HashTok.isNot(AsmToken::Dollar)) 42247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(HashTok.getLoc(), "'#' expected"); 42257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat hash token. 42269c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 42277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Expr; 42287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Expr)) 42297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 42307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Range check the immediate. 42317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsl, ror: 0 <= imm <= 31 42327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsr, asr: 0 <= imm <= 32 42337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 42347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 42357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "shift amount must be an immediate"); 42367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Imm = CE->getValue(); 42377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Imm < 0 || 42387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 42397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 42407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "immediate shift value out of range"); 42417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = Imm; 42427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 4243a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4244a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return false; 4245a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4246a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 42479d39036f62674606565217a10db28171b9594bc7Jim Grosbach/// parseFPImm - A floating point immediate expression operand. 42489d39036f62674606565217a10db28171b9594bc7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 42499d39036f62674606565217a10db28171b9594bc7Jim GrosbachparseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 42509d39036f62674606565217a10db28171b9594bc7Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 42519d39036f62674606565217a10db28171b9594bc7Jim Grosbach 42528a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 42538a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) 42549d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_NoMatch; 42550e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 42560e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Disambiguate the VMOV forms that can accept an FP immediate. 42570e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <sreg>, #imm 42580e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f64 <dreg>, #imm 42590e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <dreg>, #imm @ vector f32x2 42600e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <qreg>, #imm @ vector f32x4 42610e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // 42620e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // There are also the NEON VMOV instructions which expect an 42630e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // integer constant. Make sure we don't try to parse an FPImm 42640e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // for these: 42650e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.i{8|16|32|64} <dreg|qreg>, #imm 42660e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 42670e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 42680e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach TyOp->getToken() != ".f64")) 42690e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return MatchOperand_NoMatch; 42700e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 42719d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the '#'. 42729d39036f62674606565217a10db28171b9594bc7Jim Grosbach 42739d39036f62674606565217a10db28171b9594bc7Jim Grosbach // Handle negation, as that still comes through as a separate token. 42749d39036f62674606565217a10db28171b9594bc7Jim Grosbach bool isNegative = false; 42759d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 42769d39036f62674606565217a10db28171b9594bc7Jim Grosbach isNegative = true; 42779d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); 42789d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42799d39036f62674606565217a10db28171b9594bc7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 42809d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Real)) { 42819d39036f62674606565217a10db28171b9594bc7Jim Grosbach APFloat RealVal(APFloat::IEEEdouble, Tok.getString()); 42829d39036f62674606565217a10db28171b9594bc7Jim Grosbach uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 42839d39036f62674606565217a10db28171b9594bc7Jim Grosbach // If we had a '-' in front, toggle the sign bit. 42849d39036f62674606565217a10db28171b9594bc7Jim Grosbach IntVal ^= (uint64_t)isNegative << 63; 42859d39036f62674606565217a10db28171b9594bc7Jim Grosbach int Val = ARM_AM::getFP64Imm(APInt(64, IntVal)); 42869d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 42879d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Val == -1) { 42889d39036f62674606565217a10db28171b9594bc7Jim Grosbach TokError("floating point value out of range"); 42899d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 42909d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42919d39036f62674606565217a10db28171b9594bc7Jim Grosbach Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 42929d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 42939d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42949d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Integer)) { 42959d39036f62674606565217a10db28171b9594bc7Jim Grosbach int64_t Val = Tok.getIntVal(); 42969d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 42979d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Val > 255 || Val < 0) { 42989d39036f62674606565217a10db28171b9594bc7Jim Grosbach TokError("encoded floating point value out of range"); 42999d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 43009d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 43019d39036f62674606565217a10db28171b9594bc7Jim Grosbach Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 43029d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 43039d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 43049d39036f62674606565217a10db28171b9594bc7Jim Grosbach 43059d39036f62674606565217a10db28171b9594bc7Jim Grosbach TokError("invalid floating point immediate"); 43069d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 43079d39036f62674606565217a10db28171b9594bc7Jim Grosbach} 43089c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Parse a arm instruction operand. For now this parses the operand regardless 43099c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// of the mnemonic. 43101355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4311fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes StringRef Mnemonic) { 4312762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 4313fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4314fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // Check if the current operand has a custom associated parser, if so, try to 4315fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // custom parse the operand, or fallback to the general approach. 4316f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4317f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_Success) 4318fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return false; 4319f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // If there wasn't a custom match, try the generic matcher below. Otherwise, 4320f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // there was a match, but an error occurred, in which case, just return that 4321f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // the operand parsing failed. 4322f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_ParseFail) 4323f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return true; 4324fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4325a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby switch (getLexer().getKind()) { 4326146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling default: 4327146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling Error(Parser.getTok().getLoc(), "unexpected token in operand"); 432850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 432919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach case AsmToken::Identifier: { 43301355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (!tryParseRegisterWithWriteBack(Operands)) 433150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 43320d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int Res = tryParseShiftRegister(Operands); 433319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (Res == 0) // success 43340082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return false; 433519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach else if (Res == -1) // irrecoverable error 433619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return true; 43373cbe43fe69680df772d83947ced97ca445861213Jim Grosbach // If this is VMRS, check for the apsr_nzcv operand. 43385cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { 43395cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach S = Parser.getTok().getLoc(); 43405cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach Parser.Lex(); 43415cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S)); 43425cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach return false; 43435cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach } 4344e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 4345e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Fall though for the Identifier case that is not a register or a 4346e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // special name. 434719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 4348758a519a22b469ce8e2b8d0bf7a72813e87710d4Jim Grosbach case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 434967b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Integer: // things like 1f and 2b as a branch targets 43506284afc293c8f6e84dffab8731aa9e679d437745Jim Grosbach case AsmToken::String: // quoted label names. 435167b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Dot: { // . as a branch target 4352515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // This was not a register so parse other operands that start with an 4353515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // identifier (like labels) as expressions and create them as immediates. 4354515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby const MCExpr *IdVal; 4355762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4356515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getParser().ParseExpression(IdVal)) 435750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 4358762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 435950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 436050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 436150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling } 4362a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby case AsmToken::LBrac: 43631355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseMemory(Operands); 4364d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby case AsmToken::LCurly: 43651355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseRegisterList(Operands); 43668a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach case AsmToken::Dollar: 436763553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson case AsmToken::Hash: { 4368079469f649d8da3923b9f747d7062c84e01cc4aeKevin Enderby // #42 -> immediate. 4369079469f649d8da3923b9f747d7062c84e01cc4aeKevin Enderby // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 4370762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4371b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 437263553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson bool isNegative = Parser.getTok().is(AsmToken::Minus); 4373515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby const MCExpr *ImmVal; 4374515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getParser().ParseExpression(ImmVal)) 437550d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 437663553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4377ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach if (CE) { 4378ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach int32_t Val = CE->getValue(); 4379ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach if (isNegative && Val == 0) 4380ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 438163553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 4382762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 438350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 438450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 438563553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 43869081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim case AsmToken::Colon: { 43879081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // ":lower16:" and ":upper16:" expression prefixes 43887597212abced110723f2fee985a7d60557c092ecEvan Cheng // FIXME: Check it's an expression prefix, 43897597212abced110723f2fee985a7d60557c092ecEvan Cheng // e.g. (FOO - :lower16:BAR) isn't legal. 43907597212abced110723f2fee985a7d60557c092ecEvan Cheng ARMMCExpr::VariantKind RefKind; 43911355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parsePrefix(RefKind)) 43929081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 43939081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 43947597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *SubExprVal; 43957597212abced110723f2fee985a7d60557c092ecEvan Cheng if (getParser().ParseExpression(SubExprVal)) 43969081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 43979081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 43987597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 43997597212abced110723f2fee985a7d60557c092ecEvan Cheng getContext()); 44009081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 44017597212abced110723f2fee985a7d60557c092ecEvan Cheng Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 44029081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 44039081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 4404a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 4405a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4406a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 44071355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 44087597212abced110723f2fee985a7d60557c092ecEvan Cheng// :lower16: and :upper16:. 44091355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 44107597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_None; 44119081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44129081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // :lower16: and :upper16: modifiers 44138a8696db6b6f6e735bb9de630876af83946b45f9Jason W Kim assert(getLexer().is(AsmToken::Colon) && "expected a :"); 44149081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat ':' 44159081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44169081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Identifier)) { 44179081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 44189081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44199081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44209081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44219081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim StringRef IDVal = Parser.getTok().getIdentifier(); 44229081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (IDVal == "lower16") { 44237597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_LO16; 44249081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else if (IDVal == "upper16") { 44257597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_HI16; 44269081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else { 44279081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 44289081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44299081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44309081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); 44319081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44329081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Colon)) { 44339081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 44349081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44359081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44369081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat the last ':' 44379081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 44389081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim} 44399081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 4440352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// \brief Given a mnemonic, split out possible predication code and carry 4441352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// setting letters to form a canonical mnemonic and flags. 4442352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar// 4443badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar// FIXME: Would be nice to autogen this. 444489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach// FIXME: This is a bit of a maze of special cases. 44451355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachStringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 44465f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach unsigned &PredicationCode, 44475f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach bool &CarrySetting, 444889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned &ProcessorIMod, 444989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask) { 4450352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar PredicationCode = ARMCC::AL; 4451352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = false; 4452a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = 0; 4453352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4454badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Ignore some mnemonics we know aren't predicated forms. 4455352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // 4456352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // FIXME: Would be nice to autogen this. 44575f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach if ((Mnemonic == "movs" && isThumb()) || 44585f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 44595f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 44605f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 44615f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 44625f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 44635f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 44646849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 44656849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "fmuls") 4466352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4467badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 44683f00e317064560ad11168d22030416d853829f6eJim Grosbach // First, split out any predication code. Ignore mnemonics we know aren't 44693f00e317064560ad11168d22030416d853829f6eJim Grosbach // predicated but do have a carry-set and so weren't caught above. 4470ab40f4b737b0a87c4048a9ad2f0c02be735e3770Jim Grosbach if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 447171725a099e6d0cba24a63f9c9063f6efee3bf76eJim Grosbach Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 447204d55f1905748b0d66655e2332e1a232a3f665f4Jim Grosbach Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 44732f25d9b9334662e846460e98a8fe2dae4f233068Jim Grosbach Mnemonic != "sbcs" && Mnemonic != "rscs") { 44743f00e317064560ad11168d22030416d853829f6eJim Grosbach unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 44753f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("eq", ARMCC::EQ) 44763f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ne", ARMCC::NE) 44773f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hs", ARMCC::HS) 44783f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cs", ARMCC::HS) 44793f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lo", ARMCC::LO) 44803f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cc", ARMCC::LO) 44813f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("mi", ARMCC::MI) 44823f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("pl", ARMCC::PL) 44833f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vs", ARMCC::VS) 44843f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vc", ARMCC::VC) 44853f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hi", ARMCC::HI) 44863f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ls", ARMCC::LS) 44873f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ge", ARMCC::GE) 44883f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lt", ARMCC::LT) 44893f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("gt", ARMCC::GT) 44903f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("le", ARMCC::LE) 44913f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("al", ARMCC::AL) 44923f00e317064560ad11168d22030416d853829f6eJim Grosbach .Default(~0U); 44933f00e317064560ad11168d22030416d853829f6eJim Grosbach if (CC != ~0U) { 44943f00e317064560ad11168d22030416d853829f6eJim Grosbach Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 44953f00e317064560ad11168d22030416d853829f6eJim Grosbach PredicationCode = CC; 44963f00e317064560ad11168d22030416d853829f6eJim Grosbach } 449752925b60f1cd4cf810524ca05b00a207a926ab9fBill Wendling } 4498345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 4499352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Next, determine if we have a carry setting bit. We explicitly ignore all 4500352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // the instructions we know end in 's'. 4501352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar if (Mnemonic.endswith("s") && 450200f5d982057574cf65a4a3f29548ff9fb0ecfbd0Jim Grosbach !(Mnemonic == "cps" || Mnemonic == "mls" || 45035f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 45045f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 45055f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 450667ca1adf822c6cbc2f2bb78b8f94eefd099a8eb6Jim Grosbach Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 450748171e7fbe58bb418f09717813779d03903d35e4Jim Grosbach Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 45089c39789c361d4fe2632f28fca74c9ea5fff3dafcJim Grosbach Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 45091aa149f5acea364aa8bc9cfc3a167f78eff2e96bJim Grosbach Mnemonic == "fmuls" || Mnemonic == "fcmps" || 4510e1cf5902ec832cecdd5a94b9701930253d410741Jim Grosbach (Mnemonic == "movs" && isThumb()))) { 4511352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4512352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = true; 4513352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar } 4514352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4515a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // The "cps" instruction can have a interrupt mode operand which is glued into 4516a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // the mnemonic. Check if this is the case, split it and parse the imod op 4517a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (Mnemonic.startswith("cps")) { 4518a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Split out any imod code. 4519a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IMod = 4520a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4521a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("ie", ARM_PROC::IE) 4522a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("id", ARM_PROC::ID) 4523a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Default(~0U); 4524a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IMod != ~0U) { 4525a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4526a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = IMod; 4527a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4528a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4529a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 453089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The "it" instruction has the condition mask on the end of the mnemonic. 453189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic.startswith("it")) { 453289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = Mnemonic.slice(2, Mnemonic.size()); 453389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mnemonic = Mnemonic.slice(0, 2); 453489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 453589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4536352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4537352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar} 45383771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 45393771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// \brief Given a canonical mnemonic, determine if the instruction ever allows 45403771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// inclusion of carry set or predication code operands. 45413771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// 45423771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// FIXME: It would be nice to autogen this. 4543fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopesvoid ARMAsmParser:: 45441355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachgetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4545fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode) { 4546eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4547eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 45483443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach Mnemonic == "add" || Mnemonic == "adc" || 4549eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4550d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "orr" || Mnemonic == "mvn" || 4551eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4552d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 45533443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4554d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "mla" || Mnemonic == "smlal" || 4555d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "umlal" || Mnemonic == "umull"))) { 4556eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = true; 4557fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 4558eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = false; 45593771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 4560eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4561eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4562eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4563eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4564ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4565ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach (Mnemonic == "clrex" && !isThumb()) || 45660780b6303b99441fef04340b7a083006484f4743Jim Grosbach (Mnemonic == "nop" && isThumbOne()) || 45672bd0118472de352745a2e038245fab4974f7c87eJim Grosbach ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 45682bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 45692bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 45704af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 45714af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach !isThumb()) || 45721ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 45733771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = false; 4574fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 45753771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = true; 4576fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes 4577fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach if (isThumb()) { 4578fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 457963b46faeb8acae9b7e5f865b7417dc00b9b9dad3Jim Grosbach Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4580fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes CanAcceptPredicationCode = false; 4581fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } 4582badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar} 4583badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4584d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbachbool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4585d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 458620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // FIXME: This is all horribly hacky. We really need a better way to deal 458720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // with optional operands like this in the matcher table. 4588d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 4589d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4590d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // another does not. Specifically, the MOVW instruction does not. So we 4591d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // special case it here and remove the defaulted (non-setting) cc_out 4592d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // operand if that's the instruction we're trying to match. 4593d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // 4594d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // We do this as post-processing of the explicit operands rather than just 4595d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // conditionally adding the cc_out in the first place because we need 4596d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // to check the type of the parsed immediate operand. 45978adf62034a874adacff158e8adc9438cb3e67c01Owen Anderson if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4598d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4599d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4600d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4601d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return true; 46023912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 46033912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 46043912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // when there are only two register operands. 46053912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 46063912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 46073912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 46083912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 46093912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach return true; 461072f39f8436848885176943b0ba985a7171145423Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 461120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 461220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // have to check the immediate range here since Thumb2 has a variant 461320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // that can handle a different range and has a cc_out operand. 4614f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (((isThumb() && Mnemonic == "add") || 4615f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach (isThumbTwo() && Mnemonic == "sub")) && 4616f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 461772f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 461872f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 461972f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 462020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 462120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach (static_cast<ARMOperand*>(Operands[5])->isReg() || 462220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 462372f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 4624f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // For Thumb2, add/sub immediate does not have a cc_out operand for the 4625f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // imm0_4095 variant. That's the least-preferred variant when 462620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // selecting via the generic "add" mnemonic, so to know that we 462720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // should remove the cc_out operand, we have to explicitly check that 462820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // it's not one of the other variants. Ugh. 4629f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4630f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 463120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 463220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 463320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 463420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Nest conditions rather than one big 'if' statement for readability. 463520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // 463620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If either register is a high reg, it's either one of the SP 463720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // variants (handled above) or a 32-bit encoding, so we just 463820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // check against T3. 463920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 464020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 464120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 464220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 464320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If both registers are low, we're in an IT block, and the immediate is 464420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // in range, we should use encoding T1 instead, which has a cc_out. 464520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (inITBlock() && 464664944f48a1164c02c15ca423a53919682a89074cJim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 464720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 464820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 464920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 465020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 465120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Otherwise, we use encoding T4, which does not have a cc_out 465220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // operand. 465320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return true; 465420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach } 465520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 465664944f48a1164c02c15ca423a53919682a89074cJim Grosbach // The thumb2 multiply instruction doesn't have a CCOut register, so 465764944f48a1164c02c15ca423a53919682a89074cJim Grosbach // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 465864944f48a1164c02c15ca423a53919682a89074cJim Grosbach // use the 16-bit encoding or not. 465964944f48a1164c02c15ca423a53919682a89074cJim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 466064944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 466164944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 466264944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 466364944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->isReg() && 466464944f48a1164c02c15ca423a53919682a89074cJim Grosbach // If the registers aren't low regs, the destination reg isn't the 466564944f48a1164c02c15ca423a53919682a89074cJim Grosbach // same as one of the source regs, or the cc_out operand is zero 466664944f48a1164c02c15ca423a53919682a89074cJim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 466764944f48a1164c02c15ca423a53919682a89074cJim Grosbach // remove the cc_out operand. 466864944f48a1164c02c15ca423a53919682a89074cJim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 466964944f48a1164c02c15ca423a53919682a89074cJim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 46701de0bd194540f8bab399fb39c4ba615a7b2381d3Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 467164944f48a1164c02c15ca423a53919682a89074cJim Grosbach !inITBlock() || 467264944f48a1164c02c15ca423a53919682a89074cJim Grosbach (static_cast<ARMOperand*>(Operands[3])->getReg() != 467364944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->getReg() && 467464944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() != 467564944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg()))) 467664944f48a1164c02c15ca423a53919682a89074cJim Grosbach return true; 467764944f48a1164c02c15ca423a53919682a89074cJim Grosbach 46787f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // Also check the 'mul' syntax variant that doesn't specify an explicit 46797f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // destination register. 46807f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 46817f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 46827f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 46837f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 46847f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // If the registers aren't low regs or the cc_out operand is zero 46857f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 46867f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // remove the cc_out operand. 46877f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 46887f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 46897f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !inITBlock())) 46907f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach return true; 46917f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach 469264944f48a1164c02c15ca423a53919682a89074cJim Grosbach 469320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 4694f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // Register-register 'add/sub' for thumb does not have a cc_out operand 4695f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4696f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4697f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // right, this will result in better diagnostics (which operand is off) 4698f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // anyway. 4699f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4700f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach (Operands.size() == 5 || Operands.size() == 6) && 470172f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 470272f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 470372f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 470472f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 47053912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 4706d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return false; 4707d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach} 4708d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 47097aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool isDataTypeToken(StringRef Tok) { 47107aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 47117aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 47127aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 47137aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 47147aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 47157aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".f" || Tok == ".d"; 47167aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 47177aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 47187aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// FIXME: This bit should probably be handled via an explicit match class 47197aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// in the .td files that matches the suffix instead of having it be 47207aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// a literal string token the way it is now. 47217aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 47227aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 47237aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 47247aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 472521d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbachstatic void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4726badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar/// Parse an arm instruction mnemonic followed by its operands. 4727badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbarbool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4728badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 472921d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // Apply mnemonic aliases before doing anything else, as the destination 473021d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // mnemnonic may include suffices and we want to handle them normally. 473121d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // The generic tblgen'erated code does this later, at the start of 473221d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // MatchInstructionImpl(), but that's too late for aliases that include 473321d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // any sort of suffix. 473421d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach unsigned AvailableFeatures = getAvailableFeatures(); 473521d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach applyMnemonicAliases(Name, AvailableFeatures); 473621d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach 4737a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // First check for the ARM-specific .req directive. 4738a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier) && 4739a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.getTok().getIdentifier() == ".req") { 4740a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach parseDirectiveReq(Name, NameLoc); 4741a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // We always return 'error' for this, as we're done with this 4742a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // statement and don't need to match the 'instruction." 4743a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return true; 4744a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 4745a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 4746badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Create the leading tokens for the mnemonic, split by '.' characters. 4747badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar size_t Start = 0, Next = Name.find('.'); 4748ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach StringRef Mnemonic = Name.slice(Start, Next); 4749badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4750352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Split out the predication code and carry setting flag from the mnemonic. 4751352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar unsigned PredicationCode; 4752a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned ProcessorIMod; 4753352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar bool CarrySetting; 475489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef ITMask; 47551355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 475689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ProcessorIMod, ITMask); 4757badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 47580c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach // In Thumb1, only the branch (B) instruction can be predicated. 47590c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 47600c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach Parser.EatToEndOfStatement(); 47610c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach return Error(NameLoc, "conditional execution not supported in Thumb1"); 47620c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach } 47630c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach 4764ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4765ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 476689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // Handle the IT instruction ITMask. Convert it to a bitmask. This 476789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // is the mask as it will be for the IT encoding if the conditional 476889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 476989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // where the conditional bit0 is zero, the instruction post-processing 477089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // will adjust the mask accordingly. 477189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic == "it") { 4772f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4773f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITMask.size() > 3) { 4774f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Parser.EatToEndOfStatement(); 4775f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "too many conditions on IT instruction"); 4776f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 477789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = 8; 477889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = ITMask.size(); i != 0; --i) { 477989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach char pos = ITMask[i - 1]; 478089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (pos != 't' && pos != 'e') { 478189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.EatToEndOfStatement(); 4782f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 478389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 478489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask >>= 1; 478589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (ITMask[i - 1] == 't') 478689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask |= 8; 478789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 4788f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 478989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 479089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4791ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // FIXME: This is all a pretty gross hack. We should automatically handle 4792ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // optional operands like this via tblgen. 47939717fa9f29696bca45ddfdf206b1c382c8b40b78Bill Wendling 47943771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Next, add the CCOut and ConditionCode operands, if needed. 47953771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // 47963771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // For mnemonics which can ever incorporate a carry setting bit or predication 47973771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // code, our matching model involves us always generating CCOut and 47983771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // ConditionCode operands to match the mnemonic "as written" and then we let 47993771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // the matcher deal with finding the right instruction or generating an 48003771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // appropriate error. 48013771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar bool CanAcceptCarrySet, CanAcceptPredicationCode; 48021355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 48033771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 480433c16a27370939de39679245c3dff72383c210bdJim Grosbach // If we had a carry-set on an instruction that can't do that, issue an 480533c16a27370939de39679245c3dff72383c210bdJim Grosbach // error. 480633c16a27370939de39679245c3dff72383c210bdJim Grosbach if (!CanAcceptCarrySet && CarrySetting) { 480733c16a27370939de39679245c3dff72383c210bdJim Grosbach Parser.EatToEndOfStatement(); 4808ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 480933c16a27370939de39679245c3dff72383c210bdJim Grosbach "' can not set flags, but 's' suffix specified"); 481033c16a27370939de39679245c3dff72383c210bdJim Grosbach } 4811c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // If we had a predication code on an instruction that can't do that, issue an 4812c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // error. 4813c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 4814c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.EatToEndOfStatement(); 4815c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 4816c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach "' is not predicable, but condition code specified"); 4817c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 481833c16a27370939de39679245c3dff72383c210bdJim Grosbach 48193771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the carry setting operand, if necessary. 4820f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (CanAcceptCarrySet) { 4821f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 48223771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 4823f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Loc)); 4824f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 48253771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 48263771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the predication code operand, if necessary. 48273771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar if (CanAcceptPredicationCode) { 4828f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 4829f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CarrySetting); 48303771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCondCode( 4831f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes(PredicationCode), Loc)); 4832badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar } 4833345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 4834a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Add the processor imod operand, if necessary. 4835a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (ProcessorIMod) { 4836a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateImm( 4837a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes MCConstantExpr::Create(ProcessorIMod, getContext()), 4838a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes NameLoc, NameLoc)); 4839a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4840a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 4841345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar // Add the remaining tokens in the mnemonic. 48425747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar while (Next != StringRef::npos) { 48435747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Start = Next; 48445747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Next = Name.find('.', Start + 1); 4845a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef ExtraToken = Name.slice(Start, Next); 4846a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 48477aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // Some NEON instructions have an optional datatype suffix that is 48487aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // completely ignored. Check for that. 48497aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach if (isDataTypeToken(ExtraToken) && 48507aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 48517aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach continue; 48527aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 485381d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach if (ExtraToken != ".n") { 485481d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 485581d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 485681d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach } 48575747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar } 48585747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar 48595747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar // Read the remaining operands. 48605747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar if (getLexer().isNot(AsmToken::EndOfStatement)) { 4861a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Read the first operand. 48621355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 4863cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4864cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 4865cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4866a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4867a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby while (getLexer().is(AsmToken::Comma)) { 4868b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat the comma. 4869a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4870a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Parse and remember the operand. 48711355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 4872cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4873cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 4874cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4875a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 4876a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 487716c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 4878cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner if (getLexer().isNot(AsmToken::EndOfStatement)) { 4879186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach SMLoc Loc = getLexer().getLoc(); 4880cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4881186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach return Error(Loc, "unexpected token in argument list"); 4882cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4883146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 488434e53140c2cc02ce4c9d060e48302576d3962e1cChris Lattner Parser.Lex(); // Consume the EndOfStatement 4885ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 4886d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // Some instructions, mostly Thumb, have forms for the same mnemonic that 4887d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // do and don't have a cc_out optional-def operand. With some spot-checks 4888d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // of the operand list, we can figure out which variant we're trying to 488920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // parse and adjust accordingly before actually matching. We shouldn't ever 489020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // try to remove a cc_out operand that was explicitly set on the the 489120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // mnemonic, of course (CarrySetting == true). Reason number #317 the 489220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // table driven matcher doesn't fit well with the ARM instruction set. 489320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 4894ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4895ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.erase(Operands.begin() + 1); 4896ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach delete Op; 4897ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 4898ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 4899cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // ARM mode 'blx' need special handling, as the register operand version 4900cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // is predicable, but the label operand version is not. So, we can't rely 4901cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // on the Mnemonic based checking to correctly figure out when to put 490221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // a k_CondCode operand in the list. If we're trying to match the label 490321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // version, remove the k_CondCode operand here. 4904cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 4905cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach static_cast<ARMOperand*>(Operands[2])->isImm()) { 4906cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4907cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach Operands.erase(Operands.begin() + 1); 4908cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach delete Op; 4909cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach } 4910857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach 4911857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // The vector-compare-to-zero instructions have a literal token "#0" at 4912857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // the end that comes to here as an immediate operand. Convert it to a 4913857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // token to play nicely with the matcher. 4914857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 4915857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 4916857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 4917857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4918857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4919857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if (CE && CE->getValue() == 0) { 4920857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.erase(Operands.begin() + 5); 4921857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 492268259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach delete Op; 492368259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 492468259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 492568259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach // VCMP{E} does the same thing, but with a different operand count. 492668259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 492768259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm()) { 492868259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 492968259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 493068259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if (CE && CE->getValue() == 0) { 493168259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.erase(Operands.begin() + 4); 493268259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4933857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach delete Op; 4934857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 4935857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 4936934755ac040c516eac7fdd974e87590543acd16aJim Grosbach // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 493755b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // end. Convert it to a token here. Take care not to convert those 493855b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // that should hit the Thumb2 encoding. 4939934755ac040c516eac7fdd974e87590543acd16aJim Grosbach if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 494055b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 494155b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 4942934755ac040c516eac7fdd974e87590543acd16aJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 4943934755ac040c516eac7fdd974e87590543acd16aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4944934755ac040c516eac7fdd974e87590543acd16aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 494555b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach if (CE && CE->getValue() == 0 && 494655b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isThumbOne() || 4947d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // The cc_out operand matches the IT block. 4948d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach ((inITBlock() != CarrySetting) && 4949d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // Neither register operand is a high register. 495055b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4951d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 4952934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.erase(Operands.begin() + 5); 4953934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4954934755ac040c516eac7fdd974e87590543acd16aJim Grosbach delete Op; 4955934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 4956934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 4957934755ac040c516eac7fdd974e87590543acd16aJim Grosbach 49589898671a74d3fc924347e679c45edaa685b3fe6eChris Lattner return false; 4959ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 4960ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 4961189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// Validate context-sensitive operand constraints. 4962aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 4963aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// return 'true' if register list contains non-low GPR registers, 4964aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'false' otherwise. If Reg is in the register list or is HiReg, set 4965aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'containsReg' to true. 4966aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbachstatic bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 4967aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned HiReg, bool &containsReg) { 4968aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = false; 4969aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 4970aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 4971aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (OpReg == Reg) 4972aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = true; 4973aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach // Anything other than a low register isn't legal here. 4974aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 4975aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return true; 4976aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach } 4977aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return false; 4978aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach} 4979aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 498076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// Check if the specified regisgter is in the register list of the inst, 498176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// starting at the indicated operand number. 498276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbachstatic bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 498376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 498476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 498576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (OpReg == Reg) 498676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return true; 498776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 498876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return false; 498976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach} 499076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach 4991f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 4992f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// the ARMInsts array) instead. Getting that here requires awkward 4993f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// API changes, though. Better way? 4994f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbachnamespace llvm { 49951a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerextern const MCInstrDesc ARMInsts[]; 4996f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 49971a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerstatic const MCInstrDesc &getInstDesc(unsigned Opcode) { 4998f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return ARMInsts[Opcode]; 4999f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 5000f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 5001189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// FIXME: We would really like to be able to tablegen'erate this. 5002189610f9466686a91fb7d847b572e1645c785323Jim Grosbachbool ARMAsmParser:: 5003189610f9466686a91fb7d847b572e1645c785323Jim GrosbachvalidateInstruction(MCInst &Inst, 5004189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 50051a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5006f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = Operands[0]->getStartLoc(); 5007f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Check the IT block state first. 5008b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // NOTE: In Thumb mode, the BKPT instruction has the interesting property of 5009b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // being allowed in IT blocks, but not being predicable. It just always 5010b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // executes. 5011b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { 5012f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned bit = 1; 5013f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITState.FirstCond) 5014f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = false; 5015f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach else 5016a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5017f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // The instruction must be predicable. 5018f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (!MCID.isPredicable()) 5019f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "instructions in IT block must be predicable"); 5020f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5021f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned ITCond = bit ? ITState.Cond : 5022f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::getOppositeCondition(ITState.Cond); 5023f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (Cond != ITCond) { 5024f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Find the condition code Operand to get its SMLoc information. 5025f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc CondLoc; 5026f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach for (unsigned i = 1; i < Operands.size(); ++i) 5027f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5028f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CondLoc = Operands[i]->getStartLoc(); 5029f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(CondLoc, "incorrect condition in IT block; got '" + 5030f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5031f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach "', but expected '" + 5032f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5033f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 5034c9a9b442853ee086492d6ad1384a2de2fea9b43bJim Grosbach // Check for non-'al' condition codes outside of the IT block. 5035f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } else if (isThumbTwo() && MCID.isPredicable() && 5036f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 503751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson ARMCC::AL && Inst.getOpcode() != ARM::tB && 503851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.getOpcode() != ARM::t2B) 5039f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "predicated instructions must be in IT block"); 5040f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 5041189610f9466686a91fb7d847b572e1645c785323Jim Grosbach switch (Inst.getOpcode()) { 50422fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD: 50432fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_PRE: 50442fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_POST: 5045189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::LDREXD: { 5046189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5047189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5048189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5049189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 5050189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return Error(Operands[3]->getStartLoc(), 5051189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "destination operands must be sequential"); 5052189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5053189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 505414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach case ARM::STRD: { 505514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt2 must be Rt + 1. 505614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 505714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 505814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach if (Rt2 != Rt + 1) 505914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 506014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach "source operands must be sequential"); 506114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return false; 506214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach } 506353642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_PRE: 506453642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_POST: 5065189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::STREXD: { 5066189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5067189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5068189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 5069189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 507014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 5071189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "source operands must be sequential"); 5072189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5073189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5074fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::SBFX: 5075fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::UBFX: { 5076fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach // width must be in range [1, 32-lsb] 5077fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned lsb = Inst.getOperand(2).getImm(); 5078fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned widthm1 = Inst.getOperand(3).getImm(); 5079fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach if (widthm1 >= 32 - lsb) 5080fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach return Error(Operands[5]->getStartLoc(), 5081fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach "bitfield width must be in range [1,32-lsb]"); 508200c9a518886c4f2d1cd869c174c994c20a353906Jim Grosbach return false; 5083fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach } 508493b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach case ARM::tLDMIA: { 508576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're parsing Thumb2, the .w variant is available and handles 508676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // most cases that are normally illegal for a Thumb1 LDM 508776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instruction. We'll make the transformation in processInstruction() 508876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // if necessary. 508976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 509093b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // Thumb LDM instructions are writeback iff the base register is not 509193b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // in the register list. 509293b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 50937260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach bool hasWritebackToken = 50947260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 50957260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5096aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 509776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5098aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5099aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7"); 510093b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // If we should have writeback, then there should be a '!' token. 510176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 510293b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach return Error(Operands[2]->getStartLoc(), 510393b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach "writeback operator '!' expected"); 510476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we should not have writeback, there must not be a '!'. This is 510576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // true even for the 32-bit wide encodings. 5106aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (listContainsBase && hasWritebackToken) 51077260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach return Error(Operands[3]->getStartLoc(), 51087260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "writeback operator '!' not allowed when base register " 51097260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "in register list"); 511093b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach 511193b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach break; 511293b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach } 511376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::t2LDMIA_UPD: { 511476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 511576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return Error(Operands[4]->getStartLoc(), 511676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "writeback operator '!' not allowed when base register " 511776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "in register list"); 511876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 511976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 51205402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 51215402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // so only issue a diagnostic for thumb1. The instructions will be 51225402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // switched to the t2 encodings in processInstruction() if necessary. 51236dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPOP: { 5124aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 51255402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 51265402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5127aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5128aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or pc"); 51296dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 51306dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 51316dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPUSH: { 5132aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 51335402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 51345402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5135aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5136aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or lr"); 51376dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 51386dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 51391e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach case ARM::tSTMIA_UPD: { 51401e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach bool listContainsBase; 51418213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 51421e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach return Error(Operands[4]->getStartLoc(), 51431e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach "registers must be in range r0-r7"); 51441e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach break; 51451e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach } 5146189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5147189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 5148189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5149189610f9466686a91fb7d847b572e1645c785323Jim Grosbach} 5150189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 51515b484312c66f8d125c072517947538f301c5a805Jim Grosbachstatic unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) { 515284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach switch(Opc) { 515384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach default: assert(0 && "unexpected opcode!"); 51549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST1LN 51559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8: 51569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8: 51579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_U8: 51585b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8_UPD; 51609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16: 51619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16: 51629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_U16: 51635b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16_UPD; 51659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F: 51669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32: 51679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: 51685b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32_UPD; 51709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8: 51719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8: 51729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_U8: 51735b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8_UPD; 51759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16: 51769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16: 51779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_U16: 51785b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16_UPD; 51809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F: 51819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32: 51829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: 51835b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32_UPD; 51859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: 51869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8: 51879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_U8: 51885b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8; 51909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16: 51919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16: 51929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_U16: 51935b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16; 51959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F: 51969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: 51979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32: 51985b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51999b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32; 52009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 52019b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST2LN 52029b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: 52039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: 52049b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_U8: 52055b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52069b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8_UPD; 52079b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16: 52089b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16: 52099b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_U16: 52105b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16_UPD; 52129b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: 52139b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: 52149b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: 52155b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32_UPD; 52175b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: 52185b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: 52195b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_U16: 52205b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52215b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16_UPD; 52225b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F: 52235b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32: 52245b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32: 52255b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52265b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32_UPD; 52275b484312c66f8d125c072517947538f301c5a805Jim Grosbach 52289b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: 52299b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: 52309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_U8: 52315b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52329b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8_UPD; 52339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16: 52349b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16: 52359b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_U16: 52365b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52379b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16_UPD; 52389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: 52399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: 52409b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: 52415b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32_UPD; 52435b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: 52445b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: 52455b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_U16: 52465b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52475b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16_UPD; 52485b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F: 52495b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32: 52505b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32: 52515b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52525b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32_UPD; 52535b484312c66f8d125c072517947538f301c5a805Jim Grosbach 52549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: 52559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8: 52569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_U8: 52575b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8; 52599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16: 52609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: 52619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_U16: 52625b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16; 52649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: 52659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: 52669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32: 52675b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32; 52695b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: 52705b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: 52715b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_U16: 52725b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52735b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16; 52745b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: 52755b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32: 52765b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32: 52775b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52785b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32; 527984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 528084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach} 528184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach 528295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbachstatic unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) { 52837636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach switch(Opc) { 52847636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach default: assert(0 && "unexpected opcode!"); 52859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD1LN 52869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8: 52879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8: 52889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_U8: 528995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8_UPD; 52919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16: 52929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16: 52939b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_U16: 529495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16_UPD; 52969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F: 52979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32: 52989b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: 529995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32_UPD; 53019b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8: 53029b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8: 53039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_U8: 530495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53059b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8_UPD; 53069b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16: 53079b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16: 53089b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_U16: 530995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53109b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16_UPD; 53119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F: 53129b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32: 53139b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: 531495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53159b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32_UPD; 53169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: 53179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8: 53189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_U8: 531995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53209b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8; 53219b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16: 53229b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: 53239b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_U16: 532495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53259b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16; 53269b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: 53279b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: 53289b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32: 532995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32; 53319b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 53329b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD2LN 53339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: 53349b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: 53359b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_U8: 533695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53379b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8_UPD; 53389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16: 53399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16: 53409b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_U16: 534195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16_UPD; 53439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: 53449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: 53459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: 534695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32_UPD; 534895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: 534995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: 535095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_U16: 535195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 535295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16_UPD; 535395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: 535495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: 535595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: 535695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 535795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32_UPD; 53589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: 53599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: 53609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_U8: 536195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8_UPD; 53639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16: 53649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16: 53659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_U16: 536695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16_UPD; 53689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: 53699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: 53709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: 537195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32_UPD; 537395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: 537495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: 537595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_U16: 537695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 537795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16_UPD; 537895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: 537995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: 538095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: 538195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 538295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32_UPD; 53839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: 53849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8: 53859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_U8: 538695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8; 53889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16: 53899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: 53909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_U16: 539195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16; 53939b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: 53949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: 53959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32: 539695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32; 539895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: 539995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: 540095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_U16: 540195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 540295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16; 540395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: 540495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32: 540595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32: 540695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 540795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32; 54087636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 54097636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach} 54107636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 541183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbachbool ARMAsmParser:: 5412f8fce711e8b756adca63044f7d122648c960ab96Jim GrosbachprocessInstruction(MCInst &Inst, 5413f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5414f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach switch (Inst.getOpcode()) { 54150b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Aliases for alternate PC+imm syntax of LDR instructions. 54160b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRpcrel: 54170b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRpci); 54180b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 54190b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRBpcrel: 54200b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRBpci); 54210b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 54220b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRHpcrel: 54230b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRHpci); 54240b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 54250b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRSBpcrel: 54260b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRSBpci); 54270b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 54280b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRSHpcrel: 54290b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRSHpci); 54300b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 54319b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VST complex aliases. 54329b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8: 54339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8: 54349b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_U8: case ARM::VST1LNdWB_register_Asm_16: 54359b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_P16: case ARM::VST1LNdWB_register_Asm_I16: 54369b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_S16: case ARM::VST1LNdWB_register_Asm_U16: 54379b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F: 54389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32: 54399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: { 544084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 544184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 544284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 54435b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 54445b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 544584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 544684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 544784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 544884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 544984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 545084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 545184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 545284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 545384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 545484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 545584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 54569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 54575b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: 54585b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: 54595b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16: 54609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16: 54619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16: 54625b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: 54639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: 54645b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: 54655b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: 54665b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: 54675b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32: 54685b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32: 54695b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32: 54705b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_U32: { 54719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 54729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 54739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 54745b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 54755b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 54769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 54779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 54789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 54799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 54809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 54815b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 54825b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 54839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 54849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 54859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 54869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 54879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 54889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 54899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8: 54909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8: 54919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_U8: case ARM::VST1LNdWB_fixed_Asm_16: 54929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_P16: case ARM::VST1LNdWB_fixed_Asm_I16: 54939b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_S16: case ARM::VST1LNdWB_fixed_Asm_U16: 54949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F: 54959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32: 54969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: { 549784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 549884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 549984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 55005b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 55015b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 550284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 550384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 550484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 550584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 550684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 550784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 550884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 550984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 551084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 551184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 551284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 55139b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 55145b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: 55155b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: 55165b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16: 55179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16: 55189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16: 55195b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: 55209b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: 55215b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: 55225b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: 55235b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: 55245b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32: 55255b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32: 55265b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32: 55275b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_U32: { 55289b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 55299b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 55309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 55315b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 55325b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 55339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 55349b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 55359b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 55369b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 55379b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 55385b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 55395b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 55409b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 55419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 55429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 55439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 55449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 55459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 55469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: case ARM::VST1LNdAsm_I8: 55479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_S8: case ARM::VST1LNdAsm_U8: case ARM::VST1LNdAsm_16: 55489b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_P16: case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16: 55499b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_U16: case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F: 55509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: case ARM::VST1LNdAsm_S32: 555184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach case ARM::VST1LNdAsm_U32: { 555284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 555384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 555484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 55555b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 55565b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 555784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 555884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 555984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 556084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 556184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 556284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 556384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 556484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 556584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 55669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 55675b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: 55685b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16: 55699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: 55705b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: 55719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32: 55725b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: 55735b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16: 55745b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32: 55755b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{ 55769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 55779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 55789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 55795b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 55805b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 55819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 55829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 55839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 55845b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 55855b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 55869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 55879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 55889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 55899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 55909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 55919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 55929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VLD complex aliases. 55939b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8: 55949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8: 55959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_U8: case ARM::VLD1LNdWB_register_Asm_16: 55969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_P16: case ARM::VLD1LNdWB_register_Asm_I16: 55979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_S16: case ARM::VLD1LNdWB_register_Asm_U16: 55989b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F: 55999b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32: 56009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: { 5601872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 5602872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 5603872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 560495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 560595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 5606872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5607872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5608872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 5609872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 5610872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 5611872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5612872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 5613872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5614872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 5615872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 5616872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 5617872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 56189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 561995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: 562095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: 562195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16: 56229b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16: 56239b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16: 562495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: 56259b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: 562695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: 56275b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: 56285b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: 56295b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32: 56305b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32: 56315b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32: 56325b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_U32: { 56339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 56349b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56359b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 563695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 563795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 56389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 563995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 564095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 56429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 56449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 56459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 564695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 564795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56489b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 56499b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 56509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 56519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 56529b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 56539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 56549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 56559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8: 56569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8: 56579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_U8: case ARM::VLD1LNdWB_fixed_Asm_16: 56589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_P16: case ARM::VLD1LNdWB_fixed_Asm_I16: 56599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_S16: case ARM::VLD1LNdWB_fixed_Asm_U16: 56609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F: 56619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32: 56629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: { 5663872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 5664872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 5665872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 566695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 566795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 5668872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5669872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5670872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 5671872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 5672872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5673872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5674872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 5675872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5676872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 5677872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 5678872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 5679872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 56809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 568195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: 568295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: 568395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16: 56849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16: 56859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16: 568695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: 56879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: 568895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: 56895b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: 56905b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: 56915b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32: 56925b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32: 56935b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32: 56945b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_U32: { 56959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 56969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 569895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 569995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 57009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 570195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 570295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 57049b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57059b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57069b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 57079b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 570895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 570995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57109b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57129b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57139b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 57149b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 57159b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 57169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 57175b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: 57185b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16: 57199b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: 57205b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: 57219b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32: 5722dad2f8e7fb2df5fb080a38fa4c33a01f19729f15Jim Grosbach case ARM::VLD1LNdAsm_U32: { 57237636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach MCInst TmpInst; 57247636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // Shuffle the operands around so the lane index operand is in the 57257636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // right place. 572695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 572795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 57287636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 57297636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57307636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57317636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 57327636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57337636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57347636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57357636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst = TmpInst; 57367636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return true; 57377636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 57389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 573995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: 574095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16: 57419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: 574295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: 57439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32: 574495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: 574595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16: 574695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32: 574795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32: 574895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_U32: { 57499b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 57509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 57519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 575295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 575395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 57549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 575595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 575695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 576095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 576195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 57669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 57679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 5768863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the Thumb2 mode MOV complex aliases. 57692cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVsr: 57702cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVSsr: { 57712cc5cda464e7c936215281934193658cb799c603Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 57722cc5cda464e7c936215281934193658cb799c603Jim Grosbach // whether we're in an IT block if the register operands are low 57732cc5cda464e7c936215281934193658cb799c603Jim Grosbach // registers. 57742cc5cda464e7c936215281934193658cb799c603Jim Grosbach bool isNarrow = false; 57752cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 57762cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 57772cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg()) && 57782cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 57792cc5cda464e7c936215281934193658cb799c603Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 57802cc5cda464e7c936215281934193658cb799c603Jim Grosbach isNarrow = true; 57812cc5cda464e7c936215281934193658cb799c603Jim Grosbach MCInst TmpInst; 57822cc5cda464e7c936215281934193658cb799c603Jim Grosbach unsigned newOpc; 57832cc5cda464e7c936215281934193658cb799c603Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 57842cc5cda464e7c936215281934193658cb799c603Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 57852cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 57862cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 57872cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 57882cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 57892cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 57902cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.setOpcode(newOpc); 57912cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 57922cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isNarrow) 57932cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 57942cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 57952cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 57962cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 57972cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57982cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57992cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (!isNarrow) 58002cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 58012cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 58022cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst = TmpInst; 58032cc5cda464e7c936215281934193658cb799c603Jim Grosbach return true; 58042cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 5805863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVsi: 5806863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVSsi: { 5807863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 5808863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // whether we're in an IT block if the register operands are low 5809863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // registers. 5810863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach bool isNarrow = false; 5811863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 5812863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 5813863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 5814863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isNarrow = true; 5815863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach MCInst TmpInst; 5816863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach unsigned newOpc; 5817863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 5818863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 5819863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 5820863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 5821863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 5822863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 5823520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 5824863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 5825863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 5826863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (Ammount == 32) Ammount = 0; 5827863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.setOpcode(newOpc); 5828863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 5829863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isNarrow) 5830863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 5831863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 5832863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5833520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach if (newOpc != ARM::t2RRX) 5834520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Ammount)); 5835863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5836863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 5837863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (!isNarrow) 5838863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 5839863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 5840863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst = TmpInst; 5841863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach return true; 5842863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 5843863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the ARM mode MOV complex aliases. 584423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: 584523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: 584623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: 584723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: { 584823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 584923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach switch(Inst.getOpcode()) { 585023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 585123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 585223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 585323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 585423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: ShiftTy = ARM_AM::ror; break; 585523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 585623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 585723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach MCInst TmpInst; 585823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.setOpcode(ARM::MOVsr); 585923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 586023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 586123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 586223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 586323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 586423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 586523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 586623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach Inst = TmpInst; 586723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach return true; 586823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 5869ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: 5870ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: 5871ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: 5872ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: { 5873ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 5874ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach switch(Inst.getOpcode()) { 5875ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 5876ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 5877ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 5878ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 5879ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: ShiftTy = ARM_AM::ror; break; 5880ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 5881ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach // A shift by zero is a plain MOVr, not a MOVsi. 588248b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Amt = Inst.getOperand(2).getImm(); 5883ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 5884ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 588571810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach MCInst TmpInst; 5886ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.setOpcode(Opc); 588771810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 588871810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5889ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (Opc == ARM::MOVsi) 5890ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 589171810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 589271810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 589371810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 589471810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach Inst = TmpInst; 589583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 589671810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach } 589748b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach case ARM::RRXi: { 589848b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 589948b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach MCInst TmpInst; 590048b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.setOpcode(ARM::MOVsi); 590148b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 590248b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 590348b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 590448b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 590548b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 590648b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // cc_out 590748b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach Inst = TmpInst; 590848b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach return true; 590948b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach } 59100352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2LDMIA_UPD: { 59110352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a load of a single register, then we should use 59120352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 59130352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 59140352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 59150352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 59160352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2LDR_POST); 59170352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 59180352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 59190352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 59200352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 59210352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 59220352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 59230352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 59240352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 59250352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 59260352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2STMDB_UPD: { 59270352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a store of a single register, then we should use 59280352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 59290352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 59300352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 59310352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 59320352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2STR_PRE); 59330352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 59340352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 59350352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 59360352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 59370352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 59380352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 59390352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 59400352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 59410352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 5942f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach case ARM::LDMIA_UPD: 5943f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // If this is a load of a single register via a 'pop', then we should use 5944f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 5945f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 5946f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst.getNumOperands() == 5) { 5947f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach MCInst TmpInst; 5948f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.setOpcode(ARM::LDR_POST_IMM); 5949f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 5950f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5951f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5952f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 5953f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 5954f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5955f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 5956f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst = TmpInst; 595783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 5958f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 5959f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach break; 5960f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach case ARM::STMDB_UPD: 5961f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // If this is a store of a single register via a 'push', then we should use 5962f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 5963f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 5964f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst.getNumOperands() == 5) { 5965f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach MCInst TmpInst; 5966f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.setOpcode(ARM::STR_PRE_IMM); 5967f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5968f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 5969f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 5970f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 5971f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5972f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 5973f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst = TmpInst; 5974f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach } 5975f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach break; 5976da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2ADDri12: 5977da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 5978da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "addw"), encoding T3 is preferred. 5979da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 5980da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 5981da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 5982da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2ADDri); 5983da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 5984da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 5985da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2SUBri12: 5986da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 5987da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "subw"), encoding T3 is preferred. 5988da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 5989da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 5990da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 5991da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2SUBri); 5992da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 5993da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 599489e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach case ARM::tADDi8: 59950f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 59960f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 59970f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 59980f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T1 if <Rd> is omitted." 599983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 600089e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach Inst.setOpcode(ARM::tADDi3); 600183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 600283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 600389e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach break; 6004f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach case ARM::tSUBi8: 6005f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 6006f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 6007f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 6008f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T1 if <Rd> is omitted." 600983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 6010f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Inst.setOpcode(ARM::tSUBi3); 601183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 601283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 6013f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach break; 6014927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach case ARM::t2ADDrr: { 6015927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // If the destination and first source operand are the same, and 6016927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // there's no setting of the flags, use encoding T2 instead of T3. 6017927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // Note that this is only for ADD, not SUB. This mirrors the system 6018927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // 'as' behaviour. Make sure the wide encoding wasn't explicit. 6019927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 6020927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst.getOperand(5).getReg() != 0 || 6021713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 6022713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 6023927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach break; 6024927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach MCInst TmpInst; 6025927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.setOpcode(ARM::tADDhirr); 6026927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6027927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6028927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 6029927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6030927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6031927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst = TmpInst; 6032927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach return true; 6033927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach } 603451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::tB: 603551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb conditional branch outside of an IT block is a tBcc. 603683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 603751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::tBcc); 603883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 603983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 604051f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 604151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::t2B: 604251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 604383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 604451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::t2Bcc); 604583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 604683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 604751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 6048c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach case ARM::t2Bcc: 6049a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // If the conditional is AL or we're in an IT block, we really want t2B. 605083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 6051c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach Inst.setOpcode(ARM::t2B); 605283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 605383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 6054c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach break; 6055395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach case ARM::tBcc: 6056395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach // If the conditional is AL, we really want tB. 605783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL) { 6058395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach Inst.setOpcode(ARM::tB); 605983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 606083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 60613ce23d3d87d1ca437acb65ac01fac1c486507280Jim Grosbach break; 606276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::tLDMIA: { 606376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If the register list contains any high registers, or if the writeback 606476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 606576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instead if we're in Thumb2. Otherwise, this should have generated 606676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // an error in validateInstruction(). 606776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 606876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool hasWritebackToken = 606976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 607076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 607176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool listContainsBase; 607276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 607376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (!listContainsBase && !hasWritebackToken) || 607476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (listContainsBase && hasWritebackToken)) { 607576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 607676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach assert (isThumbTwo()); 607776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 607876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're switching to the updating version, we need to insert 607976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // the writeback tied operand. 608076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (hasWritebackToken) 608176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.insert(Inst.begin(), 608276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach MCOperand::CreateReg(Inst.getOperand(0).getReg())); 608383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 608476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 608576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 608676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 60878213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach case ARM::tSTMIA_UPD: { 60888213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // If the register list contains any high registers, we need to use 60898213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 60908213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // should have generated an error in validateInstruction(). 60918213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 60928213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach bool listContainsBase; 60938213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 60948213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 60958213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach assert (isThumbTwo()); 60968213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach Inst.setOpcode(ARM::t2STMIA_UPD); 609783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 60988213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 60998213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach break; 61008213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 61015402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPOP: { 61025402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 61035402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // If the register list contains any high registers, we need to use 61045402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 61055402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // should have generated an error in validateInstruction(). 61065402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 610783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 61085402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 61095402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2LDMIA_UPD); 61105402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 61115402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 61125402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 611383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 61145402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 61155402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPUSH: { 61165402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 61175402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 611883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 61195402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 61205402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2STMDB_UPD); 61215402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 61225402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 61235402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 612483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 61255402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 61261ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVi: { 61271ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 61281ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 61291ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 61301ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(1).getImm() <= 255 && 6131c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 6132c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR) || 6133c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 61341ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 61351ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 61361ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't in the same order for tMOVi8... 61371ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 61381ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(ARM::tMOVi8); 61391ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 61401ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 61411ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 61421ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 61431ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 61441ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 614583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 61461ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 61471ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 61481ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 61491ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVr: { 61501ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 61511ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 61521ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 61531ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 61541ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(2).getImm() == ARMCC::AL && 61551ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR && 61561ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 61571ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 61581ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't the same for tMOV[S]r... (no cc_out) 61591ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 61601ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 61611ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 61621ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 61631ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 61641ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 61651ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 616683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 61671ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 61681ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 61691ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 6170326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach case ARM::t2SXTH: 617150f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: 617250f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: 617350f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: { 6174326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 6175326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // request the 32-bit variant, transform it here. 6176326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6177326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6178326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst.getOperand(2).getImm() == 0 && 6179326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 6180326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 618150f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach unsigned NewOpc; 618250f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach switch (Inst.getOpcode()) { 618350f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach default: llvm_unreachable("Illegal opcode!"); 618450f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 618550f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 618650f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 618750f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 618850f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach } 6189326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // The operands aren't the same for thumb1 (no rotate operand). 6190326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach MCInst TmpInst; 6191326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.setOpcode(NewOpc); 6192326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6193326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 6194326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6195326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6196326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst = TmpInst; 619783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 6198326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 6199326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach break; 6200326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 620104b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach case ARM::MOVsi: { 620204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 620304b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach if (SOpc == ARM_AM::rrx) return false; 620404b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 620504b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach // Shifting by zero is accepted as a vanilla 'MOVr' 620604b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach MCInst TmpInst; 620704b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.setOpcode(ARM::MOVr); 620804b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 620904b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 621004b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 621104b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 621204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 621304b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach Inst = TmpInst; 621404b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return true; 621504b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 621604b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return false; 621704b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 62188d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: 62198d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: 62208d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: 62218d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: 62228d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: 62238d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: { 62248d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach unsigned newOpc; 62258d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 62268d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (SOpc == ARM_AM::rrx) return false; 62278d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach switch (Inst.getOpcode()) { 622819055cc2712223f6834fc3cf5b547803ba83f066Matt Beaumont-Gay default: assert(0 && "unexpected opcode!"); 62298d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 62308d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 62318d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: newOpc = ARM::EORrr; break; 62328d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: newOpc = ARM::BICrr; break; 62338d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 62348d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 62358d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 62368d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach // If the shift is by zero, use the non-shifted instruction definition. 62378d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) { 62388d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach MCInst TmpInst; 62398d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.setOpcode(newOpc); 62408d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 62418d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 62428d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 62438d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 62448d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 62458d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 62468d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach Inst = TmpInst; 62478d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return true; 62488d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 62498d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return false; 62508d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 625189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach case ARM::t2IT: { 625289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The mask bits for all but the first condition are represented as 625389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // the low bit of the condition code value implies 't'. We currently 625489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // always have 1 implies 't', so XOR toggle the bits if the low bit 625589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // of the condition code is zero. The encoding also expects the low 625689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // bit of the condition to be encoded as bit 4 of the mask operand, 625789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // so mask that in if needed 625889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MCOperand &MO = Inst.getOperand(1); 625989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = MO.getImm(); 6260f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned OrigMask = Mask; 6261f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned TZ = CountTrailingZeros_32(Mask); 626289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if ((Inst.getOperand(0).getImm() & 1) == 0) { 626389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(Mask && TZ <= 3 && "illegal IT mask value!"); 626489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = 3; i != TZ; --i) 626589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask ^= 1 << i; 626689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } else 626789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask |= 0x10; 626889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MO.setImm(Mask); 6269f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 6270f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Set up the IT block state according to the IT instruction we just 6271f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // matched. 6272f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach assert(!inITBlock() && "nested IT blocks?!"); 6273f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 6274f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Mask = OrigMask; // Use the original mask, not the updated one. 6275f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = 0; 6276f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = true; 627789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 627889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 6279f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 628083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 6281f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach} 6282f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 628347a0d52b69056250a1edaca8b28f705993094542Jim Grosbachunsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 628447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // 16-bit thumb arithmetic instructions either require or preclude the 'S' 628547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // suffix depending on whether they're in an IT block or not. 6286194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach unsigned Opc = Inst.getOpcode(); 62871a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Opc); 628847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 628947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.hasOptionalDef() && 629047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "optionally flag setting instruction missing optional def operand"); 629147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.NumOperands == Inst.getNumOperands() && 629247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "operand count mismatch!"); 629347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // Find the optional-def operand (cc_out). 629447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned OpNo; 629547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach for (OpNo = 0; 629647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 629747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ++OpNo) 629847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ; 629947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb1, reject it completely. 630047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 630147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_MnemonicFail; 630247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb2, which form is legal depends on whether we're 630347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // in an IT block. 6304f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 6305f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach !inITBlock()) 630647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_RequiresITBlock; 6307f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 6308f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach inITBlock()) 6309f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Match_RequiresNotITBlock; 631047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 6311194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Some high-register supporting Thumb1 encodings only allow both registers 6312194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // to be from r0-r7 when in Thumb2. 6313194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach else if (Opc == ARM::tADDhirr && isThumbOne() && 6314194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6315194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg())) 6316194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresThumb2; 6317194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Others only require ARMv6 or later. 63184ec6e888ec6d12b5255afd685b05c8fee1f7fc73Jim Grosbach else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 6319194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(0).getReg()) && 6320194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg())) 6321194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresV6; 632247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_Success; 632347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach} 632447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 6325fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattnerbool ARMAsmParser:: 6326fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris LattnerMatchAndEmitInstruction(SMLoc IDLoc, 6327fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner SmallVectorImpl<MCParsedAsmOperand*> &Operands, 6328fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCStreamer &Out) { 6329fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCInst Inst; 6330fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner unsigned ErrorInfo; 633119cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach unsigned MatchResult; 6332193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 6333193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby switch (MatchResult) { 633419cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach default: break; 6335e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_Success: 6336189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Context sensitive operand constraints aren't handled by the matcher, 6337189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // so check them here. 6338a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (validateInstruction(Inst, Operands)) { 6339a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Still progress the IT block, otherwise one wrong condition causes 6340a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // nasty cascading errors. 6341a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 6342189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return true; 6343a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 6344189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 6345f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // Some instructions need post-processing to, for example, tweak which 634683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // encoding is selected. Loop on it while changes happen so the 634783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // individual transformations can chain off each other. E.g., 634883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 634983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach while (processInstruction(Inst, Operands)) 635083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach ; 6351f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 6352a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Only move forward at the very end so that everything in validate 6353a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // and process gets a consistent answer about whether we're in an IT 6354a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // block. 6355a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 6356a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach 6357fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner Out.EmitInstruction(Inst); 6358fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner return false; 6359e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_MissingFeature: 6360e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 6361e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return true; 6362e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_InvalidOperand: { 6363e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner SMLoc ErrorLoc = IDLoc; 6364e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo != ~0U) { 6365e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo >= Operands.size()) 6366e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(IDLoc, "too few operands for instruction"); 636716c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6368e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 6369e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 6370e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 637116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6372e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(ErrorLoc, "invalid operand for instruction"); 6373e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 6374e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_MnemonicFail: 637547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Error(IDLoc, "invalid instruction"); 6376b412915ff6229b3e2dffedcfb0f3fb7e85259841Daniel Dunbar case Match_ConversionFail: 637788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // The converter function will have already emited a diagnostic. 637888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 6379f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach case Match_RequiresNotITBlock: 6380f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(IDLoc, "flag setting instruction only valid outside IT block"); 638147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach case Match_RequiresITBlock: 638247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Error(IDLoc, "instruction only valid inside IT block"); 6383194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresV6: 6384194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires ARMv6 or later"); 6385194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresThumb2: 6386194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires Thumb2"); 6387fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner } 638816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6389c223e2b10b4753a63dfe7e6980c650b179139983Eric Christopher llvm_unreachable("Implement any new match types added!"); 6390146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling return true; 6391fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner} 6392fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner 63931355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirective parses the arm specific directives 6394ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbybool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 6395ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby StringRef IDVal = DirectiveID.getIdentifier(); 6396ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (IDVal == ".word") 63971355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveWord(4, DirectiveID.getLoc()); 6398515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb") 63991355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumb(DirectiveID.getLoc()); 64009a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach else if (IDVal == ".arm") 64019a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return parseDirectiveARM(DirectiveID.getLoc()); 6402515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb_func") 64031355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumbFunc(DirectiveID.getLoc()); 6404515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".code") 64051355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveCode(DirectiveID.getLoc()); 6406515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".syntax") 64071355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveSyntax(DirectiveID.getLoc()); 6408a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach else if (IDVal == ".unreq") 6409a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return parseDirectiveUnreq(DirectiveID.getLoc()); 6410d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".arch") 6411d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveArch(DirectiveID.getLoc()); 6412d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".eabi_attribute") 6413d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveEabiAttr(DirectiveID.getLoc()); 6414ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 6415ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 6416ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 64171355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveWord 6418ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby/// ::= .word [ expression (, expression)* ] 64191355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 6420ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) { 6421ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby for (;;) { 6422ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby const MCExpr *Value; 6423ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getParser().ParseExpression(Value)) 6424ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 6425ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6426aaec205b87637cd0d59d4f11630db603686eb73dChris Lattner getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 6427ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6428ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().is(AsmToken::EndOfStatement)) 6429ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby break; 643016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6431ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby // FIXME: Improve diagnostic. 6432ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::Comma)) 6433ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return Error(L, "unexpected token in directive"); 6434b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6435ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 6436ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 6437ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6438b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6439ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return false; 6440ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 6441ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 64421355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumb 6443515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumb 64441355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 6445515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 6446515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 6447b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6448515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64499a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (!isThumb()) 64509a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 64519a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 64529a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return false; 64539a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach} 64549a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 64559a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// parseDirectiveARM 64569a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// ::= .arm 64579a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbachbool ARMAsmParser::parseDirectiveARM(SMLoc L) { 64589a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 64599a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return Error(L, "unexpected token in directive"); 64609a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach Parser.Lex(); 64619a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 64629a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (isThumb()) 64639a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 64649a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 6465515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6466515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6467515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64681355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumbFunc 6469515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumbfunc symbol_name 64701355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 64716469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 64726469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola bool isMachO = MAI.hasSubsectionsViaSymbols(); 64736469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola StringRef Name; 6474de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach bool needFuncName = true; 64756469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6476de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Darwin asm has (optionally) function name after .thumb_func direction 64776469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // ELF doesn't 64786469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola if (isMachO) { 64796469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const AsmToken &Tok = Parser.getTok(); 6480de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::EndOfStatement)) { 6481de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 6482de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach return Error(L, "unexpected token in .thumb_func directive"); 6483de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Name = Tok.getIdentifier(); 6484de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); // Consume the identifier token. 6485de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach needFuncName = false; 6486de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach } 64876469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 64886469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6489de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 6490515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 6491de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach 6492de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Eat the end of statement and any blank lines that follow. 6493de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach while (getLexer().is(AsmToken::EndOfStatement)) 6494de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); 6495515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64966469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // FIXME: assuming function name will be the line following .thumb_func 6497de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // We really should be checking the next symbol definition even if there's 6498de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // stuff in between. 6499de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (needFuncName) { 6500d475f8612b1c7959dbf50242c8fa9d4aea1ee1a9Jim Grosbach Name = Parser.getTok().getIdentifier(); 65016469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 65026469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6503642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach // Mark symbol as a thumb symbol. 6504642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 6505642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach getParser().getStreamer().EmitThumbFunc(Func); 6506515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6507515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6508515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 65091355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveSyntax 6510515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .syntax unified | divided 65111355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 651218b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 6513515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Identifier)) 6514515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .syntax directive"); 651538e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef Mode = Tok.getString(); 651658c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Mode == "unified" || Mode == "UNIFIED") 6517b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 651858c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Mode == "divided" || Mode == "DIVIDED") 65199e56fb12c504c82c92947fe9c46287fc60116b91Kevin Enderby return Error(L, "'.syntax divided' arm asssembly not supported"); 6520515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 6521515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unrecognized syntax mode in .syntax directive"); 6522515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6523515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 652418b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 6525b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6526515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6527515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // TODO tell the MC streamer the mode 6528515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // getParser().getStreamer().Emit???(); 6529515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6530515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6531515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 65321355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveCode 6533515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .code 16 | 32 65341355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveCode(SMLoc L) { 653518b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 6536515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Integer)) 6537515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .code directive"); 653818b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan int64_t Val = Parser.getTok().getIntVal(); 653958c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Val == 16) 6540b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 654158c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Val == 32) 6542b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6543515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 6544515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "invalid operand to .code directive"); 6545515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6546515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 654718b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 6548b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6549515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 655032869205052430f45d598fba25ab878d8b29da2dEvan Cheng if (Val == 16) { 655198447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (!isThumb()) 6552ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 655398447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 655432869205052430f45d598fba25ab878d8b29da2dEvan Cheng } else { 655598447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (isThumb()) 6556ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 655798447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 6558eb0caa115491019f7f7fe45fc70ad47682244187Evan Cheng } 65592a301704ea76535f0485d5c3b75664b323249bdbJim Grosbach 6560515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6561515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6562515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6563a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveReq 6564a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= name .req registername 6565a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 6566a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the '.req' token. 6567a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach unsigned Reg; 6568a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach SMLoc SRegLoc, ERegLoc; 6569a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 6570a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6571a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "register name expected"); 6572a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6573a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6574a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Shouldn't be anything else. 6575a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 6576a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6577a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(Parser.getTok().getLoc(), 6578a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "unexpected input in .req directive."); 6579a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6580a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6581a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Consume the EndOfStatement 6582a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6583a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 6584a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "redefinition of '" + Name + 6585a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "' does not match original."); 6586a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6587a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 6588a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 6589a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6590a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveUneq 6591a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= .unreq registername 6592a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 6593a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::Identifier)) { 6594a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6595a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(L, "unexpected input in .unreq directive."); 6596a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6597a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach RegisterReqs.erase(Parser.getTok().getIdentifier()); 6598a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the identifier. 6599a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 6600a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 6601a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6602d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveArch 6603d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .arch token 6604d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveArch(SMLoc L) { 6605d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 6606d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 6607d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 6608d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveEabiAttr 6609d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .eabi_attribute int, int 6610d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 6611d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 6612d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 6613d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 661490b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callananextern "C" void LLVMInitializeARMAsmLexer(); 661590b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan 66169c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Force static initialization. 6617ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyextern "C" void LLVMInitializeARMAsmParser() { 661894b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 661994b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 662090b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan LLVMInitializeARMAsmLexer(); 6621ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 66223483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 66230692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_REGISTER_MATCHER 66240692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_MATCHER_IMPLEMENTATION 66253483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar#include "ARMGenAsmMatcher.inc" 6626