ARMAsmParser.cpp revision 19055cc2712223f6834fc3cf5b547803ba83f066
1ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 3ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// The LLVM Compiler Infrastructure 4ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 5ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// This file is distributed under the University of Illinois Open Source 6ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// License. See LICENSE.TXT for details. 7ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 8ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===----------------------------------------------------------------------===// 9ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 1094b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "MCTargetDesc/ARMBaseInfo.h" 11ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 12ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMMCExpr.h" 13c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmLexer.h" 14c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmParser.h" 15c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 166469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola#include "llvm/MC/MCAsmInfo.h" 17642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach#include "llvm/MC/MCContext.h" 18ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCStreamer.h" 19ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCExpr.h" 20ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCInst.h" 217801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng#include "llvm/MC/MCInstrDesc.h" 2294b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCRegisterInfo.h" 23ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng#include "llvm/MC/MCSubtargetInfo.h" 2494b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCTargetAsmParser.h" 2589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach#include "llvm/Support/MathExtras.h" 26c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/Support/SourceMgr.h" 273e74d6fdd248e20a280f1dff3da9a6c689c2c4c3Evan Cheng#include "llvm/Support/TargetRegistry.h" 28fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar#include "llvm/Support/raw_ostream.h" 2911e03e7c2d0c163e54b911ad1e665616dc0bcc8cJim Grosbach#include "llvm/ADT/BitVector.h" 3075ca4b94bd9dcd3952fdc237429342a2154ba142Benjamin Kramer#include "llvm/ADT/OwningPtr.h" 3194b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/ADT/STLExtras.h" 32c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/SmallVector.h" 33345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar#include "llvm/ADT/StringSwitch.h" 34c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/Twine.h" 35ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 36ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyusing namespace llvm; 37ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 383a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 39146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 40146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand; 4116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 427636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbachenum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 4398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 4494b9550a32d189704a8eae55505edf62662c0534Evan Chengclass ARMAsmParser : public MCTargetAsmParser { 45ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng MCSubtargetInfo &STI; 46ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &Parser; 47ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 48a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Map of register aliases registers via the .req directive. 49a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StringMap<unsigned> RegisterReqs; 50a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 51f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach struct { 52f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes Cond; // Condition for IT block. 53f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Mask:4; // Condition mask for instructions. 54f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Starting at first 1 (from lsb). 55f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '1' condition as indicated in IT. 56f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '0' inverse of condition (else). 57f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Count of instructions in IT block is 58f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // 4 - trailingzeroes(mask) 59f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 60f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool FirstCond; // Explicit flag for when we're parsing the 61f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // First instruction in the IT block. It's 62f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // implied in the mask, so needs special 63f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // handling. 64f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 65f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned CurPosition; // Current position in parsing of IT 66f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // block. In range [0,3]. Initialized 67f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // according to count of instructions in block. 68f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // ~0U if no active IT block. 69f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } ITState; 70f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool inITBlock() { return ITState.CurPosition != ~0U;} 71a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach void forwardITPosition() { 72a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (!inITBlock()) return; 73a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Move to the next instruction in the IT block, if there is one. If not, 74a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // mark the block as done. 75a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach unsigned TZ = CountTrailingZeros_32(ITState.Mask); 76a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (++ITState.CurPosition == 5 - TZ) 77a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach ITState.CurPosition = ~0U; // Done with the IT block after this. 78a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 79f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 80f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 81ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &getParser() const { return Parser; } 82ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmLexer &getLexer() const { return Parser.getLexer(); } 83ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 84ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 85ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 86ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 871355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int tryParseRegister(); 881355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 890d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 901355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 921355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 931355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &ShiftAmount); 961355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveWord(unsigned Size, SMLoc L); 971355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumb(SMLoc L); 989a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach bool parseDirectiveARM(SMLoc L); 991355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumbFunc(SMLoc L); 1001355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveCode(SMLoc L); 1011355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveSyntax(SMLoc L); 102a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveReq(StringRef Name, SMLoc L); 103a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveUnreq(SMLoc L); 104d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveArch(SMLoc L); 105d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveEabiAttr(SMLoc L); 106515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 1071355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 10889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach bool &CarrySetting, unsigned &ProcessorIMod, 10989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask); 1101355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 111fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode); 11216c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 113ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumb() const { 114ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // FIXME: Can tablegen auto-generate this? 115ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 116ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 117ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumbOne() const { 118ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 119ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 12047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach bool isThumbTwo() const { 12147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 12247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 123194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach bool hasV6Ops() const { 124194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return STI.getFeatureBits() & ARM::HasV6Ops; 125194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach } 126acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool hasV7Ops() const { 127acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::HasV7Ops; 128acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 12932869205052430f45d598fba25ab878d8b29da2dEvan Cheng void SwitchMode() { 130ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 131ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(FB); 13232869205052430f45d598fba25ab878d8b29da2dEvan Cheng } 133acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool isMClass() const { 134acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::FeatureMClass; 135acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 136ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 137a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// @name Auto-generated Match Functions 138a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// { 1393483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 1400692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_ASSEMBLER_HEADER 1410692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#include "ARMGenAsmMatcher.inc" 142a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 143a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// } 144a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 14589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 14643904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocNumOperand( 147f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 14843904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocRegOperand( 149f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 1509b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OperandMatchResultTy parseCoprocOptionOperand( 1519b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 15243904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMemBarrierOptOperand( 1538bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 15443904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseProcIFlagsOperand( 1558bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 15643904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMSRMaskOperand( 1578bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 158f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 159f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef Op, int Low, int High); 160f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 161f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "lsl", 0, 31); 162f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 163f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 164f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "asr", 1, 32); 165f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 166c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 167580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 1687e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 169293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 1707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 171251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 1729d39036f62674606565217a10db28171b9594bc7Jim Grosbach OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 173862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 1747636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 175ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 176ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Asm Match Converter Methods 177a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 178a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 179a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 180a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 181eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 182eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 183ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 184ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1851355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 186ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 1879ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 1889ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &); 189548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 190548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1911355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 192ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 1937b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 1947b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 1967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 1987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2032fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2042fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 20514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 20614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 207623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 208623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 20988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 21088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21112431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 21212431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21312431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 21412431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2154334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 2164334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2174334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 2184334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 219189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 220189610f9466686a91fb7d847b572e1645c785323Jim Grosbach bool validateInstruction(MCInst &Inst, 221189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 22283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach bool processInstruction(MCInst &Inst, 223f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 224d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach bool shouldOmitCCOutOperand(StringRef Mnemonic, 225d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 226189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 227ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbypublic: 22847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach enum ARMMatchResultTy { 229194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 230f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Match_RequiresNotITBlock, 231194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresV6, 232194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresThumb2 23347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach }; 23447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 235ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 23694b9550a32d189704a8eae55505edf62662c0534Evan Cheng : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 237ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng MCAsmParserExtension::Initialize(_Parser); 23832869205052430f45d598fba25ab878d8b29da2dEvan Cheng 239ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // Initialize the set of available features. 240ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 241f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 242f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Not in an ITBlock to start with. 243f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = ~0U; 244ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 245ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 2461355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach // Implementation of the MCTargetAsmParser interface: 2471355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 2481355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseInstruction(StringRef Name, SMLoc NameLoc, 249189610f9466686a91fb7d847b572e1645c785323Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 2501355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseDirective(AsmToken DirectiveID); 2511355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach 25247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned checkTargetMatchPredicate(MCInst &Inst); 25347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 2541355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool MatchAndEmitInstruction(SMLoc IDLoc, 2551355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2561355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach MCStreamer &Out); 257ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby}; 25816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach} // end anonymous namespace 25916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2603a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 2613a69756e392942bc522193f38d7f33958ed3b131Chris Lattner 262a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ARMOperand - Instances of this class represent a parsed ARM machine 263a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// instruction. 264146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand : public MCParsedAsmOperand { 265762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan enum KindTy { 26621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CondCode, 26721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CCOut, 26821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ITCondMask, 26921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocNum, 27021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocReg, 2719b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach k_CoprocOption, 27221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Immediate, 27321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_FPImmediate, 27421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MemBarrierOpt, 27521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Memory, 27621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_PostIndexRegister, 27721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MSRMask, 27821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ProcIFlags, 279460a90540b045c102012da2492999557e6840526Jim Grosbach k_VectorIndex, 28021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Register, 28121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RegisterList, 28221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_DPRRegisterList, 28321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_SPRRegisterList, 284862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach k_VectorList, 28598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach k_VectorListAllLanes, 2867636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach k_VectorListIndexed, 28721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedRegister, 28821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedImmediate, 28921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShifterImmediate, 29021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RotateImmediate, 29121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_BitfieldDescriptor, 29221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Token 293a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Kind; 294a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 295762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc StartLoc, EndLoc; 29624d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling SmallVector<unsigned, 8> Registers; 297a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 298a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby union { 299a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 3008462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes Val; 3018462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } CC; 3028462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 3038462b30548fb5969250858036638c73c16b65b43Daniel Dunbar struct { 304fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned Val; 305fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } Cop; 306fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 307fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes struct { 3089b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach unsigned Val; 3099b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } CoprocOption; 3109b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 3119b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach struct { 31289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask:4; 31389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } ITMask; 31489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 31589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 31689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ARM_MB::MemBOpt Val; 31789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } MBOpt; 31889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 31989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 320a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags Val; 321a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } IFlags; 322a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 323a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes struct { 324584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Val; 325584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } MMask; 326584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 327584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes struct { 328a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby const char *Data; 329a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned Length; 330a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Tok; 331a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 332a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 333a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned RegNum; 334a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Reg; 335a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 336862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // A vector register list is a sequential list of 1 to 4 registers. 337862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach struct { 338862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned RegNum; 339862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count; 3407636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 3410aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced; 342862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } VectorList; 343862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3448155e5b753aca42973cf317727f3805faddcaf90Bill Wendling struct { 345460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned Val; 346460a90540b045c102012da2492999557e6840526Jim Grosbach } VectorIndex; 347460a90540b045c102012da2492999557e6840526Jim Grosbach 348460a90540b045c102012da2492999557e6840526Jim Grosbach struct { 349cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *Val; 350cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } Imm; 35116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 3529d39036f62674606565217a10db28171b9594bc7Jim Grosbach struct { 3539d39036f62674606565217a10db28171b9594bc7Jim Grosbach unsigned Val; // encoded 8-bit representation 3549d39036f62674606565217a10db28171b9594bc7Jim Grosbach } FPImm; 3559d39036f62674606565217a10db28171b9594bc7Jim Grosbach 3566a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar /// Combined record for all forms of ARM address expressions. 357a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 358a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned BaseRegNum; 3597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 3607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // was specified. 3617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm; // Offset immediate value 3627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 3637ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 36457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned ShiftImm; // shift for OffsetReg. 36557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment; // 0 = no alignment specified 366eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach // n = alignment in bytes (2, 4, 8, 16, or 32) 3677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 368e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach } Memory; 3690082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 3700082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson struct { 3717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned RegNum; 372f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isAdd; 373f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 374f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm; 3757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } PostIdxReg; 3767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach struct { 378580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 379e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned Imm; 380580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } ShifterImm; 381e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach struct { 382e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ARM_AM::ShiftOpc ShiftTy; 383e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg; 384e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg; 385e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm; 386af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedReg; 38792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson struct { 38892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson ARM_AM::ShiftOpc ShiftTy; 38992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg; 39092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm; 391af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedImm; 3927e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach struct { 3937e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach unsigned Imm; 3947e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } RotImm; 395293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach struct { 396293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned LSB; 397293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned Width; 398293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } Bitfield; 399a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby }; 40016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 401146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 402146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingpublic: 403762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 404762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Kind = o.Kind; 405762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan StartLoc = o.StartLoc; 406762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan EndLoc = o.EndLoc; 407762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan switch (Kind) { 40821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 4098462b30548fb5969250858036638c73c16b65b43Daniel Dunbar CC = o.CC; 4108462b30548fb5969250858036638c73c16b65b43Daniel Dunbar break; 41121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: 41289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = o.ITMask; 41389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 41421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 4158462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Tok = o.Tok; 416762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 41721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 41821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 419762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Reg = o.Reg; 420762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 42121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 42221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 42321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: 42424d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Registers = o.Registers; 4258d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 426862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 42798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 4287636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 429862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach VectorList = o.VectorList; 430862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 43121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 43221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 433fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Cop = o.Cop; 434fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 4359b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 4369b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach CoprocOption = o.CoprocOption; 4379b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 43821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 439762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Imm = o.Imm; 440762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 44121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_FPImmediate: 4429d39036f62674606565217a10db28171b9594bc7Jim Grosbach FPImm = o.FPImm; 4439d39036f62674606565217a10db28171b9594bc7Jim Grosbach break; 44421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 445706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes MBOpt = o.MBOpt; 446706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 44721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 448e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory = o.Memory; 449762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 45021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 4517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach PostIdxReg = o.PostIdxReg; 4527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 45321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 454584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes MMask = o.MMask; 455584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 45621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: 457a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes IFlags = o.IFlags; 4580082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 45921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 460580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm = o.ShifterImm; 4610082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 46221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 463af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedReg = o.RegShiftedReg; 464e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 46521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 466af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedImm = o.RegShiftedImm; 46792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 46821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 4697e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach RotImm = o.RotImm; 4707e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 47121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 472293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Bitfield = o.Bitfield; 473293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 474460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 475460a90540b045c102012da2492999557e6840526Jim Grosbach VectorIndex = o.VectorIndex; 476460a90540b045c102012da2492999557e6840526Jim Grosbach break; 477762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 478762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 47916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 480762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getStartLoc - Get the location of the first token of this operand. 481762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getStartLoc() const { return StartLoc; } 482762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getEndLoc - Get the location of the last token of this operand. 483762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getEndLoc() const { return EndLoc; } 484a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4858462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes getCondCode() const { 48621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_CondCode && "Invalid access!"); 4878462b30548fb5969250858036638c73c16b65b43Daniel Dunbar return CC.Val; 4888462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 4898462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 490fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned getCoproc() const { 49121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 492fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Cop.Val; 493fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 494fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 495a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby StringRef getToken() const { 49621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_Token && "Invalid access!"); 497a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return StringRef(Tok.Data, Tok.Length); 498a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 499a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 500a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned getReg() const { 50121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 5027729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling return Reg.RegNum; 503a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 504a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 5055fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &getRegList() const { 50621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 50721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind == k_SPRRegisterList) && "Invalid access!"); 50824d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling return Registers; 5098d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 5108d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 511cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *getImm() const { 51221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach assert(isImm() && "Invalid access!"); 513cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby return Imm.Val; 514cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 515cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 5169d39036f62674606565217a10db28171b9594bc7Jim Grosbach unsigned getFPImm() const { 51721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_FPImmediate && "Invalid access!"); 5189d39036f62674606565217a10db28171b9594bc7Jim Grosbach return FPImm.Val; 5199d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 5209d39036f62674606565217a10db28171b9594bc7Jim Grosbach 521460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned getVectorIndex() const { 522460a90540b045c102012da2492999557e6840526Jim Grosbach assert(Kind == k_VectorIndex && "Invalid access!"); 523460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val; 524460a90540b045c102012da2492999557e6840526Jim Grosbach } 525460a90540b045c102012da2492999557e6840526Jim Grosbach 526706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes ARM_MB::MemBOpt getMemBarrierOpt() const { 52721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MemBarrierOpt && "Invalid access!"); 528706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return MBOpt.Val; 529706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 530706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 531a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags getProcIFlags() const { 53221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_ProcIFlags && "Invalid access!"); 533a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return IFlags.Val; 534a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 535a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 536584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned getMSRMask() const { 53721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MSRMask && "Invalid access!"); 538584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MMask.Val; 539584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 540584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 54121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocNum() const { return Kind == k_CoprocNum; } 54221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocReg() const { return Kind == k_CoprocReg; } 5439b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach bool isCoprocOption() const { return Kind == k_CoprocOption; } 54421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCondCode() const { return Kind == k_CondCode; } 54521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCCOut() const { return Kind == k_CCOut; } 54621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITMask() const { return Kind == k_ITCondMask; } 54721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITCondCode() const { return Kind == k_CondCode; } 54821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isImm() const { return Kind == k_Immediate; } 54921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isFPImm() const { return Kind == k_FPImmediate; } 5504050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits16() const { 5514050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5524050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5534050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5544050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5554050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 0 && Value <= 16; 5564050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 5574050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits32() const { 5584050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5594050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5604050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5614050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5624050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 1 && Value <= 32; 5634050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 564a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isImm8s4() const { 56521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 566a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 567a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach if (!CE) return false; 568a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach int64_t Value = CE->getValue(); 569a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 570a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 57172f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_1020s4() const { 57221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 57372f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 57472f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 57572f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 57672f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 57772f39f8436848885176943b0ba985a7171145423Jim Grosbach } 57872f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_508s4() const { 57921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 58072f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 58172f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 58272f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 58372f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 58472f39f8436848885176943b0ba985a7171145423Jim Grosbach } 5856b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isImm0_255() const { 58621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 5876b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5886b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 5896b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 5906b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return Value >= 0 && Value < 256; 5916b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 592587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_1() const { 59321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 594587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 595587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 596587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 597587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 2; 598587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 599587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_3() const { 60021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 601587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 602587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 603587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 604587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 4; 605587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 60683ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_7() const { 60721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 60883ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 60983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 61083ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 61183ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 8; 61283ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 61383ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_15() const { 61421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 61583ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 61683ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 61783ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 61883ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 16; 61983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 6207c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach bool isImm0_31() const { 62121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6227c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6237c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach if (!CE) return false; 6247c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach int64_t Value = CE->getValue(); 6257c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach return Value >= 0 && Value < 32; 6267c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach } 627730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach bool isImm0_63() const { 62821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 629730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 630730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach if (!CE) return false; 631730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach int64_t Value = CE->getValue(); 632730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach return Value >= 0 && Value < 64; 633730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach } 6343b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm8() const { 63521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6363b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6373b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6383b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6393b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 8; 6403b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6413b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm16() const { 64221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6433b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6443b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6453b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6463b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 16; 6473b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6483b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm32() const { 64921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6503b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6513b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6523b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6533b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 32; 6543b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6556b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm8() const { 65621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6576b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6586b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6596b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6606b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 8; 6616b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6626b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm16() const { 66321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6646b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6656b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6666b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6676b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 16; 6686b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6696b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm32() const { 67021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6716b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6726b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6736b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6746b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 32; 6756b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6766b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm64() const { 67721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6786b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6796b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6806b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6816b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 64; 6826b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6833b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_7() const { 68421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6853b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6863b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6873b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6883b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 8; 6893b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6903b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_15() const { 69121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6923b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6933b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6943b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6953b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 16; 6963b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6973b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_31() const { 69821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6993b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7003b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 7013b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 7023b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 32; 7033b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 704f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach bool isImm1_16() const { 70521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 706f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 707f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach if (!CE) return false; 708f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach int64_t Value = CE->getValue(); 709f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach return Value > 0 && Value < 17; 710f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 7114a5ffb399f841783c201c599b88d576757f1922eJim Grosbach bool isImm1_32() const { 71221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7134a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7144a5ffb399f841783c201c599b88d576757f1922eJim Grosbach if (!CE) return false; 7154a5ffb399f841783c201c599b88d576757f1922eJim Grosbach int64_t Value = CE->getValue(); 7164a5ffb399f841783c201c599b88d576757f1922eJim Grosbach return Value > 0 && Value < 33; 7174a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 718ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach bool isImm0_32() const { 71921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 720ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 721ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (!CE) return false; 722ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach int64_t Value = CE->getValue(); 723ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach return Value >= 0 && Value < 33; 724ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 725fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach bool isImm0_65535() const { 72621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 727fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 728fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach if (!CE) return false; 729fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach int64_t Value = CE->getValue(); 730fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach return Value >= 0 && Value < 65536; 731fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach } 732ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach bool isImm0_65535Expr() const { 73321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 734ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 735ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // If it's not a constant expression, it'll generate a fixup and be 736ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // handled later. 737ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach if (!CE) return true; 738ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach int64_t Value = CE->getValue(); 739ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Value >= 0 && Value < 65536; 740ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 741ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach bool isImm24bit() const { 74221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 743ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 744ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach if (!CE) return false; 745ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach int64_t Value = CE->getValue(); 746ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach return Value >= 0 && Value <= 0xffffff; 747ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach } 74870939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach bool isImmThumbSR() const { 74921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 75070939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 75170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach if (!CE) return false; 75270939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach int64_t Value = CE->getValue(); 75370939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach return Value > 0 && Value < 33; 75470939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach } 755f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHLSLImm() const { 75621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 757f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 758f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 759f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 760f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value >= 0 && Value < 32; 761f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 762f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHASRImm() const { 76321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 764f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 765f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 766f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 767f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value > 0 && Value <= 32; 768f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 7696bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach bool isARMSOImm() const { 77021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7716bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7726bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach if (!CE) return false; 7736bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach int64_t Value = CE->getValue(); 7746bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach return ARM_AM::getSOImmVal(Value) != -1; 7756bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach } 776e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach bool isARMSOImmNot() const { 77721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 778e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 779e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach if (!CE) return false; 780e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach int64_t Value = CE->getValue(); 781e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach return ARM_AM::getSOImmVal(~Value) != -1; 782e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 7833bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isARMSOImmNeg() const { 78421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7853bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7863bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 7873bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 7883bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach return ARM_AM::getSOImmVal(-Value) != -1; 7893bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 7906b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isT2SOImm() const { 79121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7926b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7936b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 7946b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 7956b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return ARM_AM::getT2SOImmVal(Value) != -1; 7966b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 79789a633708542de5847e807f98f86edfefc9fc019Jim Grosbach bool isT2SOImmNot() const { 79821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 79989a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 80089a633708542de5847e807f98f86edfefc9fc019Jim Grosbach if (!CE) return false; 80189a633708542de5847e807f98f86edfefc9fc019Jim Grosbach int64_t Value = CE->getValue(); 80289a633708542de5847e807f98f86edfefc9fc019Jim Grosbach return ARM_AM::getT2SOImmVal(~Value) != -1; 80389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 8043bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isT2SOImmNeg() const { 80521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 8063bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8073bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 8083bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 8093bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach return ARM_AM::getT2SOImmVal(-Value) != -1; 8103bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 811c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach bool isSetEndImm() const { 81221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 813c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 814c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CE) return false; 815c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int64_t Value = CE->getValue(); 816c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Value == 1 || Value == 0; 817c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 81821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isReg() const { return Kind == k_Register; } 81921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegList() const { return Kind == k_RegisterList; } 82021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 82121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 82221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isToken() const { return Kind == k_Token; } 82321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 82421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemory() const { return Kind == k_Memory; } 82521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isShifterImm() const { return Kind == k_ShifterImmediate; } 82621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 82721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 82821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRotImm() const { return Kind == k_RotateImmediate; } 82921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 83021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 831f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isPostIdxReg() const { 832430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 833f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 83457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isMemNoOffset(bool alignOK = false) const { 835f6c35c59f515505fa2e9b74b3d0f4ab06f8266d8Jim Grosbach if (!isMemory()) 836ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return false; 8377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // No offset of any kind. 83857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 83957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach (alignOK || Memory.Alignment == 0); 84057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 84157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isAlignedMemory() const { 84257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return isMemNoOffset(true); 843ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 8447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode2() const { 84557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 847e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 8487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 849e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 850e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Val > -4096 && Val < 4096; 8527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 853039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach bool isAM2OffsetImm() const { 85421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 855039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Immediate offset in range [-4095, 4095]. 856039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 857039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (!CE) return false; 858039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int64_t Val = CE->getValue(); 859039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach return Val > -4096 && Val < 4096; 860039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 8612fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAddrMode3() const { 8622f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 8632f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 8642f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 86521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 8662f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 86757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8682fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // No shifts are legal for AM3. 869e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::no_shift) return false; 8702fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Check for register offset. 871e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 8722fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 873e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 874e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8752fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return Val > -256 && Val < 256; 8762fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 8772fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAM3Offset() const { 87821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind != k_Immediate && Kind != k_PostIndexRegister) 8792fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return false; 88021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) 8812fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return PostIdxReg.ShiftTy == ARM_AM::no_shift; 8822fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 8832fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8842fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (!CE) return false; 8852fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int64_t Val = CE->getValue(); 886251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Special case, #-0 is INT32_MIN. 887251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return (Val > -256 && Val < 256) || Val == INT32_MIN; 8882fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 8897ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode5() const { 890681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 891681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 892681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 89321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 894681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return true; 89557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 897e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return false; 8987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-1020, 1020] and a multiple of 4. 899e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 900e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 9010da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 902681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Val == INT32_MIN; 9037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 9047f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBB() const { 905e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 90657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 9077f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9087f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9097f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9107f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBH() const { 911e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 91257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 91357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0 ) 9147f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9157f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9167f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemRegOffset() const { 91857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 919ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return false; 920ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 921ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 922ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach bool isT2MemRegOffset() const { 92357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 92457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0) 925ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 926ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach // Only lsl #{0, 1, 2, 3} allowed. 927e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType == ARM_AM::no_shift) 928ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 929e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 930ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 931ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 932ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 9337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemThumbRR() const { 9347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Thumb reg+reg addressing is simple. Just two registers, a base and 9357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // an offset. No shifts, negations or any other complicating factors. 936e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 93757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 93887f4f9a946549ad93046990a364ac5190333a7ebBill Wendling return false; 939e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach return isARMLowRegister(Memory.BaseRegNum) && 940e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 94160f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 94260f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach bool isMemThumbRIs4() const { 943e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 94457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 94560f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach return false; 94660f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach // Immediate offset, multiple of 4 in range [0, 124]. 947e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 948e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 949ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 124 && (Val % 4) == 0; 950ecd858968384be029574d845eb098d357049e02eJim Grosbach } 95138466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach bool isMemThumbRIs2() const { 952e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 95357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 95438466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return false; 95538466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach // Immediate offset, multiple of 4 in range [0, 62]. 956e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 957e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 95838466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return Val >= 0 && Val <= 62 && (Val % 2) == 0; 95938466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 96048ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach bool isMemThumbRIs1() const { 961e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 96257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 96348ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return false; 96448ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach // Immediate offset in range [0, 31]. 965e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 966e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 96748ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return Val >= 0 && Val <= 31; 96848ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 969ecd858968384be029574d845eb098d357049e02eJim Grosbach bool isMemThumbSPI() const { 97057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 97157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 972ecd858968384be029574d845eb098d357049e02eJim Grosbach return false; 973ecd858968384be029574d845eb098d357049e02eJim Grosbach // Immediate offset, multiple of 4 in range [0, 1020]. 974e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 975e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 976ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 977505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 978a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isMemImm8s4Offset() const { 9792f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 9802f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 9812f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 98221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 9832f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 98457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 985a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return false; 986a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Immediate offset a multiple of 4 in range [-1020, 1020]. 987e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 988e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 989a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 990a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 991b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach bool isMemImm0_1020s4Offset() const { 99257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 993b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return false; 994b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // Immediate offset a multiple of 4 in range [0, 1020]. 995e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 996e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 997b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 998b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 9997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm8Offset() const { 100057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1001f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling return false; 10027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-255, 255]. 1003e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1004e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10054d2a00147d19b17d382644de0d6a1f0d3230e0e4Owen Anderson return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1006f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1007f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach bool isMemPosImm8Offset() const { 100857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1009f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return false; 1010f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach // Immediate offset in range [0, 255]. 1011e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1012e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1013f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return Val >= 0 && Val < 256; 1014f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1015a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemNegImm8Offset() const { 101657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1017a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 1018a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [-255, -1]. 1019df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach if (!Memory.OffsetImm) return false; 1020e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1021df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1022a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1023a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemUImm12Offset() const { 102457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1025a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 1026a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [0, 4095]. 1027e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1028e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1029a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return (Val >= 0 && Val < 4096); 1030a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 10317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm12Offset() const { 103209176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 103309176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 103409176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // and we reject it. 103521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 103609176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return true; 103709176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 103857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1039ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling return false; 10407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 1041e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1042e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10430da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 10447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 10457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isPostIdxImm8() const { 104621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 10477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1048ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling if (!CE) return false; 10497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Val = CE->getValue(); 105063553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1051ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 10522bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isPostIdxImm8s4() const { 105321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 10542bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 10552bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (!CE) return false; 10562bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int64_t Val = CE->getValue(); 10572bd0118472de352745a2e038245fab4974f7c87eJim Grosbach return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 10582bd0118472de352745a2e038245fab4974f7c87eJim Grosbach (Val == INT32_MIN); 10592bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 10607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 106121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMSRMask() const { return Kind == k_MSRMask; } 106221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isProcIFlags() const { return Kind == k_ProcIFlags; } 10633483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 10640e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // NEON operands. 10650aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isSingleSpacedVectorList() const { 10660aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && !VectorList.isDoubleSpaced; 10670aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 10680aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpacedVectorList() const { 10690aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && VectorList.isDoubleSpaced; 10700aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 1071862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach bool isVecListOneD() const { 10720aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1073862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return VectorList.Count == 1; 1074862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1075862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 1076280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach bool isVecListTwoD() const { 10770aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1078280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach return VectorList.Count == 2; 1079280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach } 1080280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach 1081cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach bool isVecListThreeD() const { 10820aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1083cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach return VectorList.Count == 3; 1084cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach } 1085cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach 1086b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach bool isVecListFourD() const { 10870aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1088b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach return VectorList.Count == 4; 1089b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach } 1090b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach 10914661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach bool isVecListTwoQ() const { 10920aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isDoubleSpacedVectorList()) return false; 10930aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return VectorList.Count == 2; 10944661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach } 10954661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach 10963471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isSingleSpacedVectorAllLanes() const { 10973471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 10983471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 10993471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpacedVectorAllLanes() const { 11003471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 11013471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 110298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach bool isVecListOneDAllLanes() const { 11033471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 110498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return VectorList.Count == 1; 110598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 110698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 110713af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach bool isVecListTwoDAllLanes() const { 11083471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 11093471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return VectorList.Count == 2; 11103471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 11113471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach 11123471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isVecListTwoQAllLanes() const { 11133471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isDoubleSpacedVectorAllLanes()) return false; 111413af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach return VectorList.Count == 2; 111513af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach } 111613af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach 111795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isSingleSpacedVectorIndexed() const { 111895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 111995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 112095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpacedVectorIndexed() const { 112195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 112295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 11237636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach bool isVecListOneDByteIndexed() const { 112495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11257636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 11267636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 11277636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1128799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDHWordIndexed() const { 112995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1130799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1131799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1132799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1133799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDWordIndexed() const { 113495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1135799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1136799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1137799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 11389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach bool isVecListTwoDByteIndexed() const { 113995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11409b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 11419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 11429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 1143799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDHWordIndexed() const { 114495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 114595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 114695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 114795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 114895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQWordIndexed() const { 114995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 115095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 115195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 115295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 115395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQHWordIndexed() const { 115495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 1155799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1156799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1157799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1158799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDWordIndexed() const { 115995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1160799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1161799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1162799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1163460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex8() const { 1164460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1165460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 8; 1166460a90540b045c102012da2492999557e6840526Jim Grosbach } 1167460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex16() const { 1168460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1169460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 4; 1170460a90540b045c102012da2492999557e6840526Jim Grosbach } 1171460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex32() const { 1172460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1173460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 2; 1174460a90540b045c102012da2492999557e6840526Jim Grosbach } 1175460a90540b045c102012da2492999557e6840526Jim Grosbach 11760e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach bool isNEONi8splat() const { 117721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 11780e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 11790e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Must be a constant. 11800e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!CE) return false; 11810e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach int64_t Value = CE->getValue(); 11820e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // i8 value splatted across 8 bytes. The immediate is just the 8 byte 11830e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // value. 11840e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return Value >= 0 && Value < 256; 11850e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 1186460a90540b045c102012da2492999557e6840526Jim Grosbach 1187ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach bool isNEONi16splat() const { 118821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1189ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1190ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // Must be a constant. 1191ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (!CE) return false; 1192ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach int64_t Value = CE->getValue(); 1193ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // i16 value in the range [0,255] or [0x0100, 0xff00] 1194ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1195ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1196ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 11976248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32splat() const { 119821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 11996248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12006248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 12016248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 12026248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 12036248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 12046248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 12056248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12066248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12076248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000); 12086248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 12096248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 12106248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32vmov() const { 121121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12126248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12136248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 12146248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 12156248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 12166248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 12176248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 12186248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 12196248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12206248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12216248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 12226248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 12236248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 12246248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 12259b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach bool isNEONi32vmovNeg() const { 122621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12279b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12289b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // Must be a constant. 12299b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (!CE) return false; 12309b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach int64_t Value = ~CE->getValue(); 12319b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 12329b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 12339b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach return (Value >= 0 && Value < 256) || 12349b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12359b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12369b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 12379b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 12389b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 12399b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 12406248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 1241f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach bool isNEONi64splat() const { 124221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1243f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1244f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // Must be a constant. 1245f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if (!CE) return false; 1246f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 1247f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // i64 value with each byte being either 0 or 0xff. 1248f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i) 1249f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1250f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach return true; 1251f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1252f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 12533483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addExpr(MCInst &Inst, const MCExpr *Expr) const { 125414b93851cc7611ae6c2000f1c162592ead954420Chris Lattner // Add as immediates when possible. Null MCExpr = 0. 125514b93851cc7611ae6c2000f1c162592ead954420Chris Lattner if (Expr == 0) 125614b93851cc7611ae6c2000f1c162592ead954420Chris Lattner Inst.addOperand(MCOperand::CreateImm(0)); 125714b93851cc7611ae6c2000f1c162592ead954420Chris Lattner else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 12583483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 12593483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar else 12603483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateExpr(Expr)); 12613483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar } 12623483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 12638462b30548fb5969250858036638c73c16b65b43Daniel Dunbar void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1264345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar assert(N == 2 && "Invalid number of operands!"); 12658462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 126604f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 126704f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegNum)); 12688462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 12698462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 1270fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1271fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1272fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1273fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1274fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 12759b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 12769b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 12779b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(getCoproc())); 12789b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 12799b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 12809b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 12819b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 12829b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 12839b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 12849b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 128589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITMaskOperands(MCInst &Inst, unsigned N) const { 128689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 128789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 128889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 128989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 129089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 129189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 129289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 129389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 129489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 1295d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach void addCCOutOperands(MCInst &Inst, unsigned N) const { 1296d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1297d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Inst.addOperand(MCOperand::CreateReg(getReg())); 1298d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 1299d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 1300a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby void addRegOperands(MCInst &Inst, unsigned N) const { 1301a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby assert(N == 1 && "Invalid number of operands!"); 1302a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby Inst.addOperand(MCOperand::CreateReg(getReg())); 1303a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1304a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 1305af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1306e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1307430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedReg() && 1308430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedRegOperands() on non RegShiftedReg!"); 1309af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1310af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1311e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Inst.addOperand(MCOperand::CreateImm( 1312af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1313e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 1314e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 1315af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1316152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(N == 2 && "Invalid number of operands!"); 1317430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedImm() && 1318430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedImmOperands() on non RegShiftedImm!"); 1319af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 132092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Inst.addOperand(MCOperand::CreateImm( 1321af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 132292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 132392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 1324580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach void addShifterImmOperands(MCInst &Inst, unsigned N) const { 13250082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(N == 1 && "Invalid number of operands!"); 1326580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1327580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm.Imm)); 13280082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 13290082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 133087f4f9a946549ad93046990a364ac5190333a7ebBill Wendling void addRegListOperands(MCInst &Inst, unsigned N) const { 13317729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling assert(N == 1 && "Invalid number of operands!"); 13325fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 13335fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 13347729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ++I) 13357729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling Inst.addOperand(MCOperand::CreateReg(*I)); 133687f4f9a946549ad93046990a364ac5190333a7ebBill Wendling } 133787f4f9a946549ad93046990a364ac5190333a7ebBill Wendling 13380f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 13390f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 13400f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 13410f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 13420f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 13430f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 13440f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 13450f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 13467e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach void addRotImmOperands(MCInst &Inst, unsigned N) const { 13477e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13487e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Encoded as val>>3. The printer handles display as 8, 16, 24. 13497e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 13507e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 13517e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 1352293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1353293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1354293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Munge the lsb/width into a bitfield mask. 1355293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned lsb = Bitfield.LSB; 1356293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned width = Bitfield.Width; 1357293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1358293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1359293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach (32 - (lsb + width))); 1360293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Mask)); 1361293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 1362293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 13633483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addImmOperands(MCInst &Inst, unsigned N) const { 13646b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13656b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach addExpr(Inst, getImm()); 13666b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 13676b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach 13684050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits16Operands(MCInst &Inst, unsigned N) const { 13694050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13704050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13714050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 13724050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 13734050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 13744050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits32Operands(MCInst &Inst, unsigned N) const { 13754050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13764050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13774050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 13784050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 13794050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 13809d39036f62674606565217a10db28171b9594bc7Jim Grosbach void addFPImmOperands(MCInst &Inst, unsigned N) const { 13819d39036f62674606565217a10db28171b9594bc7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13829d39036f62674606565217a10db28171b9594bc7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getFPImm())); 13839d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 13849d39036f62674606565217a10db28171b9594bc7Jim Grosbach 1385a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1386a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1387a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // FIXME: We really want to scale the value here, but the LDRD/STRD 1388a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // instruction don't encode operands that way yet. 1389a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1390a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1391a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1392a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 139372f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 139472f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 139572f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 139672f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 139772f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 139872f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 139972f39f8436848885176943b0ba985a7171145423Jim Grosbach } 140072f39f8436848885176943b0ba985a7171145423Jim Grosbach 140172f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 140272f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 140372f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 140472f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 140572f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 140672f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 140772f39f8436848885176943b0ba985a7171145423Jim Grosbach } 140872f39f8436848885176943b0ba985a7171145423Jim Grosbach 1409f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1410f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1411f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 1412f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // the bits as encoded, so subtract off one here. 1413f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1414f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1415f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 1416f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach 14174a5ffb399f841783c201c599b88d576757f1922eJim Grosbach void addImm1_32Operands(MCInst &Inst, unsigned N) const { 14184a5ffb399f841783c201c599b88d576757f1922eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14194a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 14204a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // the bits as encoded, so subtract off one here. 14214a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14224a5ffb399f841783c201c599b88d576757f1922eJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 14234a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 14244a5ffb399f841783c201c599b88d576757f1922eJim Grosbach 142570939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 142670939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 142770939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // The constant encodes as the immediate, except for 32, which encodes as 142870939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // zero. 142970939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 143070939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach unsigned Imm = CE->getValue(); 143170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1432ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 1433ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 1434f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1435f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1436f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // An ASR value of 32 encodes as 0, so that's how we want to add it to 1437f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // the instruction as well. 1438f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1439f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 1440f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1441f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 1442f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 144389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 144489a633708542de5847e807f98f86edfefc9fc019Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 144589a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // The operand is actually a t2_so_imm, but we have its bitwise 144689a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // negation in the assembly source, so twiddle it here. 144789a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 144889a633708542de5847e807f98f86edfefc9fc019Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 144989a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 145089a633708542de5847e807f98f86edfefc9fc019Jim Grosbach 14513bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 14523bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14533bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a t2_so_imm, but we have its 14543bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 14553bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14563bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 14573bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 14583bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 1459e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1460e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1461e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // The operand is actually a so_imm, but we have its bitwise 1462e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // negation in the assembly source, so twiddle it here. 1463e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1464e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1465e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 1466e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach 14673bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 14683bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14693bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a so_imm, but we have its 14703bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 14713bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14723bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 14733bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 14743bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 1475706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1476706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1477706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1478706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 1479706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 14807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 14817ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1482e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1483505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 1484505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes 148557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 148657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 148757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 148857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 148957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 149057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 14917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 14927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1493e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1494e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 14957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 14967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 14977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 14987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 14997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 15007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else { 15017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // For register offset, we encode the shift type and negation flag 15027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // here. 1503e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1504e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory.ShiftImm, Memory.ShiftType); 1505ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1506e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1507e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 15087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1509ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1510ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 1511039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1512039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1513039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1514039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(CE && "non-constant AM2OffsetImm operand!"); 1515039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int32_t Val = CE->getValue(); 1516039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1517039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Special case for #-0 1518039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val == INT32_MIN) Val = 0; 1519039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val < 0) Val = -Val; 1520039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1521039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 1522039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1523039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 1524039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach 15252fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 15262fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 15272f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 15282f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 15292f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 15302f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 15312f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 15322f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 15332f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 15342f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 15352f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 15362f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1537e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1538e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 15392fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15402fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 15412fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 15422fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 15432fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 15442fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } else { 15452fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // For register offset, we encode the shift type and negation flag 15462fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // here. 1547e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 15482fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 1549e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1550e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 15512fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 15522fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 15532fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 15542fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 15552fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 155621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) { 15572fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = 15582fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 15592fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 15602fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1561251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return; 15622fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 15632fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 15642fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Constant offset. 15652fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 15662fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = CE->getValue(); 15672fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15682fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 15692fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 15702fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 1571251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 15722fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 15732fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 15742fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 15752fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 15767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 15777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1578681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 1579681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 1580681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 1581681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach if (isImm()) { 1582681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 1583681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1584681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return; 1585681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach } 1586681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach 15877ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1588e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 15897ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15907ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 15917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 15927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 15937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM5Opc(AddSub, Val); 1594e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 15957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 15967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 15977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 1598a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1599a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 16002f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 16012f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 16022f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 16032f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 16042f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 16052f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 16062f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 16072f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 16082f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1609e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1610e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1611a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1612a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1613a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 1614b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1615b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1616b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1617e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1618e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1619b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1620b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 1621b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 16227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 16237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1624e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1625e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 16267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1627ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 1628ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 1629f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1630f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1631f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1632f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach 1633a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1634f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1635a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1636a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1637a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1638a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1639a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // If this is an immediate, it's a label reference. 164021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 1641a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach addExpr(Inst, getImm()); 1642a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1643a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return; 1644a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1645a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1646a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1647e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1648e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1649a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1650a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1651a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 16527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 16537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 165409176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If this is an immediate, it's a label reference. 165521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 165609176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach addExpr(Inst, getImm()); 165709176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 165809176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return; 165909176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach } 166009176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 166109176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1662e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1663e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 16647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 16657ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 166692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 16677f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBBOperands(MCInst &Inst, unsigned N) const { 16687f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1669e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1670e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 16717f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 16727f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 16737f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBHOperands(MCInst &Inst, unsigned N) const { 16747f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1675e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1676e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 16777f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 16787f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 16797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 16807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1681430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach unsigned Val = 1682430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1683430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach Memory.ShiftImm, Memory.ShiftType); 1684e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1685e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 16867ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 16877ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 1688d3df5f32c059b3ac111f1c08571d5493aa1d48c6Daniel Dunbar 1689ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1690ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1691e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1692e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1693e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1694ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 1695ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach 16967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 16977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1698e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1699e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 170014b93851cc7611ae6c2000f1c162592ead954420Chris Lattner } 17013483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 170260f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 170360f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1704e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1705e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 170660f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 170748ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 170848ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach 170938466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 171038466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1711e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1712e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 171338466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 171438466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 171538466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach 171648ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 171748ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1718e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1719e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 172048ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 172160f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 172260f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach 1723ecd858968384be029574d845eb098d357049e02eJim Grosbach void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1724ecd858968384be029574d845eb098d357049e02eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1725e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1726e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1727ecd858968384be029574d845eb098d357049e02eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1728ecd858968384be029574d845eb098d357049e02eJim Grosbach } 1729ecd858968384be029574d845eb098d357049e02eJim Grosbach 17307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 17317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 17327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 17337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(CE && "non-constant post-idx-imm8 operand!"); 17347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Imm = CE->getValue(); 17357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAdd = Imm >= 0; 173663553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson if (Imm == INT32_MIN) Imm = 0; 17377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 17387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1739f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1740ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 17412bd0118472de352745a2e038245fab4974f7c87eJim Grosbach void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 17422bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 17432bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 17442bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(CE && "non-constant post-idx-imm8s4 operand!"); 17452bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int Imm = CE->getValue(); 17462bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isAdd = Imm >= 0; 17472bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (Imm == INT32_MIN) Imm = 0; 17482bd0118472de352745a2e038245fab4974f7c87eJim Grosbach // Immediate is scaled by 4. 17492bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 17502bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 17512bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 17522bd0118472de352745a2e038245fab4974f7c87eJim Grosbach 17537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 17547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 17557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1756f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1757f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 1758f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 1759f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1760f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1761f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1762f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // The sign, shift type, and shift amount are encoded in a single operand 1763f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // using the AM2 encoding helpers. 1764f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1765f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1766f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach PostIdxReg.ShiftTy); 1767f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1768ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 1769ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 1770584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1771584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1772584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1773584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 1774584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 1775a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1776a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1777a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1778a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 1779a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 17806029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach void addVecListOperands(MCInst &Inst, unsigned N) const { 1781862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1782862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1783862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1784862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 17857636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 17867636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 17877636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 17887636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 17897636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 17907636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1791460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1792460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1793460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1794460a90540b045c102012da2492999557e6840526Jim Grosbach } 1795460a90540b045c102012da2492999557e6840526Jim Grosbach 1796460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1797460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1798460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1799460a90540b045c102012da2492999557e6840526Jim Grosbach } 1800460a90540b045c102012da2492999557e6840526Jim Grosbach 1801460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1802460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1803460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1804460a90540b045c102012da2492999557e6840526Jim Grosbach } 1805460a90540b045c102012da2492999557e6840526Jim Grosbach 18060e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 18070e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18080e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // The immediate encodes the type of constant as well as the value. 18090e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Mask in that this is an i8 splat. 18100e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18110e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 18120e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 18130e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 1814ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1815ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1816ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // The immediate encodes the type of constant as well as the value. 1817ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1818ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach unsigned Value = CE->getValue(); 1819ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (Value >= 256) 1820ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value = (Value >> 8) | 0xa00; 1821ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach else 1822ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value |= 0x800; 1823ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 1824ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1825ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 18266248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 18276248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18286248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 18296248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18306248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 18316248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xff00) 18326248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | 0x200; 18336248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xff0000) 18346248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | 0x400; 18356248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 18366248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 18376248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 18386248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 18396248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 18406248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 18416248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18426248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 18436248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18446248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 18456248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xffff) 18466248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 18476248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 18486248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 18496248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 18506248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 18519b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 18529b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 18539b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach 18549b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 18559b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18569b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // The immediate encodes the type of constant as well as the value. 18579b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18589b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach unsigned Value = ~CE->getValue(); 18599b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (Value >= 256 && Value <= 0xffff) 18609b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 18619b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 18629b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 18639b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffffff) 18649b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 24) | 0x600; 18656248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 18666248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 18676248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 1868f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 1869f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1870f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // The immediate encodes the type of constant as well as the value. 1871f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1872f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 1873f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach unsigned Imm = 0; 1874f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 1875f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Imm |= (Value & 1) << i; 1876f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1877f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 1878f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1879f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 1880b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbach virtual void print(raw_ostream &OS) const; 1881b3cb6967949493a2e1b10d015ac08b746736764eDaniel Dunbar 188289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 188321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ITCondMask); 188489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->ITMask.Mask = Mask; 188589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->StartLoc = S; 188689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->EndLoc = S; 188789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return Op; 188889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 188989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 18903a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 189121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CondCode); 1892345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->CC.Val = CC; 1893345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->StartLoc = S; 1894345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->EndLoc = S; 18953a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1896345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar } 1897345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 1898fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 189921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocNum); 1900fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 1901fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 1902fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 1903fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 1904fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1905fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 1906fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 190721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocReg); 1908fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 1909fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 1910fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 1911fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 1912fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1913fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 19149b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 19159b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocOption); 19169b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->Cop.Val = Val; 19179b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->StartLoc = S; 19189b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->EndLoc = E; 19199b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return Op; 19209b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 19219b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 1922d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 192321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CCOut); 1924d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->Reg.RegNum = RegNum; 1925d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->StartLoc = S; 1926d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->EndLoc = S; 1927d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach return Op; 1928d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 1929d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 19303a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 193121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Token); 1932762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Data = Str.data(); 1933762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Length = Str.size(); 1934762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 1935762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = S; 19363a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1937a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1938a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 193950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 194021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Register); 1941762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Reg.RegNum = RegNum; 1942762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 1943762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 19443a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1945a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1946a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 1947e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1948e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg, 1949e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg, 1950e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm, 1951e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc S, SMLoc E) { 195221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 1953af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftTy = ShTy; 1954af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.SrcReg = SrcReg; 1955af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftReg = ShiftReg; 1956af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftImm = ShiftImm; 1957e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->StartLoc = S; 1958e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->EndLoc = E; 1959e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Op; 1960e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 1961e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 196292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 196392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg, 196492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm, 196592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson SMLoc S, SMLoc E) { 196621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 1967af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftTy = ShTy; 1968af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.SrcReg = SrcReg; 1969af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftImm = ShiftImm; 197092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->StartLoc = S; 197192a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->EndLoc = E; 197292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson return Op; 197392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 197492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 1975580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 19760082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S, SMLoc E) { 197721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 1978580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.isASR = isASR; 1979580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.Imm = Imm; 19800082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->StartLoc = S; 19810082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->EndLoc = E; 19820082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return Op; 19830082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 19840082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 19857e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 198621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_RotateImmediate); 19877e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->RotImm.Imm = Imm; 19887e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->StartLoc = S; 19897e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->EndLoc = E; 19907e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return Op; 19917e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 19927e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 1993293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 1994293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S, SMLoc E) { 199521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 1996293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.LSB = LSB; 1997293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.Width = Width; 1998293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->StartLoc = S; 1999293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->EndLoc = E; 2000293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return Op; 2001293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 2002293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 20037729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling static ARMOperand * 20045fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2005cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay SMLoc StartLoc, SMLoc EndLoc) { 200621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach KindTy Kind = k_RegisterList; 20070f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 2008d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 200921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_DPRRegisterList; 2010d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2011275944afb55086d0b4b20d4d831de7c1c7507925Evan Cheng contains(Regs.front().first)) 201221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_SPRRegisterList; 20130f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 20140f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling ARMOperand *Op = new ARMOperand(Kind); 20155fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 20167729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = Regs.begin(), E = Regs.end(); I != E; ++I) 201724d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Op->Registers.push_back(I->first); 2018cb21d1c9fd1cf53f063183f7eb28af7fa4052ef0Bill Wendling array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2019cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->StartLoc = StartLoc; 2020cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->EndLoc = EndLoc; 20218d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling return Op; 20228d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 20238d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 2024862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 20250aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced, SMLoc S, SMLoc E) { 2026862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorList); 2027862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.RegNum = RegNum; 2028862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.Count = Count; 20290aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2030862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->StartLoc = S; 2031862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->EndLoc = E; 2032862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return Op; 2033862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 2034862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 203598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 20363471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpaced, 203798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc S, SMLoc E) { 203898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 203998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.RegNum = RegNum; 204098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.Count = Count; 20413471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 204298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->StartLoc = S; 204398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->EndLoc = E; 204498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Op; 204598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 204698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 20477636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 204895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Index, 204995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpaced, 205095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach SMLoc S, SMLoc E) { 20517636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 20527636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.RegNum = RegNum; 20537636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.Count = Count; 20547636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.LaneIndex = Index; 205595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 20567636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->StartLoc = S; 20577636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->EndLoc = E; 20587636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return Op; 20597636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 20607636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 2061460a90540b045c102012da2492999557e6840526Jim Grosbach static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2062460a90540b045c102012da2492999557e6840526Jim Grosbach MCContext &Ctx) { 2063460a90540b045c102012da2492999557e6840526Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorIndex); 2064460a90540b045c102012da2492999557e6840526Jim Grosbach Op->VectorIndex.Val = Idx; 2065460a90540b045c102012da2492999557e6840526Jim Grosbach Op->StartLoc = S; 2066460a90540b045c102012da2492999557e6840526Jim Grosbach Op->EndLoc = E; 2067460a90540b045c102012da2492999557e6840526Jim Grosbach return Op; 2068460a90540b045c102012da2492999557e6840526Jim Grosbach } 2069460a90540b045c102012da2492999557e6840526Jim Grosbach 20703a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 207121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Immediate); 2072762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Imm.Val = Val; 2073762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2074762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 20753a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2076cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 2077cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 20789d39036f62674606565217a10db28171b9594bc7Jim Grosbach static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) { 207921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_FPImmediate); 20809d39036f62674606565217a10db28171b9594bc7Jim Grosbach Op->FPImm.Val = Val; 20819d39036f62674606565217a10db28171b9594bc7Jim Grosbach Op->StartLoc = S; 20829d39036f62674606565217a10db28171b9594bc7Jim Grosbach Op->EndLoc = S; 20839d39036f62674606565217a10db28171b9594bc7Jim Grosbach return Op; 20849d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 20859d39036f62674606565217a10db28171b9594bc7Jim Grosbach 20867ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach static ARMOperand *CreateMem(unsigned BaseRegNum, 20877ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm, 20887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum, 20897ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType, 20900d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm, 209157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment, 20927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative, 20933a69756e392942bc522193f38d7f33958ed3b131Chris Lattner SMLoc S, SMLoc E) { 209421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Memory); 2095e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.BaseRegNum = BaseRegNum; 2096e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetImm = OffsetImm; 2097e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetRegNum = OffsetRegNum; 2098e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftType = ShiftType; 2099e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftImm = ShiftImm; 210057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Op->Memory.Alignment = Alignment; 2101e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.isNegative = isNegative; 21027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->StartLoc = S; 21037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->EndLoc = E; 21047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Op; 21057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 210616c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2107f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2108f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy, 2109f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm, 21107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S, SMLoc E) { 211121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 21127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->PostIdxReg.RegNum = RegNum; 2113f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.isAdd = isAdd; 2114f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftTy = ShiftTy; 2115f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftImm = ShiftImm; 2116762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2117762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 21183a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2119a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 2120706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 2121706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 212221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2123706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->MBOpt.Val = Opt; 2124706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->StartLoc = S; 2125706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->EndLoc = S; 2126706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return Op; 2127706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 2128a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 2129a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 213021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2131a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->IFlags.Val = IFlags; 2132a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->StartLoc = S; 2133a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->EndLoc = S; 2134a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return Op; 2135a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 2136584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 2137584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 213821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MSRMask); 2139584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->MMask.Val = MMask; 2140584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->StartLoc = S; 2141584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->EndLoc = S; 2142584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return Op; 2143584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 2144a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby}; 2145a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2146a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} // end anonymous namespace. 2147a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2148b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbachvoid ARMOperand::print(raw_ostream &OS) const { 2149fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar switch (Kind) { 215021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_FPImmediate: 21519d39036f62674606565217a10db28171b9594bc7Jim Grosbach OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm()) 21529d39036f62674606565217a10db28171b9594bc7Jim Grosbach << ") >"; 21539d39036f62674606565217a10db28171b9594bc7Jim Grosbach break; 215421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 21556a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2156fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 215721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 2158d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach OS << "<ccout " << getReg() << ">"; 2159d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach break; 216021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: { 21611a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer static const char *MaskStr[] = { 21621a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 21631a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 21641a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer }; 216589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert((ITMask.Mask & 0xf) == ITMask.Mask); 216689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 216789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 216889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 216921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 2170fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor number: " << getCoproc() << ">"; 2171fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 217221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 2173fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor register: " << getCoproc() << ">"; 2174fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 21759b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 21769b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OS << "<coprocessor option: " << CoprocOption.Val << ">"; 21779b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 217821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 2179584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes OS << "<mask: " << getMSRMask() << ">"; 2180584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 218121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 2182fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar getImm()->print(OS); 2183fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 218421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 2185706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2186706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 218721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 21886ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << "<memory " 2189e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach << " base:" << Memory.BaseRegNum; 21906ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << ">"; 2191fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 219221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 2193f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2194f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.RegNum; 2195f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2196f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2197f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.ShiftImm; 2198f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ">"; 21997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 220021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: { 2201a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << "<ARM_PROC::"; 2202a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = getProcIFlags(); 2203a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes for (int i=2; i >= 0; --i) 2204a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IFlags & (1 << i)) 2205a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ARM_PROC::IFlagsToString(1 << i); 2206a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ">"; 2207a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes break; 2208a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 220921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 221050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling OS << "<register " << getReg() << ">"; 2211fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 221221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 2213580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2214580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach << " #" << ShifterImm.Imm << ">"; 2215e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 221621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 221792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_reg " 2218efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedReg.SrcReg << " " 2219efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2220efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " " << RegShiftedReg.ShiftReg << ">"; 22210082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 222221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 222392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_imm " 2224efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedImm.SrcReg << " " 2225efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2226efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " #" << RegShiftedImm.ShiftImm << ">"; 222792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 222821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 22297e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 22307e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 223121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 2232293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OS << "<bitfield " << "lsb: " << Bitfield.LSB 2233293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach << ", width: " << Bitfield.Width << ">"; 2234293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 223521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 223621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 223721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: { 22388d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << "<register_list "; 22398d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 22405fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 22415fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 22427729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ) { 22437729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling OS << *I; 22447729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling if (++I < E) OS << ", "; 22458d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 22468d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 22478d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << ">"; 22488d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 22498d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 2250862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 2251862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OS << "<vector_list " << VectorList.Count << " * " 2252862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach << VectorList.RegNum << ">"; 2253862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 225498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 225598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach OS << "<vector_list(all lanes) " << VectorList.Count << " * " 225698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach << VectorList.RegNum << ">"; 225798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 22587636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 22597636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 22607636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach << VectorList.Count << " * " << VectorList.RegNum << ">"; 22617636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 226221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 2263fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar OS << "'" << getToken() << "'"; 2264fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 2265460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 2266460a90540b045c102012da2492999557e6840526Jim Grosbach OS << "<vectorindex " << getVectorIndex() << ">"; 2267460a90540b045c102012da2492999557e6840526Jim Grosbach break; 2268fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar } 2269fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar} 22703483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 22713483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// @name Auto-generated Match Functions 22723483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// { 22733483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 22743483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbarstatic unsigned MatchRegisterName(StringRef Name); 22753483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 22763483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// } 22773483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 227869df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilsonbool ARMAsmParser::ParseRegister(unsigned &RegNo, 227969df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson SMLoc &StartLoc, SMLoc &EndLoc) { 2280a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StartLoc = Parser.getTok().getLoc(); 22811355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach RegNo = tryParseRegister(); 2282a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach EndLoc = Parser.getTok().getLoc(); 2283bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 2284bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky return (RegNo == (unsigned)-1); 2285bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky} 2286bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 22879c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Try to parse a register name. The token must be an Identifier when called, 2288e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// and if it is a register name the token is eaten and the register number is 2289e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// returned. Otherwise return -1. 22903a69756e392942bc522193f38d7f33958ed3b131Chris Lattner/// 22911355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachint ARMAsmParser::tryParseRegister() { 229218b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 22937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) return -1; 2294d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 2295590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 22960c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson unsigned RegNum = MatchRegisterName(lowerCase); 22970c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson if (!RegNum) { 22980c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson RegNum = StringSwitch<unsigned>(lowerCase) 22990c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r13", ARM::SP) 23000c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r14", ARM::LR) 23010c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r15", ARM::PC) 23020c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("ip", ARM::R12) 230340e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach // Additional register name aliases for 'gas' compatibility. 230440e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a1", ARM::R0) 230540e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a2", ARM::R1) 230640e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a3", ARM::R2) 230740e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a4", ARM::R3) 230840e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v1", ARM::R4) 230940e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v2", ARM::R5) 231040e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v3", ARM::R6) 231140e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v4", ARM::R7) 231240e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v5", ARM::R8) 231340e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v6", ARM::R9) 231440e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v7", ARM::R10) 231540e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v8", ARM::R11) 231640e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sb", ARM::R9) 231740e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sl", ARM::R10) 231840e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("fp", ARM::R11) 23190c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Default(0); 23200c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson } 2321a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (!RegNum) { 2322aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // Check for aliases registered via .req. Canonicalize to lower case. 2323aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // That's more consistent since register names are case insensitive, and 2324aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // it's how the original entry was passed in from MC/MCParser/AsmParser. 2325aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2326a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // If no match, return failure. 2327a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Entry == RegisterReqs.end()) 2328a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return -1; 2329a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat identifier token. 2330a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Entry->getValue(); 2331a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 233269df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson 2333b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat identifier token. 2334460a90540b045c102012da2492999557e6840526Jim Grosbach 2335e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner return RegNum; 2336e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner} 2337d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 233819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 233919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// If a recoverable error occurs, return 1. If an irrecoverable error 234019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// occurs, return -1. An irrecoverable error is one where tokens have been 234119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// consumed in the process of trying to parse the shifter (i.e., when it is 234219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// indeed a shifter operand, but malformed). 23430d87ec21d79c8622733b8367aa41067169602480Jim Grosbachint ARMAsmParser::tryParseShiftRegister( 23440082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 23450082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 23460082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson const AsmToken &Tok = Parser.getTok(); 23470082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 23480082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2349590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 23500082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2351af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach .Case("asl", ARM_AM::lsl) 23520082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsl", ARM_AM::lsl) 23530082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsr", ARM_AM::lsr) 23540082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("asr", ARM_AM::asr) 23550082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("ror", ARM_AM::ror) 23560082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("rrx", ARM_AM::rrx) 23570082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Default(ARM_AM::no_shift); 23580082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 23590082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson if (ShiftTy == ARM_AM::no_shift) 236019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 1; 23610082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2362e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat the operator. 2363e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 2364e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The source register for the shift has already been added to the 2365e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // operand list, so we need to pop it off and combine it into the shifted 2366e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // register operand instead. 2367eac0796542d098caa371856d545faa6cdab5aad3Benjamin Kramer OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2368e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (!PrevOp->isReg()) 2369e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2370e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int SrcReg = PrevOp->getReg(); 2371e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int64_t Imm = 0; 2372e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int ShiftReg = 0; 2373e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (ShiftTy == ARM_AM::rrx) { 2374e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // RRX Doesn't have an explicit shift amount. The encoder expects 2375e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // the shift register to be the same as the source register. Seems odd, 2376e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // but OK. 2377e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ShiftReg = SrcReg; 2378e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else { 2379e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Figure out if this is shifted by a constant or a register (for non-RRX). 23808a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 23818a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 2382e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat hash. 2383e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc ImmLoc = Parser.getTok().getLoc(); 2384e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCExpr *ShiftExpr = 0; 238519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (getParser().ParseExpression(ShiftExpr)) { 238619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 238719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 238819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2389e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The expression must be evaluatable as an immediate. 2390e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 239119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (!CE) { 239219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 239319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 239419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2395e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Range check the immediate. 2396e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsl, ror: 0 <= imm <= 31 2397e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsr, asr: 0 <= imm <= 32 2398e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Imm = CE->getValue(); 2399e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (Imm < 0 || 2400e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2401e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 240219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "immediate shift value out of range"); 240319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 2404e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2405de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // shift by zero is a nop. Always send it through as lsl. 2406de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // ('as' compatibility) 2407de626ad8726677328e10dbdc15011254214437d7Jim Grosbach if (Imm == 0) 2408de626ad8726677328e10dbdc15011254214437d7Jim Grosbach ShiftTy = ARM_AM::lsl; 2409e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else if (Parser.getTok().is(AsmToken::Identifier)) { 24101355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach ShiftReg = tryParseRegister(); 2411e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc L = Parser.getTok().getLoc(); 241219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (ShiftReg == -1) { 241319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (L, "expected immediate or register in shift operand"); 241419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 241519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 241619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } else { 241719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (Parser.getTok().getLoc(), 2418e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach "expected immediate or register in shift operand"); 241919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 242019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2421e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2422e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 242392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson if (ShiftReg && ShiftTy != ARM_AM::rrx) 242492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2425af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ShiftReg, Imm, 24260082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson S, Parser.getTok().getLoc())); 242792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson else 242892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 242992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson S, Parser.getTok().getLoc())); 24300082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 243119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 0; 24320082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson} 24330082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 24340082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 243550d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// Try to parse a register name. The token must be an Identifier when called. 243650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// If it's a register, an AsmOperand is created. Another AsmOperand is created 243750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// if there is a "writeback". 'true' if it's not a register. 2438e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// 2439e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// TODO this is likely to change to allow different register types and or to 2440e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// parse for a specific register type. 244150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 24421355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachtryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2443e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner SMLoc S = Parser.getTok().getLoc(); 24441355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int RegNo = tryParseRegister(); 2445e717610f53e0465cde198536561a3c00ce29d59fBill Wendling if (RegNo == -1) 244650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 2447d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 244850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2449a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2450e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner const AsmToken &ExclaimTok = Parser.getTok(); 2451e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner if (ExclaimTok.is(AsmToken::Exclaim)) { 245250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 245350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling ExclaimTok.getLoc())); 2454e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner Parser.Lex(); // Eat exclaim token 2455460a90540b045c102012da2492999557e6840526Jim Grosbach return false; 2456460a90540b045c102012da2492999557e6840526Jim Grosbach } 2457460a90540b045c102012da2492999557e6840526Jim Grosbach 2458460a90540b045c102012da2492999557e6840526Jim Grosbach // Also check for an index operand. This is only legal for vector registers, 2459460a90540b045c102012da2492999557e6840526Jim Grosbach // but that'll get caught OK in operand matching, so we don't need to 2460460a90540b045c102012da2492999557e6840526Jim Grosbach // explicitly filter everything else out here. 2461460a90540b045c102012da2492999557e6840526Jim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 2462460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc SIdx = Parser.getTok().getLoc(); 2463460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat left bracket token. 2464460a90540b045c102012da2492999557e6840526Jim Grosbach 2465460a90540b045c102012da2492999557e6840526Jim Grosbach const MCExpr *ImmVal; 2466460a90540b045c102012da2492999557e6840526Jim Grosbach if (getParser().ParseExpression(ImmVal)) 2467460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2468460a90540b045c102012da2492999557e6840526Jim Grosbach const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2469460a90540b045c102012da2492999557e6840526Jim Grosbach if (!MCE) { 2470460a90540b045c102012da2492999557e6840526Jim Grosbach TokError("immediate value expected for vector index"); 2471460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2472460a90540b045c102012da2492999557e6840526Jim Grosbach } 2473460a90540b045c102012da2492999557e6840526Jim Grosbach 2474460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2475460a90540b045c102012da2492999557e6840526Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) { 2476460a90540b045c102012da2492999557e6840526Jim Grosbach Error(E, "']' expected"); 2477460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2478460a90540b045c102012da2492999557e6840526Jim Grosbach } 2479460a90540b045c102012da2492999557e6840526Jim Grosbach 2480460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat right bracket token. 2481460a90540b045c102012da2492999557e6840526Jim Grosbach 2482460a90540b045c102012da2492999557e6840526Jim Grosbach Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2483460a90540b045c102012da2492999557e6840526Jim Grosbach SIdx, E, 2484460a90540b045c102012da2492999557e6840526Jim Grosbach getContext())); 248599e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby } 248699e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby 248750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2488a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 2489a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2490fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2491fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2492fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// "c5", ... 2493fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopesstatic int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2494e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Use the same layout as the tablegen'erated register name matcher. Ugly, 2495e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // but efficient. 2496e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name.size()) { 2497e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: break; 2498e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 2: 2499fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp) 2500e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2501e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[1]) { 2502e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2503e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 0; 2504e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 1; 2505e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 2; 2506e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 3; 2507e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 4; 2508e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 5; 2509e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '6': return 6; 2510e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '7': return 7; 2511e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '8': return 8; 2512e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '9': return 9; 2513e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2514e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson break; 2515e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 3: 2516fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp || Name[1] != '1') 2517e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2518e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[2]) { 2519e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2520e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 10; 2521e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 11; 2522e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 12; 2523e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 13; 2524e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 14; 2525e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 15; 2526e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2527e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson break; 2528e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2529e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2530e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2531e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2532e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 253389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach/// parseITCondCode - Try to parse a condition code for an IT instruction. 253489df996ab20609676ecc8823f58414d598b09b46Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 253589df996ab20609676ecc8823f58414d598b09b46Jim GrosbachparseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 253689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 253789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach const AsmToken &Tok = Parser.getTok(); 253889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (!Tok.is(AsmToken::Identifier)) 253989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 254089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned CC = StringSwitch<unsigned>(Tok.getString()) 254189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("eq", ARMCC::EQ) 254289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ne", ARMCC::NE) 254389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hs", ARMCC::HS) 254489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cs", ARMCC::HS) 254589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lo", ARMCC::LO) 254689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cc", ARMCC::LO) 254789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("mi", ARMCC::MI) 254889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("pl", ARMCC::PL) 254989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vs", ARMCC::VS) 255089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vc", ARMCC::VC) 255189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hi", ARMCC::HI) 255289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ls", ARMCC::LS) 255389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ge", ARMCC::GE) 255489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lt", ARMCC::LT) 255589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("gt", ARMCC::GT) 255689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("le", ARMCC::LE) 255789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("al", ARMCC::AL) 255889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Default(~0U); 255989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (CC == ~0U) 256089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 256189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.Lex(); // Eat the token. 256289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 256389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 256489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 256589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_Success; 256689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach} 256789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 256843904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2569fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2570fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2571f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 257243904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2573e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 2574e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson const AsmToken &Tok = Parser.getTok(); 2575c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2576c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2577e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2578fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2579e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson if (Num == -1) 2580f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2581e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2582e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson Parser.Lex(); // Eat identifier token. 2583fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2584f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2585fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes} 2586fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 258743904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2588fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2589fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2590f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 259143904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2592fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 2593fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 2594c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2595c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2596fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2597fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2598fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Reg == -1) 2599f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2600fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2601fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 2602fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2603f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2604e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2605e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 26069b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 26079b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// coproc_option : '{' imm0_255 '}' 26089b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 26099b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachparseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 26109b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc S = Parser.getTok().getLoc(); 26119b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26129b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // If this isn't a '{', this isn't a coprocessor immediate operand. 26139b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 26149b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_NoMatch; 26159b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '{' 26169b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26179b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCExpr *Expr; 26189b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 26199b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (getParser().ParseExpression(Expr)) { 26209b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "illegal expression"); 26219b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26229b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 26239b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 26249b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 26259b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 26269b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26279b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 26289b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach int Val = CE->getValue(); 26299b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26309b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // Check for and consume the closing '}' 26319b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 26329b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26339b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc E = Parser.getTok().getLoc(); 26349b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '}' 26359b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26369b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 26379b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_Success; 26389b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach} 26399b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 2640d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// For register list parsing, we need to map from raw GPR register numbering 2641d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// to the enumeration values. The enumeration values aren't sorted by 2642d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// register number due to our using "sp", "lr" and "pc" as canonical names. 2643d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbachstatic unsigned getNextRegister(unsigned Reg) { 2644d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If this is a GPR, we need to do it manually, otherwise we can rely 2645d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // on the sort ordering of the enumeration since the other reg-classes 2646d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // are sane. 2647d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2648d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Reg + 1; 2649d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach switch(Reg) { 2650d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach default: assert(0 && "Invalid GPR number!"); 2651d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2652d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2653d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2654d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2655d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2656d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2657d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2658d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2659d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2660d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach} 2661d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2662ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach// Return the low-subreg of a given Q register. 2663ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbachstatic unsigned getDRegFromQReg(unsigned QReg) { 2664ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach switch (QReg) { 2665ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach default: llvm_unreachable("expected a Q register!"); 2666ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q0: return ARM::D0; 2667ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q1: return ARM::D2; 2668ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q2: return ARM::D4; 2669ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q3: return ARM::D6; 2670ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q4: return ARM::D8; 2671ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q5: return ARM::D10; 2672ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q6: return ARM::D12; 2673ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q7: return ARM::D14; 2674ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q8: return ARM::D16; 267525e0a87e9190cdca62aee5ac95cfc8ef44f35e92Jim Grosbach case ARM::Q9: return ARM::D18; 2676ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q10: return ARM::D20; 2677ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q11: return ARM::D22; 2678ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q12: return ARM::D24; 2679ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q13: return ARM::D26; 2680ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q14: return ARM::D28; 2681ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q15: return ARM::D30; 2682ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2683ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach} 2684ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2685d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach/// Parse a register list. 268650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 26871355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachparseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 268818b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LCurly) && 2689a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Curly Brace"); 2690e717610f53e0465cde198536561a3c00ce29d59fBill Wendling SMLoc S = Parser.getTok().getLoc(); 2691d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '{' token. 2692d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 269316c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2694d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Check the first register in the list to see what register class 2695d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // this is a list of. 2696d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int Reg = tryParseRegister(); 2697d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 2698d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "register expected"); 2699d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2700ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // The reglist instructions have at most 16 registers, so reserve 2701ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // space for that many. 2702ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2703ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2704ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2705ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2706ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2707ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2708ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach ++Reg; 2709ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 27101a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCRegisterClass *RC; 2711d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2712d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2713d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2714d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2715d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2716d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2717d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else 2718d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2719e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 2720ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Store the register. 2721d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2722d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2723d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // This starts immediately after the first register token in the list, 2724d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // so we can see either a comma or a minus (range separator) as a legal 2725d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // next token. 2726d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 2727d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 2728d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 2729e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 2730d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 2731d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int EndReg = tryParseRegister(); 2732d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (EndReg == -1) 2733d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "register expected"); 2734ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2735ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2736ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 2737d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If the register is the same as the start reg, there's nothing 2738d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // more to do. 2739d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == EndReg) 2740d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2741d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2742d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(EndReg)) 2743d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "invalid register in register list"); 2744d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Ranges must go from low to high. 2745d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2746d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "bad range in register list"); 2747d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2748d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Add all the registers in the range to the register list. 2749d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Reg != EndReg) { 2750d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = getNextRegister(Reg); 2751d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2752d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2753d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2754d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2755d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat the comma. 2756d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RegLoc = Parser.getTok().getLoc(); 2757d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int OldReg = Reg; 2758a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach const AsmToken RegTok = Parser.getTok(); 2759d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = tryParseRegister(); 2760d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 27612d539691a1e4b9d61853aa99d1a5580dc88595dbJim Grosbach return Error(RegLoc, "register expected"); 2762ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2763ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach bool isQReg = false; 2764ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2765ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2766ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach isQReg = true; 2767ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2768d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2769d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(Reg)) 2770d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2771d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // List must be monotonically increasing. 2772a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) 2773d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "register list not in ascending order"); 2774a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) { 2775a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2776a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach ") in register list"); 2777a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach continue; 2778a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach } 2779d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register lists must also be contiguous. 2780d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // It's OK to use the enumeration values directly here rather, as the 2781d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register classes have the enum sorted properly. 2782d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2783d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg != OldReg + 1) 2784d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "non-contiguous register range"); 2785d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2786ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (isQReg) 2787ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2788d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2789d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2790d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2791d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 2792d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(E, "'}' expected"); 2793d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '}' token. 2794e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 279527debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // Push the register list operand. 279650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 279727debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 279827debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // The ARM system instruction variants for LDM/STM have a '^' token here. 279927debd60a152d39e421c57bce511f16d8439a670Jim Grosbach if (Parser.getTok().is(AsmToken::Caret)) { 280027debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 280127debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Parser.Lex(); // Eat '^' token. 280227debd60a152d39e421c57bce511f16d8439a670Jim Grosbach } 280327debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 280450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2805d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby} 2806d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby 280798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach// Helper function to parse the lane index for vector lists. 280898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 28097636bf6530fd83bf7356ae3894246a4e558741a4Jim GrosbachparseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 28107636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Index = 0; // Always return a defined index value. 281198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 281298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the '['. 281398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::RBrac)) { 281498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // "Dn[]" is the 'all lanes' syntax. 281598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = AllLanes; 281698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the ']'. 281798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 281898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 2819c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCExpr *LaneIndex; 2820c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 2821c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (getParser().ParseExpression(LaneIndex)) { 2822c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "illegal expression"); 2823c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 28247636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 2825c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 2826c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (!CE) { 2827c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "lane index must be empty or an integer"); 2828c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2829c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2830c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) { 2831c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "']' expected"); 2832c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2833c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2834c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Parser.Lex(); // Eat the ']'. 2835c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach int64_t Val = CE->getValue(); 2836c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach 2837c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach // FIXME: Make this range check context sensitive for .8, .16, .32. 2838c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Val < 0 || Val > 7) { 2839c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "lane index out of range"); 2840c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2841c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2842c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Index = Val; 2843c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach LaneKind = IndexedLane; 2844c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_Success; 284598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 284698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = NoLanes; 284798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 284898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach} 284998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 2850862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach// parse a vector register list 2851862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2852862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachparseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 285398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy LaneKind; 28547636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 28555c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc S = Parser.getTok().getLoc(); 28565c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // As an extension (to match gas), support a plain D register or Q register 28575c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // (without encosing curly braces) as a single or double entry list, 28585c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // respectively. 28595c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) { 28605c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach int Reg = tryParseRegister(); 28615c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Reg == -1) 28625c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_NoMatch; 28635c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 28645c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 28657636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 286698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 286798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 286898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 286998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach default: 287098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach assert(0 && "unexpected lane kind!"); 287198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 287298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 28730aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 287498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 287598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 287698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 28773471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 28783471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 287998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 28807636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 28817636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 288295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 288395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 28847636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 288598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 28865c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 28875c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 28885c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 28895c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Reg = getDRegFromQReg(Reg); 28907636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 289198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 289298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 289398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 289498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach default: 289598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach assert(0 && "unexpected lane kind!"); 289698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 289798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 28980aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 289998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 290098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 290198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 29023471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 29033471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 290498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 29057636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 29067636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 290795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 290895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 29097636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 291098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 29115c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 29125c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29135c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Error(S, "vector register expected"); 29145c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_ParseFail; 29155c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29165c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach 29175c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 2918862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_NoMatch; 2919862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 2920862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '{' token. 2921862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 2922862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 2923862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int Reg = tryParseRegister(); 2924862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 2925862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 2926862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 2927862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 2928862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count = 1; 2929276ed0344c05822617934fa4a6a9920d864193a5Jim Grosbach int Spacing = 0; 2930c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach unsigned FirstReg = Reg; 2931c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 2932c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 2933c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2934c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach FirstReg = Reg = getDRegFromQReg(Reg); 29350aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // double-spacing requires explicit D registers, otherwise 29360aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // it's ambiguous with four-register single spaced. 2937c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 2938c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Count; 2939c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 29407636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 294198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 2942c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach 2943e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 2944e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 2945e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 29460aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 29470aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 29480aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 29490aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(Parser.getTok().getLoc(), 29500aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "sequential registers in double spaced list"); 29510aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 29520aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 2953e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 2954e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 2955e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach int EndReg = tryParseRegister(); 2956e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (EndReg == -1) { 2957e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "register expected"); 2958e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2959e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 2960e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2961e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2962e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 2963e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // If the register is the same as the start reg, there's nothing 2964e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // more to do. 2965e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg == EndReg) 2966e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 2967e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // The register must be in the same register class as the first. 2968e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 2969e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "invalid register in register list"); 2970e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2971e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 2972e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Ranges must go from low to high. 2973e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg > EndReg) { 2974e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "bad range in register list"); 2975e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2976e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 297798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 297898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 29797636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 29807636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 298198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 29827636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 298398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 298498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 298598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 298698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach EndLoc = Parser.getTok().getLoc(); 2987e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach 2988e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Add all the registers in the range to the register list. 2989e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Count += EndReg - Reg; 2990e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Reg = EndReg; 2991e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 2992e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 2993862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat the comma. 2994862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach RegLoc = Parser.getTok().getLoc(); 2995862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int OldReg = Reg; 2996862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Reg = tryParseRegister(); 2997862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 2998862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 2999862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3000862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3001c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // vector register lists must be contiguous. 3002862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // It's OK to use the enumeration values directly here rather, as the 3003862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // VFP register classes have the enum sorted properly. 3004c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // 3005c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 3006c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 3007c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 30080aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 30090aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 30100aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 30110aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(RegLoc, 30120aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "invalid register in double-spaced list (must be 'D' register')"); 30130aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 30140aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 3015c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Reg = getDRegFromQReg(Reg); 3016c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (Reg != OldReg + 1) { 3017c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Error(RegLoc, "non-contiguous register range"); 3018c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach return MatchOperand_ParseFail; 3019c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 3020c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 3021c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Count += 2; 302298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 302398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 30247636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 302598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 30267636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 302798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30287636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 302998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 303098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 303198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3032c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach continue; 3033c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 30340aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Normal D register. 30350aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Figure out the register spacing (single or double) of the list if 30360aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // we don't know it already. 30370aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 30380aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1 + (Reg == OldReg + 2); 30390aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach 30400aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Just check that it's contiguous and keep going. 30410aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (Reg != OldReg + Spacing) { 3042862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "non-contiguous register range"); 3043862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3044862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3045862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ++Count; 304698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 304798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 30487636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 304998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 30507636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 305198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30527636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 305398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 305498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 305598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3056862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3057862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3058862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3059862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) { 3060862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(E, "'}' expected"); 3061862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3062862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3063862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '}' token. 3064862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 306598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 306698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach default: 306798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach assert(0 && "unexpected lane kind in register list."); 306898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 30690aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 30700aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach (Spacing == 2), S, E)); 307198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 307298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 307398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 30743471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach (Spacing == 2), 307598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach S, E)); 307698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 30777636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 30787636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 307995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 308095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach (Spacing == 2), 308195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach S, E)); 30827636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 308398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3084862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_Success; 3085862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach} 3086862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 308743904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3088f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 308943904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3090706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3091706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3092706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3093706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes StringRef OptStr = Tok.getString(); 3094706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3095706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 3096706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("sy", ARM_MB::SY) 3097706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("st", ARM_MB::ST) 3098032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("sh", ARM_MB::ISH) 3099706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ish", ARM_MB::ISH) 3100032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("shst", ARM_MB::ISHST) 3101706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ishst", ARM_MB::ISHST) 3102706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nsh", ARM_MB::NSH) 3103032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("un", ARM_MB::NSH) 3104706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nshst", ARM_MB::NSHST) 3105032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("unst", ARM_MB::NSHST) 3106706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("osh", ARM_MB::OSH) 3107706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("oshst", ARM_MB::OSHST) 3108706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Default(~0U); 3109706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3110706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes if (Opt == ~0U) 3111f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 3112706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3113706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3114706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3115f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 3116706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes} 3117706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 311843904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3119a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 312043904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3121a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3122a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3123a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3124a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef IFlagsStr = Tok.getString(); 3125a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 31262dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // An iflags string of "none" is interpreted to mean that none of the AIF 31272dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // bits are set. Not a terribly useful instruction, but a valid encoding. 3128a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = 0; 31292dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (IFlagsStr != "none") { 31302dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 31312dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 31322dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("a", ARM_PROC::A) 31332dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("i", ARM_PROC::I) 31342dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("f", ARM_PROC::F) 31352dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Default(~0U); 31362dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 31372dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // If some specific iflag is already set, it means that some letter is 31382dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // present more than once, this is not acceptable. 31392dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (Flag == ~0U || (IFlags & Flag)) 31402dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson return MatchOperand_NoMatch; 31412dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 31422dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson IFlags |= Flag; 31432dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson } 3144a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 3145a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3146a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3147a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3148a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return MatchOperand_Success; 3149584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes} 3150584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 315143904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3152584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 315343904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3154584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3155584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3156584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3157584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Mask = Tok.getString(); 3158584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3159acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (isMClass()) { 3160acad68da50581de905a994ed3c6b9c197bcea687James Molloy // See ARMv6-M 10.1.1 3161acad68da50581de905a994ed3c6b9c197bcea687James Molloy unsigned FlagsVal = StringSwitch<unsigned>(Mask) 3162acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("apsr", 0) 3163acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("iapsr", 1) 3164acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("eapsr", 2) 3165acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("xpsr", 3) 3166acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("ipsr", 5) 3167acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("epsr", 6) 3168acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("iepsr", 7) 3169acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("msp", 8) 3170acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("psp", 9) 3171acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("primask", 16) 3172acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("basepri", 17) 3173acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("basepri_max", 18) 3174acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("faultmask", 19) 3175acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("control", 20) 3176acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Default(~0U); 317718c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3178acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (FlagsVal == ~0U) 3179acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 3180acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3181acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) 3182acad68da50581de905a994ed3c6b9c197bcea687James Molloy // basepri, basepri_max and faultmask only valid for V7m. 3183acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 318418c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3185acad68da50581de905a994ed3c6b9c197bcea687James Molloy Parser.Lex(); // Eat identifier token. 3186acad68da50581de905a994ed3c6b9c197bcea687James Molloy Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3187acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_Success; 3188acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 3189acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3190584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3191584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes size_t Start = 0, Next = Mask.find('_'); 3192584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Flags = ""; 3193590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string SpecReg = Mask.slice(Start, Next).lower(); 3194584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (Next != StringRef::npos) 3195584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Flags = Mask.slice(Next+1, Mask.size()); 3196584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3197584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // FlagsVal contains the complete mask: 3198584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 3-0: Mask 3199584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3200584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned FlagsVal = 0; 3201584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3202584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "apsr") { 3203584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal = StringSwitch<unsigned>(Flags) 3204b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach .Case("nzcvq", 0x8) // same as CPSR_f 3205584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("g", 0x4) // same as CPSR_s 3206584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("nzcvqg", 0xc) // same as CPSR_fs 3207584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3208584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 32094b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger if (FlagsVal == ~0U) { 3210584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (!Flags.empty()) 3211584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3212584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes else 3213bf841cf3360558d2939c9f1a244a7a7296f846dfJim Grosbach FlagsVal = 8; // No flag 32144b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger } 3215584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 321656926a39619bd644c83c4128f0b55189e52707d7Bruno Cardoso Lopes if (Flags == "all") // cpsr_all is an alias for cpsr_fc 321756926a39619bd644c83c4128f0b55189e52707d7Bruno Cardoso Lopes Flags = "fc"; 3218584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes for (int i = 0, e = Flags.size(); i != e; ++i) { 3219584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3220584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("c", 1) 3221584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("x", 2) 3222584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("s", 4) 3223584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("f", 8) 3224584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3225584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3226584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // If some specific flag is already set, it means that some letter is 3227584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // present more than once, this is not acceptable. 3228584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (FlagsVal == ~0U || (FlagsVal & Flag)) 3229584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3230584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= Flag; 3231584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 3232584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else // No match for special register. 3233584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3234584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 32357784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // Special register without flags is NOT equivalent to "fc" flags. 32367784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // NOTE: This is a divergence from gas' behavior. Uncommenting the following 32377784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // two lines would enable gas compatibility at the expense of breaking 32387784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // round-tripping. 32397784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // 32407784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // if (!FlagsVal) 32417784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // FlagsVal = 0x9; 3242584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3243584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3244584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "spsr") 3245584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= 16; 3246584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3247584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3248584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3249584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_Success; 3250a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes} 3251a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3252f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3253f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachparsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3254f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Low, int High) { 3255f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3256f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3257f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3258f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3259f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3260f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef ShiftName = Tok.getString(); 3261590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string LowerOp = Op.lower(); 3262590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string UpperOp = Op.upper(); 3263f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (ShiftName != LowerOp && ShiftName != UpperOp) { 3264f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3265f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3266f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3267f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat shift type token. 3268f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3269f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // There must be a '#' and a shift amount. 32708a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 32718a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3272f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3273f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3274f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3275f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat hash token. 3276f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3277f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCExpr *ShiftAmount; 3278f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 3279f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3280f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "illegal expression"); 3281f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3282f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3283f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3284f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) { 3285f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "constant expression expected"); 3286f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3287f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3288f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 3289f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Val < Low || Val > High) { 3290f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "immediate value out of range"); 3291f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3292f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3293f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3294f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3295f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3296f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_Success; 3297f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach} 3298f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3299c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3300c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachparseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3301c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3302c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach SMLoc S = Tok.getLoc(); 3303c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3304c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3305c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3306c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3307c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int Val = StringSwitch<int>(Tok.getString()) 3308c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("be", 1) 3309c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("le", 0) 3310c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Default(-1); 3311c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.Lex(); // Eat the token. 3312c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3313c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Val == -1) { 3314c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3315c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3316c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3317c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3318c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach getContext()), 3319c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach S, Parser.getTok().getLoc())); 3320c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_Success; 3321c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach} 3322c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3323580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3324580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// instructions. Legal values are: 3325580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// lsl #n 'n' in [0,31] 3326580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// asr #n 'n' in [1,32] 3327580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// n == 32 encoded as n == 0. 3328580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3329580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachparseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3330580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const AsmToken &Tok = Parser.getTok(); 3331580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc S = Tok.getLoc(); 3332580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3333580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3334580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3335580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3336580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach StringRef ShiftName = Tok.getString(); 3337580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 3338580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL") 3339580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = false; 3340580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else if (ShiftName == "asr" || ShiftName == "ASR") 3341580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = true; 3342580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else { 3343580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3344580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3345580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3346580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat the operator. 3347580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3348580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // A '#' and a shift amount. 33498a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 33508a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3351580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3352580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3353580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3354580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat hash token. 3355580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3356580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCExpr *ShiftAmount; 3357580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3358580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3359580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "malformed shift expression"); 3360580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3361580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3362580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3363580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (!CE) { 3364580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "shift amount must be an immediate"); 3365580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3366580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3367580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3368580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach int64_t Val = CE->getValue(); 3369580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (isASR) { 3370580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3371580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 1 || Val > 32) { 3372580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'asr' shift amount must be in range [1,32]"); 3373580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3374580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 33750afa0094afdfe589f407feb76948f273b414b278Owen Anderson // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 33760afa0094afdfe589f407feb76948f273b414b278Owen Anderson if (isThumb() && Val == 32) { 33770afa0094afdfe589f407feb76948f273b414b278Owen Anderson Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 33780afa0094afdfe589f407feb76948f273b414b278Owen Anderson return MatchOperand_ParseFail; 33790afa0094afdfe589f407feb76948f273b414b278Owen Anderson } 3380580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val == 32) Val = 0; 3381580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } else { 3382580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3383580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 0 || Val > 31) { 3384580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'lsr' shift amount must be in range [0,31]"); 3385580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3386580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3387580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3388580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3389580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach E = Parser.getTok().getLoc(); 3390580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3391580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3392580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_Success; 3393580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach} 3394580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 33957e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 33967e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// of instructions. Legal values are: 33977e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// ror #n 'n' in {0, 8, 16, 24} 33987e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 33997e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachparseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 34007e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const AsmToken &Tok = Parser.getTok(); 34017e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc S = Tok.getLoc(); 3402326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) 3403326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 34047e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach StringRef ShiftName = Tok.getString(); 3405326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (ShiftName != "ror" && ShiftName != "ROR") 3406326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 34077e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat the operator. 34087e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34097e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // A '#' and a rotate amount. 34108a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34118a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 34127e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 34137e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34147e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34157e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat hash token. 34167e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34177e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCExpr *ShiftAmount; 34187e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 34197e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 34207e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "malformed rotate expression"); 34217e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34227e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34237e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 34247e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (!CE) { 34257e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "rotate amount must be an immediate"); 34267e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34277e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34287e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34297e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach int64_t Val = CE->getValue(); 34307e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 34317e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // normally, zero is represented in asm by omitting the rotate operand 34327e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // entirely. 34337e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 34347e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "'ror' rotate amount must be 8, 16, or 24"); 34357e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34367e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34377e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34387e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach E = Parser.getTok().getLoc(); 34397e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 34407e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34417e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_Success; 34427e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach} 34437e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 3444293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3445293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachparseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3446293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 3447293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The bitfield descriptor is really two operands, the LSB and the width. 34488a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34498a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3450293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3451293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3452293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3453293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3454293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3455293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *LSBExpr; 3456293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3457293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(LSBExpr)) { 3458293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3459293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3460293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3461293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3462293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3463293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be an immediate"); 3464293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3465293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3466293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3467293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t LSB = CE->getValue(); 3468293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [0,31] 3469293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (LSB < 0 || LSB > 31) { 3470293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be in the range [0,31]"); 3471293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3472293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3473293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3474293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3475293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Expect another immediate operand. 3476293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Parser.getTok().isNot(AsmToken::Comma)) { 3477293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "too few operands"); 3478293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3479293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3480293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 34818a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34828a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3483293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3484293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3485293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3486293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3487293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3488293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *WidthExpr; 3489293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(WidthExpr)) { 3490293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3491293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3492293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3493293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach CE = dyn_cast<MCConstantExpr>(WidthExpr); 3494293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3495293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be an immediate"); 3496293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3497293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3498293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3499293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t Width = CE->getValue(); 3500293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [1,32-lsb] 3501293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Width < 1 || Width > 32 - LSB) { 3502293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be in the range [1,32-lsb]"); 3503293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3504293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3505293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3506293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3507293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3508293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3509293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_Success; 3510293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach} 3511293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 35127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 35137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 35147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3515f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // postidx_reg := '+' register {, shift} 3516f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | '-' register {, shift} 3517f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | register {, shift} 35187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 35197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 35207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // in the case where there is no match, as other alternatives take other 35217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // parse methods. 35227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach AsmToken Tok = Parser.getTok(); 35237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S = Tok.getLoc(); 35247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool haveEaten = false; 352516578b50889329eb62774148091ba0f38b681a09Jim Grosbach bool isAdd = true; 35267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Reg = -1; 35277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::Plus)) { 35287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+' token. 35297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 35307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 35317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-' token. 353216578b50889329eb62774148091ba0f38b681a09Jim Grosbach isAdd = false; 35337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 35347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 35357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 35367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Reg = tryParseRegister(); 35377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Reg == -1) { 35387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!haveEaten) 35397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_NoMatch; 35407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 35417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_ParseFail; 35427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 35437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 35447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3545f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3546f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm = 0; 35470d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 35480d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach Parser.Lex(); // Eat the ','. 35490d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 35500d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach return MatchOperand_ParseFail; 35510d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach } 3552f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 3553f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3554f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ShiftImm, S, E)); 35557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 35567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_Success; 35577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 35587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3559251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3560251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachparseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3561251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3562251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // am3offset := '+' register 3563251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | '-' register 3564251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | register 3565251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # imm 3566251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # + imm 3567251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # - imm 3568251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3569251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 3570251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // in the case where there is no match, as other alternatives take other 3571251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // parse methods. 3572251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach AsmToken Tok = Parser.getTok(); 3573251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc S = Tok.getLoc(); 3574251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3575251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Do immediates first, as we always parse those if we have a '#'. 35768a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 35778a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 3578251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '#'. 3579251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Explicitly look for a '-', as we need to encode negative zero 3580251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // differently. 3581251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isNegative = Parser.getTok().is(AsmToken::Minus); 3582251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCExpr *Offset; 3583251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (getParser().ParseExpression(Offset)) 3584251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3585251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3586251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!CE) { 3587251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(S, "constant expression expected"); 3588251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3589251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3590251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Tok.getLoc(); 3591251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Negative zero is encoded as the flag value INT32_MIN. 3592251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int32_t Val = CE->getValue(); 3593251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (isNegative && Val == 0) 3594251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = INT32_MIN; 3595251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3596251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back( 3597251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3598251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3599251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3600251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3601251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3602251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3603251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool haveEaten = false; 3604251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isAdd = true; 3605251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int Reg = -1; 3606251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Tok.is(AsmToken::Plus)) { 3607251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '+' token. 3608251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3609251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 3610251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '-' token. 3611251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach isAdd = false; 3612251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3613251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3614251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 3615251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Reg = tryParseRegister(); 3616251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Reg == -1) { 3617251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!haveEaten) 3618251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_NoMatch; 3619251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 3620251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3621251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3622251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3623251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3624251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3625251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 0, S, E)); 3626251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3627251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3628251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach} 3629251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3630a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2LdrdPre - Convert parsed operands to MCInst. 3631a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3632a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3633a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3634a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3635a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3636a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3637a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3638a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3639a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3640a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3641a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3642a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3643a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3644a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3645a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3646a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3647a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3648a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2StrdPre - Convert parsed operands to MCInst. 3649a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3650a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3651a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3652a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3653a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3654a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3655a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3656a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3657a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3658a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3659a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3660a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3661a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3662a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3663a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3664a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3665a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3666eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3667eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3668eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3669eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbachbool ARMAsmParser:: 3670eeec025cf5a2236ee9527a3312496a6ea42100c6Jim GrosbachcvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3671eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3672eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3673eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3674eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach // Create a writeback register dummy placeholder. 3675eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3676eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3677eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3678eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3679eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach return true; 3680eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach} 3681eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3682ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3683ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3684ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3685ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbachbool ARMAsmParser:: 3686ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim GrosbachcvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3687ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3688ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach // Create a writeback register dummy placeholder. 3689ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3690ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3691ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3692ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3693ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach return true; 3694ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach} 3695ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach 36961355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3697ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3698ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3699ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 37001355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3701ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3702ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3703ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 3704ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3705ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3706ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 37077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3708ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3709ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3710ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3711ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 37129ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 37139ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37149ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// when they refer multiple MIOperands inside a single one. 37159ab0f25fc194b4315db1b87d38d4024054120bf6Owen Andersonbool ARMAsmParser:: 37169ab0f25fc194b4315db1b87d38d4024054120bf6Owen AndersoncvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 37179ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37189ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37199ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37209ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson // Create a writeback register dummy placeholder. 37219ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson Inst.addOperand(MCOperand::CreateImm(0)); 37229ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37239ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 37249ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37259ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson return true; 37269ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson} 37279ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37289ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 3729548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3730548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3731548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3732548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbachbool ARMAsmParser:: 3733548340c4bfa596b602f286dfd3a8782817859d95Jim GrosbachcvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3734548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3735548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach // Create a writeback register dummy placeholder. 3736548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3737548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3738548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3739548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3740548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach return true; 3741548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach} 3742548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach 37431355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3744ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3745ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3746ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 37471355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3748ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3749ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3750ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3751548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3752548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3753548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 37557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 37567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 37577b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 37587b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37597b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// when they refer multiple MIOperands inside a single one. 37607b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbachbool ARMAsmParser:: 37617b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim GrosbachcvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 37627b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37637b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach // Create a writeback register dummy placeholder. 37647b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 37657b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37667b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 37677b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37687b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach return true; 37697b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach} 37707b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach 37717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 37727ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37737ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 37747ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 37757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 37767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3778ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 37807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 37817ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 37827ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 37837ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 37847ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 37857ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3786ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3787ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3788ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3789ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 37907ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 3791ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3792ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3793ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 37947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 37957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3797aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3798ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 3799ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 38007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 38047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 38057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 38067ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 38077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 3808aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson 38097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 38107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 38117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 38127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 38137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 38147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 38167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 38177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 38187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 38237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3824ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3825ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 3826ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 3827ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 38287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 3829ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3830ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3831ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 38327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 38337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3834ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 3835ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 38367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3837ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 38427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3843ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3844ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 3845ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 3846ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 38472fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// cvtLdrdPre - Convert parsed operands to MCInst. 38482fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 38492fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// when they refer multiple MIOperands inside a single one. 38502fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbachbool ARMAsmParser:: 38512fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim GrosbachcvtLdrdPre(MCInst &Inst, unsigned Opcode, 38522fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38532fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Rt, Rt2 38542fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38552fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 38562fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Create a writeback register dummy placeholder. 38572fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 38582fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // addr 38592fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 38602fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // pred 38612fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 38622fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return true; 38632fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach} 38642fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 386514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// cvtStrdPre - Convert parsed operands to MCInst. 386614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 386714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// when they refer multiple MIOperands inside a single one. 386814605d1a679d55ff25875656e100ff455194ee17Jim Grosbachbool ARMAsmParser:: 386914605d1a679d55ff25875656e100ff455194ee17Jim GrosbachcvtStrdPre(MCInst &Inst, unsigned Opcode, 387014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 387114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Create a writeback register dummy placeholder. 387214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 387314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt, Rt2 387414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 387514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 387614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // addr 387714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 387814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // pred 387914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 388014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return true; 388114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach} 388214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach 3883623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3884623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3885623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3886623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbachbool ARMAsmParser:: 3887623a454b0f5c300e69a19984d7855a1e976c3d09Jim GrosbachcvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3888623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3889623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3890623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach // Create a writeback register dummy placeholder. 3891623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3892623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3893623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3894623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach return true; 3895623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach} 3896623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 389788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// cvtThumbMultiple- Convert parsed operands to MCInst. 389888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 389988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// when they refer multiple MIOperands inside a single one. 390088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbachbool ARMAsmParser:: 390188ae2bc6d53bbf58422ff74729da18a53e155b4aJim GrosbachcvtThumbMultiply(MCInst &Inst, unsigned Opcode, 390288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 390388ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // The second source operand must be the same register as the destination 390488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // operand. 390588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach if (Operands.size() == 6 && 39067a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 39077a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[5])->getReg()) && 39087a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 39097a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[4])->getReg())) { 391088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach Error(Operands[3]->getStartLoc(), 39117a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach "destination register must match source register"); 391288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return false; 391388ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach } 391488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 391588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 39161b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // If we have a three-operand form, make sure to set Rn to be the operand 39171b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // that isn't the same as Rd. 39181b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach unsigned RegOp = 4; 39191b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach if (Operands.size() == 6 && 39201b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[4])->getReg() == 39211b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[3])->getReg()) 39221b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach RegOp = 5; 39231b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 39241b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach Inst.addOperand(Inst.getOperand(0)); 392588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 392688ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach 392788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 392888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach} 3929623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 393012431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 393112431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 393212431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 393312431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 39346029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 393512431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 393612431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 393712431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 393812431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 393912431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 394012431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 394112431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 394212431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 394312431329d617064d6e72dd040a58c1635cc261abJim Grosbach 394412431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 394512431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 394612431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 394712431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 39486029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 394912431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 395012431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 395112431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 395212431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 395312431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vm 395412431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 395512431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 395612431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 395712431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 395812431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 395912431329d617064d6e72dd040a58c1635cc261abJim Grosbach 39604334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 39614334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 39624334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39634334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 39644334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 39654334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 39664334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 39674334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 39686029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 39694334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 39704334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 39714334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 39724334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 39734334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 39744334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 39754334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 39764334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39774334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 39784334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 39794334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 39804334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 39814334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vm 39824334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 39834334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 39846029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 39854334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 39864334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 39874334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 39884334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 39894334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 3990e717610f53e0465cde198536561a3c00ce29d59fBill Wendling/// Parse an ARM memory expression, return false if successful else return true 39919c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// or an error. The first token must be a '[' when called. 399250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 39937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3994762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 399518b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LBrac) && 3996a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Bracket"); 3997762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 3998b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat left bracket token. 3999a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 400018b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &BaseRegTok = Parser.getTok(); 40011355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int BaseRegNum = tryParseRegister(); 40027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (BaseRegNum == -1) 40037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(BaseRegTok.getLoc(), "register expected"); 4004a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 40050571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar // The next token must either be a comma or a closing bracket. 40060571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar const AsmToken &Tok = Parser.getTok(); 40070571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 40087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Tok.getLoc(), "malformed memory operand"); 40090571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar 40107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::RBrac)) { 4011762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = Tok.getLoc(); 4012b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat right bracket token. 4013a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 40147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 401557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 0, 0, false, S, E)); 401603f44a04e63ff77af12df33e10ffdc473609dfe2Jim Grosbach 4017fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4018fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // operand. It's rather odd, but syntactically valid. 4019fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4020fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4021fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Parser.Lex(); // Eat the '!'. 4022fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach } 4023fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach 40247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 40257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 402650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 40277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 40287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the comma. 402950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 403057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a ':', it's an alignment specifier. 403157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Colon)) { 403257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the ':'. 403357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 403457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 403557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCExpr *Expr; 403657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (getParser().ParseExpression(Expr)) 403757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return true; 403857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 403957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // The expression has to be a constant. Memory references with relocations 404057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // don't come through here, as they use the <label> forms of the relevant 404157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // instructions. 404257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 404357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!CE) 404457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error (E, "constant expression expected"); 404557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 404657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Align = 0; 404757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach switch (CE->getValue()) { 404857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach default: 4049eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach return Error(E, 4050eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4051eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 16: Align = 2; break; 4052eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 32: Align = 4; break; 405357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 64: Align = 8; break; 405457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 128: Align = 16; break; 405557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 256: Align = 32; break; 405657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 405757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 405857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Now we should have the closing ']' 405957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 406057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 406157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error(E, "']' expected"); 406257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat right bracket token. 406357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 406457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Don't worry about range checking the value here. That's handled by 406557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // the is*() predicates. 406657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 406757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, Align, 406857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 406957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 407057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 407157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // operand. 407257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 407357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 407457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the '!'. 407557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 407657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 407757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return false; 407857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 407957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 408057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a '#', it's an immediate offset, else assume it's a register 40816cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // offset. Be friendly and also accept a plain integer (without a leading 40826cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // hash) for gas compatibility. 40836cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 40848a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar) || 40856cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.getTok().is(AsmToken::Integer)) { 40868a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Integer)) 40876cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.Lex(); // Eat the '#'. 40887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 408950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 40900da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson bool isNegative = getParser().getTok().is(AsmToken::Minus); 40917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Offset; 40927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Offset)) 40937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 409405d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 40957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The expression has to be a constant. Memory references with relocations 40967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // don't come through here, as they use the <label> forms of the relevant 40977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // instructions. 40987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 40997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 41007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error (E, "constant expression expected"); 41017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41020da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson // If the constant was #-0, represent it as INT32_MIN. 41030da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson int32_t Val = CE->getValue(); 41040da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson if (isNegative && Val == 0) 41050da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson CE = MCConstantExpr::Create(INT32_MIN, getContext()); 41060da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson 41077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 41087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 41107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 41117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 411205d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 41137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Don't worry about range checking the value here. That's handled by 41147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // the is*() predicates. 41157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 411657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, 0, 411757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 4118a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 41197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 41207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // operand. 41217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 41227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 41237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '!'. 4124762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 41257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 41279c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 4128d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 41297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The register offset is optionally preceded by a '+' or '-' 41307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative = false; 41317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 41327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach isNegative = true; 41337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-'. 41347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Parser.getTok().is(AsmToken::Plus)) { 41357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Nothing to do. 41367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+'. 41377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 41389c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int OffsetRegNum = tryParseRegister(); 41417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (OffsetRegNum == -1) 41427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "register expected"); 41437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a shift operator, handle it. 41457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 41460d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm = 0; 41477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 41487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the ','. 41490d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 41507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 41519c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 415216c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 41537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 41547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 41567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 41577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 41587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 416057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ShiftType, ShiftImm, 0, isNegative, 41617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach S, E)); 41627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 4163f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4164f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // operand. 4165f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4166f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4167f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Parser.Lex(); // Eat the '!'. 4168f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 41699c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41709c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby return false; 41719c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby} 41729c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41737ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// parseMemRegOffsetShift - one of these two: 4174a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ( lsl | lsr | asr | ror ) , # shift_amount 4175a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// rrx 41767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// return true if it parses a shift otherwise it returns false. 41777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 41787ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &Amount) { 41797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 418018b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 4181a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby if (Tok.isNot(AsmToken::Identifier)) 4182a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return true; 418338e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef ShiftName = Tok.getString(); 4184af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL" || 4185af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach ShiftName == "asl" || ShiftName == "ASL") 41860082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsl; 4187a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "lsr" || ShiftName == "LSR") 41880082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsr; 4189a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "asr" || ShiftName == "ASR") 41900082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::asr; 4191a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "ror" || ShiftName == "ROR") 41920082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::ror; 4193a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "rrx" || ShiftName == "RRX") 41940082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::rrx; 4195a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else 41967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "illegal shift operator"); 4197b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat shift type token. 4198a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 41997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // rrx stands alone. 42007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = 0; 42017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (St != ARM_AM::rrx) { 42027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Loc = Parser.getTok().getLoc(); 42037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // A '#' and a shift amount. 42047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const AsmToken &HashTok = Parser.getTok(); 42058a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (HashTok.isNot(AsmToken::Hash) && 42068a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach HashTok.isNot(AsmToken::Dollar)) 42077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(HashTok.getLoc(), "'#' expected"); 42087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat hash token. 42099c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 42107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Expr; 42117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Expr)) 42127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 42137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Range check the immediate. 42147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsl, ror: 0 <= imm <= 31 42157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsr, asr: 0 <= imm <= 32 42167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 42177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 42187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "shift amount must be an immediate"); 42197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Imm = CE->getValue(); 42207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Imm < 0 || 42217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 42227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 42237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "immediate shift value out of range"); 42247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = Imm; 42257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 4226a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4227a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return false; 4228a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4229a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 42309d39036f62674606565217a10db28171b9594bc7Jim Grosbach/// parseFPImm - A floating point immediate expression operand. 42319d39036f62674606565217a10db28171b9594bc7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 42329d39036f62674606565217a10db28171b9594bc7Jim GrosbachparseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 42339d39036f62674606565217a10db28171b9594bc7Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 42349d39036f62674606565217a10db28171b9594bc7Jim Grosbach 42358a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 42368a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) 42379d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_NoMatch; 42380e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 42390e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Disambiguate the VMOV forms that can accept an FP immediate. 42400e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <sreg>, #imm 42410e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f64 <dreg>, #imm 42420e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <dreg>, #imm @ vector f32x2 42430e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <qreg>, #imm @ vector f32x4 42440e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // 42450e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // There are also the NEON VMOV instructions which expect an 42460e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // integer constant. Make sure we don't try to parse an FPImm 42470e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // for these: 42480e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.i{8|16|32|64} <dreg|qreg>, #imm 42490e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 42500e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 42510e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach TyOp->getToken() != ".f64")) 42520e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return MatchOperand_NoMatch; 42530e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 42549d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the '#'. 42559d39036f62674606565217a10db28171b9594bc7Jim Grosbach 42569d39036f62674606565217a10db28171b9594bc7Jim Grosbach // Handle negation, as that still comes through as a separate token. 42579d39036f62674606565217a10db28171b9594bc7Jim Grosbach bool isNegative = false; 42589d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 42599d39036f62674606565217a10db28171b9594bc7Jim Grosbach isNegative = true; 42609d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); 42619d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42629d39036f62674606565217a10db28171b9594bc7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 42639d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Real)) { 42649d39036f62674606565217a10db28171b9594bc7Jim Grosbach APFloat RealVal(APFloat::IEEEdouble, Tok.getString()); 42659d39036f62674606565217a10db28171b9594bc7Jim Grosbach uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 42669d39036f62674606565217a10db28171b9594bc7Jim Grosbach // If we had a '-' in front, toggle the sign bit. 42679d39036f62674606565217a10db28171b9594bc7Jim Grosbach IntVal ^= (uint64_t)isNegative << 63; 42689d39036f62674606565217a10db28171b9594bc7Jim Grosbach int Val = ARM_AM::getFP64Imm(APInt(64, IntVal)); 42699d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 42709d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Val == -1) { 42719d39036f62674606565217a10db28171b9594bc7Jim Grosbach TokError("floating point value out of range"); 42729d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 42739d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42749d39036f62674606565217a10db28171b9594bc7Jim Grosbach Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 42759d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 42769d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42779d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Integer)) { 42789d39036f62674606565217a10db28171b9594bc7Jim Grosbach int64_t Val = Tok.getIntVal(); 42799d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 42809d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Val > 255 || Val < 0) { 42819d39036f62674606565217a10db28171b9594bc7Jim Grosbach TokError("encoded floating point value out of range"); 42829d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 42839d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42849d39036f62674606565217a10db28171b9594bc7Jim Grosbach Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 42859d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 42869d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42879d39036f62674606565217a10db28171b9594bc7Jim Grosbach 42889d39036f62674606565217a10db28171b9594bc7Jim Grosbach TokError("invalid floating point immediate"); 42899d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 42909d39036f62674606565217a10db28171b9594bc7Jim Grosbach} 42919c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Parse a arm instruction operand. For now this parses the operand regardless 42929c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// of the mnemonic. 42931355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4294fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes StringRef Mnemonic) { 4295762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 4296fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4297fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // Check if the current operand has a custom associated parser, if so, try to 4298fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // custom parse the operand, or fallback to the general approach. 4299f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4300f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_Success) 4301fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return false; 4302f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // If there wasn't a custom match, try the generic matcher below. Otherwise, 4303f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // there was a match, but an error occurred, in which case, just return that 4304f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // the operand parsing failed. 4305f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_ParseFail) 4306f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return true; 4307fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4308a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby switch (getLexer().getKind()) { 4309146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling default: 4310146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling Error(Parser.getTok().getLoc(), "unexpected token in operand"); 431150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 431219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach case AsmToken::Identifier: { 43131355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (!tryParseRegisterWithWriteBack(Operands)) 431450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 43150d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int Res = tryParseShiftRegister(Operands); 431619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (Res == 0) // success 43170082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return false; 431819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach else if (Res == -1) // irrecoverable error 431919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return true; 43203cbe43fe69680df772d83947ced97ca445861213Jim Grosbach // If this is VMRS, check for the apsr_nzcv operand. 43215cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { 43225cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach S = Parser.getTok().getLoc(); 43235cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach Parser.Lex(); 43245cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S)); 43255cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach return false; 43265cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach } 4327e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 4328e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Fall though for the Identifier case that is not a register or a 4329e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // special name. 433019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 4331758a519a22b469ce8e2b8d0bf7a72813e87710d4Jim Grosbach case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 433267b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Integer: // things like 1f and 2b as a branch targets 43336284afc293c8f6e84dffab8731aa9e679d437745Jim Grosbach case AsmToken::String: // quoted label names. 433467b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Dot: { // . as a branch target 4335515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // This was not a register so parse other operands that start with an 4336515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // identifier (like labels) as expressions and create them as immediates. 4337515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby const MCExpr *IdVal; 4338762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4339515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getParser().ParseExpression(IdVal)) 434050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 4341762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 434250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 434350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 434450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling } 4345a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby case AsmToken::LBrac: 43461355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseMemory(Operands); 4347d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby case AsmToken::LCurly: 43481355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseRegisterList(Operands); 43498a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach case AsmToken::Dollar: 435063553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson case AsmToken::Hash: { 4351079469f649d8da3923b9f747d7062c84e01cc4aeKevin Enderby // #42 -> immediate. 4352079469f649d8da3923b9f747d7062c84e01cc4aeKevin Enderby // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 4353762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4354b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 435563553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson bool isNegative = Parser.getTok().is(AsmToken::Minus); 4356515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby const MCExpr *ImmVal; 4357515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getParser().ParseExpression(ImmVal)) 435850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 435963553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4360ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach if (CE) { 4361ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach int32_t Val = CE->getValue(); 4362ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach if (isNegative && Val == 0) 4363ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 436463553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 4365762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 436650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 436750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 436863553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 43699081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim case AsmToken::Colon: { 43709081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // ":lower16:" and ":upper16:" expression prefixes 43717597212abced110723f2fee985a7d60557c092ecEvan Cheng // FIXME: Check it's an expression prefix, 43727597212abced110723f2fee985a7d60557c092ecEvan Cheng // e.g. (FOO - :lower16:BAR) isn't legal. 43737597212abced110723f2fee985a7d60557c092ecEvan Cheng ARMMCExpr::VariantKind RefKind; 43741355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parsePrefix(RefKind)) 43759081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 43769081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 43777597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *SubExprVal; 43787597212abced110723f2fee985a7d60557c092ecEvan Cheng if (getParser().ParseExpression(SubExprVal)) 43799081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 43809081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 43817597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 43827597212abced110723f2fee985a7d60557c092ecEvan Cheng getContext()); 43839081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 43847597212abced110723f2fee985a7d60557c092ecEvan Cheng Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 43859081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 43869081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 4387a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 4388a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4389a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 43901355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 43917597212abced110723f2fee985a7d60557c092ecEvan Cheng// :lower16: and :upper16:. 43921355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 43937597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_None; 43949081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 43959081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // :lower16: and :upper16: modifiers 43968a8696db6b6f6e735bb9de630876af83946b45f9Jason W Kim assert(getLexer().is(AsmToken::Colon) && "expected a :"); 43979081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat ':' 43989081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 43999081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Identifier)) { 44009081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 44019081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44029081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44039081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44049081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim StringRef IDVal = Parser.getTok().getIdentifier(); 44059081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (IDVal == "lower16") { 44067597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_LO16; 44079081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else if (IDVal == "upper16") { 44087597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_HI16; 44099081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else { 44109081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 44119081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44129081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44139081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); 44149081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44159081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Colon)) { 44169081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 44179081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44189081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44199081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat the last ':' 44209081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 44219081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim} 44229081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 4423352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// \brief Given a mnemonic, split out possible predication code and carry 4424352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// setting letters to form a canonical mnemonic and flags. 4425352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar// 4426badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar// FIXME: Would be nice to autogen this. 442789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach// FIXME: This is a bit of a maze of special cases. 44281355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachStringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 44295f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach unsigned &PredicationCode, 44305f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach bool &CarrySetting, 443189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned &ProcessorIMod, 443289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask) { 4433352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar PredicationCode = ARMCC::AL; 4434352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = false; 4435a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = 0; 4436352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4437badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Ignore some mnemonics we know aren't predicated forms. 4438352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // 4439352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // FIXME: Would be nice to autogen this. 44405f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach if ((Mnemonic == "movs" && isThumb()) || 44415f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 44425f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 44435f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 44445f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 44455f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 44465f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 44476849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 44486849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "fmuls") 4449352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4450badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 44513f00e317064560ad11168d22030416d853829f6eJim Grosbach // First, split out any predication code. Ignore mnemonics we know aren't 44523f00e317064560ad11168d22030416d853829f6eJim Grosbach // predicated but do have a carry-set and so weren't caught above. 4453ab40f4b737b0a87c4048a9ad2f0c02be735e3770Jim Grosbach if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 445471725a099e6d0cba24a63f9c9063f6efee3bf76eJim Grosbach Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 445504d55f1905748b0d66655e2332e1a232a3f665f4Jim Grosbach Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 44562f25d9b9334662e846460e98a8fe2dae4f233068Jim Grosbach Mnemonic != "sbcs" && Mnemonic != "rscs") { 44573f00e317064560ad11168d22030416d853829f6eJim Grosbach unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 44583f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("eq", ARMCC::EQ) 44593f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ne", ARMCC::NE) 44603f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hs", ARMCC::HS) 44613f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cs", ARMCC::HS) 44623f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lo", ARMCC::LO) 44633f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cc", ARMCC::LO) 44643f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("mi", ARMCC::MI) 44653f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("pl", ARMCC::PL) 44663f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vs", ARMCC::VS) 44673f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vc", ARMCC::VC) 44683f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hi", ARMCC::HI) 44693f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ls", ARMCC::LS) 44703f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ge", ARMCC::GE) 44713f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lt", ARMCC::LT) 44723f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("gt", ARMCC::GT) 44733f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("le", ARMCC::LE) 44743f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("al", ARMCC::AL) 44753f00e317064560ad11168d22030416d853829f6eJim Grosbach .Default(~0U); 44763f00e317064560ad11168d22030416d853829f6eJim Grosbach if (CC != ~0U) { 44773f00e317064560ad11168d22030416d853829f6eJim Grosbach Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 44783f00e317064560ad11168d22030416d853829f6eJim Grosbach PredicationCode = CC; 44793f00e317064560ad11168d22030416d853829f6eJim Grosbach } 448052925b60f1cd4cf810524ca05b00a207a926ab9fBill Wendling } 4481345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 4482352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Next, determine if we have a carry setting bit. We explicitly ignore all 4483352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // the instructions we know end in 's'. 4484352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar if (Mnemonic.endswith("s") && 448500f5d982057574cf65a4a3f29548ff9fb0ecfbd0Jim Grosbach !(Mnemonic == "cps" || Mnemonic == "mls" || 44865f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 44875f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 44885f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 448967ca1adf822c6cbc2f2bb78b8f94eefd099a8eb6Jim Grosbach Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 449048171e7fbe58bb418f09717813779d03903d35e4Jim Grosbach Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 44919c39789c361d4fe2632f28fca74c9ea5fff3dafcJim Grosbach Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 44921aa149f5acea364aa8bc9cfc3a167f78eff2e96bJim Grosbach Mnemonic == "fmuls" || Mnemonic == "fcmps" || 4493e1cf5902ec832cecdd5a94b9701930253d410741Jim Grosbach (Mnemonic == "movs" && isThumb()))) { 4494352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4495352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = true; 4496352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar } 4497352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4498a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // The "cps" instruction can have a interrupt mode operand which is glued into 4499a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // the mnemonic. Check if this is the case, split it and parse the imod op 4500a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (Mnemonic.startswith("cps")) { 4501a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Split out any imod code. 4502a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IMod = 4503a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4504a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("ie", ARM_PROC::IE) 4505a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("id", ARM_PROC::ID) 4506a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Default(~0U); 4507a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IMod != ~0U) { 4508a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4509a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = IMod; 4510a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4511a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4512a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 451389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The "it" instruction has the condition mask on the end of the mnemonic. 451489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic.startswith("it")) { 451589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = Mnemonic.slice(2, Mnemonic.size()); 451689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mnemonic = Mnemonic.slice(0, 2); 451789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 451889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4519352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4520352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar} 45213771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 45223771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// \brief Given a canonical mnemonic, determine if the instruction ever allows 45233771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// inclusion of carry set or predication code operands. 45243771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// 45253771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// FIXME: It would be nice to autogen this. 4526fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopesvoid ARMAsmParser:: 45271355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachgetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4528fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode) { 4529eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4530eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 45313443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach Mnemonic == "add" || Mnemonic == "adc" || 4532eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4533d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "orr" || Mnemonic == "mvn" || 4534eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4535d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 45363443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4537d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "mla" || Mnemonic == "smlal" || 4538d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "umlal" || Mnemonic == "umull"))) { 4539eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = true; 4540fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 4541eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = false; 45423771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 4543eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4544eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4545eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4546eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4547ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4548ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach (Mnemonic == "clrex" && !isThumb()) || 45490780b6303b99441fef04340b7a083006484f4743Jim Grosbach (Mnemonic == "nop" && isThumbOne()) || 45502bd0118472de352745a2e038245fab4974f7c87eJim Grosbach ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 45512bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 45522bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 45534af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 45544af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach !isThumb()) || 45551ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 45563771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = false; 4557fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 45583771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = true; 4559fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes 4560fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach if (isThumb()) { 4561fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 456263b46faeb8acae9b7e5f865b7417dc00b9b9dad3Jim Grosbach Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4563fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes CanAcceptPredicationCode = false; 4564fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } 4565badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar} 4566badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4567d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbachbool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4568d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 456920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // FIXME: This is all horribly hacky. We really need a better way to deal 457020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // with optional operands like this in the matcher table. 4571d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 4572d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4573d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // another does not. Specifically, the MOVW instruction does not. So we 4574d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // special case it here and remove the defaulted (non-setting) cc_out 4575d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // operand if that's the instruction we're trying to match. 4576d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // 4577d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // We do this as post-processing of the explicit operands rather than just 4578d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // conditionally adding the cc_out in the first place because we need 4579d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // to check the type of the parsed immediate operand. 45808adf62034a874adacff158e8adc9438cb3e67c01Owen Anderson if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4581d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4582d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4583d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4584d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return true; 45853912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 45863912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 45873912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // when there are only two register operands. 45883912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 45893912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 45903912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 45913912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 45923912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach return true; 459372f39f8436848885176943b0ba985a7171145423Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 459420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 459520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // have to check the immediate range here since Thumb2 has a variant 459620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // that can handle a different range and has a cc_out operand. 4597f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (((isThumb() && Mnemonic == "add") || 4598f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach (isThumbTwo() && Mnemonic == "sub")) && 4599f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 460072f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 460172f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 460272f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 460320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 460420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach (static_cast<ARMOperand*>(Operands[5])->isReg() || 460520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 460672f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 4607f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // For Thumb2, add/sub immediate does not have a cc_out operand for the 4608f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // imm0_4095 variant. That's the least-preferred variant when 460920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // selecting via the generic "add" mnemonic, so to know that we 461020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // should remove the cc_out operand, we have to explicitly check that 461120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // it's not one of the other variants. Ugh. 4612f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4613f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 461420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 461520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 461620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 461720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Nest conditions rather than one big 'if' statement for readability. 461820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // 461920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If either register is a high reg, it's either one of the SP 462020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // variants (handled above) or a 32-bit encoding, so we just 462120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // check against T3. 462220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 462320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 462420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 462520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 462620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If both registers are low, we're in an IT block, and the immediate is 462720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // in range, we should use encoding T1 instead, which has a cc_out. 462820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (inITBlock() && 462964944f48a1164c02c15ca423a53919682a89074cJim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 463020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 463120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 463220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 463320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 463420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Otherwise, we use encoding T4, which does not have a cc_out 463520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // operand. 463620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return true; 463720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach } 463820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 463964944f48a1164c02c15ca423a53919682a89074cJim Grosbach // The thumb2 multiply instruction doesn't have a CCOut register, so 464064944f48a1164c02c15ca423a53919682a89074cJim Grosbach // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 464164944f48a1164c02c15ca423a53919682a89074cJim Grosbach // use the 16-bit encoding or not. 464264944f48a1164c02c15ca423a53919682a89074cJim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 464364944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 464464944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 464564944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 464664944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->isReg() && 464764944f48a1164c02c15ca423a53919682a89074cJim Grosbach // If the registers aren't low regs, the destination reg isn't the 464864944f48a1164c02c15ca423a53919682a89074cJim Grosbach // same as one of the source regs, or the cc_out operand is zero 464964944f48a1164c02c15ca423a53919682a89074cJim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 465064944f48a1164c02c15ca423a53919682a89074cJim Grosbach // remove the cc_out operand. 465164944f48a1164c02c15ca423a53919682a89074cJim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 465264944f48a1164c02c15ca423a53919682a89074cJim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 46531de0bd194540f8bab399fb39c4ba615a7b2381d3Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 465464944f48a1164c02c15ca423a53919682a89074cJim Grosbach !inITBlock() || 465564944f48a1164c02c15ca423a53919682a89074cJim Grosbach (static_cast<ARMOperand*>(Operands[3])->getReg() != 465664944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->getReg() && 465764944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() != 465864944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg()))) 465964944f48a1164c02c15ca423a53919682a89074cJim Grosbach return true; 466064944f48a1164c02c15ca423a53919682a89074cJim Grosbach 46617f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // Also check the 'mul' syntax variant that doesn't specify an explicit 46627f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // destination register. 46637f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 46647f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 46657f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 46667f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 46677f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // If the registers aren't low regs or the cc_out operand is zero 46687f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 46697f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // remove the cc_out operand. 46707f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 46717f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 46727f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !inITBlock())) 46737f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach return true; 46747f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach 467564944f48a1164c02c15ca423a53919682a89074cJim Grosbach 467620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 4677f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // Register-register 'add/sub' for thumb does not have a cc_out operand 4678f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4679f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4680f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // right, this will result in better diagnostics (which operand is off) 4681f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // anyway. 4682f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4683f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach (Operands.size() == 5 || Operands.size() == 6) && 468472f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 468572f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 468672f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 468772f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 46883912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 4689d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return false; 4690d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach} 4691d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 46927aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool isDataTypeToken(StringRef Tok) { 46937aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 46947aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 46957aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 46967aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 46977aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 46987aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".f" || Tok == ".d"; 46997aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 47007aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 47017aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// FIXME: This bit should probably be handled via an explicit match class 47027aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// in the .td files that matches the suffix instead of having it be 47037aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// a literal string token the way it is now. 47047aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 47057aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 47067aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 47077aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 470821d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbachstatic void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4709badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar/// Parse an arm instruction mnemonic followed by its operands. 4710badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbarbool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4711badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 471221d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // Apply mnemonic aliases before doing anything else, as the destination 471321d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // mnemnonic may include suffices and we want to handle them normally. 471421d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // The generic tblgen'erated code does this later, at the start of 471521d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // MatchInstructionImpl(), but that's too late for aliases that include 471621d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // any sort of suffix. 471721d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach unsigned AvailableFeatures = getAvailableFeatures(); 471821d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach applyMnemonicAliases(Name, AvailableFeatures); 471921d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach 4720a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // First check for the ARM-specific .req directive. 4721a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier) && 4722a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.getTok().getIdentifier() == ".req") { 4723a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach parseDirectiveReq(Name, NameLoc); 4724a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // We always return 'error' for this, as we're done with this 4725a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // statement and don't need to match the 'instruction." 4726a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return true; 4727a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 4728a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 4729badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Create the leading tokens for the mnemonic, split by '.' characters. 4730badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar size_t Start = 0, Next = Name.find('.'); 4731ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach StringRef Mnemonic = Name.slice(Start, Next); 4732badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4733352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Split out the predication code and carry setting flag from the mnemonic. 4734352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar unsigned PredicationCode; 4735a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned ProcessorIMod; 4736352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar bool CarrySetting; 473789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef ITMask; 47381355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 473989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ProcessorIMod, ITMask); 4740badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 47410c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach // In Thumb1, only the branch (B) instruction can be predicated. 47420c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 47430c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach Parser.EatToEndOfStatement(); 47440c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach return Error(NameLoc, "conditional execution not supported in Thumb1"); 47450c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach } 47460c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach 4747ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4748ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 474989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // Handle the IT instruction ITMask. Convert it to a bitmask. This 475089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // is the mask as it will be for the IT encoding if the conditional 475189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 475289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // where the conditional bit0 is zero, the instruction post-processing 475389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // will adjust the mask accordingly. 475489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic == "it") { 4755f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4756f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITMask.size() > 3) { 4757f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Parser.EatToEndOfStatement(); 4758f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "too many conditions on IT instruction"); 4759f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 476089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = 8; 476189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = ITMask.size(); i != 0; --i) { 476289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach char pos = ITMask[i - 1]; 476389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (pos != 't' && pos != 'e') { 476489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.EatToEndOfStatement(); 4765f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 476689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 476789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask >>= 1; 476889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (ITMask[i - 1] == 't') 476989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask |= 8; 477089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 4771f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 477289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 477389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4774ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // FIXME: This is all a pretty gross hack. We should automatically handle 4775ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // optional operands like this via tblgen. 47769717fa9f29696bca45ddfdf206b1c382c8b40b78Bill Wendling 47773771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Next, add the CCOut and ConditionCode operands, if needed. 47783771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // 47793771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // For mnemonics which can ever incorporate a carry setting bit or predication 47803771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // code, our matching model involves us always generating CCOut and 47813771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // ConditionCode operands to match the mnemonic "as written" and then we let 47823771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // the matcher deal with finding the right instruction or generating an 47833771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // appropriate error. 47843771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar bool CanAcceptCarrySet, CanAcceptPredicationCode; 47851355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 47863771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 478733c16a27370939de39679245c3dff72383c210bdJim Grosbach // If we had a carry-set on an instruction that can't do that, issue an 478833c16a27370939de39679245c3dff72383c210bdJim Grosbach // error. 478933c16a27370939de39679245c3dff72383c210bdJim Grosbach if (!CanAcceptCarrySet && CarrySetting) { 479033c16a27370939de39679245c3dff72383c210bdJim Grosbach Parser.EatToEndOfStatement(); 4791ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 479233c16a27370939de39679245c3dff72383c210bdJim Grosbach "' can not set flags, but 's' suffix specified"); 479333c16a27370939de39679245c3dff72383c210bdJim Grosbach } 4794c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // If we had a predication code on an instruction that can't do that, issue an 4795c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // error. 4796c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 4797c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.EatToEndOfStatement(); 4798c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 4799c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach "' is not predicable, but condition code specified"); 4800c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 480133c16a27370939de39679245c3dff72383c210bdJim Grosbach 48023771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the carry setting operand, if necessary. 4803f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (CanAcceptCarrySet) { 4804f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 48053771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 4806f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Loc)); 4807f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 48083771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 48093771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the predication code operand, if necessary. 48103771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar if (CanAcceptPredicationCode) { 4811f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 4812f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CarrySetting); 48133771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCondCode( 4814f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes(PredicationCode), Loc)); 4815badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar } 4816345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 4817a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Add the processor imod operand, if necessary. 4818a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (ProcessorIMod) { 4819a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateImm( 4820a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes MCConstantExpr::Create(ProcessorIMod, getContext()), 4821a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes NameLoc, NameLoc)); 4822a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4823a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 4824345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar // Add the remaining tokens in the mnemonic. 48255747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar while (Next != StringRef::npos) { 48265747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Start = Next; 48275747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Next = Name.find('.', Start + 1); 4828a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef ExtraToken = Name.slice(Start, Next); 4829a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 48307aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // Some NEON instructions have an optional datatype suffix that is 48317aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // completely ignored. Check for that. 48327aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach if (isDataTypeToken(ExtraToken) && 48337aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 48347aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach continue; 48357aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 483681d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach if (ExtraToken != ".n") { 483781d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 483881d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 483981d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach } 48405747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar } 48415747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar 48425747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar // Read the remaining operands. 48435747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar if (getLexer().isNot(AsmToken::EndOfStatement)) { 4844a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Read the first operand. 48451355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 4846cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4847cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 4848cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4849a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4850a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby while (getLexer().is(AsmToken::Comma)) { 4851b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat the comma. 4852a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4853a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Parse and remember the operand. 48541355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 4855cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4856cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 4857cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4858a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 4859a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 486016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 4861cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner if (getLexer().isNot(AsmToken::EndOfStatement)) { 4862186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach SMLoc Loc = getLexer().getLoc(); 4863cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4864186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach return Error(Loc, "unexpected token in argument list"); 4865cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4866146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 486734e53140c2cc02ce4c9d060e48302576d3962e1cChris Lattner Parser.Lex(); // Consume the EndOfStatement 4868ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 4869d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // Some instructions, mostly Thumb, have forms for the same mnemonic that 4870d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // do and don't have a cc_out optional-def operand. With some spot-checks 4871d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // of the operand list, we can figure out which variant we're trying to 487220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // parse and adjust accordingly before actually matching. We shouldn't ever 487320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // try to remove a cc_out operand that was explicitly set on the the 487420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // mnemonic, of course (CarrySetting == true). Reason number #317 the 487520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // table driven matcher doesn't fit well with the ARM instruction set. 487620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 4877ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4878ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.erase(Operands.begin() + 1); 4879ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach delete Op; 4880ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 4881ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 4882cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // ARM mode 'blx' need special handling, as the register operand version 4883cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // is predicable, but the label operand version is not. So, we can't rely 4884cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // on the Mnemonic based checking to correctly figure out when to put 488521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // a k_CondCode operand in the list. If we're trying to match the label 488621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // version, remove the k_CondCode operand here. 4887cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 4888cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach static_cast<ARMOperand*>(Operands[2])->isImm()) { 4889cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4890cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach Operands.erase(Operands.begin() + 1); 4891cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach delete Op; 4892cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach } 4893857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach 4894857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // The vector-compare-to-zero instructions have a literal token "#0" at 4895857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // the end that comes to here as an immediate operand. Convert it to a 4896857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // token to play nicely with the matcher. 4897857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 4898857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 4899857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 4900857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4901857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4902857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if (CE && CE->getValue() == 0) { 4903857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.erase(Operands.begin() + 5); 4904857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 490568259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach delete Op; 490668259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 490768259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 490868259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach // VCMP{E} does the same thing, but with a different operand count. 490968259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 491068259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm()) { 491168259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 491268259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 491368259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if (CE && CE->getValue() == 0) { 491468259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.erase(Operands.begin() + 4); 491568259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4916857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach delete Op; 4917857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 4918857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 4919934755ac040c516eac7fdd974e87590543acd16aJim Grosbach // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 492055b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // end. Convert it to a token here. Take care not to convert those 492155b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // that should hit the Thumb2 encoding. 4922934755ac040c516eac7fdd974e87590543acd16aJim Grosbach if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 492355b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 492455b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 4925934755ac040c516eac7fdd974e87590543acd16aJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 4926934755ac040c516eac7fdd974e87590543acd16aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4927934755ac040c516eac7fdd974e87590543acd16aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 492855b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach if (CE && CE->getValue() == 0 && 492955b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isThumbOne() || 4930d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // The cc_out operand matches the IT block. 4931d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach ((inITBlock() != CarrySetting) && 4932d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // Neither register operand is a high register. 493355b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4934d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 4935934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.erase(Operands.begin() + 5); 4936934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4937934755ac040c516eac7fdd974e87590543acd16aJim Grosbach delete Op; 4938934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 4939934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 4940934755ac040c516eac7fdd974e87590543acd16aJim Grosbach 49419898671a74d3fc924347e679c45edaa685b3fe6eChris Lattner return false; 4942ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 4943ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 4944189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// Validate context-sensitive operand constraints. 4945aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 4946aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// return 'true' if register list contains non-low GPR registers, 4947aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'false' otherwise. If Reg is in the register list or is HiReg, set 4948aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'containsReg' to true. 4949aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbachstatic bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 4950aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned HiReg, bool &containsReg) { 4951aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = false; 4952aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 4953aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 4954aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (OpReg == Reg) 4955aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = true; 4956aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach // Anything other than a low register isn't legal here. 4957aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 4958aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return true; 4959aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach } 4960aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return false; 4961aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach} 4962aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 496376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// Check if the specified regisgter is in the register list of the inst, 496476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// starting at the indicated operand number. 496576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbachstatic bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 496676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 496776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 496876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (OpReg == Reg) 496976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return true; 497076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 497176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return false; 497276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach} 497376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach 4974f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 4975f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// the ARMInsts array) instead. Getting that here requires awkward 4976f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// API changes, though. Better way? 4977f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbachnamespace llvm { 49781a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerextern const MCInstrDesc ARMInsts[]; 4979f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 49801a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerstatic const MCInstrDesc &getInstDesc(unsigned Opcode) { 4981f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return ARMInsts[Opcode]; 4982f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 4983f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 4984189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// FIXME: We would really like to be able to tablegen'erate this. 4985189610f9466686a91fb7d847b572e1645c785323Jim Grosbachbool ARMAsmParser:: 4986189610f9466686a91fb7d847b572e1645c785323Jim GrosbachvalidateInstruction(MCInst &Inst, 4987189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 49881a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 4989f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = Operands[0]->getStartLoc(); 4990f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Check the IT block state first. 4991b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // NOTE: In Thumb mode, the BKPT instruction has the interesting property of 4992b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // being allowed in IT blocks, but not being predicable. It just always 4993b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // executes. 4994b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { 4995f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned bit = 1; 4996f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITState.FirstCond) 4997f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = false; 4998f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach else 4999a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5000f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // The instruction must be predicable. 5001f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (!MCID.isPredicable()) 5002f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "instructions in IT block must be predicable"); 5003f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5004f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned ITCond = bit ? ITState.Cond : 5005f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::getOppositeCondition(ITState.Cond); 5006f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (Cond != ITCond) { 5007f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Find the condition code Operand to get its SMLoc information. 5008f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc CondLoc; 5009f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach for (unsigned i = 1; i < Operands.size(); ++i) 5010f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5011f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CondLoc = Operands[i]->getStartLoc(); 5012f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(CondLoc, "incorrect condition in IT block; got '" + 5013f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5014f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach "', but expected '" + 5015f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5016f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 5017c9a9b442853ee086492d6ad1384a2de2fea9b43bJim Grosbach // Check for non-'al' condition codes outside of the IT block. 5018f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } else if (isThumbTwo() && MCID.isPredicable() && 5019f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 502051f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson ARMCC::AL && Inst.getOpcode() != ARM::tB && 502151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.getOpcode() != ARM::t2B) 5022f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "predicated instructions must be in IT block"); 5023f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 5024189610f9466686a91fb7d847b572e1645c785323Jim Grosbach switch (Inst.getOpcode()) { 50252fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD: 50262fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_PRE: 50272fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_POST: 5028189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::LDREXD: { 5029189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5030189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5031189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5032189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 5033189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return Error(Operands[3]->getStartLoc(), 5034189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "destination operands must be sequential"); 5035189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5036189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 503714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach case ARM::STRD: { 503814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt2 must be Rt + 1. 503914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 504014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 504114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach if (Rt2 != Rt + 1) 504214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 504314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach "source operands must be sequential"); 504414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return false; 504514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach } 504653642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_PRE: 504753642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_POST: 5048189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::STREXD: { 5049189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5050189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5051189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 5052189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 505314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 5054189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "source operands must be sequential"); 5055189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5056189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5057fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::SBFX: 5058fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::UBFX: { 5059fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach // width must be in range [1, 32-lsb] 5060fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned lsb = Inst.getOperand(2).getImm(); 5061fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned widthm1 = Inst.getOperand(3).getImm(); 5062fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach if (widthm1 >= 32 - lsb) 5063fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach return Error(Operands[5]->getStartLoc(), 5064fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach "bitfield width must be in range [1,32-lsb]"); 506500c9a518886c4f2d1cd869c174c994c20a353906Jim Grosbach return false; 5066fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach } 506793b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach case ARM::tLDMIA: { 506876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're parsing Thumb2, the .w variant is available and handles 506976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // most cases that are normally illegal for a Thumb1 LDM 507076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instruction. We'll make the transformation in processInstruction() 507176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // if necessary. 507276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 507393b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // Thumb LDM instructions are writeback iff the base register is not 507493b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // in the register list. 507593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 50767260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach bool hasWritebackToken = 50777260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 50787260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5079aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 508076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5081aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5082aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7"); 508393b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // If we should have writeback, then there should be a '!' token. 508476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 508593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach return Error(Operands[2]->getStartLoc(), 508693b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach "writeback operator '!' expected"); 508776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we should not have writeback, there must not be a '!'. This is 508876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // true even for the 32-bit wide encodings. 5089aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (listContainsBase && hasWritebackToken) 50907260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach return Error(Operands[3]->getStartLoc(), 50917260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "writeback operator '!' not allowed when base register " 50927260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "in register list"); 509393b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach 509493b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach break; 509593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach } 509676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::t2LDMIA_UPD: { 509776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 509876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return Error(Operands[4]->getStartLoc(), 509976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "writeback operator '!' not allowed when base register " 510076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "in register list"); 510176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 510276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 51035402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 51045402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // so only issue a diagnostic for thumb1. The instructions will be 51055402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // switched to the t2 encodings in processInstruction() if necessary. 51066dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPOP: { 5107aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 51085402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 51095402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5110aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5111aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or pc"); 51126dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 51136dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 51146dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPUSH: { 5115aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 51165402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 51175402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5118aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5119aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or lr"); 51206dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 51216dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 51221e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach case ARM::tSTMIA_UPD: { 51231e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach bool listContainsBase; 51248213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 51251e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach return Error(Operands[4]->getStartLoc(), 51261e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach "registers must be in range r0-r7"); 51271e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach break; 51281e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach } 5129189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5130189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 5131189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5132189610f9466686a91fb7d847b572e1645c785323Jim Grosbach} 5133189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 51345b484312c66f8d125c072517947538f301c5a805Jim Grosbachstatic unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) { 513584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach switch(Opc) { 513684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach default: assert(0 && "unexpected opcode!"); 51379b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST1LN 51389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8: 51399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8: 51409b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_U8: 51415b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8_UPD; 51439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16: 51449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16: 51459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_U16: 51465b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16_UPD; 51489b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F: 51499b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32: 51509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: 51515b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51529b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32_UPD; 51539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8: 51549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8: 51559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_U8: 51565b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8_UPD; 51589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16: 51599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16: 51609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_U16: 51615b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16_UPD; 51639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F: 51649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32: 51659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: 51665b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32_UPD; 51689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: 51699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8: 51709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_U8: 51715b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8; 51739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16: 51749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16: 51759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_U16: 51765b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16; 51789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F: 51799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: 51809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32: 51815b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32; 51839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 51849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST2LN 51859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: 51869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: 51879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_U8: 51885b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8_UPD; 51909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16: 51919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16: 51929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_U16: 51935b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16_UPD; 51959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: 51969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: 51979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: 51985b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51999b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32_UPD; 52005b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: 52015b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: 52025b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_U16: 52035b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52045b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16_UPD; 52055b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F: 52065b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32: 52075b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32: 52085b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52095b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32_UPD; 52105b484312c66f8d125c072517947538f301c5a805Jim Grosbach 52119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: 52129b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: 52139b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_U8: 52145b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52159b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8_UPD; 52169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16: 52179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16: 52189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_U16: 52195b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52209b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16_UPD; 52219b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: 52229b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: 52239b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: 52245b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52259b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32_UPD; 52265b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: 52275b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: 52285b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_U16: 52295b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52305b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16_UPD; 52315b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F: 52325b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32: 52335b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32: 52345b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52355b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32_UPD; 52365b484312c66f8d125c072517947538f301c5a805Jim Grosbach 52379b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: 52389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8: 52399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_U8: 52405b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8; 52429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16: 52439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: 52449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_U16: 52455b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16; 52479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: 52489b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: 52499b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32: 52505b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32; 52525b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: 52535b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: 52545b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_U16: 52555b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52565b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16; 52575b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: 52585b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32: 52595b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32: 52605b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52615b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32; 526284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 526384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach} 526484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach 526595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbachstatic unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) { 52667636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach switch(Opc) { 52677636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach default: assert(0 && "unexpected opcode!"); 52689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD1LN 52699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8: 52709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8: 52719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_U8: 527295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8_UPD; 52749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16: 52759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16: 52769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_U16: 527795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16_UPD; 52799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F: 52809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32: 52819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: 528295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32_UPD; 52849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8: 52859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8: 52869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_U8: 528795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8_UPD; 52899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16: 52909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16: 52919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_U16: 529295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52939b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16_UPD; 52949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F: 52959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32: 52969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: 529795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 52989b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32_UPD; 52999b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: 53009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8: 53019b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_U8: 530295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8; 53049b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16: 53059b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: 53069b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_U16: 530795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53089b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16; 53099b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: 53109b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: 53119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32: 531295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53139b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32; 53149b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 53159b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD2LN 53169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: 53179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: 53189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_U8: 531995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53209b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8_UPD; 53219b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16: 53229b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16: 53239b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_U16: 532495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53259b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16_UPD; 53269b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: 53279b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: 53289b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: 532995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32_UPD; 533195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: 533295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: 533395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_U16: 533495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 533595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16_UPD; 533695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F: 533795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32: 533895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: 533995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 534095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32_UPD; 53419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: 53429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: 53439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_U8: 534495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8_UPD; 53469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16: 53479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16: 53489b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_U16: 534995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16_UPD; 53519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: 53529b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: 53539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: 535495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32_UPD; 535695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: 535795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: 535895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_U16: 535995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 536095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16_UPD; 536195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F: 536295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32: 536395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: 536495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 536595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32_UPD; 53669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: 53679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8: 53689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_U8: 536995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8; 53719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16: 53729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: 53739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_U16: 537495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16; 53769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: 53779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: 53789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32: 537995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32; 538195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: 538295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: 538395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_U16: 538495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 538595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16; 538695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: 538795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32: 538895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32: 538995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 539095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32; 53917636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 53927636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach} 53937636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 539483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbachbool ARMAsmParser:: 5395f8fce711e8b756adca63044f7d122648c960ab96Jim GrosbachprocessInstruction(MCInst &Inst, 5396f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5397f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach switch (Inst.getOpcode()) { 53989b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VST complex aliases. 53999b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8: 54009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8: 54019b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_U8: case ARM::VST1LNdWB_register_Asm_16: 54029b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_P16: case ARM::VST1LNdWB_register_Asm_I16: 54039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_S16: case ARM::VST1LNdWB_register_Asm_U16: 54049b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F: 54059b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32: 54069b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: { 540784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 540884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 540984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 54105b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 54115b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 541284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 541384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 541484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 541584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 541684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 541784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 541884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 541984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 542084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 542184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 542284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 54239b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 54245b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8: 54255b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8: 54265b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16: 54279b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16: 54289b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16: 54295b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F: 54309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32: 54315b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: 54325b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16: 54335b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16: 54345b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32: 54355b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32: 54365b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32: 54375b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_register_Asm_U32: { 54389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 54399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 54409b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 54415b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 54425b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 54439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 54449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 54459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 54469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 54479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 54485b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 54495b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 54509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 54519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 54529b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 54539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 54549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 54559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 54569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8: 54579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8: 54589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_U8: case ARM::VST1LNdWB_fixed_Asm_16: 54599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_P16: case ARM::VST1LNdWB_fixed_Asm_I16: 54609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_S16: case ARM::VST1LNdWB_fixed_Asm_U16: 54619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F: 54629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32: 54639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: { 546484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 546584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 546684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 54675b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 54685b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 546984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 547084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 547184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 547284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 547384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 547484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 547584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 547684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 547784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 547884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 547984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 54809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 54815b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8: 54825b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8: 54835b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16: 54849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16: 54859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16: 54865b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F: 54879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32: 54885b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: 54895b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16: 54905b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16: 54915b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32: 54925b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32: 54935b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32: 54945b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_U32: { 54959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 54969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 54979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 54985b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 54995b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 55009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 55019b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 55029b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 55039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 55049b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 55055b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 55065b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 55079b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 55089b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 55099b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 55109b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 55119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 55129b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 55139b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: case ARM::VST1LNdAsm_I8: 55149b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_S8: case ARM::VST1LNdAsm_U8: case ARM::VST1LNdAsm_16: 55159b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_P16: case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16: 55169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_U16: case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F: 55179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: case ARM::VST1LNdAsm_S32: 551884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach case ARM::VST1LNdAsm_U32: { 551984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 552084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 552184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 55225b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 55235b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 552484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 552584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 552684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 552784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 552884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 552984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 553084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 553184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 553284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 55339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 55345b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8: 55355b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16: 55369b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16: 55375b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F: 55389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32: 55395b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16: 55405b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16: 55415b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32: 55425b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{ 55439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 55449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 55459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 55465b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 55475b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); 55489b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 55499b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 55509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 55515b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 55525b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 55539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 55549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 55559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 55569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 55579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 55589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 55599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VLD complex aliases. 55609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8: 55619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8: 55629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_U8: case ARM::VLD1LNdWB_register_Asm_16: 55639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_P16: case ARM::VLD1LNdWB_register_Asm_I16: 55649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_S16: case ARM::VLD1LNdWB_register_Asm_U16: 55659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F: 55669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32: 55679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: { 5568872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 5569872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 5570872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 557195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 557295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 5573872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5574872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5575872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 5576872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 5577872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 5578872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5579872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 5580872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5581872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 5582872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 5583872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 5584872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 55859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 558695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8: 558795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8: 558895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16: 55899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16: 55909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16: 559195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F: 55929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32: 559395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32: 55945b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16: 55955b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16: 55965b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32: 55975b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32: 55985b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32: 55995b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_register_Asm_U32: { 56009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 56019b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56029b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 560395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 560495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 56059b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 560695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 560795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56089b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 56099b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56109b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 56119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 56129b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 561395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 561495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56159b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 56169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 56179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 56189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 56199b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 56209b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 56219b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 56229b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8: 56239b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8: 56249b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_U8: case ARM::VLD1LNdWB_fixed_Asm_16: 56259b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_P16: case ARM::VLD1LNdWB_fixed_Asm_I16: 56269b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_S16: case ARM::VLD1LNdWB_fixed_Asm_U16: 56279b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F: 56289b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32: 56299b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: { 5630872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 5631872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 5632872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 563395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 563495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 5635872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5636872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5637872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 5638872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 5639872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5640872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5641872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 5642872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5643872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 5644872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 5645872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 5646872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 56479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 564895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8: 564995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8: 565095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16: 56519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16: 56529b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16: 565395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F: 56549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32: 565595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32: 56565b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16: 56575b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16: 56585b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32: 56595b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32: 56605b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32: 56615b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_U32: { 56629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 56639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 566595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 566695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 56679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 566895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 566995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 56719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 56739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 56749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 567595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 567695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 56789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 56799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 56809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 56819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 56829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 56839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 56845b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8: 56855b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16: 56869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16: 56875b484312c66f8d125c072517947538f301c5a805Jim Grosbach case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F: 56889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32: 5689dad2f8e7fb2df5fb080a38fa4c33a01f19729f15Jim Grosbach case ARM::VLD1LNdAsm_U32: { 56907636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach MCInst TmpInst; 56917636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56927636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // right place. 569395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 569495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 56957636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 56967636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56977636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 56987636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 56997636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57007636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57017636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57027636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst = TmpInst; 57037636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return true; 57047636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 57059b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 570695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8: 570795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16: 57089b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16: 570995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F: 57109b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32: 571195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16: 571295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16: 571395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32: 571495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32: 571595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach case ARM::VLD2LNqAsm_U32: { 57169b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 57179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 57189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 571995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 572095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); 57219b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 572295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 572395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57249b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57259b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57269b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 572795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 572895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57299b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57319b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57329b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 57339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 57349b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 5735863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the Thumb2 mode MOV complex aliases. 57362cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVsr: 57372cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVSsr: { 57382cc5cda464e7c936215281934193658cb799c603Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 57392cc5cda464e7c936215281934193658cb799c603Jim Grosbach // whether we're in an IT block if the register operands are low 57402cc5cda464e7c936215281934193658cb799c603Jim Grosbach // registers. 57412cc5cda464e7c936215281934193658cb799c603Jim Grosbach bool isNarrow = false; 57422cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 57432cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 57442cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg()) && 57452cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 57462cc5cda464e7c936215281934193658cb799c603Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 57472cc5cda464e7c936215281934193658cb799c603Jim Grosbach isNarrow = true; 57482cc5cda464e7c936215281934193658cb799c603Jim Grosbach MCInst TmpInst; 57492cc5cda464e7c936215281934193658cb799c603Jim Grosbach unsigned newOpc; 57502cc5cda464e7c936215281934193658cb799c603Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 57512cc5cda464e7c936215281934193658cb799c603Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 57522cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 57532cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 57542cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 57552cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 57562cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 57572cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.setOpcode(newOpc); 57582cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 57592cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isNarrow) 57602cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 57612cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 57622cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 57632cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 57642cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57652cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57662cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (!isNarrow) 57672cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 57682cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 57692cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst = TmpInst; 57702cc5cda464e7c936215281934193658cb799c603Jim Grosbach return true; 57712cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 5772863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVsi: 5773863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVSsi: { 5774863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 5775863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // whether we're in an IT block if the register operands are low 5776863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // registers. 5777863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach bool isNarrow = false; 5778863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 5779863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 5780863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 5781863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isNarrow = true; 5782863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach MCInst TmpInst; 5783863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach unsigned newOpc; 5784863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 5785863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 5786863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 5787863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 5788863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 5789863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 5790520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 5791863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 5792863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 5793863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (Ammount == 32) Ammount = 0; 5794863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.setOpcode(newOpc); 5795863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 5796863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isNarrow) 5797863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 5798863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 5799863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5800520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach if (newOpc != ARM::t2RRX) 5801520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Ammount)); 5802863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5803863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 5804863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (!isNarrow) 5805863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 5806863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 5807863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst = TmpInst; 5808863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach return true; 5809863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 5810863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the ARM mode MOV complex aliases. 581123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: 581223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: 581323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: 581423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: { 581523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 581623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach switch(Inst.getOpcode()) { 581723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 581823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 581923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 582023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 582123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: ShiftTy = ARM_AM::ror; break; 582223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 582323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 582423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach MCInst TmpInst; 582523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.setOpcode(ARM::MOVsr); 582623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 582723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 582823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 582923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 583023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 583123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 583223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 583323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach Inst = TmpInst; 583423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach return true; 583523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 5836ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: 5837ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: 5838ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: 5839ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: { 5840ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 5841ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach switch(Inst.getOpcode()) { 5842ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 5843ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 5844ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 5845ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 5846ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: ShiftTy = ARM_AM::ror; break; 5847ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 5848ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach // A shift by zero is a plain MOVr, not a MOVsi. 584948b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Amt = Inst.getOperand(2).getImm(); 5850ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 5851ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 585271810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach MCInst TmpInst; 5853ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.setOpcode(Opc); 585471810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 585571810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5856ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (Opc == ARM::MOVsi) 5857ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 585871810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 585971810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 586071810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 586171810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach Inst = TmpInst; 586283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 586371810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach } 586448b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach case ARM::RRXi: { 586548b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 586648b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach MCInst TmpInst; 586748b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.setOpcode(ARM::MOVsi); 586848b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 586948b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 587048b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 587148b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 587248b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 587348b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // cc_out 587448b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach Inst = TmpInst; 587548b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach return true; 587648b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach } 58770352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2LDMIA_UPD: { 58780352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a load of a single register, then we should use 58790352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 58800352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 58810352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 58820352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 58830352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2LDR_POST); 58840352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 58850352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 58860352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 58870352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 58880352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 58890352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 58900352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 58910352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 58920352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 58930352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2STMDB_UPD: { 58940352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a store of a single register, then we should use 58950352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 58960352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 58970352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 58980352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 58990352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2STR_PRE); 59000352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 59010352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 59020352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 59030352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 59040352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 59050352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 59060352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 59070352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 59080352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 5909f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach case ARM::LDMIA_UPD: 5910f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // If this is a load of a single register via a 'pop', then we should use 5911f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 5912f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 5913f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst.getNumOperands() == 5) { 5914f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach MCInst TmpInst; 5915f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.setOpcode(ARM::LDR_POST_IMM); 5916f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 5917f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5918f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5919f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 5920f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 5921f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5922f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 5923f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst = TmpInst; 592483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 5925f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 5926f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach break; 5927f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach case ARM::STMDB_UPD: 5928f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // If this is a store of a single register via a 'push', then we should use 5929f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 5930f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 5931f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst.getNumOperands() == 5) { 5932f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach MCInst TmpInst; 5933f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.setOpcode(ARM::STR_PRE_IMM); 5934f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5935f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 5936f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 5937f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 5938f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5939f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 5940f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst = TmpInst; 5941f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach } 5942f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach break; 5943da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2ADDri12: 5944da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 5945da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "addw"), encoding T3 is preferred. 5946da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 5947da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 5948da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 5949da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2ADDri); 5950da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 5951da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 5952da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2SUBri12: 5953da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 5954da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "subw"), encoding T3 is preferred. 5955da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 5956da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 5957da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 5958da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2SUBri); 5959da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 5960da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 596189e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach case ARM::tADDi8: 59620f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 59630f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 59640f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 59650f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T1 if <Rd> is omitted." 596683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 596789e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach Inst.setOpcode(ARM::tADDi3); 596883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 596983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 597089e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach break; 5971f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach case ARM::tSUBi8: 5972f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 5973f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 5974f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 5975f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T1 if <Rd> is omitted." 597683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 5977f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Inst.setOpcode(ARM::tSUBi3); 597883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 597983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 5980f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach break; 5981927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach case ARM::t2ADDrr: { 5982927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // If the destination and first source operand are the same, and 5983927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // there's no setting of the flags, use encoding T2 instead of T3. 5984927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // Note that this is only for ADD, not SUB. This mirrors the system 5985927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // 'as' behaviour. Make sure the wide encoding wasn't explicit. 5986927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 5987927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst.getOperand(5).getReg() != 0 || 5988713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 5989713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 5990927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach break; 5991927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach MCInst TmpInst; 5992927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.setOpcode(ARM::tADDhirr); 5993927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 5994927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 5995927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 5996927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 5997927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 5998927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst = TmpInst; 5999927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach return true; 6000927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach } 600151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::tB: 600251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb conditional branch outside of an IT block is a tBcc. 600383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 600451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::tBcc); 600583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 600683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 600751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 600851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::t2B: 600951f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 601083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 601151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::t2Bcc); 601283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 601383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 601451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 6015c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach case ARM::t2Bcc: 6016a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // If the conditional is AL or we're in an IT block, we really want t2B. 601783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 6018c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach Inst.setOpcode(ARM::t2B); 601983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 602083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 6021c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach break; 6022395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach case ARM::tBcc: 6023395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach // If the conditional is AL, we really want tB. 602483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL) { 6025395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach Inst.setOpcode(ARM::tB); 602683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 602783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 60283ce23d3d87d1ca437acb65ac01fac1c486507280Jim Grosbach break; 602976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::tLDMIA: { 603076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If the register list contains any high registers, or if the writeback 603176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 603276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instead if we're in Thumb2. Otherwise, this should have generated 603376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // an error in validateInstruction(). 603476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 603576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool hasWritebackToken = 603676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 603776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 603876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool listContainsBase; 603976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 604076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (!listContainsBase && !hasWritebackToken) || 604176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (listContainsBase && hasWritebackToken)) { 604276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 604376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach assert (isThumbTwo()); 604476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 604576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're switching to the updating version, we need to insert 604676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // the writeback tied operand. 604776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (hasWritebackToken) 604876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.insert(Inst.begin(), 604976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach MCOperand::CreateReg(Inst.getOperand(0).getReg())); 605083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 605176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 605276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 605376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 60548213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach case ARM::tSTMIA_UPD: { 60558213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // If the register list contains any high registers, we need to use 60568213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 60578213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // should have generated an error in validateInstruction(). 60588213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 60598213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach bool listContainsBase; 60608213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 60618213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 60628213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach assert (isThumbTwo()); 60638213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach Inst.setOpcode(ARM::t2STMIA_UPD); 606483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 60658213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 60668213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach break; 60678213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 60685402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPOP: { 60695402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 60705402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // If the register list contains any high registers, we need to use 60715402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 60725402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // should have generated an error in validateInstruction(). 60735402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 607483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 60755402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 60765402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2LDMIA_UPD); 60775402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 60785402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 60795402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 608083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 60815402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 60825402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPUSH: { 60835402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 60845402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 608583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 60865402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 60875402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2STMDB_UPD); 60885402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 60895402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 60905402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 609183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 60925402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 60931ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVi: { 60941ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 60951ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 60961ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 60971ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(1).getImm() <= 255 && 6098c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 6099c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR) || 6100c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 61011ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 61021ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 61031ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't in the same order for tMOVi8... 61041ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 61051ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(ARM::tMOVi8); 61061ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 61071ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 61081ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 61091ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 61101ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 61111ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 611283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 61131ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 61141ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 61151ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 61161ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVr: { 61171ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 61181ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 61191ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 61201ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 61211ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(2).getImm() == ARMCC::AL && 61221ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR && 61231ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 61241ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 61251ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't the same for tMOV[S]r... (no cc_out) 61261ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 61271ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 61281ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 61291ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 61301ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 61311ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 61321ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 613383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 61341ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 61351ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 61361ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 6137326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach case ARM::t2SXTH: 613850f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: 613950f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: 614050f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: { 6141326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 6142326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // request the 32-bit variant, transform it here. 6143326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6144326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6145326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst.getOperand(2).getImm() == 0 && 6146326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 6147326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 614850f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach unsigned NewOpc; 614950f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach switch (Inst.getOpcode()) { 615050f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach default: llvm_unreachable("Illegal opcode!"); 615150f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 615250f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 615350f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 615450f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 615550f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach } 6156326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // The operands aren't the same for thumb1 (no rotate operand). 6157326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach MCInst TmpInst; 6158326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.setOpcode(NewOpc); 6159326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6160326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 6161326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6162326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6163326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst = TmpInst; 616483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 6165326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 6166326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach break; 6167326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 616804b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach case ARM::MOVsi: { 616904b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 617004b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach if (SOpc == ARM_AM::rrx) return false; 617104b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 617204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach // Shifting by zero is accepted as a vanilla 'MOVr' 617304b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach MCInst TmpInst; 617404b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.setOpcode(ARM::MOVr); 617504b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 617604b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 617704b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 617804b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 617904b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 618004b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach Inst = TmpInst; 618104b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return true; 618204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 618304b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return false; 618404b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 61858d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: 61868d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: 61878d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: 61888d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: 61898d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: 61908d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: { 61918d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach unsigned newOpc; 61928d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 61938d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (SOpc == ARM_AM::rrx) return false; 61948d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach switch (Inst.getOpcode()) { 619519055cc2712223f6834fc3cf5b547803ba83f066Matt Beaumont-Gay default: assert(0 && "unexpected opcode!"); 61968d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 61978d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 61988d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: newOpc = ARM::EORrr; break; 61998d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: newOpc = ARM::BICrr; break; 62008d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 62018d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 62028d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 62038d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach // If the shift is by zero, use the non-shifted instruction definition. 62048d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) { 62058d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach MCInst TmpInst; 62068d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.setOpcode(newOpc); 62078d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 62088d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 62098d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 62108d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 62118d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 62128d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 62138d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach Inst = TmpInst; 62148d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return true; 62158d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 62168d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return false; 62178d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 621889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach case ARM::t2IT: { 621989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The mask bits for all but the first condition are represented as 622089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // the low bit of the condition code value implies 't'. We currently 622189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // always have 1 implies 't', so XOR toggle the bits if the low bit 622289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // of the condition code is zero. The encoding also expects the low 622389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // bit of the condition to be encoded as bit 4 of the mask operand, 622489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // so mask that in if needed 622589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MCOperand &MO = Inst.getOperand(1); 622689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = MO.getImm(); 6227f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned OrigMask = Mask; 6228f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned TZ = CountTrailingZeros_32(Mask); 622989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if ((Inst.getOperand(0).getImm() & 1) == 0) { 623089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(Mask && TZ <= 3 && "illegal IT mask value!"); 623189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = 3; i != TZ; --i) 623289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask ^= 1 << i; 623389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } else 623489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask |= 0x10; 623589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MO.setImm(Mask); 6236f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 6237f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Set up the IT block state according to the IT instruction we just 6238f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // matched. 6239f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach assert(!inITBlock() && "nested IT blocks?!"); 6240f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 6241f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Mask = OrigMask; // Use the original mask, not the updated one. 6242f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = 0; 6243f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = true; 624489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 624589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 6246f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 624783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 6248f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach} 6249f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 625047a0d52b69056250a1edaca8b28f705993094542Jim Grosbachunsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 625147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // 16-bit thumb arithmetic instructions either require or preclude the 'S' 625247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // suffix depending on whether they're in an IT block or not. 6253194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach unsigned Opc = Inst.getOpcode(); 62541a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Opc); 625547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 625647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.hasOptionalDef() && 625747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "optionally flag setting instruction missing optional def operand"); 625847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.NumOperands == Inst.getNumOperands() && 625947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "operand count mismatch!"); 626047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // Find the optional-def operand (cc_out). 626147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned OpNo; 626247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach for (OpNo = 0; 626347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 626447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ++OpNo) 626547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ; 626647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb1, reject it completely. 626747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 626847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_MnemonicFail; 626947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb2, which form is legal depends on whether we're 627047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // in an IT block. 6271f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 6272f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach !inITBlock()) 627347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_RequiresITBlock; 6274f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 6275f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach inITBlock()) 6276f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Match_RequiresNotITBlock; 627747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 6278194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Some high-register supporting Thumb1 encodings only allow both registers 6279194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // to be from r0-r7 when in Thumb2. 6280194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach else if (Opc == ARM::tADDhirr && isThumbOne() && 6281194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6282194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg())) 6283194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresThumb2; 6284194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Others only require ARMv6 or later. 62854ec6e888ec6d12b5255afd685b05c8fee1f7fc73Jim Grosbach else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 6286194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(0).getReg()) && 6287194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg())) 6288194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresV6; 628947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_Success; 629047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach} 629147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 6292fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattnerbool ARMAsmParser:: 6293fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris LattnerMatchAndEmitInstruction(SMLoc IDLoc, 6294fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner SmallVectorImpl<MCParsedAsmOperand*> &Operands, 6295fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCStreamer &Out) { 6296fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCInst Inst; 6297fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner unsigned ErrorInfo; 629819cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach unsigned MatchResult; 6299193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 6300193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby switch (MatchResult) { 630119cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach default: break; 6302e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_Success: 6303189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Context sensitive operand constraints aren't handled by the matcher, 6304189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // so check them here. 6305a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (validateInstruction(Inst, Operands)) { 6306a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Still progress the IT block, otherwise one wrong condition causes 6307a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // nasty cascading errors. 6308a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 6309189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return true; 6310a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 6311189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 6312f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // Some instructions need post-processing to, for example, tweak which 631383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // encoding is selected. Loop on it while changes happen so the 631483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // individual transformations can chain off each other. E.g., 631583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 631683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach while (processInstruction(Inst, Operands)) 631783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach ; 6318f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 6319a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Only move forward at the very end so that everything in validate 6320a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // and process gets a consistent answer about whether we're in an IT 6321a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // block. 6322a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 6323a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach 6324fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner Out.EmitInstruction(Inst); 6325fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner return false; 6326e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_MissingFeature: 6327e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 6328e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return true; 6329e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_InvalidOperand: { 6330e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner SMLoc ErrorLoc = IDLoc; 6331e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo != ~0U) { 6332e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo >= Operands.size()) 6333e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(IDLoc, "too few operands for instruction"); 633416c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6335e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 6336e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 6337e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 633816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6339e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(ErrorLoc, "invalid operand for instruction"); 6340e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 6341e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_MnemonicFail: 634247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Error(IDLoc, "invalid instruction"); 6343b412915ff6229b3e2dffedcfb0f3fb7e85259841Daniel Dunbar case Match_ConversionFail: 634488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // The converter function will have already emited a diagnostic. 634588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 6346f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach case Match_RequiresNotITBlock: 6347f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(IDLoc, "flag setting instruction only valid outside IT block"); 634847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach case Match_RequiresITBlock: 634947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Error(IDLoc, "instruction only valid inside IT block"); 6350194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresV6: 6351194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires ARMv6 or later"); 6352194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresThumb2: 6353194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires Thumb2"); 6354fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner } 635516c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6356c223e2b10b4753a63dfe7e6980c650b179139983Eric Christopher llvm_unreachable("Implement any new match types added!"); 6357146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling return true; 6358fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner} 6359fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner 63601355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirective parses the arm specific directives 6361ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbybool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 6362ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby StringRef IDVal = DirectiveID.getIdentifier(); 6363ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (IDVal == ".word") 63641355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveWord(4, DirectiveID.getLoc()); 6365515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb") 63661355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumb(DirectiveID.getLoc()); 63679a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach else if (IDVal == ".arm") 63689a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return parseDirectiveARM(DirectiveID.getLoc()); 6369515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb_func") 63701355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumbFunc(DirectiveID.getLoc()); 6371515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".code") 63721355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveCode(DirectiveID.getLoc()); 6373515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".syntax") 63741355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveSyntax(DirectiveID.getLoc()); 6375a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach else if (IDVal == ".unreq") 6376a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return parseDirectiveUnreq(DirectiveID.getLoc()); 6377d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".arch") 6378d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveArch(DirectiveID.getLoc()); 6379d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".eabi_attribute") 6380d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveEabiAttr(DirectiveID.getLoc()); 6381ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 6382ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 6383ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 63841355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveWord 6385ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby/// ::= .word [ expression (, expression)* ] 63861355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 6387ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) { 6388ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby for (;;) { 6389ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby const MCExpr *Value; 6390ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getParser().ParseExpression(Value)) 6391ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 6392ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6393aaec205b87637cd0d59d4f11630db603686eb73dChris Lattner getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 6394ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6395ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().is(AsmToken::EndOfStatement)) 6396ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby break; 639716c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6398ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby // FIXME: Improve diagnostic. 6399ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::Comma)) 6400ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return Error(L, "unexpected token in directive"); 6401b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6402ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 6403ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 6404ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6405b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6406ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return false; 6407ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 6408ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 64091355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumb 6410515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumb 64111355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 6412515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 6413515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 6414b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6415515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64169a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (!isThumb()) 64179a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 64189a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 64199a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return false; 64209a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach} 64219a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 64229a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// parseDirectiveARM 64239a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// ::= .arm 64249a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbachbool ARMAsmParser::parseDirectiveARM(SMLoc L) { 64259a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 64269a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return Error(L, "unexpected token in directive"); 64279a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach Parser.Lex(); 64289a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 64299a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (isThumb()) 64309a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 64319a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 6432515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6433515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6434515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64351355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumbFunc 6436515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumbfunc symbol_name 64371355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 64386469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 64396469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola bool isMachO = MAI.hasSubsectionsViaSymbols(); 64406469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola StringRef Name; 6441de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach bool needFuncName = true; 64426469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6443de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Darwin asm has (optionally) function name after .thumb_func direction 64446469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // ELF doesn't 64456469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola if (isMachO) { 64466469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const AsmToken &Tok = Parser.getTok(); 6447de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::EndOfStatement)) { 6448de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 6449de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach return Error(L, "unexpected token in .thumb_func directive"); 6450de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Name = Tok.getIdentifier(); 6451de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); // Consume the identifier token. 6452de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach needFuncName = false; 6453de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach } 64546469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 64556469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6456de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 6457515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 6458de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach 6459de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Eat the end of statement and any blank lines that follow. 6460de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach while (getLexer().is(AsmToken::EndOfStatement)) 6461de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); 6462515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64636469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // FIXME: assuming function name will be the line following .thumb_func 6464de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // We really should be checking the next symbol definition even if there's 6465de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // stuff in between. 6466de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (needFuncName) { 6467d475f8612b1c7959dbf50242c8fa9d4aea1ee1a9Jim Grosbach Name = Parser.getTok().getIdentifier(); 64686469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 64696469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6470642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach // Mark symbol as a thumb symbol. 6471642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 6472642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach getParser().getStreamer().EmitThumbFunc(Func); 6473515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6474515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6475515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64761355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveSyntax 6477515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .syntax unified | divided 64781355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 647918b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 6480515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Identifier)) 6481515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .syntax directive"); 648238e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef Mode = Tok.getString(); 648358c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Mode == "unified" || Mode == "UNIFIED") 6484b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 648558c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Mode == "divided" || Mode == "DIVIDED") 64869e56fb12c504c82c92947fe9c46287fc60116b91Kevin Enderby return Error(L, "'.syntax divided' arm asssembly not supported"); 6487515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 6488515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unrecognized syntax mode in .syntax directive"); 6489515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6490515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 649118b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 6492b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6493515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6494515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // TODO tell the MC streamer the mode 6495515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // getParser().getStreamer().Emit???(); 6496515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6497515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6498515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 64991355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveCode 6500515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .code 16 | 32 65011355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveCode(SMLoc L) { 650218b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 6503515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Integer)) 6504515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .code directive"); 650518b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan int64_t Val = Parser.getTok().getIntVal(); 650658c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Val == 16) 6507b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 650858c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Val == 32) 6509b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6510515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 6511515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "invalid operand to .code directive"); 6512515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6513515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 651418b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 6515b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6516515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 651732869205052430f45d598fba25ab878d8b29da2dEvan Cheng if (Val == 16) { 651898447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (!isThumb()) 6519ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 652098447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 652132869205052430f45d598fba25ab878d8b29da2dEvan Cheng } else { 652298447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (isThumb()) 6523ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 652498447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 6525eb0caa115491019f7f7fe45fc70ad47682244187Evan Cheng } 65262a301704ea76535f0485d5c3b75664b323249bdbJim Grosbach 6527515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6528515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6529515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6530a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveReq 6531a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= name .req registername 6532a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 6533a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the '.req' token. 6534a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach unsigned Reg; 6535a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach SMLoc SRegLoc, ERegLoc; 6536a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 6537a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6538a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "register name expected"); 6539a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6540a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6541a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Shouldn't be anything else. 6542a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 6543a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6544a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(Parser.getTok().getLoc(), 6545a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "unexpected input in .req directive."); 6546a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6547a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6548a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Consume the EndOfStatement 6549a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6550a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 6551a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "redefinition of '" + Name + 6552a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "' does not match original."); 6553a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6554a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 6555a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 6556a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6557a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveUneq 6558a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= .unreq registername 6559a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 6560a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::Identifier)) { 6561a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6562a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(L, "unexpected input in .unreq directive."); 6563a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6564a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach RegisterReqs.erase(Parser.getTok().getIdentifier()); 6565a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the identifier. 6566a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 6567a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 6568a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6569d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveArch 6570d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .arch token 6571d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveArch(SMLoc L) { 6572d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 6573d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 6574d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 6575d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveEabiAttr 6576d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .eabi_attribute int, int 6577d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 6578d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 6579d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 6580d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 658190b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callananextern "C" void LLVMInitializeARMAsmLexer(); 658290b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan 65839c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Force static initialization. 6584ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyextern "C" void LLVMInitializeARMAsmParser() { 658594b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 658694b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 658790b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan LLVMInitializeARMAsmLexer(); 6588ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 65893483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 65900692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_REGISTER_MATCHER 65910692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_MATCHER_IMPLEMENTATION 65923483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar#include "ARMGenAsmMatcher.inc" 6593