ARMAsmParser.cpp revision 70c9bf3c1a77b5707c92a7cfe74104c320480391
1ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 3ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// The LLVM Compiler Infrastructure 4ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 5ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// This file is distributed under the University of Illinois Open Source 6ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// License. See LICENSE.TXT for details. 7ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 8ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===----------------------------------------------------------------------===// 9ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 1094b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "MCTargetDesc/ARMBaseInfo.h" 11ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 12ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMMCExpr.h" 13c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmLexer.h" 14c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmParser.h" 15c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 166469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola#include "llvm/MC/MCAsmInfo.h" 17642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach#include "llvm/MC/MCContext.h" 18ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCStreamer.h" 19ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCExpr.h" 20ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCInst.h" 217801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng#include "llvm/MC/MCInstrDesc.h" 2294b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCRegisterInfo.h" 23ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng#include "llvm/MC/MCSubtargetInfo.h" 2494b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCTargetAsmParser.h" 2589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach#include "llvm/Support/MathExtras.h" 26c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/Support/SourceMgr.h" 273e74d6fdd248e20a280f1dff3da9a6c689c2c4c3Evan Cheng#include "llvm/Support/TargetRegistry.h" 28fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar#include "llvm/Support/raw_ostream.h" 2911e03e7c2d0c163e54b911ad1e665616dc0bcc8cJim Grosbach#include "llvm/ADT/BitVector.h" 3075ca4b94bd9dcd3952fdc237429342a2154ba142Benjamin Kramer#include "llvm/ADT/OwningPtr.h" 3194b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/ADT/STLExtras.h" 32c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/SmallVector.h" 33345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar#include "llvm/ADT/StringSwitch.h" 34c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/Twine.h" 35ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 36ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyusing namespace llvm; 37ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 383a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 39146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 40146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand; 4116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 427636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbachenum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 4398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 4494b9550a32d189704a8eae55505edf62662c0534Evan Chengclass ARMAsmParser : public MCTargetAsmParser { 45ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng MCSubtargetInfo &STI; 46ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &Parser; 4728f08c93e75d291695ea89b9004145103292e85bJim Grosbach const MCRegisterInfo *MRI; 48ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 49a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Map of register aliases registers via the .req directive. 50a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StringMap<unsigned> RegisterReqs; 51a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 52f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach struct { 53f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes Cond; // Condition for IT block. 54f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Mask:4; // Condition mask for instructions. 55f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Starting at first 1 (from lsb). 56f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '1' condition as indicated in IT. 57f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '0' inverse of condition (else). 58f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Count of instructions in IT block is 59f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // 4 - trailingzeroes(mask) 60f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 61f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool FirstCond; // Explicit flag for when we're parsing the 62f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // First instruction in the IT block. It's 63f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // implied in the mask, so needs special 64f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // handling. 65f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 66f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned CurPosition; // Current position in parsing of IT 67f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // block. In range [0,3]. Initialized 68f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // according to count of instructions in block. 69f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // ~0U if no active IT block. 70f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } ITState; 71f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool inITBlock() { return ITState.CurPosition != ~0U;} 72a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach void forwardITPosition() { 73a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (!inITBlock()) return; 74a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Move to the next instruction in the IT block, if there is one. If not, 75a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // mark the block as done. 76a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach unsigned TZ = CountTrailingZeros_32(ITState.Mask); 77a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (++ITState.CurPosition == 5 - TZ) 78a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach ITState.CurPosition = ~0U; // Done with the IT block after this. 79a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 80f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 81f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 82ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &getParser() const { return Parser; } 83ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmLexer &getLexer() const { return Parser.getLexer(); } 84ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 85362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer bool Warning(SMLoc L, const Twine &Msg, 86362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 87362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer return Parser.Warning(L, Msg, Ranges); 88362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer } 89362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer bool Error(SMLoc L, const Twine &Msg, 90362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 91362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer return Parser.Error(L, Msg, Ranges); 92362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer } 93ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 941355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int tryParseRegister(); 951355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 960d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 971355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 991355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 1001355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 1017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 1027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &ShiftAmount); 1031355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveWord(unsigned Size, SMLoc L); 1041355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumb(SMLoc L); 1059a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach bool parseDirectiveARM(SMLoc L); 1061355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumbFunc(SMLoc L); 1071355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveCode(SMLoc L); 1081355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveSyntax(SMLoc L); 109a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveReq(StringRef Name, SMLoc L); 110a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveUnreq(SMLoc L); 111d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveArch(SMLoc L); 112d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveEabiAttr(SMLoc L); 113515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 1141355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 11589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach bool &CarrySetting, unsigned &ProcessorIMod, 11689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask); 1171355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 118fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode); 11916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 120ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumb() const { 121ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // FIXME: Can tablegen auto-generate this? 122ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 123ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 124ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumbOne() const { 125ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 126ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 12747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach bool isThumbTwo() const { 12847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 12947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 130194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach bool hasV6Ops() const { 131194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return STI.getFeatureBits() & ARM::HasV6Ops; 132194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach } 133acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool hasV7Ops() const { 134acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::HasV7Ops; 135acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 13632869205052430f45d598fba25ab878d8b29da2dEvan Cheng void SwitchMode() { 137ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 138ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(FB); 13932869205052430f45d598fba25ab878d8b29da2dEvan Cheng } 140acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool isMClass() const { 141acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::FeatureMClass; 142acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 143ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 144a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// @name Auto-generated Match Functions 145a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// { 1463483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 1470692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_ASSEMBLER_HEADER 1480692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#include "ARMGenAsmMatcher.inc" 149a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 150a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// } 151a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 15289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 15343904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocNumOperand( 154f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 15543904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocRegOperand( 156f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 1579b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OperandMatchResultTy parseCoprocOptionOperand( 1589b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 15943904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMemBarrierOptOperand( 1608bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 16143904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseProcIFlagsOperand( 1628bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 16343904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMSRMaskOperand( 1648bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 165f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 166f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef Op, int Low, int High); 167f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 168f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "lsl", 0, 31); 169f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 170f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 171f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "asr", 1, 32); 172f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 173c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 174580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 1757e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 176293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 1777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 178251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 1799d39036f62674606565217a10db28171b9594bc7Jim Grosbach OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 180862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 1817636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 182ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 183ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Asm Match Converter Methods 184a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 185a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 186a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 187a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 188eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 189eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 190ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 191ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1921355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 193ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 1949ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 1959ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &); 196548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 197548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1981355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 199ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 2007b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 2017b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2067ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2102fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2112fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 21314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 214623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 215623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21688ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 21788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21812431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 21912431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 22012431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 22112431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2224334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 2234334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2244334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 2254334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 226189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 227189610f9466686a91fb7d847b572e1645c785323Jim Grosbach bool validateInstruction(MCInst &Inst, 228189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 22983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach bool processInstruction(MCInst &Inst, 230f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 231d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach bool shouldOmitCCOutOperand(StringRef Mnemonic, 232d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 233189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 234ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbypublic: 23547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach enum ARMMatchResultTy { 236194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 237f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Match_RequiresNotITBlock, 238194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresV6, 23970c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach Match_RequiresThumb2, 24070c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach#define GET_OPERAND_DIAGNOSTIC_TYPES 24170c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach#include "ARMGenAsmMatcher.inc" 24270c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach 24347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach }; 24447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 245ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 24694b9550a32d189704a8eae55505edf62662c0534Evan Cheng : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 247ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng MCAsmParserExtension::Initialize(_Parser); 24832869205052430f45d598fba25ab878d8b29da2dEvan Cheng 24928f08c93e75d291695ea89b9004145103292e85bJim Grosbach // Cache the MCRegisterInfo. 25028f08c93e75d291695ea89b9004145103292e85bJim Grosbach MRI = &getContext().getRegisterInfo(); 25128f08c93e75d291695ea89b9004145103292e85bJim Grosbach 252ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // Initialize the set of available features. 253ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 254f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 255f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Not in an ITBlock to start with. 256f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = ~0U; 257ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 258ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 2591355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach // Implementation of the MCTargetAsmParser interface: 2601355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 2611355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseInstruction(StringRef Name, SMLoc NameLoc, 262189610f9466686a91fb7d847b572e1645c785323Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 2631355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseDirective(AsmToken DirectiveID); 2641355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach 26547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned checkTargetMatchPredicate(MCInst &Inst); 26647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 2671355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool MatchAndEmitInstruction(SMLoc IDLoc, 2681355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2691355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach MCStreamer &Out); 270ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby}; 27116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach} // end anonymous namespace 27216c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2733a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 2743a69756e392942bc522193f38d7f33958ed3b131Chris Lattner 275a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ARMOperand - Instances of this class represent a parsed ARM machine 276a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// instruction. 277146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand : public MCParsedAsmOperand { 278762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan enum KindTy { 27921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CondCode, 28021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CCOut, 28121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ITCondMask, 28221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocNum, 28321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocReg, 2849b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach k_CoprocOption, 28521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Immediate, 28621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MemBarrierOpt, 28721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Memory, 28821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_PostIndexRegister, 28921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MSRMask, 29021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ProcIFlags, 291460a90540b045c102012da2492999557e6840526Jim Grosbach k_VectorIndex, 29221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Register, 29321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RegisterList, 29421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_DPRRegisterList, 29521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_SPRRegisterList, 296862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach k_VectorList, 29798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach k_VectorListAllLanes, 2987636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach k_VectorListIndexed, 29921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedRegister, 30021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedImmediate, 30121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShifterImmediate, 30221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RotateImmediate, 30321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_BitfieldDescriptor, 30421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Token 305a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Kind; 306a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 307762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc StartLoc, EndLoc; 30824d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling SmallVector<unsigned, 8> Registers; 309a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 310a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby union { 311a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 3128462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes Val; 3138462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } CC; 3148462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 3158462b30548fb5969250858036638c73c16b65b43Daniel Dunbar struct { 316fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned Val; 317fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } Cop; 318fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 319fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes struct { 3209b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach unsigned Val; 3219b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } CoprocOption; 3229b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 3239b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach struct { 32489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask:4; 32589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } ITMask; 32689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 32789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 32889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ARM_MB::MemBOpt Val; 32989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } MBOpt; 33089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 33189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 332a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags Val; 333a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } IFlags; 334a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 335a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes struct { 336584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Val; 337584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } MMask; 338584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 339584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes struct { 340a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby const char *Data; 341a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned Length; 342a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Tok; 343a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 344a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 345a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned RegNum; 346a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Reg; 347a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 348862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // A vector register list is a sequential list of 1 to 4 registers. 349862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach struct { 350862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned RegNum; 351862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count; 3527636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 3530aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced; 354862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } VectorList; 355862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3568155e5b753aca42973cf317727f3805faddcaf90Bill Wendling struct { 357460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned Val; 358460a90540b045c102012da2492999557e6840526Jim Grosbach } VectorIndex; 359460a90540b045c102012da2492999557e6840526Jim Grosbach 360460a90540b045c102012da2492999557e6840526Jim Grosbach struct { 361cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *Val; 362cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } Imm; 36316c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 3646a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar /// Combined record for all forms of ARM address expressions. 365a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 366a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned BaseRegNum; 3677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 3687ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // was specified. 3697ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm; // Offset immediate value 3707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 3717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 37257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned ShiftImm; // shift for OffsetReg. 37357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment; // 0 = no alignment specified 374eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach // n = alignment in bytes (2, 4, 8, 16, or 32) 3757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 376e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach } Memory; 3770082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 3780082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson struct { 3797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned RegNum; 380f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isAdd; 381f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 382f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm; 3837ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } PostIdxReg; 3847ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3857ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach struct { 386580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 387e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned Imm; 388580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } ShifterImm; 389e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach struct { 390e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ARM_AM::ShiftOpc ShiftTy; 391e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg; 392e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg; 393e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm; 394af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedReg; 39592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson struct { 39692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson ARM_AM::ShiftOpc ShiftTy; 39792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg; 39892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm; 399af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedImm; 4007e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach struct { 4017e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach unsigned Imm; 4027e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } RotImm; 403293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach struct { 404293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned LSB; 405293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned Width; 406293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } Bitfield; 407a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby }; 40816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 409146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 410146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingpublic: 411762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 412762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Kind = o.Kind; 413762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan StartLoc = o.StartLoc; 414762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan EndLoc = o.EndLoc; 415762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan switch (Kind) { 41621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 4178462b30548fb5969250858036638c73c16b65b43Daniel Dunbar CC = o.CC; 4188462b30548fb5969250858036638c73c16b65b43Daniel Dunbar break; 41921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: 42089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = o.ITMask; 42189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 42221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 4238462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Tok = o.Tok; 424762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 42521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 42621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 427762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Reg = o.Reg; 428762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 42921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 43021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 43121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: 43224d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Registers = o.Registers; 4338d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 434862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 43598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 4367636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 437862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach VectorList = o.VectorList; 438862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 43921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 44021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 441fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Cop = o.Cop; 442fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 4439b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 4449b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach CoprocOption = o.CoprocOption; 4459b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 44621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 447762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Imm = o.Imm; 448762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 44921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 450706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes MBOpt = o.MBOpt; 451706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 45221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 453e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory = o.Memory; 454762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 45521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 4567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach PostIdxReg = o.PostIdxReg; 4577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 45821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 459584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes MMask = o.MMask; 460584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 46121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: 462a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes IFlags = o.IFlags; 4630082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 46421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 465580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm = o.ShifterImm; 4660082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 46721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 468af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedReg = o.RegShiftedReg; 469e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 47021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 471af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedImm = o.RegShiftedImm; 47292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 47321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 4747e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach RotImm = o.RotImm; 4757e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 47621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 477293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Bitfield = o.Bitfield; 478293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 479460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 480460a90540b045c102012da2492999557e6840526Jim Grosbach VectorIndex = o.VectorIndex; 481460a90540b045c102012da2492999557e6840526Jim Grosbach break; 482762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 483762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 48416c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 485762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getStartLoc - Get the location of the first token of this operand. 486762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getStartLoc() const { return StartLoc; } 487762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getEndLoc - Get the location of the last token of this operand. 488762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getEndLoc() const { return EndLoc; } 489a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 490362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 491362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer 4928462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes getCondCode() const { 49321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_CondCode && "Invalid access!"); 4948462b30548fb5969250858036638c73c16b65b43Daniel Dunbar return CC.Val; 4958462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 4968462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 497fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned getCoproc() const { 49821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 499fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Cop.Val; 500fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 501fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 502a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby StringRef getToken() const { 50321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_Token && "Invalid access!"); 504a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return StringRef(Tok.Data, Tok.Length); 505a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 506a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 507a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned getReg() const { 50821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 5097729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling return Reg.RegNum; 510a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 511a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 5125fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &getRegList() const { 51321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 51421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind == k_SPRRegisterList) && "Invalid access!"); 51524d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling return Registers; 5168d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 5178d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 518cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *getImm() const { 51921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach assert(isImm() && "Invalid access!"); 520cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby return Imm.Val; 521cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 522cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 523460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned getVectorIndex() const { 524460a90540b045c102012da2492999557e6840526Jim Grosbach assert(Kind == k_VectorIndex && "Invalid access!"); 525460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val; 526460a90540b045c102012da2492999557e6840526Jim Grosbach } 527460a90540b045c102012da2492999557e6840526Jim Grosbach 528706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes ARM_MB::MemBOpt getMemBarrierOpt() const { 52921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MemBarrierOpt && "Invalid access!"); 530706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return MBOpt.Val; 531706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 532706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 533a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags getProcIFlags() const { 53421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_ProcIFlags && "Invalid access!"); 535a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return IFlags.Val; 536a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 537a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 538584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned getMSRMask() const { 53921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MSRMask && "Invalid access!"); 540584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MMask.Val; 541584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 542584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 54321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocNum() const { return Kind == k_CoprocNum; } 54421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocReg() const { return Kind == k_CoprocReg; } 5459b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach bool isCoprocOption() const { return Kind == k_CoprocOption; } 54621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCondCode() const { return Kind == k_CondCode; } 54721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCCOut() const { return Kind == k_CCOut; } 54821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITMask() const { return Kind == k_ITCondMask; } 54921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITCondCode() const { return Kind == k_CondCode; } 55021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isImm() const { return Kind == k_Immediate; } 55151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach bool isFPImm() const { 55251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach if (!isImm()) return false; 55351222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 55451222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach if (!CE) return false; 55551222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 55651222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach return Val != -1; 55751222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach } 5584050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits16() const { 5594050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5604050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5614050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5624050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5634050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 0 && Value <= 16; 5644050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 5654050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits32() const { 5664050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5674050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5684050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5694050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5704050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 1 && Value <= 32; 5714050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 572a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isImm8s4() const { 57321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 574a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 575a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach if (!CE) return false; 576a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach int64_t Value = CE->getValue(); 577a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 578a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 57972f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_1020s4() const { 58021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 58172f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 58272f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 58372f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 58472f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 58572f39f8436848885176943b0ba985a7171145423Jim Grosbach } 58672f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_508s4() const { 58721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 58872f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 58972f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 59072f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 59172f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 59272f39f8436848885176943b0ba985a7171145423Jim Grosbach } 5934e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach bool isImm0_508s4Neg() const { 5944e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach if (!isImm()) return false; 5954e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5964e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach if (!CE) return false; 5974e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach int64_t Value = -CE->getValue(); 5984e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach // explicitly exclude zero. we want that to use the normal 0_508 version. 5994e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach return ((Value & 3) == 0) && Value > 0 && Value <= 508; 6004e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach } 6016b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isImm0_255() const { 60221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6036b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6046b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 6056b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 6066b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return Value >= 0 && Value < 256; 6076b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 6084e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach bool isImm0_4095() const { 6094e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach if (!isImm()) return false; 6104e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6114e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach if (!CE) return false; 6124e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach int64_t Value = CE->getValue(); 6134e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach return Value >= 0 && Value < 4096; 6144e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach } 6154e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach bool isImm0_4095Neg() const { 6164e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach if (!isImm()) return false; 6174e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6184e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach if (!CE) return false; 6194e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach int64_t Value = -CE->getValue(); 6204e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach return Value > 0 && Value < 4096; 6214e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach } 622587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_1() const { 62321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 624587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 625587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 626587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 627587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 2; 628587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 629587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_3() const { 63021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 631587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 632587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 633587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 634587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 4; 635587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 63683ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_7() const { 63721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 63883ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 63983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 64083ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 64183ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 8; 64283ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 64383ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_15() const { 64421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 64583ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 64683ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 64783ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 64883ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 16; 64983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 6507c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach bool isImm0_31() const { 65121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6527c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6537c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach if (!CE) return false; 6547c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach int64_t Value = CE->getValue(); 6557c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach return Value >= 0 && Value < 32; 6567c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach } 657730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach bool isImm0_63() const { 65821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 659730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 660730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach if (!CE) return false; 661730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach int64_t Value = CE->getValue(); 662730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach return Value >= 0 && Value < 64; 663730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach } 6643b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm8() const { 66521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6663b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6673b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6683b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6693b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 8; 6703b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6713b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm16() const { 67221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6733b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6743b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6753b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6763b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 16; 6773b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6783b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm32() const { 67921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6803b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6813b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6823b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6833b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 32; 6843b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6856b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm8() const { 68621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6876b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6886b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6896b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6906b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 8; 6916b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6926b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm16() const { 69321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6946b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6956b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6966b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6976b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 16; 6986b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6996b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm32() const { 70021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7016b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7026b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 7036b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 7046b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 32; 7056b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 7066b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm64() const { 70721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7086b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7096b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 7106b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 7116b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 64; 7126b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 7133b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_7() const { 71421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7153b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7163b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 7173b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 7183b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 8; 7193b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 7203b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_15() const { 72121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7223b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7233b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 7243b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 7253b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 16; 7263b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 7273b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_31() const { 72821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7293b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7303b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 7313b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 7323b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 32; 7333b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 734f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach bool isImm1_16() const { 73521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 736f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 737f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach if (!CE) return false; 738f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach int64_t Value = CE->getValue(); 739f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach return Value > 0 && Value < 17; 740f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 7414a5ffb399f841783c201c599b88d576757f1922eJim Grosbach bool isImm1_32() const { 74221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7434a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7444a5ffb399f841783c201c599b88d576757f1922eJim Grosbach if (!CE) return false; 7454a5ffb399f841783c201c599b88d576757f1922eJim Grosbach int64_t Value = CE->getValue(); 7464a5ffb399f841783c201c599b88d576757f1922eJim Grosbach return Value > 0 && Value < 33; 7474a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 748ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach bool isImm0_32() const { 74921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 750ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 751ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (!CE) return false; 752ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach int64_t Value = CE->getValue(); 753ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach return Value >= 0 && Value < 33; 754ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 755fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach bool isImm0_65535() const { 75621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 757fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 758fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach if (!CE) return false; 759fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach int64_t Value = CE->getValue(); 760fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach return Value >= 0 && Value < 65536; 761fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach } 762ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach bool isImm0_65535Expr() const { 76321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 764ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 765ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // If it's not a constant expression, it'll generate a fixup and be 766ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // handled later. 767ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach if (!CE) return true; 768ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach int64_t Value = CE->getValue(); 769ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Value >= 0 && Value < 65536; 770ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 771ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach bool isImm24bit() const { 77221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 773ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 774ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach if (!CE) return false; 775ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach int64_t Value = CE->getValue(); 776ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach return Value >= 0 && Value <= 0xffffff; 777ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach } 77870939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach bool isImmThumbSR() const { 77921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 78070939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 78170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach if (!CE) return false; 78270939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach int64_t Value = CE->getValue(); 78370939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach return Value > 0 && Value < 33; 78470939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach } 785f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHLSLImm() const { 78621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 787f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 788f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 789f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 790f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value >= 0 && Value < 32; 791f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 792f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHASRImm() const { 79321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 794f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 795f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 796f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 797f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value > 0 && Value <= 32; 798f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 7996bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach bool isARMSOImm() const { 80021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 8016bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8026bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach if (!CE) return false; 8036bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach int64_t Value = CE->getValue(); 8046bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach return ARM_AM::getSOImmVal(Value) != -1; 8056bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach } 806e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach bool isARMSOImmNot() const { 80721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 808e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 809e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach if (!CE) return false; 810e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach int64_t Value = CE->getValue(); 811e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach return ARM_AM::getSOImmVal(~Value) != -1; 812e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 8133bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isARMSOImmNeg() const { 81421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 8153bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8163bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 8173bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 818ad353c630359d285018a250d72c80b7022d8e67eJim Grosbach // Only use this when not representable as a plain so_imm. 819ad353c630359d285018a250d72c80b7022d8e67eJim Grosbach return ARM_AM::getSOImmVal(Value) == -1 && 820ad353c630359d285018a250d72c80b7022d8e67eJim Grosbach ARM_AM::getSOImmVal(-Value) != -1; 8213bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 8226b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isT2SOImm() const { 82321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 8246b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8256b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 8266b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 8276b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return ARM_AM::getT2SOImmVal(Value) != -1; 8286b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 82989a633708542de5847e807f98f86edfefc9fc019Jim Grosbach bool isT2SOImmNot() const { 83021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 83189a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 83289a633708542de5847e807f98f86edfefc9fc019Jim Grosbach if (!CE) return false; 83389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach int64_t Value = CE->getValue(); 83489a633708542de5847e807f98f86edfefc9fc019Jim Grosbach return ARM_AM::getT2SOImmVal(~Value) != -1; 83589a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 8363bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isT2SOImmNeg() const { 83721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 8383bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8393bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 8403bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 841ad353c630359d285018a250d72c80b7022d8e67eJim Grosbach // Only use this when not representable as a plain so_imm. 842ad353c630359d285018a250d72c80b7022d8e67eJim Grosbach return ARM_AM::getT2SOImmVal(Value) == -1 && 843ad353c630359d285018a250d72c80b7022d8e67eJim Grosbach ARM_AM::getT2SOImmVal(-Value) != -1; 8443bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 845c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach bool isSetEndImm() const { 84621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 847c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 848c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CE) return false; 849c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int64_t Value = CE->getValue(); 850c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Value == 1 || Value == 0; 851c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 85221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isReg() const { return Kind == k_Register; } 85321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegList() const { return Kind == k_RegisterList; } 85421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 85521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 85621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isToken() const { return Kind == k_Token; } 85721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 85821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemory() const { return Kind == k_Memory; } 85921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isShifterImm() const { return Kind == k_ShifterImmediate; } 86021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 86121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 86221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRotImm() const { return Kind == k_RotateImmediate; } 86321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 86421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 865f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isPostIdxReg() const { 866430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 867f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 86857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isMemNoOffset(bool alignOK = false) const { 869f6c35c59f515505fa2e9b74b3d0f4ab06f8266d8Jim Grosbach if (!isMemory()) 870ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return false; 8717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // No offset of any kind. 87257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 87357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach (alignOK || Memory.Alignment == 0); 87457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 8750b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach bool isMemPCRelImm12() const { 8760b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 8770b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return false; 8780b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base register must be PC. 8790b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum != ARM::PC) 8800b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return false; 8810b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Immediate offset in range [-4095, 4095]. 8820b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (!Memory.OffsetImm) return true; 8830b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8840b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 8850b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach } 88657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isAlignedMemory() const { 88757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return isMemNoOffset(true); 888ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 8897ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode2() const { 89057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 892e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 8937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 894e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 895e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Val > -4096 && Val < 4096; 8977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 898039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach bool isAM2OffsetImm() const { 89921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 900039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Immediate offset in range [-4095, 4095]. 901039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 902039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (!CE) return false; 903039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int64_t Val = CE->getValue(); 904039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach return Val > -4096 && Val < 4096; 905039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 9062fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAddrMode3() const { 9072f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 9082f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 9092f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 91021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 9112f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 91257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 9132fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // No shifts are legal for AM3. 914e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::no_shift) return false; 9152fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Check for register offset. 916e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 9172fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 918e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 919e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 920ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga // The #-0 offset is encoded as INT32_MIN, and we have to check 921ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga // for this too. 922ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga return (Val > -256 && Val < 256) || Val == INT32_MIN; 9232fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 9242fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAM3Offset() const { 92521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind != k_Immediate && Kind != k_PostIndexRegister) 9262fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return false; 92721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) 9282fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return PostIdxReg.ShiftTy == ARM_AM::no_shift; 9292fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 9302fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 9312fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (!CE) return false; 9322fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int64_t Val = CE->getValue(); 933251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Special case, #-0 is INT32_MIN. 934251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return (Val > -256 && Val < 256) || Val == INT32_MIN; 9352fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 9367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode5() const { 937681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 938681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 939681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 94021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 941681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return true; 94257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 9437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 944e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return false; 9457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-1020, 1020] and a multiple of 4. 946e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 947e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 9480da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 949681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Val == INT32_MIN; 9507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 9517f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBB() const { 952e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 95357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 9547f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9557f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9567f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9577f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBH() const { 958e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 95957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 96057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0 ) 9617f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9627f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9637f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemRegOffset() const { 96557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 966ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return false; 967ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 968ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 969ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach bool isT2MemRegOffset() const { 97057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 97157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0) 972ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 973ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach // Only lsl #{0, 1, 2, 3} allowed. 974e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType == ARM_AM::no_shift) 975ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 976e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 977ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 978ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 979ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 9807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemThumbRR() const { 9817ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Thumb reg+reg addressing is simple. Just two registers, a base and 9827ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // an offset. No shifts, negations or any other complicating factors. 983e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 98457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 98587f4f9a946549ad93046990a364ac5190333a7ebBill Wendling return false; 986e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach return isARMLowRegister(Memory.BaseRegNum) && 987e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 98860f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 98960f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach bool isMemThumbRIs4() const { 990e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 99157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 99260f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach return false; 99360f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach // Immediate offset, multiple of 4 in range [0, 124]. 994e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 995e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 996ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 124 && (Val % 4) == 0; 997ecd858968384be029574d845eb098d357049e02eJim Grosbach } 99838466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach bool isMemThumbRIs2() const { 999e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 100057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 100138466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return false; 100238466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach // Immediate offset, multiple of 4 in range [0, 62]. 1003e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1004e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 100538466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return Val >= 0 && Val <= 62 && (Val % 2) == 0; 100638466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 100748ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach bool isMemThumbRIs1() const { 1008e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 100957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 101048ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return false; 101148ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach // Immediate offset in range [0, 31]. 1012e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1013e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 101448ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return Val >= 0 && Val <= 31; 101548ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 1016ecd858968384be029574d845eb098d357049e02eJim Grosbach bool isMemThumbSPI() const { 101757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 101857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1019ecd858968384be029574d845eb098d357049e02eJim Grosbach return false; 1020ecd858968384be029574d845eb098d357049e02eJim Grosbach // Immediate offset, multiple of 4 in range [0, 1020]. 1021e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1022e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1023ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1024505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 1025a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isMemImm8s4Offset() const { 10262f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 10272f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 10282f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 102921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 10302f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 103157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1032a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return false; 1033a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Immediate offset a multiple of 4 in range [-1020, 1020]. 1034e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1035e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1036a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 1037a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1038b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach bool isMemImm0_1020s4Offset() const { 103957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1040b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return false; 1041b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // Immediate offset a multiple of 4 in range [0, 1020]. 1042e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1043e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1044b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1045b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 10467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm8Offset() const { 104757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1048f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling return false; 10490b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base reg of PC isn't allowed for these encodings. 10500b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum == ARM::PC) return false; 10517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-255, 255]. 1052e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1053e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10544d2a00147d19b17d382644de0d6a1f0d3230e0e4Owen Anderson return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1055f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1056f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach bool isMemPosImm8Offset() const { 105757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1058f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return false; 1059f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach // Immediate offset in range [0, 255]. 1060e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1061e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1062f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return Val >= 0 && Val < 256; 1063f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1064a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemNegImm8Offset() const { 106557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1066a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 10670b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base reg of PC isn't allowed for these encodings. 10680b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum == ARM::PC) return false; 1069a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [-255, -1]. 1070df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach if (!Memory.OffsetImm) return false; 1071e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1072df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1073a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1074a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemUImm12Offset() const { 107557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1076a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 1077a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [0, 4095]. 1078e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1079e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1080a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return (Val >= 0 && Val < 4096); 1081a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 10827ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm12Offset() const { 108309176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 108409176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 108509176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // and we reject it. 108621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 108709176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return true; 108809176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 108957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1090ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling return false; 10917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 1092e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1093e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10940da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 10957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 10967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isPostIdxImm8() const { 109721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 10987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1099ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling if (!CE) return false; 11007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Val = CE->getValue(); 110163553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1102ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 11032bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isPostIdxImm8s4() const { 110421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 11052bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 11062bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (!CE) return false; 11072bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int64_t Val = CE->getValue(); 11082bd0118472de352745a2e038245fab4974f7c87eJim Grosbach return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 11092bd0118472de352745a2e038245fab4974f7c87eJim Grosbach (Val == INT32_MIN); 11102bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 11117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 111221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMSRMask() const { return Kind == k_MSRMask; } 111321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isProcIFlags() const { return Kind == k_ProcIFlags; } 11143483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 11150e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // NEON operands. 11160aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isSingleSpacedVectorList() const { 11170aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && !VectorList.isDoubleSpaced; 11180aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 11190aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpacedVectorList() const { 11200aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && VectorList.isDoubleSpaced; 11210aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 1122862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach bool isVecListOneD() const { 11230aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1124862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return VectorList.Count == 1; 1125862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1126862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 112728f08c93e75d291695ea89b9004145103292e85bJim Grosbach bool isVecListDPair() const { 112828f08c93e75d291695ea89b9004145103292e85bJim Grosbach if (!isSingleSpacedVectorList()) return false; 112928f08c93e75d291695ea89b9004145103292e85bJim Grosbach return (ARMMCRegisterClasses[ARM::DPairRegClassID] 113028f08c93e75d291695ea89b9004145103292e85bJim Grosbach .contains(VectorList.RegNum)); 113128f08c93e75d291695ea89b9004145103292e85bJim Grosbach } 113228f08c93e75d291695ea89b9004145103292e85bJim Grosbach 1133cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach bool isVecListThreeD() const { 11340aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1135cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach return VectorList.Count == 3; 1136cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach } 1137cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach 1138b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach bool isVecListFourD() const { 11390aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1140b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach return VectorList.Count == 4; 1141b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach } 1142b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach 1143c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach bool isVecListDPairSpaced() const { 11449f2e160f7ae90a7a80b17e38ad06f2c706515115Kevin Enderby if (isSingleSpacedVectorList()) return false; 1145c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1146c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach .contains(VectorList.RegNum)); 1147c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach } 1148c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach 1149c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach bool isVecListThreeQ() const { 1150c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach if (!isDoubleSpacedVectorList()) return false; 1151c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return VectorList.Count == 3; 1152c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 1153c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 11547945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach bool isVecListFourQ() const { 11557945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach if (!isDoubleSpacedVectorList()) return false; 11567945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach return VectorList.Count == 4; 11577945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach } 11587945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach 11593471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isSingleSpacedVectorAllLanes() const { 11603471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 11613471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 11623471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpacedVectorAllLanes() const { 11633471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 11643471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 116598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach bool isVecListOneDAllLanes() const { 11663471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 116798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return VectorList.Count == 1; 116898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 116998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 1170c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach bool isVecListDPairAllLanes() const { 11713471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 1172c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1173c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach .contains(VectorList.RegNum)); 11743471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 11753471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach 11764d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach bool isVecListDPairSpacedAllLanes() const { 11773471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isDoubleSpacedVectorAllLanes()) return false; 117813af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach return VectorList.Count == 2; 117913af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach } 118013af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach 11815e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach bool isVecListThreeDAllLanes() const { 11825e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 11835e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach return VectorList.Count == 3; 11845e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach } 11855e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 11865e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach bool isVecListThreeQAllLanes() const { 11875e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach if (!isDoubleSpacedVectorAllLanes()) return false; 11885e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach return VectorList.Count == 3; 11895e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach } 11905e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 1191a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach bool isVecListFourDAllLanes() const { 1192a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 1193a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach return VectorList.Count == 4; 1194a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach } 1195a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 1196a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach bool isVecListFourQAllLanes() const { 1197a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach if (!isDoubleSpacedVectorAllLanes()) return false; 1198a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach return VectorList.Count == 4; 1199a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach } 1200a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 120195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isSingleSpacedVectorIndexed() const { 120295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 120395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 120495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpacedVectorIndexed() const { 120595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 120695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 12077636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach bool isVecListOneDByteIndexed() const { 120895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 12097636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 12107636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 12117636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1212799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDHWordIndexed() const { 121395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1214799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1215799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1216799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1217799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDWordIndexed() const { 121895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1219799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1220799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1221799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 12229b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach bool isVecListTwoDByteIndexed() const { 122395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 12249b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 12259b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 12269b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 1227799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDHWordIndexed() const { 122895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 122995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 123095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 123195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 123295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQWordIndexed() const { 123395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 123495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 123595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 123695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 123795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQHWordIndexed() const { 123895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 1239799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1240799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1241799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1242799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDWordIndexed() const { 124395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1244799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1245799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1246799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 12473a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeDByteIndexed() const { 12483a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 12493a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 12503a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 12513a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 12523a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeDHWordIndexed() const { 12533a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 12543a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 12553a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 12563a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 12573a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeQWordIndexed() const { 12583a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 12593a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 12603a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 12613a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 12623a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeQHWordIndexed() const { 12633a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 12643a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 12653a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 12663a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 12673a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeDWordIndexed() const { 12683a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 12693a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 12703a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 12713a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 1272e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach bool isVecListFourDByteIndexed() const { 1273e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1274e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1275e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 1276e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 1277e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach bool isVecListFourDHWordIndexed() const { 1278e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1279e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1280e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 1281e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 1282e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach bool isVecListFourQWordIndexed() const { 1283e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 1284e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1285e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 1286e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 1287e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach bool isVecListFourQHWordIndexed() const { 1288e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 1289e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1290e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 1291e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 1292e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach bool isVecListFourDWordIndexed() const { 1293e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1294e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1295e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 1296e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 1297460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex8() const { 1298460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1299460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 8; 1300460a90540b045c102012da2492999557e6840526Jim Grosbach } 1301460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex16() const { 1302460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1303460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 4; 1304460a90540b045c102012da2492999557e6840526Jim Grosbach } 1305460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex32() const { 1306460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1307460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 2; 1308460a90540b045c102012da2492999557e6840526Jim Grosbach } 1309460a90540b045c102012da2492999557e6840526Jim Grosbach 13100e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach bool isNEONi8splat() const { 131121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 13120e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13130e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Must be a constant. 13140e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!CE) return false; 13150e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach int64_t Value = CE->getValue(); 13160e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // i8 value splatted across 8 bytes. The immediate is just the 8 byte 13170e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // value. 13180e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return Value >= 0 && Value < 256; 13190e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 1320460a90540b045c102012da2492999557e6840526Jim Grosbach 1321ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach bool isNEONi16splat() const { 132221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1323ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1324ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // Must be a constant. 1325ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (!CE) return false; 1326ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach int64_t Value = CE->getValue(); 1327ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // i16 value in the range [0,255] or [0x0100, 0xff00] 1328ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1329ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1330ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 13316248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32splat() const { 133221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 13336248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13346248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 13356248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 13366248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 13376248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 13386248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 13396248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 13406248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 13416248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000); 13426248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 13436248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 13446248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32vmov() const { 134521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 13466248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13476248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 13486248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 13496248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 13506248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 13516248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 13526248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 13536248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 13546248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 13556248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 13566248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 13576248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 13586248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 13599b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach bool isNEONi32vmovNeg() const { 136021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 13619b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 13629b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // Must be a constant. 13639b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (!CE) return false; 13649b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach int64_t Value = ~CE->getValue(); 13659b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 13669b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 13679b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach return (Value >= 0 && Value < 256) || 13689b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 13699b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 13709b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 13719b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 13729b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 13739b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 13746248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 1375f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach bool isNEONi64splat() const { 137621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1377f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1378f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // Must be a constant. 1379f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if (!CE) return false; 1380f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 1381f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // i64 value with each byte being either 0 or 0xff. 1382f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i) 1383f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1384f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach return true; 1385f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1386f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 13873483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addExpr(MCInst &Inst, const MCExpr *Expr) const { 138814b93851cc7611ae6c2000f1c162592ead954420Chris Lattner // Add as immediates when possible. Null MCExpr = 0. 138914b93851cc7611ae6c2000f1c162592ead954420Chris Lattner if (Expr == 0) 139014b93851cc7611ae6c2000f1c162592ead954420Chris Lattner Inst.addOperand(MCOperand::CreateImm(0)); 139114b93851cc7611ae6c2000f1c162592ead954420Chris Lattner else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 13923483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 13933483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar else 13943483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateExpr(Expr)); 13953483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar } 13963483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 13978462b30548fb5969250858036638c73c16b65b43Daniel Dunbar void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1398345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar assert(N == 2 && "Invalid number of operands!"); 13998462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 140004f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 140104f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegNum)); 14028462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 14038462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 1404fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1405fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1406fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1407fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1408fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 14099b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 14109b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14119b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(getCoproc())); 14129b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 14139b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 14149b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 14159b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14169b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 14179b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 14189b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 141989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITMaskOperands(MCInst &Inst, unsigned N) const { 142089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 142189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 142289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 142389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 142489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 142589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 142689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 142789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 142889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 1429d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach void addCCOutOperands(MCInst &Inst, unsigned N) const { 1430d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1431d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Inst.addOperand(MCOperand::CreateReg(getReg())); 1432d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 1433d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 1434a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby void addRegOperands(MCInst &Inst, unsigned N) const { 1435a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby assert(N == 1 && "Invalid number of operands!"); 1436a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby Inst.addOperand(MCOperand::CreateReg(getReg())); 1437a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1438a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 1439af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1440e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1441430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedReg() && 1442430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedRegOperands() on non RegShiftedReg!"); 1443af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1444af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1445e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Inst.addOperand(MCOperand::CreateImm( 1446af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1447e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 1448e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 1449af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1450152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(N == 2 && "Invalid number of operands!"); 1451430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedImm() && 1452430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedImmOperands() on non RegShiftedImm!"); 1453af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1454b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton // Shift of #32 is encoded as 0 where permitted 1455b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 145692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Inst.addOperand(MCOperand::CreateImm( 1457b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 145892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 145992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 1460580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach void addShifterImmOperands(MCInst &Inst, unsigned N) const { 14610082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(N == 1 && "Invalid number of operands!"); 1462580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1463580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm.Imm)); 14640082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 14650082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 146687f4f9a946549ad93046990a364ac5190333a7ebBill Wendling void addRegListOperands(MCInst &Inst, unsigned N) const { 14677729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling assert(N == 1 && "Invalid number of operands!"); 14685fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 14695fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 14707729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ++I) 14717729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling Inst.addOperand(MCOperand::CreateReg(*I)); 147287f4f9a946549ad93046990a364ac5190333a7ebBill Wendling } 147387f4f9a946549ad93046990a364ac5190333a7ebBill Wendling 14740f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 14750f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 14760f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 14770f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 14780f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 14790f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 14800f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 14810f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 14827e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach void addRotImmOperands(MCInst &Inst, unsigned N) const { 14837e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 14847e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Encoded as val>>3. The printer handles display as 8, 16, 24. 14857e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 14867e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 14877e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 1488293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1489293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1490293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Munge the lsb/width into a bitfield mask. 1491293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned lsb = Bitfield.LSB; 1492293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned width = Bitfield.Width; 1493293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1494293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1495293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach (32 - (lsb + width))); 1496293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Mask)); 1497293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 1498293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 14993483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addImmOperands(MCInst &Inst, unsigned N) const { 15006b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 15016b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach addExpr(Inst, getImm()); 15026b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 15036b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach 15044050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits16Operands(MCInst &Inst, unsigned N) const { 15054050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 15064050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 15074050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 15084050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 15094050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 15104050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits32Operands(MCInst &Inst, unsigned N) const { 15114050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 15124050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 15134050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 15144050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 15154050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 15169d39036f62674606565217a10db28171b9594bc7Jim Grosbach void addFPImmOperands(MCInst &Inst, unsigned N) const { 15179d39036f62674606565217a10db28171b9594bc7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 151851222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 151951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 152051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 15219d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 15229d39036f62674606565217a10db28171b9594bc7Jim Grosbach 1523a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1524a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1525a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // FIXME: We really want to scale the value here, but the LDRD/STRD 1526a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // instruction don't encode operands that way yet. 1527a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1528a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1529a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1530a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 153172f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 153272f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 153372f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 153472f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 153572f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 153672f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 153772f39f8436848885176943b0ba985a7171145423Jim Grosbach } 153872f39f8436848885176943b0ba985a7171145423Jim Grosbach 15394e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 15404e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 15414e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach // The immediate is scaled by four in the encoding and is stored 15424e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach // in the MCInst as such. Lop off the low two bits here. 15434e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 15444e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 15454e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach } 15464e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach 154772f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 154872f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 154972f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 155072f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 155172f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 155272f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 155372f39f8436848885176943b0ba985a7171145423Jim Grosbach } 155472f39f8436848885176943b0ba985a7171145423Jim Grosbach 1555f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1556f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1557f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 1558f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // the bits as encoded, so subtract off one here. 1559f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1560f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1561f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 1562f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach 15634a5ffb399f841783c201c599b88d576757f1922eJim Grosbach void addImm1_32Operands(MCInst &Inst, unsigned N) const { 15644a5ffb399f841783c201c599b88d576757f1922eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 15654a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 15664a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // the bits as encoded, so subtract off one here. 15674a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 15684a5ffb399f841783c201c599b88d576757f1922eJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 15694a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 15704a5ffb399f841783c201c599b88d576757f1922eJim Grosbach 157170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 157270939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 157370939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // The constant encodes as the immediate, except for 32, which encodes as 157470939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // zero. 157570939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 157670939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach unsigned Imm = CE->getValue(); 157770939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1578ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 1579ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 1580f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1581f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1582f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // An ASR value of 32 encodes as 0, so that's how we want to add it to 1583f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // the instruction as well. 1584f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1585f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 1586f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1587f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 1588f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 158989a633708542de5847e807f98f86edfefc9fc019Jim Grosbach void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 159089a633708542de5847e807f98f86edfefc9fc019Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 159189a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // The operand is actually a t2_so_imm, but we have its bitwise 159289a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // negation in the assembly source, so twiddle it here. 159389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 159489a633708542de5847e807f98f86edfefc9fc019Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 159589a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 159689a633708542de5847e807f98f86edfefc9fc019Jim Grosbach 15973bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 15983bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 15993bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a t2_so_imm, but we have its 16003bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 16013bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 16023bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 16033bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 16043bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 16054e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 16064e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 16074e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach // The operand is actually an imm0_4095, but we have its 16084e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach // negation in the assembly source, so twiddle it here. 16094e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 16104e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 16114e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach } 16124e53fe8dc61ad48650ac6fe30d7268ec92b7fc1aJim Grosbach 1613e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1614e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1615e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // The operand is actually a so_imm, but we have its bitwise 1616e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // negation in the assembly source, so twiddle it here. 1617e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1618e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1619e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 1620e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach 16213bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 16223bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 16233bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a so_imm, but we have its 16243bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 16253bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 16263bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 16273bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 16283bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 1629706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1630706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1631706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1632706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 1633706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 16347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 16357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1636e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1637505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 1638505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes 16390b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 16400b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 16410b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach int32_t Imm = Memory.OffsetImm->getValue(); 16420b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // FIXME: Handle #-0 16430b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Imm == INT32_MIN) Imm = 0; 16440b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 16450b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach } 16460b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach 164757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 164857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 164957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 165057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 165157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 165257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 16537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 16547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1655e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1656e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 16577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 16587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 16597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 16607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 16617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 16627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else { 16637ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // For register offset, we encode the shift type and negation flag 16647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // here. 1665e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1666e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory.ShiftImm, Memory.ShiftType); 1667ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1668e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1669e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 16707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1671ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1672ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 1673039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1674039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1675039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1676039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(CE && "non-constant AM2OffsetImm operand!"); 1677039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int32_t Val = CE->getValue(); 1678039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1679039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Special case for #-0 1680039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val == INT32_MIN) Val = 0; 1681039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val < 0) Val = -Val; 1682039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1683039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 1684039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1685039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 1686039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach 16872fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 16882fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 16892f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 16902f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 16912f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 16922f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 16932f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 16942f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 16952f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 16962f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 16972f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 16982f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1699e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1700e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 17012fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 17022fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 17032fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 17042fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 17052fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 17062fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } else { 17072fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // For register offset, we encode the shift type and negation flag 17082fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // here. 1709e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 17102fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 1711e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1712e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 17132fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 17142fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 17152fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 17162fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 17172fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 171821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) { 17192fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = 17202fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 17212fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 17222fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1723251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return; 17242fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 17252fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 17262fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Constant offset. 17272fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 17282fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = CE->getValue(); 17292fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 17302fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 17312fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 17322fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 1733251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 17342fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 17352fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 17362fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 17372fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 17387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 17397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1740681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 1741681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 1742681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 1743681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach if (isImm()) { 1744681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 1745681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1746681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return; 1747681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach } 1748681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach 17497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1750e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 17517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 17527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 17537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 17547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 17557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM5Opc(AddSub, Val); 1756e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 17577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 17587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 17597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 1760a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1761a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 17622f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 17632f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 17642f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 17652f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 17662f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 17672f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 17682f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 17692f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 17702f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1771e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1772e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1773a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1774a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1775a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 1776b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1777b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1778b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1779e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1780e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1781b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1782b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 1783b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 17847ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 17857ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1786e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1787e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 17887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1789ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 1790ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 1791f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1792f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1793f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1794f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach 1795a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1796f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1797a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1798a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1799a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1800a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1801a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // If this is an immediate, it's a label reference. 180221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 1803a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach addExpr(Inst, getImm()); 1804a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1805a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return; 1806a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1807a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1808a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1809e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1810e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1811a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1812a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1813a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 18147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 18157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 181609176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If this is an immediate, it's a label reference. 181721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 181809176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach addExpr(Inst, getImm()); 181909176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 182009176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return; 182109176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach } 182209176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 182309176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1824e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1825e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 18267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 18277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 182892b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 18297f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBBOperands(MCInst &Inst, unsigned N) const { 18307f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1831e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1832e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 18337f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 18347f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 18357f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBHOperands(MCInst &Inst, unsigned N) const { 18367f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1837e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1838e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 18397f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 18407f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 18417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 18427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1843430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach unsigned Val = 1844430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1845430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach Memory.ShiftImm, Memory.ShiftType); 1846e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1847e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 18487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 18497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 1850d3df5f32c059b3ac111f1c08571d5493aa1d48c6Daniel Dunbar 1851ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1852ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1853e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1854e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1855e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1856ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 1857ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach 18587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 18597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1860e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1861e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 186214b93851cc7611ae6c2000f1c162592ead954420Chris Lattner } 18633483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 186460f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 186560f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1866e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1867e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 186860f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 186948ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 187048ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach 187138466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 187238466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1873e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1874e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 187538466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 187638466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 187738466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach 187848ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 187948ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1880e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1881e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 188248ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 188360f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 188460f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach 1885ecd858968384be029574d845eb098d357049e02eJim Grosbach void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1886ecd858968384be029574d845eb098d357049e02eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1887e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1888e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1889ecd858968384be029574d845eb098d357049e02eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1890ecd858968384be029574d845eb098d357049e02eJim Grosbach } 1891ecd858968384be029574d845eb098d357049e02eJim Grosbach 18927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 18937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(CE && "non-constant post-idx-imm8 operand!"); 18967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Imm = CE->getValue(); 18977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAdd = Imm >= 0; 189863553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson if (Imm == INT32_MIN) Imm = 0; 18997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 19007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1901f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1902ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 19032bd0118472de352745a2e038245fab4974f7c87eJim Grosbach void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 19042bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 19052bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 19062bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(CE && "non-constant post-idx-imm8s4 operand!"); 19072bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int Imm = CE->getValue(); 19082bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isAdd = Imm >= 0; 19092bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (Imm == INT32_MIN) Imm = 0; 19102bd0118472de352745a2e038245fab4974f7c87eJim Grosbach // Immediate is scaled by 4. 19112bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 19122bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 19132bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 19142bd0118472de352745a2e038245fab4974f7c87eJim Grosbach 19157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 19167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 19177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1918f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1919f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 1920f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 1921f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1922f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1923f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1924f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // The sign, shift type, and shift amount are encoded in a single operand 1925f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // using the AM2 encoding helpers. 1926f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1927f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1928f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach PostIdxReg.ShiftTy); 1929f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1930ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 1931ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 1932584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1933584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1934584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1935584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 1936584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 1937a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1938a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1939a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1940a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 1941a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 19426029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach void addVecListOperands(MCInst &Inst, unsigned N) const { 1943862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1944862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1945862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1946862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 19477636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 19487636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 19497636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 19507636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 19517636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 19527636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1953460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1954460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1955460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1956460a90540b045c102012da2492999557e6840526Jim Grosbach } 1957460a90540b045c102012da2492999557e6840526Jim Grosbach 1958460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1959460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1960460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1961460a90540b045c102012da2492999557e6840526Jim Grosbach } 1962460a90540b045c102012da2492999557e6840526Jim Grosbach 1963460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1964460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1965460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1966460a90540b045c102012da2492999557e6840526Jim Grosbach } 1967460a90540b045c102012da2492999557e6840526Jim Grosbach 19680e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 19690e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 19700e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // The immediate encodes the type of constant as well as the value. 19710e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Mask in that this is an i8 splat. 19720e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 19730e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 19740e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 19750e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 1976ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1977ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1978ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // The immediate encodes the type of constant as well as the value. 1979ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1980ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach unsigned Value = CE->getValue(); 1981ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (Value >= 256) 1982ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value = (Value >> 8) | 0xa00; 1983ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach else 1984ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value |= 0x800; 1985ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 1986ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1987ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 19886248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 19896248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 19906248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 19916248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 19926248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 19936248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xff00) 19946248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | 0x200; 19956248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xff0000) 19966248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | 0x400; 19976248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 19986248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 19996248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 20006248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 20016248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 20026248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 20036248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 20046248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 20056248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 20066248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 20076248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xffff) 20086248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 20096248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 20106248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 20116248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 20126248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 20139b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 20149b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 20159b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach 20169b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 20179b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 20189b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // The immediate encodes the type of constant as well as the value. 20199b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 20209b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach unsigned Value = ~CE->getValue(); 20219b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (Value >= 256 && Value <= 0xffff) 20229b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 20239b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 20249b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 20259b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffffff) 20269b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 24) | 0x600; 20276248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 20286248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 20296248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 2030f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2031f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 2032f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // The immediate encodes the type of constant as well as the value. 2033f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2034f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 2035f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach unsigned Imm = 0; 2036f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2037f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Imm |= (Value & 1) << i; 2038f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 2039f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2040f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 2041f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 2042b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbach virtual void print(raw_ostream &OS) const; 2043b3cb6967949493a2e1b10d015ac08b746736764eDaniel Dunbar 204489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 204521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ITCondMask); 204689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->ITMask.Mask = Mask; 204789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->StartLoc = S; 204889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->EndLoc = S; 204989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return Op; 205089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 205189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 20523a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 205321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CondCode); 2054345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->CC.Val = CC; 2055345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->StartLoc = S; 2056345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->EndLoc = S; 20573a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2058345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar } 2059345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 2060fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 206121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocNum); 2062fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 2063fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 2064fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 2065fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 2066fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 2067fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2068fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 206921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocReg); 2070fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 2071fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 2072fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 2073fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 2074fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 2075fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 20769b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 20779b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocOption); 20789b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->Cop.Val = Val; 20799b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->StartLoc = S; 20809b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->EndLoc = E; 20819b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return Op; 20829b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 20839b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 2084d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 208521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CCOut); 2086d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->Reg.RegNum = RegNum; 2087d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->StartLoc = S; 2088d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->EndLoc = S; 2089d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach return Op; 2090d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 2091d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 20923a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 209321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Token); 2094762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Data = Str.data(); 2095762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Length = Str.size(); 2096762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2097762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = S; 20983a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2099a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 2100a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 210150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 210221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Register); 2103762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Reg.RegNum = RegNum; 2104762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2105762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 21063a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2107a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 2108a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2109e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2110e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg, 2111e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg, 2112e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm, 2113e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc S, SMLoc E) { 211421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2115af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftTy = ShTy; 2116af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.SrcReg = SrcReg; 2117af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftReg = ShiftReg; 2118af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftImm = ShiftImm; 2119e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->StartLoc = S; 2120e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->EndLoc = E; 2121e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Op; 2122e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2123e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 212492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 212592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg, 212692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm, 212792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson SMLoc S, SMLoc E) { 212821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2129af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftTy = ShTy; 2130af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.SrcReg = SrcReg; 2131af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftImm = ShiftImm; 213292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->StartLoc = S; 213392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->EndLoc = E; 213492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson return Op; 213592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 213692a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 2137580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 21380082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S, SMLoc E) { 213921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2140580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.isASR = isASR; 2141580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.Imm = Imm; 21420082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->StartLoc = S; 21430082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->EndLoc = E; 21440082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return Op; 21450082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 21460082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 21477e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 214821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_RotateImmediate); 21497e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->RotImm.Imm = Imm; 21507e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->StartLoc = S; 21517e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->EndLoc = E; 21527e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return Op; 21537e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 21547e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 2155293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2156293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S, SMLoc E) { 215721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2158293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.LSB = LSB; 2159293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.Width = Width; 2160293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->StartLoc = S; 2161293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->EndLoc = E; 2162293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return Op; 2163293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 2164293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 21657729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling static ARMOperand * 21665fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2167cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay SMLoc StartLoc, SMLoc EndLoc) { 216821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach KindTy Kind = k_RegisterList; 21690f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 2170d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 217121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_DPRRegisterList; 2172d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2173275944afb55086d0b4b20d4d831de7c1c7507925Evan Cheng contains(Regs.front().first)) 217421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_SPRRegisterList; 21750f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 21760f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling ARMOperand *Op = new ARMOperand(Kind); 21775fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 21787729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = Regs.begin(), E = Regs.end(); I != E; ++I) 217924d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Op->Registers.push_back(I->first); 2180cb21d1c9fd1cf53f063183f7eb28af7fa4052ef0Bill Wendling array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2181cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->StartLoc = StartLoc; 2182cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->EndLoc = EndLoc; 21838d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling return Op; 21848d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 21858d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 2186862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 21870aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced, SMLoc S, SMLoc E) { 2188862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorList); 2189862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.RegNum = RegNum; 2190862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.Count = Count; 21910aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2192862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->StartLoc = S; 2193862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->EndLoc = E; 2194862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return Op; 2195862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 2196862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 219798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 21983471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpaced, 219998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc S, SMLoc E) { 220098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 220198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.RegNum = RegNum; 220298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.Count = Count; 22033471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 220498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->StartLoc = S; 220598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->EndLoc = E; 220698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Op; 220798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 220898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 22097636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 221095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Index, 221195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpaced, 221295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach SMLoc S, SMLoc E) { 22137636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 22147636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.RegNum = RegNum; 22157636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.Count = Count; 22167636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.LaneIndex = Index; 221795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 22187636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->StartLoc = S; 22197636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->EndLoc = E; 22207636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return Op; 22217636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 22227636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 2223460a90540b045c102012da2492999557e6840526Jim Grosbach static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2224460a90540b045c102012da2492999557e6840526Jim Grosbach MCContext &Ctx) { 2225460a90540b045c102012da2492999557e6840526Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorIndex); 2226460a90540b045c102012da2492999557e6840526Jim Grosbach Op->VectorIndex.Val = Idx; 2227460a90540b045c102012da2492999557e6840526Jim Grosbach Op->StartLoc = S; 2228460a90540b045c102012da2492999557e6840526Jim Grosbach Op->EndLoc = E; 2229460a90540b045c102012da2492999557e6840526Jim Grosbach return Op; 2230460a90540b045c102012da2492999557e6840526Jim Grosbach } 2231460a90540b045c102012da2492999557e6840526Jim Grosbach 22323a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 223321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Immediate); 2234762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Imm.Val = Val; 2235762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2236762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 22373a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2238cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 2239cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 22407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach static ARMOperand *CreateMem(unsigned BaseRegNum, 22417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm, 22427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum, 22437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType, 22440d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm, 224557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment, 22467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative, 22473a69756e392942bc522193f38d7f33958ed3b131Chris Lattner SMLoc S, SMLoc E) { 224821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Memory); 2249e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.BaseRegNum = BaseRegNum; 2250e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetImm = OffsetImm; 2251e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetRegNum = OffsetRegNum; 2252e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftType = ShiftType; 2253e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftImm = ShiftImm; 225457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Op->Memory.Alignment = Alignment; 2255e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.isNegative = isNegative; 22567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->StartLoc = S; 22577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->EndLoc = E; 22587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Op; 22597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 226016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2261f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2262f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy, 2263f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm, 22647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S, SMLoc E) { 226521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 22667ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->PostIdxReg.RegNum = RegNum; 2267f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.isAdd = isAdd; 2268f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftTy = ShiftTy; 2269f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftImm = ShiftImm; 2270762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2271762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 22723a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2273a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 2274706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 2275706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 227621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2277706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->MBOpt.Val = Opt; 2278706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->StartLoc = S; 2279706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->EndLoc = S; 2280706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return Op; 2281706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 2282a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 2283a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 228421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2285a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->IFlags.Val = IFlags; 2286a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->StartLoc = S; 2287a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->EndLoc = S; 2288a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return Op; 2289a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 2290584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 2291584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 229221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MSRMask); 2293584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->MMask.Val = MMask; 2294584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->StartLoc = S; 2295584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->EndLoc = S; 2296584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return Op; 2297584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 2298a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby}; 2299a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2300a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} // end anonymous namespace. 2301a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2302b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbachvoid ARMOperand::print(raw_ostream &OS) const { 2303fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar switch (Kind) { 230421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 23056a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2306fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 230721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 2308d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach OS << "<ccout " << getReg() << ">"; 2309d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach break; 231021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: { 2311032f441afcdd70eb6bda477d32e8c372443b4e6fCraig Topper static const char *const MaskStr[] = { 23121a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 23131a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 23141a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer }; 231589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert((ITMask.Mask & 0xf) == ITMask.Mask); 231689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 231789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 231889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 231921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 2320fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor number: " << getCoproc() << ">"; 2321fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 232221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 2323fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor register: " << getCoproc() << ">"; 2324fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 23259b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 23269b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OS << "<coprocessor option: " << CoprocOption.Val << ">"; 23279b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 232821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 2329584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes OS << "<mask: " << getMSRMask() << ">"; 2330584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 233121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 2332fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar getImm()->print(OS); 2333fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 233421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 2335706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2336706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 233721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 23386ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << "<memory " 2339e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach << " base:" << Memory.BaseRegNum; 23406ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << ">"; 2341fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 234221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 2343f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2344f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.RegNum; 2345f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2346f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2347f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.ShiftImm; 2348f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ">"; 23497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 235021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: { 2351a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << "<ARM_PROC::"; 2352a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = getProcIFlags(); 2353a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes for (int i=2; i >= 0; --i) 2354a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IFlags & (1 << i)) 2355a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ARM_PROC::IFlagsToString(1 << i); 2356a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ">"; 2357a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes break; 2358a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 235921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 236050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling OS << "<register " << getReg() << ">"; 2361fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 236221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 2363580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2364580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach << " #" << ShifterImm.Imm << ">"; 2365e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 236621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 236792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_reg " 2368efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedReg.SrcReg << " " 2369efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2370efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " " << RegShiftedReg.ShiftReg << ">"; 23710082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 237221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 237392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_imm " 2374efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedImm.SrcReg << " " 2375efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2376efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " #" << RegShiftedImm.ShiftImm << ">"; 237792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 237821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 23797e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 23807e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 238121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 2382293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OS << "<bitfield " << "lsb: " << Bitfield.LSB 2383293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach << ", width: " << Bitfield.Width << ">"; 2384293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 238521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 238621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 238721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: { 23888d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << "<register_list "; 23898d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 23905fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 23915fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 23927729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ) { 23937729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling OS << *I; 23947729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling if (++I < E) OS << ", "; 23958d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 23968d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 23978d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << ">"; 23988d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 23998d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 2400862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 2401862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OS << "<vector_list " << VectorList.Count << " * " 2402862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach << VectorList.RegNum << ">"; 2403862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 240498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 240598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach OS << "<vector_list(all lanes) " << VectorList.Count << " * " 240698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach << VectorList.RegNum << ">"; 240798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 24087636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 24097636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 24107636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach << VectorList.Count << " * " << VectorList.RegNum << ">"; 24117636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 241221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 2413fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar OS << "'" << getToken() << "'"; 2414fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 2415460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 2416460a90540b045c102012da2492999557e6840526Jim Grosbach OS << "<vectorindex " << getVectorIndex() << ">"; 2417460a90540b045c102012da2492999557e6840526Jim Grosbach break; 2418fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar } 2419fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar} 24203483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 24213483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// @name Auto-generated Match Functions 24223483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// { 24233483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 24243483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbarstatic unsigned MatchRegisterName(StringRef Name); 24253483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 24263483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// } 24273483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 242869df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilsonbool ARMAsmParser::ParseRegister(unsigned &RegNo, 242969df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson SMLoc &StartLoc, SMLoc &EndLoc) { 2430a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StartLoc = Parser.getTok().getLoc(); 24311355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach RegNo = tryParseRegister(); 2432a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach EndLoc = Parser.getTok().getLoc(); 2433bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 2434bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky return (RegNo == (unsigned)-1); 2435bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky} 2436bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 24379c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Try to parse a register name. The token must be an Identifier when called, 2438e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// and if it is a register name the token is eaten and the register number is 2439e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// returned. Otherwise return -1. 24403a69756e392942bc522193f38d7f33958ed3b131Chris Lattner/// 24411355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachint ARMAsmParser::tryParseRegister() { 244218b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 24437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) return -1; 2444d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 2445590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 24460c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson unsigned RegNum = MatchRegisterName(lowerCase); 24470c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson if (!RegNum) { 24480c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson RegNum = StringSwitch<unsigned>(lowerCase) 24490c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r13", ARM::SP) 24500c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r14", ARM::LR) 24510c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r15", ARM::PC) 24520c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("ip", ARM::R12) 245340e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach // Additional register name aliases for 'gas' compatibility. 245440e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a1", ARM::R0) 245540e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a2", ARM::R1) 245640e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a3", ARM::R2) 245740e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a4", ARM::R3) 245840e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v1", ARM::R4) 245940e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v2", ARM::R5) 246040e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v3", ARM::R6) 246140e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v4", ARM::R7) 246240e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v5", ARM::R8) 246340e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v6", ARM::R9) 246440e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v7", ARM::R10) 246540e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v8", ARM::R11) 246640e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sb", ARM::R9) 246740e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sl", ARM::R10) 246840e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("fp", ARM::R11) 24690c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Default(0); 24700c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson } 2471a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (!RegNum) { 2472aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // Check for aliases registered via .req. Canonicalize to lower case. 2473aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // That's more consistent since register names are case insensitive, and 2474aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // it's how the original entry was passed in from MC/MCParser/AsmParser. 2475aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2476a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // If no match, return failure. 2477a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Entry == RegisterReqs.end()) 2478a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return -1; 2479a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat identifier token. 2480a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Entry->getValue(); 2481a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 248269df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson 2483b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat identifier token. 2484460a90540b045c102012da2492999557e6840526Jim Grosbach 2485e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner return RegNum; 2486e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner} 2487d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 248819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 248919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// If a recoverable error occurs, return 1. If an irrecoverable error 249019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// occurs, return -1. An irrecoverable error is one where tokens have been 249119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// consumed in the process of trying to parse the shifter (i.e., when it is 249219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// indeed a shifter operand, but malformed). 24930d87ec21d79c8622733b8367aa41067169602480Jim Grosbachint ARMAsmParser::tryParseShiftRegister( 24940082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 24950082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 24960082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson const AsmToken &Tok = Parser.getTok(); 24970082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 24980082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2499590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 25000082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2501af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach .Case("asl", ARM_AM::lsl) 25020082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsl", ARM_AM::lsl) 25030082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsr", ARM_AM::lsr) 25040082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("asr", ARM_AM::asr) 25050082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("ror", ARM_AM::ror) 25060082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("rrx", ARM_AM::rrx) 25070082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Default(ARM_AM::no_shift); 25080082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 25090082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson if (ShiftTy == ARM_AM::no_shift) 251019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 1; 25110082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2512e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat the operator. 2513e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 2514e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The source register for the shift has already been added to the 2515e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // operand list, so we need to pop it off and combine it into the shifted 2516e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // register operand instead. 2517eac0796542d098caa371856d545faa6cdab5aad3Benjamin Kramer OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2518e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (!PrevOp->isReg()) 2519e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2520e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int SrcReg = PrevOp->getReg(); 2521e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int64_t Imm = 0; 2522e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int ShiftReg = 0; 2523e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (ShiftTy == ARM_AM::rrx) { 2524e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // RRX Doesn't have an explicit shift amount. The encoder expects 2525e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // the shift register to be the same as the source register. Seems odd, 2526e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // but OK. 2527e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ShiftReg = SrcReg; 2528e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else { 2529e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Figure out if this is shifted by a constant or a register (for non-RRX). 25308a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 25318a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 2532e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat hash. 2533e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc ImmLoc = Parser.getTok().getLoc(); 2534e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCExpr *ShiftExpr = 0; 253519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (getParser().ParseExpression(ShiftExpr)) { 253619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 253719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 253819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2539e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The expression must be evaluatable as an immediate. 2540e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 254119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (!CE) { 254219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 254319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 254419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2545e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Range check the immediate. 2546e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsl, ror: 0 <= imm <= 31 2547e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsr, asr: 0 <= imm <= 32 2548e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Imm = CE->getValue(); 2549e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (Imm < 0 || 2550e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2551e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 255219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "immediate shift value out of range"); 255319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 2554e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2555de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // shift by zero is a nop. Always send it through as lsl. 2556de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // ('as' compatibility) 2557de626ad8726677328e10dbdc15011254214437d7Jim Grosbach if (Imm == 0) 2558de626ad8726677328e10dbdc15011254214437d7Jim Grosbach ShiftTy = ARM_AM::lsl; 2559e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else if (Parser.getTok().is(AsmToken::Identifier)) { 25601355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach ShiftReg = tryParseRegister(); 2561e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc L = Parser.getTok().getLoc(); 256219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (ShiftReg == -1) { 256319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (L, "expected immediate or register in shift operand"); 256419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 256519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 256619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } else { 256719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (Parser.getTok().getLoc(), 2568e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach "expected immediate or register in shift operand"); 256919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 257019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2571e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2572e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 257392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson if (ShiftReg && ShiftTy != ARM_AM::rrx) 257492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2575af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ShiftReg, Imm, 25760082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson S, Parser.getTok().getLoc())); 257792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson else 257892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 257992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson S, Parser.getTok().getLoc())); 25800082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 258119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 0; 25820082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson} 25830082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 25840082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 258550d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// Try to parse a register name. The token must be an Identifier when called. 258650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// If it's a register, an AsmOperand is created. Another AsmOperand is created 258750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// if there is a "writeback". 'true' if it's not a register. 2588e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// 2589e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// TODO this is likely to change to allow different register types and or to 2590e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// parse for a specific register type. 259150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 25921355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachtryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2593e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner SMLoc S = Parser.getTok().getLoc(); 25941355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int RegNo = tryParseRegister(); 2595e717610f53e0465cde198536561a3c00ce29d59fBill Wendling if (RegNo == -1) 259650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 2597d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 259850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2599a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2600e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner const AsmToken &ExclaimTok = Parser.getTok(); 2601e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner if (ExclaimTok.is(AsmToken::Exclaim)) { 260250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 260350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling ExclaimTok.getLoc())); 2604e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner Parser.Lex(); // Eat exclaim token 2605460a90540b045c102012da2492999557e6840526Jim Grosbach return false; 2606460a90540b045c102012da2492999557e6840526Jim Grosbach } 2607460a90540b045c102012da2492999557e6840526Jim Grosbach 2608460a90540b045c102012da2492999557e6840526Jim Grosbach // Also check for an index operand. This is only legal for vector registers, 2609460a90540b045c102012da2492999557e6840526Jim Grosbach // but that'll get caught OK in operand matching, so we don't need to 2610460a90540b045c102012da2492999557e6840526Jim Grosbach // explicitly filter everything else out here. 2611460a90540b045c102012da2492999557e6840526Jim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 2612460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc SIdx = Parser.getTok().getLoc(); 2613460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat left bracket token. 2614460a90540b045c102012da2492999557e6840526Jim Grosbach 2615460a90540b045c102012da2492999557e6840526Jim Grosbach const MCExpr *ImmVal; 2616460a90540b045c102012da2492999557e6840526Jim Grosbach if (getParser().ParseExpression(ImmVal)) 261724dda217052b48373ed89d043a778aabb2f65080Jim Grosbach return true; 2618460a90540b045c102012da2492999557e6840526Jim Grosbach const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2619ef4d3ebe2a36ebfd9370e1efbe74dff13f64c40fJim Grosbach if (!MCE) 2620ef4d3ebe2a36ebfd9370e1efbe74dff13f64c40fJim Grosbach return TokError("immediate value expected for vector index"); 2621460a90540b045c102012da2492999557e6840526Jim Grosbach 2622460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2623ef4d3ebe2a36ebfd9370e1efbe74dff13f64c40fJim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 2624ef4d3ebe2a36ebfd9370e1efbe74dff13f64c40fJim Grosbach return Error(E, "']' expected"); 2625460a90540b045c102012da2492999557e6840526Jim Grosbach 2626460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat right bracket token. 2627460a90540b045c102012da2492999557e6840526Jim Grosbach 2628460a90540b045c102012da2492999557e6840526Jim Grosbach Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2629460a90540b045c102012da2492999557e6840526Jim Grosbach SIdx, E, 2630460a90540b045c102012da2492999557e6840526Jim Grosbach getContext())); 263199e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby } 263299e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby 263350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2634a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 2635a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2636fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2637fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2638fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// "c5", ... 2639fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopesstatic int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2640e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Use the same layout as the tablegen'erated register name matcher. Ugly, 2641e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // but efficient. 2642e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name.size()) { 26434d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie default: return -1; 2644e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 2: 2645fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp) 2646e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2647e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[1]) { 2648e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2649e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 0; 2650e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 1; 2651e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 2; 2652e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 3; 2653e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 4; 2654e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 5; 2655e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '6': return 6; 2656e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '7': return 7; 2657e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '8': return 8; 2658e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '9': return 9; 2659e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2660e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 3: 2661fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp || Name[1] != '1') 2662e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2663e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[2]) { 2664e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2665e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 10; 2666e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 11; 2667e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 12; 2668e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 13; 2669e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 14; 2670e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 15; 2671e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2672e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2673e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2674e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 267589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach/// parseITCondCode - Try to parse a condition code for an IT instruction. 267689df996ab20609676ecc8823f58414d598b09b46Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 267789df996ab20609676ecc8823f58414d598b09b46Jim GrosbachparseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 267889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 267989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach const AsmToken &Tok = Parser.getTok(); 268089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (!Tok.is(AsmToken::Identifier)) 268189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 268204a09a461beb4ec629fe53e601b7665547ac35c3Richard Barton unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 268389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("eq", ARMCC::EQ) 268489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ne", ARMCC::NE) 268589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hs", ARMCC::HS) 268689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cs", ARMCC::HS) 268789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lo", ARMCC::LO) 268889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cc", ARMCC::LO) 268989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("mi", ARMCC::MI) 269089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("pl", ARMCC::PL) 269189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vs", ARMCC::VS) 269289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vc", ARMCC::VC) 269389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hi", ARMCC::HI) 269489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ls", ARMCC::LS) 269589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ge", ARMCC::GE) 269689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lt", ARMCC::LT) 269789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("gt", ARMCC::GT) 269889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("le", ARMCC::LE) 269989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("al", ARMCC::AL) 270089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Default(~0U); 270189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (CC == ~0U) 270289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 270389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.Lex(); // Eat the token. 270489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 270589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 270689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 270789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_Success; 270889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach} 270989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 271043904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2711fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2712fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2713f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 271443904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2715e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 2716e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson const AsmToken &Tok = Parser.getTok(); 2717c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2718c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2719e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2720fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2721e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson if (Num == -1) 2722f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2723e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2724e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson Parser.Lex(); // Eat identifier token. 2725fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2726f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2727fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes} 2728fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 272943904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2730fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2731fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2732f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 273343904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2734fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 2735fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 2736c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2737c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2738fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2739fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2740fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Reg == -1) 2741f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2742fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2743fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 2744fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2745f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2746e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2747e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 27489b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 27499b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// coproc_option : '{' imm0_255 '}' 27509b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 27519b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachparseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 27529b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc S = Parser.getTok().getLoc(); 27539b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 27549b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // If this isn't a '{', this isn't a coprocessor immediate operand. 27559b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 27569b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_NoMatch; 27579b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '{' 27589b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 27599b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCExpr *Expr; 27609b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 27619b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (getParser().ParseExpression(Expr)) { 27629b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "illegal expression"); 27639b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 27649b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 27659b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 27669b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 27679b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 27689b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 27699b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 27709b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach int Val = CE->getValue(); 27719b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 27729b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // Check for and consume the closing '}' 27739b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 27749b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 27759b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc E = Parser.getTok().getLoc(); 27769b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '}' 27779b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 27789b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 27799b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_Success; 27809b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach} 27819b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 2782d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// For register list parsing, we need to map from raw GPR register numbering 2783d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// to the enumeration values. The enumeration values aren't sorted by 2784d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// register number due to our using "sp", "lr" and "pc" as canonical names. 2785d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbachstatic unsigned getNextRegister(unsigned Reg) { 2786d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If this is a GPR, we need to do it manually, otherwise we can rely 2787d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // on the sort ordering of the enumeration since the other reg-classes 2788d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // are sane. 2789d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2790d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Reg + 1; 2791d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach switch(Reg) { 2792bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Invalid GPR number!"); 2793d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2794d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2795d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2796d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2797d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2798d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2799d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2800d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2801d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2802d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach} 2803d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2804ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach// Return the low-subreg of a given Q register. 2805ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbachstatic unsigned getDRegFromQReg(unsigned QReg) { 2806ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach switch (QReg) { 2807ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach default: llvm_unreachable("expected a Q register!"); 2808ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q0: return ARM::D0; 2809ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q1: return ARM::D2; 2810ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q2: return ARM::D4; 2811ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q3: return ARM::D6; 2812ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q4: return ARM::D8; 2813ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q5: return ARM::D10; 2814ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q6: return ARM::D12; 2815ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q7: return ARM::D14; 2816ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q8: return ARM::D16; 281725e0a87e9190cdca62aee5ac95cfc8ef44f35e92Jim Grosbach case ARM::Q9: return ARM::D18; 2818ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q10: return ARM::D20; 2819ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q11: return ARM::D22; 2820ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q12: return ARM::D24; 2821ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q13: return ARM::D26; 2822ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q14: return ARM::D28; 2823ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q15: return ARM::D30; 2824ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2825ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach} 2826ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2827d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach/// Parse a register list. 282850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 28291355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachparseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 283018b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LCurly) && 2831a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Curly Brace"); 2832e717610f53e0465cde198536561a3c00ce29d59fBill Wendling SMLoc S = Parser.getTok().getLoc(); 2833d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '{' token. 2834d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 283516c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2836d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Check the first register in the list to see what register class 2837d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // this is a list of. 2838d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int Reg = tryParseRegister(); 2839d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 2840d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "register expected"); 2841d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2842ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // The reglist instructions have at most 16 registers, so reserve 2843ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // space for that many. 2844ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2845ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2846ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2847ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2848ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2849ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2850ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach ++Reg; 2851ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 28521a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCRegisterClass *RC; 2853d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2854d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2855d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2856d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2857d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2858d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2859d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else 2860d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2861e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 2862ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Store the register. 2863d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2864d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2865d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // This starts immediately after the first register token in the list, 2866d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // so we can see either a comma or a minus (range separator) as a legal 2867d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // next token. 2868d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 2869d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 2870d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 2871e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 2872d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 2873d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int EndReg = tryParseRegister(); 2874d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (EndReg == -1) 2875d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "register expected"); 2876ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2877ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2878ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 2879d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If the register is the same as the start reg, there's nothing 2880d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // more to do. 2881d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == EndReg) 2882d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2883d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2884d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(EndReg)) 2885d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "invalid register in register list"); 2886d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Ranges must go from low to high. 2887d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2888d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "bad range in register list"); 2889d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2890d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Add all the registers in the range to the register list. 2891d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Reg != EndReg) { 2892d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = getNextRegister(Reg); 2893d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2894d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2895d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2896d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2897d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat the comma. 2898d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RegLoc = Parser.getTok().getLoc(); 2899d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int OldReg = Reg; 2900a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach const AsmToken RegTok = Parser.getTok(); 2901d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = tryParseRegister(); 2902d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 29032d539691a1e4b9d61853aa99d1a5580dc88595dbJim Grosbach return Error(RegLoc, "register expected"); 2904ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2905ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach bool isQReg = false; 2906ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2907ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2908ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach isQReg = true; 2909ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2910d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2911d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(Reg)) 2912d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2913d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // List must be monotonically increasing. 2914be7cf2b377d987f46d10f54f89ae4e1a71c37f55Jim Grosbach if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) { 2915be7cf2b377d987f46d10f54f89ae4e1a71c37f55Jim Grosbach if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2916be7cf2b377d987f46d10f54f89ae4e1a71c37f55Jim Grosbach Warning(RegLoc, "register list not in ascending order"); 2917be7cf2b377d987f46d10f54f89ae4e1a71c37f55Jim Grosbach else 2918be7cf2b377d987f46d10f54f89ae4e1a71c37f55Jim Grosbach return Error(RegLoc, "register list not in ascending order"); 2919be7cf2b377d987f46d10f54f89ae4e1a71c37f55Jim Grosbach } 2920a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) { 2921a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2922a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach ") in register list"); 2923a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach continue; 2924a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach } 2925d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register lists must also be contiguous. 2926d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // It's OK to use the enumeration values directly here rather, as the 2927d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register classes have the enum sorted properly. 2928d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2929d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg != OldReg + 1) 2930d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "non-contiguous register range"); 2931d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2932ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (isQReg) 2933ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2934d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2935d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2936d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2937d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 2938d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(E, "'}' expected"); 2939d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '}' token. 2940e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 294127debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // Push the register list operand. 294250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 294327debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 294427debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // The ARM system instruction variants for LDM/STM have a '^' token here. 294527debd60a152d39e421c57bce511f16d8439a670Jim Grosbach if (Parser.getTok().is(AsmToken::Caret)) { 294627debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 294727debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Parser.Lex(); // Eat '^' token. 294827debd60a152d39e421c57bce511f16d8439a670Jim Grosbach } 294927debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 295050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2951d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby} 2952d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby 295398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach// Helper function to parse the lane index for vector lists. 295498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 29557636bf6530fd83bf7356ae3894246a4e558741a4Jim GrosbachparseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 29567636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Index = 0; // Always return a defined index value. 295798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 295898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the '['. 295998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::RBrac)) { 296098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // "Dn[]" is the 'all lanes' syntax. 296198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = AllLanes; 296298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the ']'. 296398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 296498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 2965ceee984302a1cf1d659a186cf94149c779866da5Jim Grosbach 2966ceee984302a1cf1d659a186cf94149c779866da5Jim Grosbach // There's an optional '#' token here. Normally there wouldn't be, but 2967ceee984302a1cf1d659a186cf94149c779866da5Jim Grosbach // inline assemble puts one in, and it's friendly to accept that. 2968ceee984302a1cf1d659a186cf94149c779866da5Jim Grosbach if (Parser.getTok().is(AsmToken::Hash)) 2969ceee984302a1cf1d659a186cf94149c779866da5Jim Grosbach Parser.Lex(); // Eat the '#' 2970ceee984302a1cf1d659a186cf94149c779866da5Jim Grosbach 2971c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCExpr *LaneIndex; 2972c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 2973c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (getParser().ParseExpression(LaneIndex)) { 2974c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "illegal expression"); 2975c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 29767636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 2977c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 2978c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (!CE) { 2979c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "lane index must be empty or an integer"); 2980c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2981c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2982c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) { 2983c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "']' expected"); 2984c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2985c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2986c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Parser.Lex(); // Eat the ']'. 2987c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach int64_t Val = CE->getValue(); 2988c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach 2989c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach // FIXME: Make this range check context sensitive for .8, .16, .32. 2990c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Val < 0 || Val > 7) { 2991c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "lane index out of range"); 2992c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2993c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2994c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Index = Val; 2995c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach LaneKind = IndexedLane; 2996c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_Success; 299798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 299898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = NoLanes; 299998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 300098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach} 300198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 3002862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach// parse a vector register list 3003862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3004862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachparseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 300598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy LaneKind; 30067636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 30075c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc S = Parser.getTok().getLoc(); 30085c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // As an extension (to match gas), support a plain D register or Q register 30095c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // (without encosing curly braces) as a single or double entry list, 30105c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // respectively. 30115c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) { 30125c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach int Reg = tryParseRegister(); 30135c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Reg == -1) 30145c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_NoMatch; 30155c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 30165c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 30177636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 301898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 301998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 302098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 302198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 302298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 30230aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 302498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 302598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 302698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 30273471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 30283471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 302998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 30307636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 30317636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 303295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 303395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 30347636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 303598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 30365c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 30375c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 30385c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 30395c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Reg = getDRegFromQReg(Reg); 30407636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 304198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 304298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 304398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 304498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 304598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 304628f08c93e75d291695ea89b9004145103292e85bJim Grosbach Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3047c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach &ARMMCRegisterClasses[ARM::DPairRegClassID]); 30480aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 304998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 305098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 305198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 3052c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3053c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach &ARMMCRegisterClasses[ARM::DPairRegClassID]); 30543471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 30553471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 305698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 30577636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 30587636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 305995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 306095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 30617636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 306298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 30635c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 30645c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 30655c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Error(S, "vector register expected"); 30665c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_ParseFail; 30675c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 30685c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach 30695c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 3070862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_NoMatch; 3071862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3072862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '{' token. 3073862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 3074862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3075862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int Reg = tryParseRegister(); 3076862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 3077862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 3078862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3079862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3080862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count = 1; 3081276ed0344c05822617934fa4a6a9920d864193a5Jim Grosbach int Spacing = 0; 3082c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach unsigned FirstReg = Reg; 3083c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 3084c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 3085c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3086c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach FirstReg = Reg = getDRegFromQReg(Reg); 30870aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // double-spacing requires explicit D registers, otherwise 30880aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // it's ambiguous with four-register single spaced. 3089c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 3090c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Count; 3091c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 30927636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 309398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 3094c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach 3095e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 3096e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 3097e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 30980aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 30990aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 31000aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 31010aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(Parser.getTok().getLoc(), 31020aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "sequential registers in double spaced list"); 31030aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 31040aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 3105e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 3106e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 3107e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach int EndReg = tryParseRegister(); 3108e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (EndReg == -1) { 3109e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "register expected"); 3110e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 3111e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 3112e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 3113e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3114e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 3115e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // If the register is the same as the start reg, there's nothing 3116e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // more to do. 3117e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg == EndReg) 3118e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 3119e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // The register must be in the same register class as the first. 3120e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3121e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "invalid register in register list"); 3122e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 3123e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 3124e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Ranges must go from low to high. 3125e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg > EndReg) { 3126e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "bad range in register list"); 3127e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 3128e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 312998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 313098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 31317636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 31327636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 313398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 31347636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 313598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 313698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 313798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 313898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach EndLoc = Parser.getTok().getLoc(); 3139e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach 3140e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Add all the registers in the range to the register list. 3141e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Count += EndReg - Reg; 3142e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Reg = EndReg; 3143e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 3144e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 3145862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat the comma. 3146862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach RegLoc = Parser.getTok().getLoc(); 3147862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int OldReg = Reg; 3148862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Reg = tryParseRegister(); 3149862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 3150862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 3151862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3152862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3153c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // vector register lists must be contiguous. 3154862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // It's OK to use the enumeration values directly here rather, as the 3155862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // VFP register classes have the enum sorted properly. 3156c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // 3157c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 3158c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 3159c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 31600aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 31610aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 31620aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 31630aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(RegLoc, 31640aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "invalid register in double-spaced list (must be 'D' register')"); 31650aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 31660aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 3167c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Reg = getDRegFromQReg(Reg); 3168c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (Reg != OldReg + 1) { 3169c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Error(RegLoc, "non-contiguous register range"); 3170c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach return MatchOperand_ParseFail; 3171c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 3172c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 3173c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Count += 2; 317498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 317598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 31767636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 317798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 31787636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 317998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 31807636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 318198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 318298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 318398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3184c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach continue; 3185c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 31860aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Normal D register. 31870aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Figure out the register spacing (single or double) of the list if 31880aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // we don't know it already. 31890aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 31900aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1 + (Reg == OldReg + 2); 31910aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach 31920aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Just check that it's contiguous and keep going. 31930aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (Reg != OldReg + Spacing) { 3194862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "non-contiguous register range"); 3195862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3196862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3197862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ++Count; 319898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 319998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 32007636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 320198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 32027636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 320398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 32047636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 320598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 320698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 320798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3208862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3209862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3210862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3211862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) { 3212862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(E, "'}' expected"); 3213862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3214862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3215862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '}' token. 3216862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 321798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 321898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 3219c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach // Two-register operands have been converted to the 3220c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach // composite register classes. 3221c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach if (Count == 2) { 3222c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach const MCRegisterClass *RC = (Spacing == 1) ? 3223c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3224c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3225c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3226c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach } 322728f08c93e75d291695ea89b9004145103292e85bJim Grosbach 32280aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 32290aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach (Spacing == 2), S, E)); 323098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 323198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 3232c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach // Two-register operands have been converted to the 3233c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach // composite register classes. 32344d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach if (Count == 2) { 32354d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach const MCRegisterClass *RC = (Spacing == 1) ? 32364d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach &ARMMCRegisterClasses[ARM::DPairRegClassID] : 32374d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3238c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3239c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach } 324098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 32413471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach (Spacing == 2), 324298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach S, E)); 324398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 32447636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 32457636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 324695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 324795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach (Spacing == 2), 324895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach S, E)); 32497636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 325098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3251862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_Success; 3252862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach} 3253862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 325443904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3255f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 325643904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3257706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3258706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3259706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3260706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes StringRef OptStr = Tok.getString(); 3261706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3262706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 3263706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("sy", ARM_MB::SY) 3264706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("st", ARM_MB::ST) 3265032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("sh", ARM_MB::ISH) 3266706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ish", ARM_MB::ISH) 3267032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("shst", ARM_MB::ISHST) 3268706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ishst", ARM_MB::ISHST) 3269706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nsh", ARM_MB::NSH) 3270032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("un", ARM_MB::NSH) 3271706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nshst", ARM_MB::NSHST) 3272032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("unst", ARM_MB::NSHST) 3273706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("osh", ARM_MB::OSH) 3274706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("oshst", ARM_MB::OSHST) 3275706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Default(~0U); 3276706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3277706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes if (Opt == ~0U) 3278f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 3279706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3280706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3281706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3282f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 3283706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes} 3284706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 328543904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3286a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 328743904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3288a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3289a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3290a1c7367a5bed459acc88e3ea2a482b4b5dac942aRichard Barton if (!Tok.is(AsmToken::Identifier)) 3291a1c7367a5bed459acc88e3ea2a482b4b5dac942aRichard Barton return MatchOperand_NoMatch; 3292a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef IFlagsStr = Tok.getString(); 3293a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 32942dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // An iflags string of "none" is interpreted to mean that none of the AIF 32952dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // bits are set. Not a terribly useful instruction, but a valid encoding. 3296a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = 0; 32972dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (IFlagsStr != "none") { 32982dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 32992dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 33002dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("a", ARM_PROC::A) 33012dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("i", ARM_PROC::I) 33022dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("f", ARM_PROC::F) 33032dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Default(~0U); 33042dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 33052dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // If some specific iflag is already set, it means that some letter is 33062dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // present more than once, this is not acceptable. 33072dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (Flag == ~0U || (IFlags & Flag)) 33082dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson return MatchOperand_NoMatch; 33092dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 33102dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson IFlags |= Flag; 33112dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson } 3312a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 3313a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3314a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3315a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3316a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return MatchOperand_Success; 3317584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes} 3318584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 331943904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3320584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 332143904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3322584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3323584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3324584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3325584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Mask = Tok.getString(); 3326584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3327acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (isMClass()) { 3328acad68da50581de905a994ed3c6b9c197bcea687James Molloy // See ARMv6-M 10.1.1 3329b84ad4aa7dacfba5337520740d47770f2200201cJim Grosbach std::string Name = Mask.lower(); 3330b84ad4aa7dacfba5337520740d47770f2200201cJim Grosbach unsigned FlagsVal = StringSwitch<unsigned>(Name) 33310fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // Note: in the documentation: 33320fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 33330fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // for MSR APSR_nzcvq. 33340fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // but we do make it an alias here. This is so to get the "mask encoding" 33350fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // bits correct on MSR APSR writes. 33360fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // 33370fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 33380fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // should really only be allowed when writing a special register. Note 33390fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // they get dropped in the MRS instruction reading a special register as 33400fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // the SYSm field is only 8 bits. 33410fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // 33420fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // FIXME: the _g and _nzcvqg versions are only allowed if the processor 33430fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // includes the DSP extension but that is not checked. 33440fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("apsr", 0x800) 33450fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("apsr_nzcvq", 0x800) 33460fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("apsr_g", 0x400) 33470fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("apsr_nzcvqg", 0xc00) 33480fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("iapsr", 0x801) 33490fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("iapsr_nzcvq", 0x801) 33500fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("iapsr_g", 0x401) 33510fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("iapsr_nzcvqg", 0xc01) 33520fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("eapsr", 0x802) 33530fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("eapsr_nzcvq", 0x802) 33540fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("eapsr_g", 0x402) 33550fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("eapsr_nzcvqg", 0xc02) 33560fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("xpsr", 0x803) 33570fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("xpsr_nzcvq", 0x803) 33580fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("xpsr_g", 0x403) 33590fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby .Case("xpsr_nzcvqg", 0xc03) 3360f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("ipsr", 0x805) 3361f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("epsr", 0x806) 3362f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("iepsr", 0x807) 3363f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("msp", 0x808) 3364f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("psp", 0x809) 3365f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("primask", 0x810) 3366f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("basepri", 0x811) 3367f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("basepri_max", 0x812) 3368f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("faultmask", 0x813) 3369f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby .Case("control", 0x814) 3370acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Default(~0U); 337118c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3372acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (FlagsVal == ~0U) 3373acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 3374acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3375f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3376acad68da50581de905a994ed3c6b9c197bcea687James Molloy // basepri, basepri_max and faultmask only valid for V7m. 3377acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 337818c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3379acad68da50581de905a994ed3c6b9c197bcea687James Molloy Parser.Lex(); // Eat identifier token. 3380acad68da50581de905a994ed3c6b9c197bcea687James Molloy Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3381acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_Success; 3382acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 3383acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3384584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3385584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes size_t Start = 0, Next = Mask.find('_'); 3386584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Flags = ""; 3387590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string SpecReg = Mask.slice(Start, Next).lower(); 3388584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (Next != StringRef::npos) 3389584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Flags = Mask.slice(Next+1, Mask.size()); 3390584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3391584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // FlagsVal contains the complete mask: 3392584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 3-0: Mask 3393584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3394584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned FlagsVal = 0; 3395584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3396584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "apsr") { 3397584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal = StringSwitch<unsigned>(Flags) 3398b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach .Case("nzcvq", 0x8) // same as CPSR_f 3399584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("g", 0x4) // same as CPSR_s 3400584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("nzcvqg", 0xc) // same as CPSR_fs 3401584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3402584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 34034b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger if (FlagsVal == ~0U) { 3404584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (!Flags.empty()) 3405584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3406584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes else 3407bf841cf3360558d2939c9f1a244a7a7296f846dfJim Grosbach FlagsVal = 8; // No flag 34084b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger } 3409584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3410b657a90929867716ca1c7c12d442bb5d32281bd4Jim Grosbach // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3411b657a90929867716ca1c7c12d442bb5d32281bd4Jim Grosbach if (Flags == "all" || Flags == "") 341256926a39619bd644c83c4128f0b55189e52707d7Bruno Cardoso Lopes Flags = "fc"; 3413584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes for (int i = 0, e = Flags.size(); i != e; ++i) { 3414584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3415584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("c", 1) 3416584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("x", 2) 3417584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("s", 4) 3418584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("f", 8) 3419584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3420584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3421584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // If some specific flag is already set, it means that some letter is 3422584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // present more than once, this is not acceptable. 3423584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (FlagsVal == ~0U || (FlagsVal & Flag)) 3424584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3425584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= Flag; 3426584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 3427584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else // No match for special register. 3428584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3429584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 34307784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // Special register without flags is NOT equivalent to "fc" flags. 34317784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // NOTE: This is a divergence from gas' behavior. Uncommenting the following 34327784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // two lines would enable gas compatibility at the expense of breaking 34337784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // round-tripping. 34347784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // 34357784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // if (!FlagsVal) 34367784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // FlagsVal = 0x9; 3437584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3438584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3439584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "spsr") 3440584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= 16; 3441584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3442584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3443584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3444584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_Success; 3445a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes} 3446a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3447f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3448f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachparsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3449f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Low, int High) { 3450f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3451f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3452f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3453f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3454f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3455f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef ShiftName = Tok.getString(); 3456590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string LowerOp = Op.lower(); 3457590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string UpperOp = Op.upper(); 3458f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (ShiftName != LowerOp && ShiftName != UpperOp) { 3459f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3460f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3461f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3462f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat shift type token. 3463f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3464f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // There must be a '#' and a shift amount. 34658a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34668a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3467f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3468f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3469f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3470f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat hash token. 3471f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3472f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCExpr *ShiftAmount; 3473f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 3474f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3475f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "illegal expression"); 3476f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3477f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3478f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3479f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) { 3480f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "constant expression expected"); 3481f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3482f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3483f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 3484f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Val < Low || Val > High) { 3485f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "immediate value out of range"); 3486f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3487f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3488f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3489f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3490f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3491f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_Success; 3492f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach} 3493f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3494c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3495c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachparseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3496c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3497c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach SMLoc S = Tok.getLoc(); 3498c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3499c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3500c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3501c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3502c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int Val = StringSwitch<int>(Tok.getString()) 3503c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("be", 1) 3504c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("le", 0) 3505c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Default(-1); 3506c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.Lex(); // Eat the token. 3507c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3508c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Val == -1) { 3509c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3510c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3511c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3512c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3513c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach getContext()), 3514c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach S, Parser.getTok().getLoc())); 3515c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_Success; 3516c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach} 3517c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3518580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3519580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// instructions. Legal values are: 3520580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// lsl #n 'n' in [0,31] 3521580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// asr #n 'n' in [1,32] 3522580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// n == 32 encoded as n == 0. 3523580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3524580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachparseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3525580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const AsmToken &Tok = Parser.getTok(); 3526580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc S = Tok.getLoc(); 3527580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3528580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3529580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3530580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3531580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach StringRef ShiftName = Tok.getString(); 3532580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 3533580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL") 3534580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = false; 3535580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else if (ShiftName == "asr" || ShiftName == "ASR") 3536580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = true; 3537580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else { 3538580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3539580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3540580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3541580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat the operator. 3542580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3543580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // A '#' and a shift amount. 35448a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 35458a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3546580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3547580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3548580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3549580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat hash token. 3550580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3551580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCExpr *ShiftAmount; 3552580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3553580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3554580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "malformed shift expression"); 3555580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3556580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3557580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3558580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (!CE) { 3559580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "shift amount must be an immediate"); 3560580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3561580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3562580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3563580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach int64_t Val = CE->getValue(); 3564580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (isASR) { 3565580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3566580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 1 || Val > 32) { 3567580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'asr' shift amount must be in range [1,32]"); 3568580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3569580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 35700afa0094afdfe589f407feb76948f273b414b278Owen Anderson // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 35710afa0094afdfe589f407feb76948f273b414b278Owen Anderson if (isThumb() && Val == 32) { 35720afa0094afdfe589f407feb76948f273b414b278Owen Anderson Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 35730afa0094afdfe589f407feb76948f273b414b278Owen Anderson return MatchOperand_ParseFail; 35740afa0094afdfe589f407feb76948f273b414b278Owen Anderson } 3575580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val == 32) Val = 0; 3576580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } else { 3577580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3578580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 0 || Val > 31) { 3579580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'lsr' shift amount must be in range [0,31]"); 3580580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3581580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3582580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3583580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3584580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach E = Parser.getTok().getLoc(); 3585580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3586580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3587580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_Success; 3588580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach} 3589580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 35907e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 35917e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// of instructions. Legal values are: 35927e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// ror #n 'n' in {0, 8, 16, 24} 35937e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 35947e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachparseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 35957e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const AsmToken &Tok = Parser.getTok(); 35967e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc S = Tok.getLoc(); 3597326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) 3598326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 35997e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach StringRef ShiftName = Tok.getString(); 3600326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (ShiftName != "ror" && ShiftName != "ROR") 3601326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 36027e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat the operator. 36037e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 36047e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // A '#' and a rotate amount. 36058a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 36068a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 36077e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 36087e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 36097e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 36107e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat hash token. 36117e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 36127e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCExpr *ShiftAmount; 36137e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 36147e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 36157e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "malformed rotate expression"); 36167e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 36177e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 36187e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 36197e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (!CE) { 36207e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "rotate amount must be an immediate"); 36217e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 36227e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 36237e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 36247e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach int64_t Val = CE->getValue(); 36257e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 36267e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // normally, zero is represented in asm by omitting the rotate operand 36277e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // entirely. 36287e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 36297e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "'ror' rotate amount must be 8, 16, or 24"); 36307e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 36317e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 36327e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 36337e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach E = Parser.getTok().getLoc(); 36347e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 36357e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 36367e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_Success; 36377e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach} 36387e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 3639293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3640293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachparseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3641293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 3642293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The bitfield descriptor is really two operands, the LSB and the width. 36438a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 36448a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3645293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3646293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3647293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3648293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3649293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3650293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *LSBExpr; 3651293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3652293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(LSBExpr)) { 3653293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3654293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3655293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3656293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3657293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3658293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be an immediate"); 3659293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3660293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3661293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3662293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t LSB = CE->getValue(); 3663293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [0,31] 3664293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (LSB < 0 || LSB > 31) { 3665293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be in the range [0,31]"); 3666293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3667293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3668293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3669293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3670293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Expect another immediate operand. 3671293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Parser.getTok().isNot(AsmToken::Comma)) { 3672293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "too few operands"); 3673293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3674293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3675293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 36768a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 36778a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3678293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3679293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3680293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3681293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3682293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3683293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *WidthExpr; 3684293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(WidthExpr)) { 3685293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3686293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3687293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3688293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach CE = dyn_cast<MCConstantExpr>(WidthExpr); 3689293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3690293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be an immediate"); 3691293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3692293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3693293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3694293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t Width = CE->getValue(); 3695293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [1,32-lsb] 3696293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Width < 1 || Width > 32 - LSB) { 3697293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be in the range [1,32-lsb]"); 3698293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3699293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3700293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3701293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3702293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3703293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3704293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_Success; 3705293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach} 3706293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 37077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 37087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3710f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // postidx_reg := '+' register {, shift} 3711f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | '-' register {, shift} 3712f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | register {, shift} 37137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 37147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 37157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // in the case where there is no match, as other alternatives take other 37167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // parse methods. 37177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach AsmToken Tok = Parser.getTok(); 37187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S = Tok.getLoc(); 37197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool haveEaten = false; 372016578b50889329eb62774148091ba0f38b681a09Jim Grosbach bool isAdd = true; 37217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Reg = -1; 37227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::Plus)) { 37237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+' token. 37247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 37257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 37267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-' token. 372716578b50889329eb62774148091ba0f38b681a09Jim Grosbach isAdd = false; 37287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 37297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 37307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 37317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Reg = tryParseRegister(); 37327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Reg == -1) { 37337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!haveEaten) 37347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_NoMatch; 37357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 37367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_ParseFail; 37377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 37387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 37397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3740f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3741f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm = 0; 37420d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 37430d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach Parser.Lex(); // Eat the ','. 37440d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 37450d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach return MatchOperand_ParseFail; 37460d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach } 3747f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 3748f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3749f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ShiftImm, S, E)); 37507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 37517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_Success; 37527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 37537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3754251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3755251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachparseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3756251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3757251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // am3offset := '+' register 3758251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | '-' register 3759251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | register 3760251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # imm 3761251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # + imm 3762251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # - imm 3763251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3764251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 3765251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // in the case where there is no match, as other alternatives take other 3766251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // parse methods. 3767251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach AsmToken Tok = Parser.getTok(); 3768251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc S = Tok.getLoc(); 3769251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3770251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Do immediates first, as we always parse those if we have a '#'. 37718a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 37728a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 3773251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '#'. 3774251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Explicitly look for a '-', as we need to encode negative zero 3775251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // differently. 3776251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isNegative = Parser.getTok().is(AsmToken::Minus); 3777251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCExpr *Offset; 3778251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (getParser().ParseExpression(Offset)) 3779251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3780251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3781251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!CE) { 3782251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(S, "constant expression expected"); 3783251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3784251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3785251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Tok.getLoc(); 3786251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Negative zero is encoded as the flag value INT32_MIN. 3787251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int32_t Val = CE->getValue(); 3788251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (isNegative && Val == 0) 3789251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = INT32_MIN; 3790251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3791251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back( 3792251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3793251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3794251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3795251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3796251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3797251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3798251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool haveEaten = false; 3799251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isAdd = true; 3800251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int Reg = -1; 3801251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Tok.is(AsmToken::Plus)) { 3802251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '+' token. 3803251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3804251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 3805251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '-' token. 3806251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach isAdd = false; 3807251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3808251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3809251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 3810251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Reg = tryParseRegister(); 3811251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Reg == -1) { 3812251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!haveEaten) 3813251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_NoMatch; 3814251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 3815251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3816251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3817251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3818251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3819251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3820251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 0, S, E)); 3821251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3822251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3823251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach} 3824251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3825a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2LdrdPre - Convert parsed operands to MCInst. 3826a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3827a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3828a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3829a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3830a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3831a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3832a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3833a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3834a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3835a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3836a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3837a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3838a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3839a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3840a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3841a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3842a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3843a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2StrdPre - Convert parsed operands to MCInst. 3844a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3845a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3846a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3847a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3848a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3849a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3850a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3851a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3852a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3853a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3854a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3855a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3856a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3857a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3858a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3859a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3860a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3861eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3862eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3863eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3864eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbachbool ARMAsmParser:: 3865eeec025cf5a2236ee9527a3312496a6ea42100c6Jim GrosbachcvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3866eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3867eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3868eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3869eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach // Create a writeback register dummy placeholder. 3870eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3871eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3872eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3873eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3874eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach return true; 3875eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach} 3876eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3877ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3878ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3879ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3880ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbachbool ARMAsmParser:: 3881ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim GrosbachcvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3882ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3883ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach // Create a writeback register dummy placeholder. 3884ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3885ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3886ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3887ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3888ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach return true; 3889ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach} 3890ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach 38911355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3892ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3893ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3894ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 38951355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3896ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3897ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3898ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 3899ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3900ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3901ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 39027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3903ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3904ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3905ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3906ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 39079ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 39089ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// Needed here because the Asm Gen Matcher can't handle properly tied operands 39099ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// when they refer multiple MIOperands inside a single one. 39109ab0f25fc194b4315db1b87d38d4024054120bf6Owen Andersonbool ARMAsmParser:: 39119ab0f25fc194b4315db1b87d38d4024054120bf6Owen AndersoncvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 39129ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39139ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 39149ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 39159ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson // Create a writeback register dummy placeholder. 39169ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson Inst.addOperand(MCOperand::CreateImm(0)); 39179ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 39189ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 39199ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 39209ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson return true; 39219ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson} 39229ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 39239ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 3924548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3925548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3926548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3927548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbachbool ARMAsmParser:: 3928548340c4bfa596b602f286dfd3a8782817859d95Jim GrosbachcvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3929548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3930548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach // Create a writeback register dummy placeholder. 3931548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3932548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3933548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3934548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3935548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach return true; 3936548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach} 3937548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach 39381355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3939ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3940ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3941ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 39421355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3943ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3944ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3945ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3946548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3947548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3948548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 39497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 39507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 39517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 39527b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 39537b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 39547b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// when they refer multiple MIOperands inside a single one. 39557b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbachbool ARMAsmParser:: 39567b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim GrosbachcvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 39577b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39587b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach // Create a writeback register dummy placeholder. 39597b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 39607b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 39617b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 39627b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 39637b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach return true; 39647b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach} 39657b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach 39667ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 39677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 39687ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 39697ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 39707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 39717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39727ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3973ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 39747ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 39757ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 39767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 39777ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 39787ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 39797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 39807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3981ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3982ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3983ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3984ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 39857ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 3986ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3987ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3988ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 39897ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 39907ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3992aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3993ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 3994ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 39957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 39967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 39977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 39987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 39997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 40007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 40017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 40027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 4003aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson 40047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 40057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 40067ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 40077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 40087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 40097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 40107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 40117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 40127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 40137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 40147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 40157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 40167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 40177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 40187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 4019ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4020ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 4021ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 4022ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 40237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 4024ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4025ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 4026ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 40277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 40287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4029ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 4030ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 40317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 4032ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 40337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 40347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 40357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 40367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 40377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 4038ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4039ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 4040ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 4041ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 40422fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// cvtLdrdPre - Convert parsed operands to MCInst. 40432fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 40442fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// when they refer multiple MIOperands inside a single one. 40452fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbachbool ARMAsmParser:: 40462fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim GrosbachcvtLdrdPre(MCInst &Inst, unsigned Opcode, 40472fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 40482fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Rt, Rt2 40492fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 40502fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 40512fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Create a writeback register dummy placeholder. 40522fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 40532fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // addr 40542fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 40552fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // pred 40562fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 40572fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return true; 40582fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach} 40592fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 406014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// cvtStrdPre - Convert parsed operands to MCInst. 406114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 406214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// when they refer multiple MIOperands inside a single one. 406314605d1a679d55ff25875656e100ff455194ee17Jim Grosbachbool ARMAsmParser:: 406414605d1a679d55ff25875656e100ff455194ee17Jim GrosbachcvtStrdPre(MCInst &Inst, unsigned Opcode, 406514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 406614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Create a writeback register dummy placeholder. 406714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 406814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt, Rt2 406914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 407014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 407114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // addr 407214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 407314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // pred 407414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 407514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return true; 407614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach} 407714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach 4078623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4079623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4080623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// when they refer multiple MIOperands inside a single one. 4081623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbachbool ARMAsmParser:: 4082623a454b0f5c300e69a19984d7855a1e976c3d09Jim GrosbachcvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 4083623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4084623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4085623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach // Create a writeback register dummy placeholder. 4086623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 4087623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4088623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4089623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach return true; 4090623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach} 4091623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 409288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// cvtThumbMultiple- Convert parsed operands to MCInst. 409388ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 409488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// when they refer multiple MIOperands inside a single one. 409588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbachbool ARMAsmParser:: 409688ae2bc6d53bbf58422ff74729da18a53e155b4aJim GrosbachcvtThumbMultiply(MCInst &Inst, unsigned Opcode, 409788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 409888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // The second source operand must be the same register as the destination 409988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // operand. 410088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach if (Operands.size() == 6 && 41017a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 41027a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[5])->getReg()) && 41037a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 41047a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[4])->getReg())) { 410588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach Error(Operands[3]->getStartLoc(), 41067a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach "destination register must match source register"); 410788ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return false; 410888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach } 410988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 411088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 41111b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // If we have a three-operand form, make sure to set Rn to be the operand 41121b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // that isn't the same as Rd. 41131b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach unsigned RegOp = 4; 41141b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach if (Operands.size() == 6 && 41151b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[4])->getReg() == 41161b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[3])->getReg()) 41171b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach RegOp = 5; 41181b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 41191b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach Inst.addOperand(Inst.getOperand(0)); 412088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 412188ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach 412288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 412388ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach} 4124623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 412512431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 412612431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 412712431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 412812431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 41296029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 413012431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 413112431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 413212431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 413312431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 413412431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 413512431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 413612431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 413712431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 413812431329d617064d6e72dd040a58c1635cc261abJim Grosbach 413912431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 414012431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 414112431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 414212431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 41436029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 414412431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 414512431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 414612431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 414712431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 414812431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vm 414912431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 415012431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 415112431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 415212431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 415312431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 415412431329d617064d6e72dd040a58c1635cc261abJim Grosbach 41554334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 41564334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 41574334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 41584334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 41594334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 41604334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 41614334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 41624334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 41636029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 41644334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 41654334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 41664334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 41674334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 41684334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 41694334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 41704334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 41714334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 41724334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 41734334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 41744334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 41754334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 41764334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vm 41774334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 41784334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 41796029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 41804334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 41814334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 41824334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 41834334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 41844334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 4185e717610f53e0465cde198536561a3c00ce29d59fBill Wendling/// Parse an ARM memory expression, return false if successful else return true 41869c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// or an error. The first token must be a '[' when called. 418750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 41887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4189762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 419018b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LBrac) && 4191a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Bracket"); 4192762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4193b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat left bracket token. 4194a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 419518b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &BaseRegTok = Parser.getTok(); 41961355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int BaseRegNum = tryParseRegister(); 41977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (BaseRegNum == -1) 41987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(BaseRegTok.getLoc(), "register expected"); 4199a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 42000571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar // The next token must either be a comma or a closing bracket. 42010571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar const AsmToken &Tok = Parser.getTok(); 42020571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 42037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Tok.getLoc(), "malformed memory operand"); 42040571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar 42057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::RBrac)) { 4206762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = Tok.getLoc(); 4207b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat right bracket token. 4208a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 42097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 421057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 0, 0, false, S, E)); 421103f44a04e63ff77af12df33e10ffdc473609dfe2Jim Grosbach 4212fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4213fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // operand. It's rather odd, but syntactically valid. 4214fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4215fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4216fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Parser.Lex(); // Eat the '!'. 4217fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach } 4218fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach 42197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 42207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 422150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 42227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 42237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the comma. 422450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 422557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a ':', it's an alignment specifier. 422657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Colon)) { 422757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the ':'. 422857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 422957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 423057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCExpr *Expr; 423157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (getParser().ParseExpression(Expr)) 423257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return true; 423357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 423457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // The expression has to be a constant. Memory references with relocations 423557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // don't come through here, as they use the <label> forms of the relevant 423657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // instructions. 423757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 423857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!CE) 423957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error (E, "constant expression expected"); 424057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 424157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Align = 0; 424257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach switch (CE->getValue()) { 424357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach default: 4244eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach return Error(E, 4245eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4246eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 16: Align = 2; break; 4247eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 32: Align = 4; break; 424857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 64: Align = 8; break; 424957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 128: Align = 16; break; 425057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 256: Align = 32; break; 425157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 425257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 425357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Now we should have the closing ']' 425457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 425557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 425657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error(E, "']' expected"); 425757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat right bracket token. 425857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 425957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Don't worry about range checking the value here. That's handled by 426057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // the is*() predicates. 426157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 426257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, Align, 426357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 426457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 426557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 426657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // operand. 426757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 426857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 426957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the '!'. 427057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 427157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 427257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return false; 427357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 427457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 427557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a '#', it's an immediate offset, else assume it's a register 42766cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // offset. Be friendly and also accept a plain integer (without a leading 42776cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // hash) for gas compatibility. 42786cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 42798a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar) || 42806cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.getTok().is(AsmToken::Integer)) { 42818a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Integer)) 42826cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.Lex(); // Eat the '#'. 42837ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 428450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 42850da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson bool isNegative = getParser().getTok().is(AsmToken::Minus); 42867ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Offset; 42877ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Offset)) 42887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 428905d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 42907ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The expression has to be a constant. Memory references with relocations 42917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // don't come through here, as they use the <label> forms of the relevant 42927ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // instructions. 42937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 42947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 42957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error (E, "constant expression expected"); 42967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 42970da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson // If the constant was #-0, represent it as INT32_MIN. 42980da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson int32_t Val = CE->getValue(); 42990da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson if (isNegative && Val == 0) 43000da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson CE = MCConstantExpr::Create(INT32_MIN, getContext()); 43010da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson 43027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 43037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 43047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 43057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 43067ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 430705d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 43087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Don't worry about range checking the value here. That's handled by 43097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // the is*() predicates. 43107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 431157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, 0, 431257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 4313a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 43147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 43157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // operand. 43167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 43177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 43187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '!'. 4319762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 43207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 43217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 43229c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 4323d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 43247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The register offset is optionally preceded by a '+' or '-' 43257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative = false; 43267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 43277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach isNegative = true; 43287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-'. 43297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Parser.getTok().is(AsmToken::Plus)) { 43307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Nothing to do. 43317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+'. 43327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 43339c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 43347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 43357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int OffsetRegNum = tryParseRegister(); 43367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (OffsetRegNum == -1) 43377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "register expected"); 43387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 43397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a shift operator, handle it. 43407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 43410d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm = 0; 43427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 43437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the ','. 43440d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 43457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 43469c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 434716c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 43487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 43497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 43507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 43517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 43527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 43537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 43547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 435557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ShiftType, ShiftImm, 0, isNegative, 43567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach S, E)); 43577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 4358f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4359f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // operand. 4360f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4361f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4362f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Parser.Lex(); // Eat the '!'. 4363f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 43649c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 43659c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby return false; 43669c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby} 43679c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 43687ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// parseMemRegOffsetShift - one of these two: 4369a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ( lsl | lsr | asr | ror ) , # shift_amount 4370a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// rrx 43717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// return true if it parses a shift otherwise it returns false. 43727ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 43737ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &Amount) { 43747ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 437518b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 4376a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby if (Tok.isNot(AsmToken::Identifier)) 4377a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return true; 437838e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef ShiftName = Tok.getString(); 4379af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL" || 4380af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach ShiftName == "asl" || ShiftName == "ASL") 43810082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsl; 4382a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "lsr" || ShiftName == "LSR") 43830082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsr; 4384a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "asr" || ShiftName == "ASR") 43850082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::asr; 4386a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "ror" || ShiftName == "ROR") 43870082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::ror; 4388a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "rrx" || ShiftName == "RRX") 43890082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::rrx; 4390a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else 43917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "illegal shift operator"); 4392b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat shift type token. 4393a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 43947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // rrx stands alone. 43957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = 0; 43967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (St != ARM_AM::rrx) { 43977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Loc = Parser.getTok().getLoc(); 43987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // A '#' and a shift amount. 43997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const AsmToken &HashTok = Parser.getTok(); 44008a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (HashTok.isNot(AsmToken::Hash) && 44018a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach HashTok.isNot(AsmToken::Dollar)) 44027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(HashTok.getLoc(), "'#' expected"); 44037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat hash token. 44049c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 44057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Expr; 44067ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Expr)) 44077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 44087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Range check the immediate. 44097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsl, ror: 0 <= imm <= 31 44107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsr, asr: 0 <= imm <= 32 44117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 44127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 44137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "shift amount must be an immediate"); 44147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Imm = CE->getValue(); 44157ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Imm < 0 || 44167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 44177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 44187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "immediate shift value out of range"); 44197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = Imm; 44207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 4421a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4422a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return false; 4423a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4424a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 44259d39036f62674606565217a10db28171b9594bc7Jim Grosbach/// parseFPImm - A floating point immediate expression operand. 44269d39036f62674606565217a10db28171b9594bc7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 44279d39036f62674606565217a10db28171b9594bc7Jim GrosbachparseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 442851222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // Anything that can accept a floating point constant as an operand 442951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // needs to go through here, as the regular ParseExpression is 443051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // integer only. 443151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // 443251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // This routine still creates a generic Immediate operand, containing 443351222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // a bitcast of the 64-bit floating point value. The various operands 443451222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // that accept floats can check whether the value is valid for them 443551222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // via the standard is*() predicates. 443651222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach 44379d39036f62674606565217a10db28171b9594bc7Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 44389d39036f62674606565217a10db28171b9594bc7Jim Grosbach 44398a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 44408a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) 44419d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_NoMatch; 44420e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 44430e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Disambiguate the VMOV forms that can accept an FP immediate. 44440e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <sreg>, #imm 44450e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f64 <dreg>, #imm 44460e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <dreg>, #imm @ vector f32x2 44470e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <qreg>, #imm @ vector f32x4 44480e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // 44490e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // There are also the NEON VMOV instructions which expect an 44500e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // integer constant. Make sure we don't try to parse an FPImm 44510e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // for these: 44520e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.i{8|16|32|64} <dreg|qreg>, #imm 44530e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 44540e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 44550e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach TyOp->getToken() != ".f64")) 44560e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return MatchOperand_NoMatch; 44570e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 44589d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the '#'. 44599d39036f62674606565217a10db28171b9594bc7Jim Grosbach 44609d39036f62674606565217a10db28171b9594bc7Jim Grosbach // Handle negation, as that still comes through as a separate token. 44619d39036f62674606565217a10db28171b9594bc7Jim Grosbach bool isNegative = false; 44629d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 44639d39036f62674606565217a10db28171b9594bc7Jim Grosbach isNegative = true; 44649d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); 44659d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 44669d39036f62674606565217a10db28171b9594bc7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 4467ae69f703d59410fc96f04be3c1afeaa1c17a45ceJim Grosbach SMLoc Loc = Tok.getLoc(); 44689d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Real)) { 446951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 44709d39036f62674606565217a10db28171b9594bc7Jim Grosbach uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 44719d39036f62674606565217a10db28171b9594bc7Jim Grosbach // If we had a '-' in front, toggle the sign bit. 447251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach IntVal ^= (uint64_t)isNegative << 31; 44739d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 447451222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Operands.push_back(ARMOperand::CreateImm( 447551222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach MCConstantExpr::Create(IntVal, getContext()), 447651222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach S, Parser.getTok().getLoc())); 44779d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 44789d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 447951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // Also handle plain integers. Instructions which allow floating point 448051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // immediates also allow a raw encoded 8-bit value. 44819d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Integer)) { 44829d39036f62674606565217a10db28171b9594bc7Jim Grosbach int64_t Val = Tok.getIntVal(); 44839d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 44849d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Val > 255 || Val < 0) { 4485ae69f703d59410fc96f04be3c1afeaa1c17a45ceJim Grosbach Error(Loc, "encoded floating point value out of range"); 44869d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 44879d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 448851222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach double RealVal = ARM_AM::getFPImmFloat(Val); 448951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 449051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Operands.push_back(ARMOperand::CreateImm( 449151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach MCConstantExpr::Create(Val, getContext()), S, 449251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Parser.getTok().getLoc())); 44939d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 44949d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 44959d39036f62674606565217a10db28171b9594bc7Jim Grosbach 4496ae69f703d59410fc96f04be3c1afeaa1c17a45ceJim Grosbach Error(Loc, "invalid floating point immediate"); 44979d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 44989d39036f62674606565217a10db28171b9594bc7Jim Grosbach} 449951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach 45009c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Parse a arm instruction operand. For now this parses the operand regardless 45019c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// of the mnemonic. 45021355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4503fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes StringRef Mnemonic) { 4504762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 4505fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4506fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // Check if the current operand has a custom associated parser, if so, try to 4507fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // custom parse the operand, or fallback to the general approach. 4508f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4509f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_Success) 4510fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return false; 4511f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // If there wasn't a custom match, try the generic matcher below. Otherwise, 4512f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // there was a match, but an error occurred, in which case, just return that 4513f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // the operand parsing failed. 4514f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_ParseFail) 4515f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return true; 4516fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4517a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby switch (getLexer().getKind()) { 4518146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling default: 4519146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling Error(Parser.getTok().getLoc(), "unexpected token in operand"); 452050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 452119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach case AsmToken::Identifier: { 45221355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (!tryParseRegisterWithWriteBack(Operands)) 452350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 45240d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int Res = tryParseShiftRegister(Operands); 452519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (Res == 0) // success 45260082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return false; 452719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach else if (Res == -1) // irrecoverable error 452819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return true; 45293cbe43fe69680df772d83947ced97ca445861213Jim Grosbach // If this is VMRS, check for the apsr_nzcv operand. 4530b84ad4aa7dacfba5337520740d47770f2200201cJim Grosbach if (Mnemonic == "vmrs" && 4531b84ad4aa7dacfba5337520740d47770f2200201cJim Grosbach Parser.getTok().getString().equals_lower("apsr_nzcv")) { 45325cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach S = Parser.getTok().getLoc(); 45335cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach Parser.Lex(); 4534b84ad4aa7dacfba5337520740d47770f2200201cJim Grosbach Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 45355cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach return false; 45365cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach } 4537e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 4538e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Fall though for the Identifier case that is not a register or a 4539e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // special name. 454019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 4541758a519a22b469ce8e2b8d0bf7a72813e87710d4Jim Grosbach case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 454267b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Integer: // things like 1f and 2b as a branch targets 45436284afc293c8f6e84dffab8731aa9e679d437745Jim Grosbach case AsmToken::String: // quoted label names. 454467b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Dot: { // . as a branch target 4545515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // This was not a register so parse other operands that start with an 4546515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // identifier (like labels) as expressions and create them as immediates. 4547515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby const MCExpr *IdVal; 4548762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4549515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getParser().ParseExpression(IdVal)) 455050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 4551762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 455250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 455350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 455450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling } 4555a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby case AsmToken::LBrac: 45561355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseMemory(Operands); 4557d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby case AsmToken::LCurly: 45581355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseRegisterList(Operands); 45598a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach case AsmToken::Dollar: 456063553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson case AsmToken::Hash: { 4561079469f649d8da3923b9f747d7062c84e01cc4aeKevin Enderby // #42 -> immediate. 4562762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4563b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 4564b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach 4565b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach if (Parser.getTok().isNot(AsmToken::Colon)) { 4566b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach bool isNegative = Parser.getTok().is(AsmToken::Minus); 4567b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach const MCExpr *ImmVal; 4568b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach if (getParser().ParseExpression(ImmVal)) 4569b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach return true; 4570b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4571b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach if (CE) { 4572b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach int32_t Val = CE->getValue(); 4573b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach if (isNegative && Val == 0) 4574b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4575b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach } 4576b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4577b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4578b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach return false; 457963553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 4580b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach // w/ a ':' after the '#', it's just like a plain ':'. 4581b8768dc32df0bf3edfa2777cdef57bb066e54344Jim Grosbach // FALLTHROUGH 458263553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 45839081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim case AsmToken::Colon: { 45849081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // ":lower16:" and ":upper16:" expression prefixes 45857597212abced110723f2fee985a7d60557c092ecEvan Cheng // FIXME: Check it's an expression prefix, 45867597212abced110723f2fee985a7d60557c092ecEvan Cheng // e.g. (FOO - :lower16:BAR) isn't legal. 45877597212abced110723f2fee985a7d60557c092ecEvan Cheng ARMMCExpr::VariantKind RefKind; 45881355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parsePrefix(RefKind)) 45899081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 45909081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 45917597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *SubExprVal; 45927597212abced110723f2fee985a7d60557c092ecEvan Cheng if (getParser().ParseExpression(SubExprVal)) 45939081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 45949081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 45957597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 45967597212abced110723f2fee985a7d60557c092ecEvan Cheng getContext()); 45979081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 45987597212abced110723f2fee985a7d60557c092ecEvan Cheng Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 45999081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 46009081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 4601a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 4602a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4603a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 46041355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 46057597212abced110723f2fee985a7d60557c092ecEvan Cheng// :lower16: and :upper16:. 46061355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 46077597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_None; 46089081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 46099081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // :lower16: and :upper16: modifiers 46108a8696db6b6f6e735bb9de630876af83946b45f9Jason W Kim assert(getLexer().is(AsmToken::Colon) && "expected a :"); 46119081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat ':' 46129081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 46139081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Identifier)) { 46149081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 46159081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 46169081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 46179081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 46189081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim StringRef IDVal = Parser.getTok().getIdentifier(); 46199081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (IDVal == "lower16") { 46207597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_LO16; 46219081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else if (IDVal == "upper16") { 46227597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_HI16; 46239081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else { 46249081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 46259081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 46269081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 46279081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); 46289081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 46299081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Colon)) { 46309081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 46319081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 46329081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 46339081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat the last ':' 46349081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 46359081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim} 46369081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 4637352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// \brief Given a mnemonic, split out possible predication code and carry 4638352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// setting letters to form a canonical mnemonic and flags. 4639352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar// 4640badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar// FIXME: Would be nice to autogen this. 464189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach// FIXME: This is a bit of a maze of special cases. 46421355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachStringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 46435f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach unsigned &PredicationCode, 46445f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach bool &CarrySetting, 464589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned &ProcessorIMod, 464689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask) { 4647352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar PredicationCode = ARMCC::AL; 4648352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = false; 4649a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = 0; 4650352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4651badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Ignore some mnemonics we know aren't predicated forms. 4652352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // 4653352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // FIXME: Would be nice to autogen this. 46545f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach if ((Mnemonic == "movs" && isThumb()) || 46555f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 46565f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 46575f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 46585f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 46595f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 46605f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 46616849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 46626849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "fmuls") 4663352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4664badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 46653f00e317064560ad11168d22030416d853829f6eJim Grosbach // First, split out any predication code. Ignore mnemonics we know aren't 46663f00e317064560ad11168d22030416d853829f6eJim Grosbach // predicated but do have a carry-set and so weren't caught above. 4667ab40f4b737b0a87c4048a9ad2f0c02be735e3770Jim Grosbach if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 466871725a099e6d0cba24a63f9c9063f6efee3bf76eJim Grosbach Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 466904d55f1905748b0d66655e2332e1a232a3f665f4Jim Grosbach Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 46702f25d9b9334662e846460e98a8fe2dae4f233068Jim Grosbach Mnemonic != "sbcs" && Mnemonic != "rscs") { 46713f00e317064560ad11168d22030416d853829f6eJim Grosbach unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 46723f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("eq", ARMCC::EQ) 46733f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ne", ARMCC::NE) 46743f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hs", ARMCC::HS) 46753f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cs", ARMCC::HS) 46763f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lo", ARMCC::LO) 46773f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cc", ARMCC::LO) 46783f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("mi", ARMCC::MI) 46793f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("pl", ARMCC::PL) 46803f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vs", ARMCC::VS) 46813f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vc", ARMCC::VC) 46823f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hi", ARMCC::HI) 46833f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ls", ARMCC::LS) 46843f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ge", ARMCC::GE) 46853f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lt", ARMCC::LT) 46863f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("gt", ARMCC::GT) 46873f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("le", ARMCC::LE) 46883f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("al", ARMCC::AL) 46893f00e317064560ad11168d22030416d853829f6eJim Grosbach .Default(~0U); 46903f00e317064560ad11168d22030416d853829f6eJim Grosbach if (CC != ~0U) { 46913f00e317064560ad11168d22030416d853829f6eJim Grosbach Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 46923f00e317064560ad11168d22030416d853829f6eJim Grosbach PredicationCode = CC; 46933f00e317064560ad11168d22030416d853829f6eJim Grosbach } 469452925b60f1cd4cf810524ca05b00a207a926ab9fBill Wendling } 4695345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 4696352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Next, determine if we have a carry setting bit. We explicitly ignore all 4697352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // the instructions we know end in 's'. 4698352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar if (Mnemonic.endswith("s") && 469900f5d982057574cf65a4a3f29548ff9fb0ecfbd0Jim Grosbach !(Mnemonic == "cps" || Mnemonic == "mls" || 47005f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 47015f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 47025f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 470367ca1adf822c6cbc2f2bb78b8f94eefd099a8eb6Jim Grosbach Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 470448171e7fbe58bb418f09717813779d03903d35e4Jim Grosbach Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 47059c39789c361d4fe2632f28fca74c9ea5fff3dafcJim Grosbach Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 47066357caec785268d1e39059d03eb2034dee65467fJim Grosbach Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 470782509e5c62a99912c636b22e227b810eaf6eda78Evan Cheng Mnemonic == "vfms" || Mnemonic == "vfnms" || 4708e1cf5902ec832cecdd5a94b9701930253d410741Jim Grosbach (Mnemonic == "movs" && isThumb()))) { 4709352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4710352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = true; 4711352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar } 4712352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4713a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // The "cps" instruction can have a interrupt mode operand which is glued into 4714a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // the mnemonic. Check if this is the case, split it and parse the imod op 4715a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (Mnemonic.startswith("cps")) { 4716a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Split out any imod code. 4717a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IMod = 4718a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4719a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("ie", ARM_PROC::IE) 4720a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("id", ARM_PROC::ID) 4721a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Default(~0U); 4722a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IMod != ~0U) { 4723a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4724a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = IMod; 4725a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4726a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4727a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 472889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The "it" instruction has the condition mask on the end of the mnemonic. 472989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic.startswith("it")) { 473089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = Mnemonic.slice(2, Mnemonic.size()); 473189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mnemonic = Mnemonic.slice(0, 2); 473289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 473389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4734352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4735352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar} 47363771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 47373771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// \brief Given a canonical mnemonic, determine if the instruction ever allows 47383771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// inclusion of carry set or predication code operands. 47393771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// 47403771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// FIXME: It would be nice to autogen this. 4741fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopesvoid ARMAsmParser:: 47421355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachgetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4743fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode) { 4744eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4745eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 47463443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach Mnemonic == "add" || Mnemonic == "adc" || 4747eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4748d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "orr" || Mnemonic == "mvn" || 4749eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4750d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 475182509e5c62a99912c636b22e227b810eaf6eda78Evan Cheng Mnemonic == "vfm" || Mnemonic == "vfnm" || 47523443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4753d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "mla" || Mnemonic == "smlal" || 4754d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "umlal" || Mnemonic == "umull"))) { 4755eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = true; 4756fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 4757eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = false; 47583771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 4759eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4760eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4761eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4762eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4763ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4764ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach (Mnemonic == "clrex" && !isThumb()) || 47650780b6303b99441fef04340b7a083006484f4743Jim Grosbach (Mnemonic == "nop" && isThumbOne()) || 47662bd0118472de352745a2e038245fab4974f7c87eJim Grosbach ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 47672bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 47682bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 47694af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 47704af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach !isThumb()) || 47711ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 47723771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = false; 4773fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 47743771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = true; 4775fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes 4776fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach if (isThumb()) { 4777fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 477863b46faeb8acae9b7e5f865b7417dc00b9b9dad3Jim Grosbach Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4779fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes CanAcceptPredicationCode = false; 4780fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } 4781badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar} 4782badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4783d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbachbool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4784d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 478520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // FIXME: This is all horribly hacky. We really need a better way to deal 478620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // with optional operands like this in the matcher table. 4787d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 4788d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4789d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // another does not. Specifically, the MOVW instruction does not. So we 4790d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // special case it here and remove the defaulted (non-setting) cc_out 4791d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // operand if that's the instruction we're trying to match. 4792d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // 4793d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // We do this as post-processing of the explicit operands rather than just 4794d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // conditionally adding the cc_out in the first place because we need 4795d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // to check the type of the parsed immediate operand. 47968adf62034a874adacff158e8adc9438cb3e67c01Owen Anderson if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4797d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4798d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4799d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4800d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return true; 48013912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 48023912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 48033912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // when there are only two register operands. 48043912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 48053912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 48063912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 48073912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 48083912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach return true; 480972f39f8436848885176943b0ba985a7171145423Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 481020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 481120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // have to check the immediate range here since Thumb2 has a variant 481220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // that can handle a different range and has a cc_out operand. 4813f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (((isThumb() && Mnemonic == "add") || 4814f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach (isThumbTwo() && Mnemonic == "sub")) && 4815f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 481672f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 481772f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 481872f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 481920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4820a23ecc2ba945c9685a76552276e5f6f41859b4abJim Grosbach ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 482120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 482272f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 4823f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // For Thumb2, add/sub immediate does not have a cc_out operand for the 4824f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // imm0_4095 variant. That's the least-preferred variant when 482520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // selecting via the generic "add" mnemonic, so to know that we 482620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // should remove the cc_out operand, we have to explicitly check that 482720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // it's not one of the other variants. Ugh. 4828f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4829f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 483020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 483120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 483220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 483320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Nest conditions rather than one big 'if' statement for readability. 483420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // 483520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If either register is a high reg, it's either one of the SP 483620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // variants (handled above) or a 32-bit encoding, so we just 483712a8863828879168ffd634df09f3aa91b0b256eeJim Grosbach // check against T3. If the second register is the PC, this is an 483812a8863828879168ffd634df09f3aa91b0b256eeJim Grosbach // alternate form of ADR, which uses encoding T4, so check for that too. 483920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 484020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 484112a8863828879168ffd634df09f3aa91b0b256eeJim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 484220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 484320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 484420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If both registers are low, we're in an IT block, and the immediate is 484520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // in range, we should use encoding T1 instead, which has a cc_out. 484620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (inITBlock() && 484764944f48a1164c02c15ca423a53919682a89074cJim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 484820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 484920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 485020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 485120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 485220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Otherwise, we use encoding T4, which does not have a cc_out 485320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // operand. 485420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return true; 485520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach } 485620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 485764944f48a1164c02c15ca423a53919682a89074cJim Grosbach // The thumb2 multiply instruction doesn't have a CCOut register, so 485864944f48a1164c02c15ca423a53919682a89074cJim Grosbach // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 485964944f48a1164c02c15ca423a53919682a89074cJim Grosbach // use the 16-bit encoding or not. 486064944f48a1164c02c15ca423a53919682a89074cJim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 486164944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 486264944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 486364944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 486464944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->isReg() && 486564944f48a1164c02c15ca423a53919682a89074cJim Grosbach // If the registers aren't low regs, the destination reg isn't the 486664944f48a1164c02c15ca423a53919682a89074cJim Grosbach // same as one of the source regs, or the cc_out operand is zero 486764944f48a1164c02c15ca423a53919682a89074cJim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 486864944f48a1164c02c15ca423a53919682a89074cJim Grosbach // remove the cc_out operand. 486964944f48a1164c02c15ca423a53919682a89074cJim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 487064944f48a1164c02c15ca423a53919682a89074cJim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 48711de0bd194540f8bab399fb39c4ba615a7b2381d3Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 487264944f48a1164c02c15ca423a53919682a89074cJim Grosbach !inITBlock() || 487364944f48a1164c02c15ca423a53919682a89074cJim Grosbach (static_cast<ARMOperand*>(Operands[3])->getReg() != 487464944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->getReg() && 487564944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() != 487664944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg()))) 487764944f48a1164c02c15ca423a53919682a89074cJim Grosbach return true; 487864944f48a1164c02c15ca423a53919682a89074cJim Grosbach 48797f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // Also check the 'mul' syntax variant that doesn't specify an explicit 48807f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // destination register. 48817f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 48827f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 48837f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 48847f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 48857f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // If the registers aren't low regs or the cc_out operand is zero 48867f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 48877f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // remove the cc_out operand. 48887f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 48897f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 48907f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !inITBlock())) 48917f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach return true; 48927f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach 489364944f48a1164c02c15ca423a53919682a89074cJim Grosbach 489420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 4895f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // Register-register 'add/sub' for thumb does not have a cc_out operand 4896f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4897f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4898f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // right, this will result in better diagnostics (which operand is off) 4899f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // anyway. 4900f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4901f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach (Operands.size() == 5 || Operands.size() == 6) && 490272f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 490372f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4904a23ecc2ba945c9685a76552276e5f6f41859b4abJim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4905a23ecc2ba945c9685a76552276e5f6f41859b4abJim Grosbach (static_cast<ARMOperand*>(Operands[4])->isImm() || 4906a23ecc2ba945c9685a76552276e5f6f41859b4abJim Grosbach (Operands.size() == 6 && 4907a23ecc2ba945c9685a76552276e5f6f41859b4abJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()))) 490872f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 49093912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 4910d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return false; 4911d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach} 4912d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 49137aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool isDataTypeToken(StringRef Tok) { 49147aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 49157aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 49167aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 49177aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 49187aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 49197aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".f" || Tok == ".d"; 49207aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 49217aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 49227aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// FIXME: This bit should probably be handled via an explicit match class 49237aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// in the .td files that matches the suffix instead of having it be 49247aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// a literal string token the way it is now. 49257aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 49267aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 49277aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 49287aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 492921d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbachstatic void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4930badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar/// Parse an arm instruction mnemonic followed by its operands. 4931badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbarbool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4932badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 493321d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // Apply mnemonic aliases before doing anything else, as the destination 493421d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // mnemnonic may include suffices and we want to handle them normally. 493521d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // The generic tblgen'erated code does this later, at the start of 493621d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // MatchInstructionImpl(), but that's too late for aliases that include 493721d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // any sort of suffix. 493821d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach unsigned AvailableFeatures = getAvailableFeatures(); 493921d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach applyMnemonicAliases(Name, AvailableFeatures); 494021d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach 4941a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // First check for the ARM-specific .req directive. 4942a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier) && 4943a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.getTok().getIdentifier() == ".req") { 4944a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach parseDirectiveReq(Name, NameLoc); 4945a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // We always return 'error' for this, as we're done with this 4946a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // statement and don't need to match the 'instruction." 4947a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return true; 4948a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 4949a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 4950badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Create the leading tokens for the mnemonic, split by '.' characters. 4951badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar size_t Start = 0, Next = Name.find('.'); 4952ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach StringRef Mnemonic = Name.slice(Start, Next); 4953badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4954352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Split out the predication code and carry setting flag from the mnemonic. 4955352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar unsigned PredicationCode; 4956a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned ProcessorIMod; 4957352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar bool CarrySetting; 495889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef ITMask; 49591355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 496089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ProcessorIMod, ITMask); 4961badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 49620c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach // In Thumb1, only the branch (B) instruction can be predicated. 49630c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 49640c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach Parser.EatToEndOfStatement(); 49650c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach return Error(NameLoc, "conditional execution not supported in Thumb1"); 49660c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach } 49670c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach 4968ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4969ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 497089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // Handle the IT instruction ITMask. Convert it to a bitmask. This 497189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // is the mask as it will be for the IT encoding if the conditional 497289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 497389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // where the conditional bit0 is zero, the instruction post-processing 497489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // will adjust the mask accordingly. 497589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic == "it") { 4976f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4977f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITMask.size() > 3) { 4978f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Parser.EatToEndOfStatement(); 4979f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "too many conditions on IT instruction"); 4980f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 498189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = 8; 498289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = ITMask.size(); i != 0; --i) { 498389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach char pos = ITMask[i - 1]; 498489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (pos != 't' && pos != 'e') { 498589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.EatToEndOfStatement(); 4986f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 498789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 498889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask >>= 1; 498989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (ITMask[i - 1] == 't') 499089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask |= 8; 499189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 4992f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 499389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 499489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4995ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // FIXME: This is all a pretty gross hack. We should automatically handle 4996ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // optional operands like this via tblgen. 49979717fa9f29696bca45ddfdf206b1c382c8b40b78Bill Wendling 49983771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Next, add the CCOut and ConditionCode operands, if needed. 49993771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // 50003771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // For mnemonics which can ever incorporate a carry setting bit or predication 50013771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // code, our matching model involves us always generating CCOut and 50023771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // ConditionCode operands to match the mnemonic "as written" and then we let 50033771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // the matcher deal with finding the right instruction or generating an 50043771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // appropriate error. 50053771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar bool CanAcceptCarrySet, CanAcceptPredicationCode; 50061355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 50073771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 500833c16a27370939de39679245c3dff72383c210bdJim Grosbach // If we had a carry-set on an instruction that can't do that, issue an 500933c16a27370939de39679245c3dff72383c210bdJim Grosbach // error. 501033c16a27370939de39679245c3dff72383c210bdJim Grosbach if (!CanAcceptCarrySet && CarrySetting) { 501133c16a27370939de39679245c3dff72383c210bdJim Grosbach Parser.EatToEndOfStatement(); 5012ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 501333c16a27370939de39679245c3dff72383c210bdJim Grosbach "' can not set flags, but 's' suffix specified"); 501433c16a27370939de39679245c3dff72383c210bdJim Grosbach } 5015c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // If we had a predication code on an instruction that can't do that, issue an 5016c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // error. 5017c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5018c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.EatToEndOfStatement(); 5019c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 5020c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach "' is not predicable, but condition code specified"); 5021c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 502233c16a27370939de39679245c3dff72383c210bdJim Grosbach 50233771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the carry setting operand, if necessary. 5024f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (CanAcceptCarrySet) { 5025f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 50263771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5027f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Loc)); 5028f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 50293771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 50303771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the predication code operand, if necessary. 50313771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar if (CanAcceptPredicationCode) { 5032f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5033f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CarrySetting); 50343771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCondCode( 5035f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes(PredicationCode), Loc)); 5036badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar } 5037345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 5038a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Add the processor imod operand, if necessary. 5039a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (ProcessorIMod) { 5040a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateImm( 5041a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes MCConstantExpr::Create(ProcessorIMod, getContext()), 5042a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes NameLoc, NameLoc)); 5043a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 5044a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 5045345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar // Add the remaining tokens in the mnemonic. 50465747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar while (Next != StringRef::npos) { 50475747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Start = Next; 50485747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Next = Name.find('.', Start + 1); 5049a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef ExtraToken = Name.slice(Start, Next); 5050a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 50517aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // Some NEON instructions have an optional datatype suffix that is 50527aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // completely ignored. Check for that. 50537aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach if (isDataTypeToken(ExtraToken) && 50547aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 50557aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach continue; 50567aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 505781d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach if (ExtraToken != ".n") { 505881d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 505981d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 506081d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach } 50615747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar } 50625747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar 50635747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar // Read the remaining operands. 50645747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar if (getLexer().isNot(AsmToken::EndOfStatement)) { 5065a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Read the first operand. 50661355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 5067cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 5068cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 5069cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 5070a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 5071a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby while (getLexer().is(AsmToken::Comma)) { 5072b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat the comma. 5073a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 5074a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Parse and remember the operand. 50751355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 5076cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 5077cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 5078cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 5079a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 5080a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 508116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 5082cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner if (getLexer().isNot(AsmToken::EndOfStatement)) { 5083186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach SMLoc Loc = getLexer().getLoc(); 5084cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 5085186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach return Error(Loc, "unexpected token in argument list"); 5086cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 5087146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 508834e53140c2cc02ce4c9d060e48302576d3962e1cChris Lattner Parser.Lex(); // Consume the EndOfStatement 5089ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 5090d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // Some instructions, mostly Thumb, have forms for the same mnemonic that 5091d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // do and don't have a cc_out optional-def operand. With some spot-checks 5092d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // of the operand list, we can figure out which variant we're trying to 509320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // parse and adjust accordingly before actually matching. We shouldn't ever 509420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // try to remove a cc_out operand that was explicitly set on the the 509520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // mnemonic, of course (CarrySetting == true). Reason number #317 the 509620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // table driven matcher doesn't fit well with the ARM instruction set. 509720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5098ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5099ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.erase(Operands.begin() + 1); 5100ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach delete Op; 5101ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 5102ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 5103cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // ARM mode 'blx' need special handling, as the register operand version 5104cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // is predicable, but the label operand version is not. So, we can't rely 5105cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // on the Mnemonic based checking to correctly figure out when to put 510621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // a k_CondCode operand in the list. If we're trying to match the label 510721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // version, remove the k_CondCode operand here. 5108cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5109cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach static_cast<ARMOperand*>(Operands[2])->isImm()) { 5110cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5111cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach Operands.erase(Operands.begin() + 1); 5112cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach delete Op; 5113cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach } 5114857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach 5115857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // The vector-compare-to-zero instructions have a literal token "#0" at 5116857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // the end that comes to here as an immediate operand. Convert it to a 5117857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // token to play nicely with the matcher. 5118857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 5119857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 5120857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 5121857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5122857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5123857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if (CE && CE->getValue() == 0) { 5124857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.erase(Operands.begin() + 5); 5125857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 512668259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach delete Op; 512768259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 512868259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 512968259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach // VCMP{E} does the same thing, but with a different operand count. 513068259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 513168259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm()) { 513268259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 513368259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 513468259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if (CE && CE->getValue() == 0) { 513568259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.erase(Operands.begin() + 4); 513668259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5137857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach delete Op; 5138857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 5139857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 5140934755ac040c516eac7fdd974e87590543acd16aJim Grosbach // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 514155b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // end. Convert it to a token here. Take care not to convert those 514255b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // that should hit the Thumb2 encoding. 5143934755ac040c516eac7fdd974e87590543acd16aJim Grosbach if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 514455b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 514555b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 5146934755ac040c516eac7fdd974e87590543acd16aJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 5147934755ac040c516eac7fdd974e87590543acd16aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5148934755ac040c516eac7fdd974e87590543acd16aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 514955b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach if (CE && CE->getValue() == 0 && 515055b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isThumbOne() || 5151d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // The cc_out operand matches the IT block. 5152d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach ((inITBlock() != CarrySetting) && 5153d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // Neither register operand is a high register. 515455b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5155d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 5156934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.erase(Operands.begin() + 5); 5157934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5158934755ac040c516eac7fdd974e87590543acd16aJim Grosbach delete Op; 5159934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 5160934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 5161934755ac040c516eac7fdd974e87590543acd16aJim Grosbach 51629898671a74d3fc924347e679c45edaa685b3fe6eChris Lattner return false; 5163ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 5164ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 5165189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// Validate context-sensitive operand constraints. 5166aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 5167aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// return 'true' if register list contains non-low GPR registers, 5168aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'false' otherwise. If Reg is in the register list or is HiReg, set 5169aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'containsReg' to true. 5170aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbachstatic bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5171aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned HiReg, bool &containsReg) { 5172aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = false; 5173aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5174aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 5175aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (OpReg == Reg) 5176aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = true; 5177aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach // Anything other than a low register isn't legal here. 5178aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5179aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return true; 5180aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach } 5181aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return false; 5182aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach} 5183aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 518476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// Check if the specified regisgter is in the register list of the inst, 518576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// starting at the indicated operand number. 518676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbachstatic bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 518776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 518876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 518976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (OpReg == Reg) 519076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return true; 519176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 519276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return false; 519376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach} 519476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach 5195f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5196f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// the ARMInsts array) instead. Getting that here requires awkward 5197f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// API changes, though. Better way? 5198f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbachnamespace llvm { 51991a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerextern const MCInstrDesc ARMInsts[]; 5200f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 52011a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerstatic const MCInstrDesc &getInstDesc(unsigned Opcode) { 5202f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return ARMInsts[Opcode]; 5203f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 5204f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 5205189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// FIXME: We would really like to be able to tablegen'erate this. 5206189610f9466686a91fb7d847b572e1645c785323Jim Grosbachbool ARMAsmParser:: 5207189610f9466686a91fb7d847b572e1645c785323Jim GrosbachvalidateInstruction(MCInst &Inst, 5208189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 52091a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5210f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = Operands[0]->getStartLoc(); 5211f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Check the IT block state first. 521274423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach // NOTE: BKPT instruction has the interesting property of being 521374423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach // allowed in IT blocks, but not being predicable. It just always 5214b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // executes. 521574423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 521674423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach Inst.getOpcode() != ARM::BKPT) { 5217f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned bit = 1; 5218f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITState.FirstCond) 5219f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = false; 5220f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach else 5221a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5222f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // The instruction must be predicable. 5223f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (!MCID.isPredicable()) 5224f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "instructions in IT block must be predicable"); 5225f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5226f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned ITCond = bit ? ITState.Cond : 5227f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::getOppositeCondition(ITState.Cond); 5228f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (Cond != ITCond) { 5229f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Find the condition code Operand to get its SMLoc information. 5230f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc CondLoc; 5231f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach for (unsigned i = 1; i < Operands.size(); ++i) 5232f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5233f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CondLoc = Operands[i]->getStartLoc(); 5234f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(CondLoc, "incorrect condition in IT block; got '" + 5235f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5236f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach "', but expected '" + 5237f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5238f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 5239c9a9b442853ee086492d6ad1384a2de2fea9b43bJim Grosbach // Check for non-'al' condition codes outside of the IT block. 5240f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } else if (isThumbTwo() && MCID.isPredicable() && 5241f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 524251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson ARMCC::AL && Inst.getOpcode() != ARM::tB && 524351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.getOpcode() != ARM::t2B) 5244f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "predicated instructions must be in IT block"); 5245f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 5246189610f9466686a91fb7d847b572e1645c785323Jim Grosbach switch (Inst.getOpcode()) { 52472fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD: 52482fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_PRE: 52492fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_POST: 5250189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::LDREXD: { 5251189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5252189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5253189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5254189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 5255189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return Error(Operands[3]->getStartLoc(), 5256189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "destination operands must be sequential"); 5257189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5258189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 525914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach case ARM::STRD: { 526014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt2 must be Rt + 1. 526114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 526214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 526314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach if (Rt2 != Rt + 1) 526414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 526514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach "source operands must be sequential"); 526614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return false; 526714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach } 526853642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_PRE: 526953642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_POST: 5270189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::STREXD: { 5271189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5272189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5273189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 5274189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 527514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 5276189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "source operands must be sequential"); 5277189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5278189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5279fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::SBFX: 5280fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::UBFX: { 5281fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach // width must be in range [1, 32-lsb] 5282fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned lsb = Inst.getOperand(2).getImm(); 5283fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned widthm1 = Inst.getOperand(3).getImm(); 5284fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach if (widthm1 >= 32 - lsb) 5285fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach return Error(Operands[5]->getStartLoc(), 5286fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach "bitfield width must be in range [1,32-lsb]"); 528700c9a518886c4f2d1cd869c174c994c20a353906Jim Grosbach return false; 5288fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach } 528993b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach case ARM::tLDMIA: { 529076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're parsing Thumb2, the .w variant is available and handles 529176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // most cases that are normally illegal for a Thumb1 LDM 529276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instruction. We'll make the transformation in processInstruction() 529376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // if necessary. 529476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 529593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // Thumb LDM instructions are writeback iff the base register is not 529693b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // in the register list. 529793b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 52987260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach bool hasWritebackToken = 52997260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 53007260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5301aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 530276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5303aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5304aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7"); 530593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // If we should have writeback, then there should be a '!' token. 530676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 530793b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach return Error(Operands[2]->getStartLoc(), 530893b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach "writeback operator '!' expected"); 530976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we should not have writeback, there must not be a '!'. This is 531076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // true even for the 32-bit wide encodings. 5311aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (listContainsBase && hasWritebackToken) 53127260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach return Error(Operands[3]->getStartLoc(), 53137260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "writeback operator '!' not allowed when base register " 53147260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "in register list"); 531593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach 531693b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach break; 531793b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach } 531876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::t2LDMIA_UPD: { 531976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 532076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return Error(Operands[4]->getStartLoc(), 532176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "writeback operator '!' not allowed when base register " 532276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "in register list"); 532376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 532476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 53255402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 53265402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // so only issue a diagnostic for thumb1. The instructions will be 53275402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // switched to the t2 encodings in processInstruction() if necessary. 53286dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPOP: { 5329aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 53305402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 53315402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5332aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5333aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or pc"); 53346dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 53356dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 53366dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPUSH: { 5337aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 53385402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 53395402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5340aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5341aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or lr"); 53426dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 53436dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 53441e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach case ARM::tSTMIA_UPD: { 53451e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach bool listContainsBase; 53468213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 53471e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach return Error(Operands[4]->getStartLoc(), 53481e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach "registers must be in range r0-r7"); 53491e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach break; 53501e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach } 5351a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach case ARM::tADDrSP: { 5352a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach // If the non-SP source operand and the destination operand are not the 5353a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach // same, we need thumb2 (for the wide encoding), or we have an error. 5354a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach if (!isThumbTwo() && 5355a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5356a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach return Error(Operands[4]->getStartLoc(), 5357a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach "source register must be the same as destination"); 5358a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach } 5359a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach break; 5360a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach } 5361189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5362189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 5363189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5364189610f9466686a91fb7d847b572e1645c785323Jim Grosbach} 5365189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 5366d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbachstatic unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 536784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach switch(Opc) { 5368bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("unexpected opcode!"); 53699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST1LN 53707945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 53717945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 53727945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 53737945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 53747945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 53757945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 53767945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 53777945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 53787945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 53799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 53809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST2LN 53817945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 53827945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 53837945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 53847945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 53857945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 53867945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach 53877945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 53887945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 53897945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 53907945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 53917945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 53927945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach 53937945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 53947945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 53957945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 53967945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 53977945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5398d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 53994adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach // VST3LN 54007945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 54017945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 54027945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 54037945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 54047945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 54057945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 54067945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 54077945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 54087945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 54097945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 54107945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 54117945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 54127945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 54137945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 54147945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 54154adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach 5416d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach // VST3 54177945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 54187945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 54197945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 54207945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 54217945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 54227945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 54237945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 54247945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 54257945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 54267945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 54277945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 54287945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 54297945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 54307945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 54317945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 54327945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 54337945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 54347945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5435539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach 543688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach // VST4LN 543788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 543888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 543988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 544088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 544188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 544288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 544388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 544488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 544588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 544688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 544788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 544888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 544988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 545088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 545188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 545288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach 5453539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach // VST4 5454539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5455539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5456539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5457539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5458539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5459539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5460539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5461539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5462539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5463539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5464539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5465539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5466539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5467539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5468539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5469539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5470539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5471539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 547284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 547384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach} 547484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach 5475d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbachstatic unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 54767636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach switch(Opc) { 5477bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("unexpected opcode!"); 54789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD1LN 54797945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 54807945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 54817945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 54827945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 54837945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 54847945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 54857945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 54867945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 54877945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 54889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 54899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD2LN 54907945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 54917945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 54927945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 54937945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 54947945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 54957945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 54967945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 54977945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 54987945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 54997945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 55007945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 55017945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 55027945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 55037945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 55047945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 55053a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 55065e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // VLD3DUP 55075e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 55085e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 55095e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 55105e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 55115e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 55125e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 55135e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 55145e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 55155e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 55165e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 55175e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 55185e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 55195e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 55205e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 55215e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 55225e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 55235e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 55245e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 55255e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 55263a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // VLD3LN 55277945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 55287945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 55297945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 55307945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 55317945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 55327945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 55337945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 55347945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 55357945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 55367945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 55377945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 55387945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 55397945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 55407945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 55417945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5542c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 5543c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach // VLD3 55447945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 55457945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 55467945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 55477945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 55487945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 55497945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 55507945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 55517945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 55527945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 55537945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 55547945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 55557945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 55567945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 55577945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 55587945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 55597945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 55607945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 55617945eade3d8db8c1dd52a291cee5d55ac0539586Jim Grosbach case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 55628abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach 5563e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach // VLD4LN 5564e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5565e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5566e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5567e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5568e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5569e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5570e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5571e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5572e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5573e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5574e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5575e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5576e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5577e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5578e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5579e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 5580a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // VLD4DUP 5581a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5582a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5583a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5584a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5585a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5586a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5587a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5588a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5589a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5590a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5591a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5592a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5593a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5594a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5595a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5596a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5597a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5598a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5599a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 56008abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach // VLD4 56018abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 56028abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 56038abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 56048abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 56058abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 56068abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 56078abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 56088abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 56098abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 56108abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 56118abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 56128abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 56138abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 56148abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 56158abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 56168abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 56178abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 56188abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 56197636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 56207636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach} 56217636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 562283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbachbool ARMAsmParser:: 5623f8fce711e8b756adca63044f7d122648c960ab96Jim GrosbachprocessInstruction(MCInst &Inst, 5624f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5625f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach switch (Inst.getOpcode()) { 56260b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Aliases for alternate PC+imm syntax of LDR instructions. 56270b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRpcrel: 56280b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRpci); 56290b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 56300b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRBpcrel: 56310b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRBpci); 56320b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 56330b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRHpcrel: 56340b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRHpci); 56350b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 56360b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRSBpcrel: 56370b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRSBpci); 56380b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 56390b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRSHpcrel: 56400b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRSHpci); 56410b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 56429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VST complex aliases. 56438b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_8: 56448b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_16: 56458b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_32: { 564684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 564784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 564884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 56495b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5650d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 565184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 565284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 565384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 565484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 565584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 565684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 565784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 565884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 565984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 566084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 566184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 56629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 56638b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_8: 56648b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_16: 56658b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_32: 56668b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_register_Asm_16: 56678b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_register_Asm_32: { 56689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 56699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 56715b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5672d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 56739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 56749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 56769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 56779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 56785b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 56795b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 56809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 56819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 56829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 56839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 56849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 56859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 56864adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach 56874adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdWB_register_Asm_8: 56884adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdWB_register_Asm_16: 56894adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdWB_register_Asm_32: 56904adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNqWB_register_Asm_16: 56914adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNqWB_register_Asm_32: { 56924adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach MCInst TmpInst; 56934adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56944adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach // right place. 56954adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach unsigned Spacing; 56964adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 56974adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 56984adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56994adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57004adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 57014adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 57024adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 57034adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Spacing)); 57044adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 57054adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Spacing * 2)); 57064adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57074adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 57084adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 57094adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Inst = TmpInst; 57104adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach return true; 57114adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach } 57124adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach 571388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_register_Asm_8: 571488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_register_Asm_16: 571588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_register_Asm_32: 571688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_register_Asm_16: 571788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_register_Asm_32: { 571888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach MCInst TmpInst; 571988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach // Shuffle the operands around so the lane index operand is in the 572088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach // right place. 572188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach unsigned Spacing; 572288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 572388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 572488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 572588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 572688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 572788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 572888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 572988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing)); 573088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 573188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing * 2)); 573288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 573388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing * 3)); 573488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 573588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 573688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 573788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Inst = TmpInst; 573888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach return true; 573988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach } 574088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach 57418b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: 57428b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_16: 57438b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: { 574484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 574584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 574684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 57475b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5748d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 574984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 575084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 575184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 575284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 575384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 575484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 575584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 575684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 575784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 575884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 575984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 57609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 57618b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: 57628b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_16: 57638b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: 57648b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: 57658b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_fixed_Asm_32: { 57669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 57679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 57689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 57695b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5770d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 57719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 57729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 57759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 57765b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 57775b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 57789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 57829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 57839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 57844adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach 57854adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdWB_fixed_Asm_8: 57864adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdWB_fixed_Asm_16: 57874adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdWB_fixed_Asm_32: 57884adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNqWB_fixed_Asm_16: 57894adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNqWB_fixed_Asm_32: { 57904adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach MCInst TmpInst; 57914adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach // Shuffle the operands around so the lane index operand is in the 57924adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach // right place. 57934adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach unsigned Spacing; 57944adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 57954adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 57964adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57974adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57984adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 57994adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 58004adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 58014adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Spacing)); 58024adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 58034adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Spacing * 2)); 58044adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 58054adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 58064adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 58074adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Inst = TmpInst; 58084adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach return true; 58094adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach } 58104adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach 581188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_fixed_Asm_8: 581288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_fixed_Asm_16: 581388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdWB_fixed_Asm_32: 581488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_fixed_Asm_16: 581588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqWB_fixed_Asm_32: { 581688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach MCInst TmpInst; 581788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach // Shuffle the operands around so the lane index operand is in the 581888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach // right place. 581988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach unsigned Spacing; 582088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 582188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 582288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 582388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 582488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 582588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 582688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 582788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing)); 582888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 582988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing * 2)); 583088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 583188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing * 3)); 583288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 583388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 583488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 583588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Inst = TmpInst; 583688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach return true; 583788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach } 583888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach 58398b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_8: 58408b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_16: 58418b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_32: { 584284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 584384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 584484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 58455b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5846d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 584784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 584884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 584984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 585084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 585184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 585284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 585384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 585484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 585584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 58569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 58578b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_8: 58588b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_16: 58598b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_32: 58608b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqAsm_16: 58618b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqAsm_32: { 58629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 58639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 58649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 58655b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5866d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 58679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 58689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 58699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 58705b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 58715b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 58729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 58739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 58749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 58759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 58769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 58779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 58784adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach 58794adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdAsm_8: 58804adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdAsm_16: 58814adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNdAsm_32: 58824adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNqAsm_16: 58834adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach case ARM::VST3LNqAsm_32: { 58844adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach MCInst TmpInst; 58854adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach // Shuffle the operands around so the lane index operand is in the 58864adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach // right place. 58874adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach unsigned Spacing; 58884adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 58894adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 58904adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 58914adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 58924adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 58934adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Spacing)); 58944adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 58954adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Spacing * 2)); 58964adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 58974adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 58984adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 589988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Inst = TmpInst; 590088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach return true; 590188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach } 590288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach 590388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdAsm_8: 590488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdAsm_16: 590588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNdAsm_32: 590688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqAsm_16: 590788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach case ARM::VST4LNqAsm_32: { 590888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach MCInst TmpInst; 590988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach // Shuffle the operands around so the lane index operand is in the 591088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach // right place. 591188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach unsigned Spacing; 591288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 591388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 591488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 591588a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 591688a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 591788a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing)); 591888a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 591988a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing * 2)); 592088a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 592188a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach Spacing * 3)); 592288a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 592388a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 592488a54de799240d5de2e79dfff4671ad5653e7cebJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 59254adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach Inst = TmpInst; 59264adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach return true; 59274adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach } 59284adb18234278d6d40e5791e0dd6970be9a4b0b57Jim Grosbach 59299b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VLD complex aliases. 59308b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_8: 59318b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_16: 59328b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_32: { 5933872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 5934872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 5935872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 593695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5937d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5938872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5939872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5940872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 5941872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 5942872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 5943872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5944872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 5945872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5946872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 5947872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 5948872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 5949872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 59509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 59518b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_8: 59528b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_16: 59538b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_32: 59548b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_register_Asm_16: 59558b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_register_Asm_32: { 59569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 59579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 59589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 595995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5960d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 59619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 596295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 596395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 59649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 59659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 59669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 59679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 59689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 596995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 597095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 59719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 59729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 59739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 59749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 59759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 59769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 59779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 59783a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_8: 59793a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_16: 59803a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_32: 59813a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_register_Asm_16: 59823a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_register_Asm_32: { 59833a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach MCInst TmpInst; 59843a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // Shuffle the operands around so the lane index operand is in the 59853a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // right place. 59863a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach unsigned Spacing; 5987d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 59883a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 59893a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 59903a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 59913a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5992c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 59933a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 59943a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 59953a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 59963a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 59973a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 59983a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 59993a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 60003a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6001c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 60023a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 60033a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 60043a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 60053a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Inst = TmpInst; 60063a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return true; 60073a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 60083a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 6009e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_register_Asm_8: 6010e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_register_Asm_16: 6011e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_register_Asm_32: 6012e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_register_Asm_16: 6013e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_register_Asm_32: { 6014e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach MCInst TmpInst; 6015e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach // Shuffle the operands around so the lane index operand is in the 6016e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach // right place. 6017e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach unsigned Spacing; 6018e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6019e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6020e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6021e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing)); 6022e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6023e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 2)); 6024e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6025e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 3)); 6026e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6027e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 6028e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 6029e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 6030e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6031e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6032e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing)); 6033e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6034e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 2)); 6035e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6036e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 3)); 6037e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 6038e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6039e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 6040e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Inst = TmpInst; 6041e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return true; 6042e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 6043e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 60448b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: 60458b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_16: 60468b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: { 6047872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 6048872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 6049872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 605095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 6051d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6052872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6053872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6054872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 6055872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 6056872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6057872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6058872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 6059872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6060872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6061872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 6062872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 6063872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 60649b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 60658b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: 60668b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_16: 60678b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: 60688b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: 60698b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_32: { 60709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 60719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 60729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 607395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 6074d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 60759b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 607695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 607795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 60789b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 60799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 60809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 60819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 60829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 608395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 608495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 60859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 60869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 60879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 60889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 60899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 60909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 60919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 60923a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_8: 60933a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_16: 60943a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_32: 60953a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_fixed_Asm_16: 60963a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_fixed_Asm_32: { 60973a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach MCInst TmpInst; 60983a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // Shuffle the operands around so the lane index operand is in the 60993a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // right place. 61003a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach unsigned Spacing; 6101d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 61023a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 61033a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 61043a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 61053a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6106c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 61073a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 61083a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 61093a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 61103a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 61113a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 61123a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 61133a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 61143a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6115c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 61163a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 61173a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 61183a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 61193a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Inst = TmpInst; 61203a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return true; 61213a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 61223a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 6123e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_fixed_Asm_8: 6124e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_fixed_Asm_16: 6125e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdWB_fixed_Asm_32: 6126e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_fixed_Asm_16: 6127e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqWB_fixed_Asm_32: { 6128e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach MCInst TmpInst; 6129e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach // Shuffle the operands around so the lane index operand is in the 6130e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach // right place. 6131e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach unsigned Spacing; 6132e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6133e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6134e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6135e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing)); 6136e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6137e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 2)); 6138e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6139e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 3)); 6140e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6141e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 6142e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 6143e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6144e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6145e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6146e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing)); 6147e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6148e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 2)); 6149e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6150e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 3)); 6151e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 6152e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6153e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6154e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Inst = TmpInst; 6155e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return true; 6156e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 6157e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 61588b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_8: 61598b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_16: 61608b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_32: { 61617636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach MCInst TmpInst; 61627636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // Shuffle the operands around so the lane index operand is in the 61637636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // right place. 616495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 6165d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 61667636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 61677636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 61687636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 61697636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 61707636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 61717636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 61727636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 61737636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst = TmpInst; 61747636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return true; 61757636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 61769b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 61778b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_8: 61788b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_16: 61798b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_32: 61808b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqAsm_16: 61818b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqAsm_32: { 61829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 61839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 61849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 618595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 6186d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 61879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 618895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 618995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 61909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 61919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 61929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 619395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 619495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 61959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 61969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 61979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 61989b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 61999b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 62009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 62013a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 62023a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_8: 62033a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_16: 62043a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_32: 62053a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqAsm_16: 62063a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqAsm_32: { 62073a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach MCInst TmpInst; 62083a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // Shuffle the operands around so the lane index operand is in the 62093a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // right place. 62103a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach unsigned Spacing; 6211d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 62123a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 62133a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 62143a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 62153a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6216c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 62173a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 62183a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 62193a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 62203a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 62213a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 62223a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6223c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 62243a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 62253a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 62263a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 62273a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Inst = TmpInst; 62283a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return true; 62293a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 62303a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 6231e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdAsm_8: 6232e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdAsm_16: 6233e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNdAsm_32: 6234e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqAsm_16: 6235e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach case ARM::VLD4LNqAsm_32: { 6236e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach MCInst TmpInst; 6237e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach // Shuffle the operands around so the lane index operand is in the 6238e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach // right place. 6239e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach unsigned Spacing; 6240e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6241e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6242e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6243e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing)); 6244e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6245e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 2)); 6246e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6247e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 3)); 6248e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 6249e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 6250e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6251e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6252e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing)); 6253e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6254e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 2)); 6255e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6256e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Spacing * 3)); 6257e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 6258e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6259e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6260e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach Inst = TmpInst; 6261e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach return true; 6262e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach } 6263e983a134e7e40e214f590c3d8ba565bb85f39628Jim Grosbach 62645e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // VLD3DUP single 3-element structure to all lanes instructions. 62655e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdAsm_8: 62665e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdAsm_16: 62675e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdAsm_32: 62685e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqAsm_8: 62695e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqAsm_16: 62705e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqAsm_32: { 62715e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach MCInst TmpInst; 62725e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach unsigned Spacing; 62735e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 62745e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 62755e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 62765e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Spacing)); 62775e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 62785e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Spacing * 2)); 62795e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 62805e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 62815e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 62825e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 62835e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Inst = TmpInst; 62845e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach return true; 62855e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach } 62865e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 62875e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_fixed_Asm_8: 62885e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_fixed_Asm_16: 62895e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_fixed_Asm_32: 62905e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_fixed_Asm_8: 62915e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_fixed_Asm_16: 62925e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_fixed_Asm_32: { 62935e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach MCInst TmpInst; 62945e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach unsigned Spacing; 62955e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 62965e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 62975e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 62985e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Spacing)); 62995e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 63005e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Spacing * 2)); 63015e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 63025e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 63035e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 63045e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 63055e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 63065e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 63075e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Inst = TmpInst; 63085e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach return true; 63095e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach } 63105e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 63115e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_register_Asm_8: 63125e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_register_Asm_16: 63135e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPdWB_register_Asm_32: 63145e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_register_Asm_8: 63155e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_register_Asm_16: 63165e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach case ARM::VLD3DUPqWB_register_Asm_32: { 63175e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach MCInst TmpInst; 63185e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach unsigned Spacing; 63195e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 63205e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 63215e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 63225e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Spacing)); 63235e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 63245e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Spacing * 2)); 63255e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 63265e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 63275e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 63285e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 63295e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 63305e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 63315e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach Inst = TmpInst; 63325e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach return true; 63335e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach } 63345e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 6335c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach // VLD3 multiple 3-element structure instructions. 6336c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_8: 6337c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_16: 6338c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_32: 6339c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_8: 6340c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_16: 6341c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_32: { 6342c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach MCInst TmpInst; 6343c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach unsigned Spacing; 6344d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6345c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6346c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6347c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing)); 6348c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6349c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 6350c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6351c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6352c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6353c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6354c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Inst = TmpInst; 6355c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return true; 6356c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 6357c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 6358c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_8: 6359c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_16: 6360c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_32: 6361c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_8: 6362c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_16: 6363c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_32: { 6364c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach MCInst TmpInst; 6365c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach unsigned Spacing; 6366d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6367c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6368c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6369c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing)); 6370c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6371c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 6372c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6373c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6374c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6375c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6376c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6377c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6378c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Inst = TmpInst; 6379c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return true; 6380c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 6381c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 6382c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_8: 6383c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_16: 6384c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_32: 6385c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_8: 6386c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_16: 6387c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_32: { 6388c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach MCInst TmpInst; 6389c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach unsigned Spacing; 6390d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6391d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6392d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6393d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing)); 6394d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6395d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing * 2)); 6396d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6397d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6398d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6399d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 6400d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6401d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6402d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Inst = TmpInst; 6403d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return true; 6404d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach } 6405d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 6406a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // VLD4DUP single 3-element structure to all lanes instructions. 6407a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdAsm_8: 6408a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdAsm_16: 6409a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdAsm_32: 6410a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqAsm_8: 6411a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqAsm_16: 6412a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqAsm_32: { 6413a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach MCInst TmpInst; 6414a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach unsigned Spacing; 6415a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6416a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6417a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6418a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing)); 6419a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6420a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing * 2)); 6421a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6422a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing * 3)); 6423a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6424a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6425a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6426a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6427a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Inst = TmpInst; 6428a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach return true; 6429a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach } 6430a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 6431a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_fixed_Asm_8: 6432a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_fixed_Asm_16: 6433a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_fixed_Asm_32: 6434a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_fixed_Asm_8: 6435a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_fixed_Asm_16: 6436a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_fixed_Asm_32: { 6437a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach MCInst TmpInst; 6438a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach unsigned Spacing; 6439a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6440a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6441a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6442a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing)); 6443a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6444a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing * 2)); 6445a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6446a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing * 3)); 6447a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6448a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6449a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6450a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6451a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6452a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6453a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Inst = TmpInst; 6454a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach return true; 6455a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach } 6456a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 6457a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_register_Asm_8: 6458a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_register_Asm_16: 6459a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPdWB_register_Asm_32: 6460a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_register_Asm_8: 6461a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_register_Asm_16: 6462a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach case ARM::VLD4DUPqWB_register_Asm_32: { 6463a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach MCInst TmpInst; 6464a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach unsigned Spacing; 6465a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6466a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6467a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6468a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing)); 6469a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6470a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing * 2)); 6471a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6472a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Spacing * 3)); 6473a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6474a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6475a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6476a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 6477a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6478a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6479a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach Inst = TmpInst; 6480a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach return true; 6481a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach } 6482a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 6483a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // VLD4 multiple 4-element structure instructions. 64848abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dAsm_8: 64858abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dAsm_16: 64868abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dAsm_32: 64878abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qAsm_8: 64888abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qAsm_16: 64898abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qAsm_32: { 64908abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach MCInst TmpInst; 64918abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach unsigned Spacing; 64928abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 64938abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 64948abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 64958abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing)); 64968abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 64978abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing * 2)); 64988abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 64998abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing * 3)); 65008abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 65018abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 65028abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 65038abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 65048abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Inst = TmpInst; 65058abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach return true; 65068abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach } 65078abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach 65088abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_fixed_Asm_8: 65098abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_fixed_Asm_16: 65108abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_fixed_Asm_32: 65118abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_fixed_Asm_8: 65128abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_fixed_Asm_16: 65138abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_fixed_Asm_32: { 65148abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach MCInst TmpInst; 65158abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach unsigned Spacing; 65168abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 65178abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 65188abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 65198abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing)); 65208abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 65218abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing * 2)); 65228abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 65238abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing * 3)); 65248abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 65258abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 65268abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 65278abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 65288abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 65298abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 65308abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Inst = TmpInst; 65318abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach return true; 65328abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach } 65338abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach 65348abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_register_Asm_8: 65358abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_register_Asm_16: 65368abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4dWB_register_Asm_32: 65378abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_register_Asm_8: 65388abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_register_Asm_16: 65398abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach case ARM::VLD4qWB_register_Asm_32: { 65408abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach MCInst TmpInst; 65418abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach unsigned Spacing; 65428abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 65438abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 65448abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 65458abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing)); 65468abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 65478abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing * 2)); 65488abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 65498abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Spacing * 3)); 65508abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 65518abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 65528abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 65538abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 65548abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 65558abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 65568abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach Inst = TmpInst; 65578abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach return true; 65588abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach } 65598abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach 6560d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach // VST3 multiple 3-element structure instructions. 6561d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_8: 6562d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_16: 6563d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_32: 6564d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_8: 6565d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_16: 6566d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_32: { 6567d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach MCInst TmpInst; 6568d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach unsigned Spacing; 6569d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6570d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6571d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6572d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6573d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6574d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing)); 6575d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6576d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing * 2)); 6577d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6578d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6579d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Inst = TmpInst; 6580d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return true; 6581d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach } 6582d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 6583d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_8: 6584d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_16: 6585d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_32: 6586d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_8: 6587d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_16: 6588d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_32: { 6589d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach MCInst TmpInst; 6590d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach unsigned Spacing; 6591d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6592d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6593d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6594d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6595d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6596c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6597c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6598c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing)); 6599c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6600c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 6601d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6602d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6603d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Inst = TmpInst; 6604d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return true; 6605d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach } 6606d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 6607d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_8: 6608d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_16: 6609d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_32: 6610d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_8: 6611d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_16: 6612d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_32: { 6613d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach MCInst TmpInst; 6614d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach unsigned Spacing; 6615d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6616c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6617c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6618c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6619c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 6620d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6621d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6622d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing)); 6623d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6624d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing * 2)); 6625c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6626c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6627c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Inst = TmpInst; 6628c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return true; 6629c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 6630c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 6631539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach // VST4 multiple 3-element structure instructions. 6632539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dAsm_8: 6633539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dAsm_16: 6634539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dAsm_32: 6635539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qAsm_8: 6636539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qAsm_16: 6637539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qAsm_32: { 6638539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach MCInst TmpInst; 6639539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach unsigned Spacing; 6640539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6641539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6642539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6643539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6644539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6645539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing)); 6646539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6647539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing * 2)); 6648539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6649539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing * 3)); 6650539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6651539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6652539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Inst = TmpInst; 6653539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach return true; 6654539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach } 6655539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach 6656539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_fixed_Asm_8: 6657539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_fixed_Asm_16: 6658539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_fixed_Asm_32: 6659539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_fixed_Asm_8: 6660539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_fixed_Asm_16: 6661539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_fixed_Asm_32: { 6662539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach MCInst TmpInst; 6663539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach unsigned Spacing; 6664539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6665539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6666539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6667539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6668539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6669539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6670539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6671539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing)); 6672539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6673539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing * 2)); 6674539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6675539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing * 3)); 6676539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6677539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6678539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Inst = TmpInst; 6679539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach return true; 6680539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach } 6681539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach 6682539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_register_Asm_8: 6683539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_register_Asm_16: 6684539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4dWB_register_Asm_32: 6685539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_register_Asm_8: 6686539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_register_Asm_16: 6687539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach case ARM::VST4qWB_register_Asm_32: { 6688539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach MCInst TmpInst; 6689539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach unsigned Spacing; 6690539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6691539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6692539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6693539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6694539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 6695539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6696539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6697539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing)); 6698539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6699539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing * 2)); 6700539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6701539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Spacing * 3)); 6702539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6703539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6704539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach Inst = TmpInst; 6705539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach return true; 6706539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach } 6707539aab771fea06bd230789e19c9672ef80ad1c7eJim Grosbach 6708a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach // Handle encoding choice for the shift-immediate instructions. 6709a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach case ARM::t2LSLri: 6710a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach case ARM::t2LSRri: 6711a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach case ARM::t2ASRri: { 6712a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6713a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6714a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6715a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6716a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6717a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach unsigned NewOpc; 6718a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach switch (Inst.getOpcode()) { 6719a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach default: llvm_unreachable("unexpected opcode"); 6720a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6721a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6722a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6723a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach } 6724a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach // The Thumb1 operands aren't in the same order. Awesome, eh? 6725a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach MCInst TmpInst; 6726a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach TmpInst.setOpcode(NewOpc); 6727a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6728a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6729a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 6730a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 6731a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6732a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6733a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach Inst = TmpInst; 6734a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach return true; 6735a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach } 6736a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach return false; 6737a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach } 6738a5378ebe7890aa9a4974f2872aa6632f1b7f2400Jim Grosbach 6739863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the Thumb2 mode MOV complex aliases. 67402cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVsr: 67412cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVSsr: { 67422cc5cda464e7c936215281934193658cb799c603Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 67432cc5cda464e7c936215281934193658cb799c603Jim Grosbach // whether we're in an IT block if the register operands are low 67442cc5cda464e7c936215281934193658cb799c603Jim Grosbach // registers. 67452cc5cda464e7c936215281934193658cb799c603Jim Grosbach bool isNarrow = false; 67462cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 67472cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 67482cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg()) && 67492cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 67502cc5cda464e7c936215281934193658cb799c603Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 67512cc5cda464e7c936215281934193658cb799c603Jim Grosbach isNarrow = true; 67522cc5cda464e7c936215281934193658cb799c603Jim Grosbach MCInst TmpInst; 67532cc5cda464e7c936215281934193658cb799c603Jim Grosbach unsigned newOpc; 67542cc5cda464e7c936215281934193658cb799c603Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 67552cc5cda464e7c936215281934193658cb799c603Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 67562cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 67572cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 67582cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 67592cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 67602cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 67612cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.setOpcode(newOpc); 67622cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 67632cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isNarrow) 67642cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 67652cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 67662cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 67672cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 67682cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 67692cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 67702cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (!isNarrow) 67712cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 67722cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 67732cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst = TmpInst; 67742cc5cda464e7c936215281934193658cb799c603Jim Grosbach return true; 67752cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 6776863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVsi: 6777863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVSsi: { 6778863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 6779863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // whether we're in an IT block if the register operands are low 6780863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // registers. 6781863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach bool isNarrow = false; 6782863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6783863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6784863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 6785863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isNarrow = true; 6786863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach MCInst TmpInst; 6787863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach unsigned newOpc; 6788863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 6789863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 6790863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 6791863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 6792863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 6793863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 6794520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 6795863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 6796d9b0b025612992a0b724eeca8bdf10b1d7a5c355Benjamin Kramer unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 6797d9b0b025612992a0b724eeca8bdf10b1d7a5c355Benjamin Kramer if (Amount == 32) Amount = 0; 6798863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.setOpcode(newOpc); 6799863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 6800863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isNarrow) 6801863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 6802863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6803863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6804520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach if (newOpc != ARM::t2RRX) 6805d9b0b025612992a0b724eeca8bdf10b1d7a5c355Benjamin Kramer TmpInst.addOperand(MCOperand::CreateImm(Amount)); 6806863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6807863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6808863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (!isNarrow) 6809863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 6810863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6811863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst = TmpInst; 6812863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach return true; 6813863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 6814863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the ARM mode MOV complex aliases. 681523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: 681623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: 681723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: 681823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: { 681923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 682023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach switch(Inst.getOpcode()) { 682123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 682223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 682323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 682423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 682523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: ShiftTy = ARM_AM::ror; break; 682623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 682723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 682823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach MCInst TmpInst; 682923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.setOpcode(ARM::MOVsr); 683023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 683123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 683223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 683323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 683423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 683523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 683623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 683723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach Inst = TmpInst; 683823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach return true; 683923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 6840ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: 6841ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: 6842ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: 6843ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: { 6844ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 6845ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach switch(Inst.getOpcode()) { 6846ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 6847ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 6848ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 6849ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 6850ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: ShiftTy = ARM_AM::ror; break; 6851ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 6852ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach // A shift by zero is a plain MOVr, not a MOVsi. 685348b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Amt = Inst.getOperand(2).getImm(); 6854ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6855b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton // A shift by 32 should be encoded as 0 when permitted 6856b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 6857b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton Amt = 0; 6858ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 685971810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach MCInst TmpInst; 6860ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.setOpcode(Opc); 686171810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 686271810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6863ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (Opc == ARM::MOVsi) 6864ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 686571810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 686671810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 686771810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 686871810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach Inst = TmpInst; 686983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 687071810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach } 687148b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach case ARM::RRXi: { 687248b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 687348b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach MCInst TmpInst; 687448b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.setOpcode(ARM::MOVsi); 687548b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 687648b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 687748b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 687848b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 687948b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 688048b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // cc_out 688148b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach Inst = TmpInst; 688248b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach return true; 688348b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach } 68840352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2LDMIA_UPD: { 68850352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a load of a single register, then we should use 68860352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 68870352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 68880352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 68890352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 68900352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2LDR_POST); 68910352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 68920352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 68930352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 68940352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 68950352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 68960352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 68970352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 68980352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 68990352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 69000352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2STMDB_UPD: { 69010352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a store of a single register, then we should use 69020352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 69030352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 69040352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 69050352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 69060352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2STR_PRE); 69070352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 69080352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 69090352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 69100352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 69110352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 69120352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 69130352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 69140352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 69150352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 6916f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach case ARM::LDMIA_UPD: 6917f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // If this is a load of a single register via a 'pop', then we should use 6918f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 6919f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 6920f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst.getNumOperands() == 5) { 6921f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach MCInst TmpInst; 6922f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.setOpcode(ARM::LDR_POST_IMM); 6923f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 6924f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6925f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6926f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 6927f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 6928f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6929f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6930f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst = TmpInst; 693183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 6932f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 6933f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach break; 6934f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach case ARM::STMDB_UPD: 6935f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // If this is a store of a single register via a 'push', then we should use 6936f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 6937f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 6938f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst.getNumOperands() == 5) { 6939f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach MCInst TmpInst; 6940f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.setOpcode(ARM::STR_PRE_IMM); 6941f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6942f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 6943f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 6944f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 6945f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6946f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6947f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst = TmpInst; 6948f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach } 6949f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach break; 6950da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2ADDri12: 6951da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 6952da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "addw"), encoding T3 is preferred. 6953da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 6954da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6955da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 6956da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2ADDri); 6957da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 6958da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 6959da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2SUBri12: 6960da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 6961da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "subw"), encoding T3 is preferred. 6962da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 6963da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6964da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 6965da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2SUBri); 6966da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 6967da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 696889e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach case ARM::tADDi8: 69690f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 69700f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 69710f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 69720f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T1 if <Rd> is omitted." 6973c0164f86080bc9d7a41fd5eabd0d6556396f5b38Jim Grosbach if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 697489e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach Inst.setOpcode(ARM::tADDi3); 697583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 697683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 697789e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach break; 6978f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach case ARM::tSUBi8: 6979f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 6980f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 6981f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 6982f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T1 if <Rd> is omitted." 6983c0164f86080bc9d7a41fd5eabd0d6556396f5b38Jim Grosbach if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 6984f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Inst.setOpcode(ARM::tSUBi3); 698583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 698683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 6987f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach break; 69882d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach case ARM::t2ADDri: 69892d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach case ARM::t2SUBri: { 69902d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach // If the destination and first source operand are the same, and 69912d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach // the flags are compatible with the current IT status, use encoding T2 69922d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach // instead of T3. For compatibility with the system 'as'. Make sure the 69932d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach // wide encoding wasn't explicit. 69942d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 69958f1148bd07d57a1324ed39250642119baa540b7cJim Grosbach !isARMLowRegister(Inst.getOperand(0).getReg()) || 69962d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach (unsigned)Inst.getOperand(2).getImm() > 255 || 69972d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 69982d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 69992d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 70002d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 70012d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach break; 70022d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach MCInst TmpInst; 70032d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 70042d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach ARM::tADDi8 : ARM::tSUBi8); 70052d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 70062d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 70072d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 70082d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 70092d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 70102d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 70112d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach Inst = TmpInst; 70122d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach return true; 70132d30d947ec2626e8b1a9b577cdfa4121f476c3f5Jim Grosbach } 7014927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach case ARM::t2ADDrr: { 7015927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // If the destination and first source operand are the same, and 7016927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // there's no setting of the flags, use encoding T2 instead of T3. 7017927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // Note that this is only for ADD, not SUB. This mirrors the system 7018927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7019927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7020927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst.getOperand(5).getReg() != 0 || 7021713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 7022713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7023927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach break; 7024927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach MCInst TmpInst; 7025927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.setOpcode(ARM::tADDhirr); 7026927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 7027927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 7028927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 7029927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 7030927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 7031927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst = TmpInst; 7032927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach return true; 7033927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach } 7034a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach case ARM::tADDrSP: { 7035a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach // If the non-SP source operand and the destination operand are not the 7036a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach // same, we need to use the 32-bit encoding if it's available. 7037a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7038a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach Inst.setOpcode(ARM::t2ADDrr); 7039a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7040a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach return true; 7041a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach } 7042a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach break; 7043a9cc08f24f61e2663a131d7ac16c329b75162e7bJim Grosbach } 704451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::tB: 704551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb conditional branch outside of an IT block is a tBcc. 704683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 704751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::tBcc); 704883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 704983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 705051f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 705151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::t2B: 705251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 705383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 705451f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::t2Bcc); 705583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 705683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 705751f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 7058c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach case ARM::t2Bcc: 7059a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // If the conditional is AL or we're in an IT block, we really want t2B. 706083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7061c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach Inst.setOpcode(ARM::t2B); 706283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 706383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 7064c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach break; 7065395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach case ARM::tBcc: 7066395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach // If the conditional is AL, we really want tB. 706783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7068395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach Inst.setOpcode(ARM::tB); 706983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 707083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 70713ce23d3d87d1ca437acb65ac01fac1c486507280Jim Grosbach break; 707276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::tLDMIA: { 707376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If the register list contains any high registers, or if the writeback 707476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 707576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instead if we're in Thumb2. Otherwise, this should have generated 707676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // an error in validateInstruction(). 707776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 707876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool hasWritebackToken = 707976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 708076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 708176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool listContainsBase; 708276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 708376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (!listContainsBase && !hasWritebackToken) || 708476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (listContainsBase && hasWritebackToken)) { 708576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 708676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach assert (isThumbTwo()); 708776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 708876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're switching to the updating version, we need to insert 708976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // the writeback tied operand. 709076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (hasWritebackToken) 709176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.insert(Inst.begin(), 709276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach MCOperand::CreateReg(Inst.getOperand(0).getReg())); 709383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 709476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 709576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 709676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 70978213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach case ARM::tSTMIA_UPD: { 70988213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // If the register list contains any high registers, we need to use 70998213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 71008213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // should have generated an error in validateInstruction(). 71018213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 71028213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach bool listContainsBase; 71038213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 71048213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 71058213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach assert (isThumbTwo()); 71068213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach Inst.setOpcode(ARM::t2STMIA_UPD); 710783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 71088213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 71098213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach break; 71108213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 71115402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPOP: { 71125402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 71135402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // If the register list contains any high registers, we need to use 71145402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 71155402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // should have generated an error in validateInstruction(). 71165402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 711783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 71185402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 71195402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2LDMIA_UPD); 71205402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 71215402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 71225402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 712383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 71245402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 71255402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPUSH: { 71265402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 71275402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 712883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 71295402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 71305402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2STMDB_UPD); 71315402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 71325402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 71335402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 713483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 71355402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 71361ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVi: { 71371ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 71381ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 71391ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7140c0164f86080bc9d7a41fd5eabd0d6556396f5b38Jim Grosbach (unsigned)Inst.getOperand(1).getImm() <= 255 && 7141c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7142c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR) || 7143c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 71441ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 71451ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 71461ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't in the same order for tMOVi8... 71471ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 71481ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(ARM::tMOVi8); 71491ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 71501ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 71511ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 71521ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 71531ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 71541ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 715583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 71561ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 71571ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 71581ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 71591ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVr: { 71601ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 71611ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 71621ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 71631ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 71641ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(2).getImm() == ARMCC::AL && 71651ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR && 71661ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 71671ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 71681ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't the same for tMOV[S]r... (no cc_out) 71691ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 71701ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 71711ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 71721ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 71731ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 71741ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 71751ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 717683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 71771ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 71781ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 71791ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 7180326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach case ARM::t2SXTH: 718150f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: 718250f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: 718350f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: { 7184326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 7185326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // request the 32-bit variant, transform it here. 7186326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7187326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 7188326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst.getOperand(2).getImm() == 0 && 7189326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7190326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 719150f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach unsigned NewOpc; 719250f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach switch (Inst.getOpcode()) { 719350f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach default: llvm_unreachable("Illegal opcode!"); 719450f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 719550f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 719650f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 719750f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 719850f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach } 7199326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // The operands aren't the same for thumb1 (no rotate operand). 7200326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach MCInst TmpInst; 7201326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.setOpcode(NewOpc); 7202326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 7203326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 7204326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 7205326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 7206326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst = TmpInst; 720783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 7208326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 7209326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach break; 7210326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 721104b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach case ARM::MOVsi: { 721204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7213b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton // rrx shifts and asr/lsr of #32 is encoded as 0 7214b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7215b56e4115ed33dae56108ed4ce88ee3a0e0392bfcRichard Barton return false; 721604b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 721704b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach // Shifting by zero is accepted as a vanilla 'MOVr' 721804b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach MCInst TmpInst; 721904b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.setOpcode(ARM::MOVr); 722004b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 722104b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 722204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 722304b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 722404b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 722504b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach Inst = TmpInst; 722604b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return true; 722704b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 722804b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return false; 722904b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 72308d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: 72318d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: 72328d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: 72338d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: 72348d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: 72358d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: { 72368d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach unsigned newOpc; 72378d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 72388d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (SOpc == ARM_AM::rrx) return false; 72398d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach switch (Inst.getOpcode()) { 7240bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("unexpected opcode!"); 72418d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 72428d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 72438d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: newOpc = ARM::EORrr; break; 72448d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: newOpc = ARM::BICrr; break; 72458d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 72468d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 72478d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 72488d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach // If the shift is by zero, use the non-shifted instruction definition. 72498d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) { 72508d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach MCInst TmpInst; 72518d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.setOpcode(newOpc); 72528d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 72538d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 72548d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 72558d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 72568d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 72578d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 72588d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach Inst = TmpInst; 72598d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return true; 72608d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 72618d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return false; 72628d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 726374423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach case ARM::ITasm: 726489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach case ARM::t2IT: { 726589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The mask bits for all but the first condition are represented as 726689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // the low bit of the condition code value implies 't'. We currently 726789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // always have 1 implies 't', so XOR toggle the bits if the low bit 72684d2f077df1b46a126b5595d983f233ec896b757eRichard Barton // of the condition code is zero. 726989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MCOperand &MO = Inst.getOperand(1); 727089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = MO.getImm(); 7271f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned OrigMask = Mask; 7272f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned TZ = CountTrailingZeros_32(Mask); 727389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if ((Inst.getOperand(0).getImm() & 1) == 0) { 727489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(Mask && TZ <= 3 && "illegal IT mask value!"); 727589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = 3; i != TZ; --i) 727689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask ^= 1 << i; 72774d2f077df1b46a126b5595d983f233ec896b757eRichard Barton } 727889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MO.setImm(Mask); 7279f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 7280f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Set up the IT block state according to the IT instruction we just 7281f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // matched. 7282f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach assert(!inITBlock() && "nested IT blocks?!"); 7283f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7284f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7285f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = 0; 7286f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = true; 728789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 728889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 7289f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 729083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 7291f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach} 7292f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 729347a0d52b69056250a1edaca8b28f705993094542Jim Grosbachunsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 729447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // 16-bit thumb arithmetic instructions either require or preclude the 'S' 729547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // suffix depending on whether they're in an IT block or not. 7296194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach unsigned Opc = Inst.getOpcode(); 72971a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Opc); 729847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 729947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.hasOptionalDef() && 730047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "optionally flag setting instruction missing optional def operand"); 730147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.NumOperands == Inst.getNumOperands() && 730247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "operand count mismatch!"); 730347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // Find the optional-def operand (cc_out). 730447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned OpNo; 730547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach for (OpNo = 0; 730647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 730747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ++OpNo) 730847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ; 730947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb1, reject it completely. 731047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 731147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_MnemonicFail; 731247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb2, which form is legal depends on whether we're 731347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // in an IT block. 7314f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7315f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach !inITBlock()) 731647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_RequiresITBlock; 7317f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7318f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach inITBlock()) 7319f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Match_RequiresNotITBlock; 732047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 7321194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Some high-register supporting Thumb1 encodings only allow both registers 7322194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // to be from r0-r7 when in Thumb2. 7323194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach else if (Opc == ARM::tADDhirr && isThumbOne() && 7324194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 7325194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg())) 7326194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresThumb2; 7327194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Others only require ARMv6 or later. 73284ec6e888ec6d12b5255afd685b05c8fee1f7fc73Jim Grosbach else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7329194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(0).getReg()) && 7330194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg())) 7331194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresV6; 733247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_Success; 733347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach} 733447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 733514ce6fac242228dacc5c08040e544141a96880e5Jim Grosbachstatic const char *getSubtargetFeatureName(unsigned Val); 7336fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattnerbool ARMAsmParser:: 7337fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris LattnerMatchAndEmitInstruction(SMLoc IDLoc, 7338fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7339fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCStreamer &Out) { 7340fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCInst Inst; 7341fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner unsigned ErrorInfo; 734219cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach unsigned MatchResult; 7343193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 7344193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby switch (MatchResult) { 734519cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach default: break; 7346e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_Success: 7347189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Context sensitive operand constraints aren't handled by the matcher, 7348189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // so check them here. 7349a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (validateInstruction(Inst, Operands)) { 7350a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Still progress the IT block, otherwise one wrong condition causes 7351a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // nasty cascading errors. 7352a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 7353189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return true; 7354a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 7355189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 7356f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // Some instructions need post-processing to, for example, tweak which 735783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // encoding is selected. Loop on it while changes happen so the 735883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // individual transformations can chain off each other. E.g., 735983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 736083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach while (processInstruction(Inst, Operands)) 736183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach ; 7362f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 7363a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Only move forward at the very end so that everything in validate 7364a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // and process gets a consistent answer about whether we're in an IT 7365a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // block. 7366a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 7367a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach 736874423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 736974423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach // doesn't actually encode. 737074423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach if (Inst.getOpcode() == ARM::ITasm) 737174423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach return false; 737274423e32ce7f426b624bfb0c31481bcf6a36394dJim Grosbach 737342e6bd38e02e2e1c2cc50d2f12036c38c4ea3ab0Jim Grosbach Inst.setLoc(IDLoc); 7374fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner Out.EmitInstruction(Inst); 7375fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner return false; 737614ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach case Match_MissingFeature: { 737714ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach assert(ErrorInfo && "Unknown missing feature!"); 737814ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach // Special case the error message for the very common case where only 737914ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 738014ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach std::string Msg = "instruction requires:"; 738114ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach unsigned Mask = 1; 738214ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 738314ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach if (ErrorInfo & Mask) { 738414ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach Msg += " "; 738514ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach Msg += getSubtargetFeatureName(ErrorInfo & Mask); 738614ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach } 738714ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach Mask <<= 1; 738814ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach } 738914ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach return Error(IDLoc, Msg); 739014ce6fac242228dacc5c08040e544141a96880e5Jim Grosbach } 7391e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_InvalidOperand: { 7392e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner SMLoc ErrorLoc = IDLoc; 7393e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo != ~0U) { 7394e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo >= Operands.size()) 7395e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(IDLoc, "too few operands for instruction"); 739616c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 7397e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7398e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7399e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 740016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 7401e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(ErrorLoc, "invalid operand for instruction"); 7402e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 7403e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_MnemonicFail: 7404362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer return Error(IDLoc, "invalid instruction", 7405362a05a635379ca1151e5ccf735295aed814dd4bBenjamin Kramer ((ARMOperand*)Operands[0])->getLocRange()); 7406b412915ff6229b3e2dffedcfb0f3fb7e85259841Daniel Dunbar case Match_ConversionFail: 7407d9b0b025612992a0b724eeca8bdf10b1d7a5c355Benjamin Kramer // The converter function will have already emitted a diagnostic. 740888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 7409f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach case Match_RequiresNotITBlock: 7410f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(IDLoc, "flag setting instruction only valid outside IT block"); 741147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach case Match_RequiresITBlock: 741247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Error(IDLoc, "instruction only valid inside IT block"); 7413194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresV6: 7414194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7415194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresThumb2: 7416194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires Thumb2"); 741770c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach case Match_ImmRange0_15: { 741870c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 741970c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 742070c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 742170c9bf3c1a77b5707c92a7cfe74104c320480391Jim Grosbach } 7422fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner } 742316c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 7424c223e2b10b4753a63dfe7e6980c650b179139983Eric Christopher llvm_unreachable("Implement any new match types added!"); 7425fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner} 7426fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner 74271355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirective parses the arm specific directives 7428ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbybool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7429ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby StringRef IDVal = DirectiveID.getIdentifier(); 7430ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (IDVal == ".word") 74311355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveWord(4, DirectiveID.getLoc()); 7432515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb") 74331355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumb(DirectiveID.getLoc()); 74349a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach else if (IDVal == ".arm") 74359a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return parseDirectiveARM(DirectiveID.getLoc()); 7436515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb_func") 74371355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7438515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".code") 74391355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveCode(DirectiveID.getLoc()); 7440515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".syntax") 74411355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveSyntax(DirectiveID.getLoc()); 7442a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach else if (IDVal == ".unreq") 7443a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return parseDirectiveUnreq(DirectiveID.getLoc()); 7444d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".arch") 7445d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveArch(DirectiveID.getLoc()); 7446d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".eabi_attribute") 7447d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7448ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 7449ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 7450ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 74511355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveWord 7452ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby/// ::= .word [ expression (, expression)* ] 74531355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7454ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) { 7455ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby for (;;) { 7456ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby const MCExpr *Value; 7457ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getParser().ParseExpression(Value)) 7458ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 7459ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 7460aaec205b87637cd0d59d4f11630db603686eb73dChris Lattner getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 7461ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 7462ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().is(AsmToken::EndOfStatement)) 7463ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby break; 746416c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 7465ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby // FIXME: Improve diagnostic. 7466ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::Comma)) 7467ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return Error(L, "unexpected token in directive"); 7468b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 7469ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 7470ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 7471ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 7472b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 7473ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return false; 7474ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 7475ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 74761355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumb 7477515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumb 74781355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7479515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 7480515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 7481b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 7482515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 74839a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (!isThumb()) 74849a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 74859a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 74869a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return false; 74879a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach} 74889a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 74899a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// parseDirectiveARM 74909a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// ::= .arm 74919a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbachbool ARMAsmParser::parseDirectiveARM(SMLoc L) { 74929a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 74939a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return Error(L, "unexpected token in directive"); 74949a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach Parser.Lex(); 74959a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 74969a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (isThumb()) 74979a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 74989a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7499515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 7500515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 7501515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 75021355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumbFunc 7503515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumbfunc symbol_name 75041355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 75056469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 75066469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola bool isMachO = MAI.hasSubsectionsViaSymbols(); 75076469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola StringRef Name; 7508de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach bool needFuncName = true; 75096469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 7510de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Darwin asm has (optionally) function name after .thumb_func direction 75116469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // ELF doesn't 75126469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola if (isMachO) { 75136469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const AsmToken &Tok = Parser.getTok(); 7514de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::EndOfStatement)) { 7515de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7516de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach return Error(L, "unexpected token in .thumb_func directive"); 7517de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Name = Tok.getIdentifier(); 7518de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); // Consume the identifier token. 7519de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach needFuncName = false; 7520de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach } 75216469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 75226469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 7523de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 7524515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 7525de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach 7526de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Eat the end of statement and any blank lines that follow. 7527de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach while (getLexer().is(AsmToken::EndOfStatement)) 7528de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); 7529515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 75306469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // FIXME: assuming function name will be the line following .thumb_func 7531de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // We really should be checking the next symbol definition even if there's 7532de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // stuff in between. 7533de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (needFuncName) { 7534d475f8612b1c7959dbf50242c8fa9d4aea1ee1a9Jim Grosbach Name = Parser.getTok().getIdentifier(); 75356469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 75366469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 7537642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach // Mark symbol as a thumb symbol. 7538642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 7539642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach getParser().getStreamer().EmitThumbFunc(Func); 7540515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 7541515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 7542515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 75431355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveSyntax 7544515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .syntax unified | divided 75451355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 754618b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 7547515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Identifier)) 7548515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .syntax directive"); 754938e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef Mode = Tok.getString(); 755058c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Mode == "unified" || Mode == "UNIFIED") 7551b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 755258c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Mode == "divided" || Mode == "DIVIDED") 75539e56fb12c504c82c92947fe9c46287fc60116b91Kevin Enderby return Error(L, "'.syntax divided' arm asssembly not supported"); 7554515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 7555515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unrecognized syntax mode in .syntax directive"); 7556515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 7557515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 755818b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7559b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 7560515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 7561515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // TODO tell the MC streamer the mode 7562515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // getParser().getStreamer().Emit???(); 7563515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 7564515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 7565515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 75661355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveCode 7567515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .code 16 | 32 75681355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveCode(SMLoc L) { 756918b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 7570515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Integer)) 7571515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .code directive"); 757218b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan int64_t Val = Parser.getTok().getIntVal(); 757358c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Val == 16) 7574b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 757558c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Val == 32) 7576b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 7577515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 7578515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "invalid operand to .code directive"); 7579515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 7580515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 758118b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7582b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 7583515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 758432869205052430f45d598fba25ab878d8b29da2dEvan Cheng if (Val == 16) { 758598447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (!isThumb()) 7586ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 758798447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 758832869205052430f45d598fba25ab878d8b29da2dEvan Cheng } else { 758998447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (isThumb()) 7590ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 759198447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7592eb0caa115491019f7f7fe45fc70ad47682244187Evan Cheng } 75932a301704ea76535f0485d5c3b75664b323249bdbJim Grosbach 7594515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 7595515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 7596515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 7597a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveReq 7598a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= name .req registername 7599a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7600a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the '.req' token. 7601a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach unsigned Reg; 7602a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach SMLoc SRegLoc, ERegLoc; 7603a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7604a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 7605a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "register name expected"); 7606a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 7607a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 7608a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Shouldn't be anything else. 7609a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7610a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 7611a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(Parser.getTok().getLoc(), 7612a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "unexpected input in .req directive."); 7613a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 7614a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 7615a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Consume the EndOfStatement 7616a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 7617a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7618a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "redefinition of '" + Name + 7619a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "' does not match original."); 7620a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 7621a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 7622a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 7623a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 7624a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveUneq 7625a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= .unreq registername 7626a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7627a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::Identifier)) { 7628a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 7629a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(L, "unexpected input in .unreq directive."); 7630a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 7631a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach RegisterReqs.erase(Parser.getTok().getIdentifier()); 7632a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the identifier. 7633a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 7634a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 7635a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 7636d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveArch 7637d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .arch token 7638d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveArch(SMLoc L) { 7639d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 7640d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 7641d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 7642d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveEabiAttr 7643d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .eabi_attribute int, int 7644d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 7645d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 7646d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 7647d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 764890b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callananextern "C" void LLVMInitializeARMAsmLexer(); 764990b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan 76509c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Force static initialization. 7651ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyextern "C" void LLVMInitializeARMAsmParser() { 765294b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 765394b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 765490b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan LLVMInitializeARMAsmLexer(); 7655ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 76563483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 76570692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_REGISTER_MATCHER 76588030e1a0df630ec6ed1cd5ec673f6472558a4dbeCraig Topper#define GET_SUBTARGET_FEATURE_NAME 76590692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_MATCHER_IMPLEMENTATION 76603483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar#include "ARMGenAsmMatcher.inc" 7661