ARMAsmParser.cpp revision d7433e2873706265d545edc5cdd0a728dd71ef66
1ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 3ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// The LLVM Compiler Infrastructure 4ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 5ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// This file is distributed under the University of Illinois Open Source 6ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// License. See LICENSE.TXT for details. 7ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby// 8ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby//===----------------------------------------------------------------------===// 9ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 1094b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "MCTargetDesc/ARMBaseInfo.h" 11ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 12ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMMCExpr.h" 13c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmLexer.h" 14c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCAsmParser.h" 15c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 166469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola#include "llvm/MC/MCAsmInfo.h" 17642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach#include "llvm/MC/MCContext.h" 18ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCStreamer.h" 19ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCExpr.h" 20ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby#include "llvm/MC/MCInst.h" 217801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng#include "llvm/MC/MCInstrDesc.h" 2294b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCRegisterInfo.h" 23ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng#include "llvm/MC/MCSubtargetInfo.h" 2494b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/MC/MCTargetAsmParser.h" 2589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach#include "llvm/Support/MathExtras.h" 26c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/Support/SourceMgr.h" 273e74d6fdd248e20a280f1dff3da9a6c689c2c4c3Evan Cheng#include "llvm/Support/TargetRegistry.h" 28fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar#include "llvm/Support/raw_ostream.h" 2911e03e7c2d0c163e54b911ad1e665616dc0bcc8cJim Grosbach#include "llvm/ADT/BitVector.h" 3075ca4b94bd9dcd3952fdc237429342a2154ba142Benjamin Kramer#include "llvm/ADT/OwningPtr.h" 3194b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "llvm/ADT/STLExtras.h" 32c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/SmallVector.h" 33345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar#include "llvm/ADT/StringSwitch.h" 34c6ef277a0b8f43af22d86aea9d5053749cacfbbbChris Lattner#include "llvm/ADT/Twine.h" 35ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 36ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyusing namespace llvm; 37ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 383a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 39146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 40146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand; 4116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 427636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbachenum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 4398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 4494b9550a32d189704a8eae55505edf62662c0534Evan Chengclass ARMAsmParser : public MCTargetAsmParser { 45ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng MCSubtargetInfo &STI; 46ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &Parser; 47ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 48a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Map of register aliases registers via the .req directive. 49a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StringMap<unsigned> RegisterReqs; 50a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 51f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach struct { 52f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes Cond; // Condition for IT block. 53f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Mask:4; // Condition mask for instructions. 54f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Starting at first 1 (from lsb). 55f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '1' condition as indicated in IT. 56f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // '0' inverse of condition (else). 57f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Count of instructions in IT block is 58f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // 4 - trailingzeroes(mask) 59f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 60f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool FirstCond; // Explicit flag for when we're parsing the 61f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // First instruction in the IT block. It's 62f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // implied in the mask, so needs special 63f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // handling. 64f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 65f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned CurPosition; // Current position in parsing of IT 66f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // block. In range [0,3]. Initialized 67f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // according to count of instructions in block. 68f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // ~0U if no active IT block. 69f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } ITState; 70f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach bool inITBlock() { return ITState.CurPosition != ~0U;} 71a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach void forwardITPosition() { 72a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (!inITBlock()) return; 73a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Move to the next instruction in the IT block, if there is one. If not, 74a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // mark the block as done. 75a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach unsigned TZ = CountTrailingZeros_32(ITState.Mask); 76a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (++ITState.CurPosition == 5 - TZ) 77a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach ITState.CurPosition = ~0U; // Done with the IT block after this. 78a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 79f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 80f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 81ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmParser &getParser() const { return Parser; } 82ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby MCAsmLexer &getLexer() const { return Parser.getLexer(); } 83ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 84ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 85ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 86ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 871355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int tryParseRegister(); 881355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 890d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 901355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 917ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 921355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 931355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 947ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &ShiftAmount); 961355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveWord(unsigned Size, SMLoc L); 971355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumb(SMLoc L); 989a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach bool parseDirectiveARM(SMLoc L); 991355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveThumbFunc(SMLoc L); 1001355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveCode(SMLoc L); 1011355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool parseDirectiveSyntax(SMLoc L); 102a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveReq(StringRef Name, SMLoc L); 103a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach bool parseDirectiveUnreq(SMLoc L); 104d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveArch(SMLoc L); 105d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim bool parseDirectiveEabiAttr(SMLoc L); 106515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 1071355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 10889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach bool &CarrySetting, unsigned &ProcessorIMod, 10989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask); 1101355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 111fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode); 11216c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 113ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumb() const { 114ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // FIXME: Can tablegen auto-generate this? 115ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 116ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 117ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng bool isThumbOne() const { 118ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 119ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 12047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach bool isThumbTwo() const { 12147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 12247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 123194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach bool hasV6Ops() const { 124194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return STI.getFeatureBits() & ARM::HasV6Ops; 125194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach } 126acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool hasV7Ops() const { 127acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::HasV7Ops; 128acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 12932869205052430f45d598fba25ab878d8b29da2dEvan Cheng void SwitchMode() { 130ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 131ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(FB); 13232869205052430f45d598fba25ab878d8b29da2dEvan Cheng } 133acad68da50581de905a994ed3c6b9c197bcea687James Molloy bool isMClass() const { 134acad68da50581de905a994ed3c6b9c197bcea687James Molloy return STI.getFeatureBits() & ARM::FeatureMClass; 135acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 136ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 137a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// @name Auto-generated Match Functions 138a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// { 1393483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 1400692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_ASSEMBLER_HEADER 1410692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#include "ARMGenAsmMatcher.inc" 142a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 143a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby /// } 144a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 14589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 14643904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocNumOperand( 147f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 14843904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseCoprocRegOperand( 149f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 1509b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OperandMatchResultTy parseCoprocOptionOperand( 1519b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SmallVectorImpl<MCParsedAsmOperand*>&); 15243904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMemBarrierOptOperand( 1538bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 15443904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseProcIFlagsOperand( 1558bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 15643904299b05bdf579415749041f77c4490fe5f5bJim Grosbach OperandMatchResultTy parseMSRMaskOperand( 1578bba1a5ef0f8a71de2e58c7f05b8714a73464ca8Bruno Cardoso Lopes SmallVectorImpl<MCParsedAsmOperand*>&); 158f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 159f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef Op, int Low, int High); 160f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 161f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "lsl", 0, 31); 162f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 163f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 164f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return parsePKHImm(O, "asr", 1, 32); 165f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 166c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 167580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 1687e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 169293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 1707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 171251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 1729d39036f62674606565217a10db28171b9594bc7Jim Grosbach OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 173862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 1747636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 175ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 176ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Asm Match Converter Methods 177a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 178a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 179a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 180a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 181eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 182eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 183ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 184ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1851355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 186ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 1879ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 1889ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &); 189548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 190548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1911355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 192ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &); 1937b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 1947b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1957ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 1967ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 1987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 1997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2032fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2042fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 20514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 20614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 207623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 208623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 20988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 21088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21112431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 21212431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 21312431329d617064d6e72dd040a58c1635cc261abJim Grosbach bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 21412431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2154334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 2164334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 2174334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 2184334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &); 219189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 220189610f9466686a91fb7d847b572e1645c785323Jim Grosbach bool validateInstruction(MCInst &Inst, 221189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 22283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach bool processInstruction(MCInst &Inst, 223f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 224d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach bool shouldOmitCCOutOperand(StringRef Mnemonic, 225d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 226189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 227ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbypublic: 22847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach enum ARMMatchResultTy { 229194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 230f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Match_RequiresNotITBlock, 231194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresV6, 232194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach Match_RequiresThumb2 23347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach }; 23447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 235ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 23694b9550a32d189704a8eae55505edf62662c0534Evan Cheng : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 237ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng MCAsmParserExtension::Initialize(_Parser); 23832869205052430f45d598fba25ab878d8b29da2dEvan Cheng 239ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng // Initialize the set of available features. 240ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 241f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 242f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Not in an ITBlock to start with. 243f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = ~0U; 244ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng } 245ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 2461355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach // Implementation of the MCTargetAsmParser interface: 2471355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 2481355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseInstruction(StringRef Name, SMLoc NameLoc, 249189610f9466686a91fb7d847b572e1645c785323Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands); 2501355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool ParseDirective(AsmToken DirectiveID); 2511355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach 25247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned checkTargetMatchPredicate(MCInst &Inst); 25347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 2541355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach bool MatchAndEmitInstruction(SMLoc IDLoc, 2551355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2561355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach MCStreamer &Out); 257ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby}; 25816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach} // end anonymous namespace 25916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2603a69756e392942bc522193f38d7f33958ed3b131Chris Lattnernamespace { 2613a69756e392942bc522193f38d7f33958ed3b131Chris Lattner 262a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ARMOperand - Instances of this class represent a parsed ARM machine 263a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// instruction. 264146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingclass ARMOperand : public MCParsedAsmOperand { 265762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan enum KindTy { 26621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CondCode, 26721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CCOut, 26821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ITCondMask, 26921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocNum, 27021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_CoprocReg, 2719b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach k_CoprocOption, 27221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Immediate, 27321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MemBarrierOpt, 27421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Memory, 27521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_PostIndexRegister, 27621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_MSRMask, 27721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ProcIFlags, 278460a90540b045c102012da2492999557e6840526Jim Grosbach k_VectorIndex, 27921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Register, 28021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RegisterList, 28121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_DPRRegisterList, 28221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_SPRRegisterList, 283862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach k_VectorList, 28498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach k_VectorListAllLanes, 2857636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach k_VectorListIndexed, 28621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedRegister, 28721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShiftedImmediate, 28821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_ShifterImmediate, 28921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_RotateImmediate, 29021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_BitfieldDescriptor, 29121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach k_Token 292a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Kind; 293a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 294762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc StartLoc, EndLoc; 29524d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling SmallVector<unsigned, 8> Registers; 296a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 297a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby union { 298a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 2998462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes Val; 3008462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } CC; 3018462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 3028462b30548fb5969250858036638c73c16b65b43Daniel Dunbar struct { 303fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned Val; 304fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } Cop; 305fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 306fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes struct { 3079b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach unsigned Val; 3089b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } CoprocOption; 3099b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 3109b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach struct { 31189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask:4; 31289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } ITMask; 31389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 31489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 31589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ARM_MB::MemBOpt Val; 31689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } MBOpt; 31789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 31889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach struct { 319a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags Val; 320a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } IFlags; 321a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 322a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes struct { 323584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Val; 324584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } MMask; 325584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 326584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes struct { 327a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby const char *Data; 328a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned Length; 329a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Tok; 330a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 331a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 332a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned RegNum; 333a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } Reg; 334a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 335862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // A vector register list is a sequential list of 1 to 4 registers. 336862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach struct { 337862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned RegNum; 338862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count; 3397636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 3400aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced; 341862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } VectorList; 342862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3438155e5b753aca42973cf317727f3805faddcaf90Bill Wendling struct { 344460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned Val; 345460a90540b045c102012da2492999557e6840526Jim Grosbach } VectorIndex; 346460a90540b045c102012da2492999557e6840526Jim Grosbach 347460a90540b045c102012da2492999557e6840526Jim Grosbach struct { 348cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *Val; 349cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } Imm; 35016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 3516a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar /// Combined record for all forms of ARM address expressions. 352a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby struct { 353a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned BaseRegNum; 3547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 3557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // was specified. 3567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm; // Offset immediate value 3577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 3587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 35957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned ShiftImm; // shift for OffsetReg. 36057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment; // 0 = no alignment specified 361eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach // n = alignment in bytes (2, 4, 8, 16, or 32) 3627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 363e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach } Memory; 3640082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 3650082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson struct { 3667ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned RegNum; 367f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isAdd; 368f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 369f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm; 3707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } PostIdxReg; 3717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3727ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach struct { 373580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 374e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned Imm; 375580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } ShifterImm; 376e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach struct { 377e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ARM_AM::ShiftOpc ShiftTy; 378e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg; 379e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg; 380e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm; 381af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedReg; 38292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson struct { 38392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson ARM_AM::ShiftOpc ShiftTy; 38492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg; 38592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm; 386af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach } RegShiftedImm; 3877e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach struct { 3887e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach unsigned Imm; 3897e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } RotImm; 390293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach struct { 391293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned LSB; 392293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned Width; 393293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } Bitfield; 394a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby }; 39516c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 396146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 397146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendlingpublic: 398762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 399762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Kind = o.Kind; 400762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan StartLoc = o.StartLoc; 401762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan EndLoc = o.EndLoc; 402762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan switch (Kind) { 40321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 4048462b30548fb5969250858036638c73c16b65b43Daniel Dunbar CC = o.CC; 4058462b30548fb5969250858036638c73c16b65b43Daniel Dunbar break; 40621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: 40789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = o.ITMask; 40889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 40921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 4108462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Tok = o.Tok; 411762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 41221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 41321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 414762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Reg = o.Reg; 415762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 41621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 41721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 41821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: 41924d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Registers = o.Registers; 4208d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 421862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 42298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 4237636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 424862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach VectorList = o.VectorList; 425862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 42621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 42721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 428fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Cop = o.Cop; 429fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 4309b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 4319b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach CoprocOption = o.CoprocOption; 4329b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 43321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 434762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Imm = o.Imm; 435762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 43621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 437706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes MBOpt = o.MBOpt; 438706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 43921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 440e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory = o.Memory; 441762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan break; 44221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 4437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach PostIdxReg = o.PostIdxReg; 4447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 44521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 446584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes MMask = o.MMask; 447584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 44821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: 449a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes IFlags = o.IFlags; 4500082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 45121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 452580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm = o.ShifterImm; 4530082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 45421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 455af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedReg = o.RegShiftedReg; 456e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 45721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 458af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach RegShiftedImm = o.RegShiftedImm; 45992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 46021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 4617e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach RotImm = o.RotImm; 4627e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 46321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 464293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Bitfield = o.Bitfield; 465293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 466460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 467460a90540b045c102012da2492999557e6840526Jim Grosbach VectorIndex = o.VectorIndex; 468460a90540b045c102012da2492999557e6840526Jim Grosbach break; 469762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 470762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 47116c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 472762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getStartLoc - Get the location of the first token of this operand. 473762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getStartLoc() const { return StartLoc; } 474762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan /// getEndLoc - Get the location of the last token of this operand. 475762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc getEndLoc() const { return EndLoc; } 476a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4778462b30548fb5969250858036638c73c16b65b43Daniel Dunbar ARMCC::CondCodes getCondCode() const { 47821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_CondCode && "Invalid access!"); 4798462b30548fb5969250858036638c73c16b65b43Daniel Dunbar return CC.Val; 4808462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 4818462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 482fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes unsigned getCoproc() const { 48321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 484fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Cop.Val; 485fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 486fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 487a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby StringRef getToken() const { 48821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_Token && "Invalid access!"); 489a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return StringRef(Tok.Data, Tok.Length); 490a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 491a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 492a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby unsigned getReg() const { 49321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 4947729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling return Reg.RegNum; 495a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 496a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4975fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &getRegList() const { 49821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 49921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind == k_SPRRegisterList) && "Invalid access!"); 50024d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling return Registers; 5018d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 5028d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 503cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby const MCExpr *getImm() const { 50421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach assert(isImm() && "Invalid access!"); 505cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby return Imm.Val; 506cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 507cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 508460a90540b045c102012da2492999557e6840526Jim Grosbach unsigned getVectorIndex() const { 509460a90540b045c102012da2492999557e6840526Jim Grosbach assert(Kind == k_VectorIndex && "Invalid access!"); 510460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val; 511460a90540b045c102012da2492999557e6840526Jim Grosbach } 512460a90540b045c102012da2492999557e6840526Jim Grosbach 513706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes ARM_MB::MemBOpt getMemBarrierOpt() const { 51421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MemBarrierOpt && "Invalid access!"); 515706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return MBOpt.Val; 516706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 517706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 518a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ARM_PROC::IFlags getProcIFlags() const { 51921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_ProcIFlags && "Invalid access!"); 520a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return IFlags.Val; 521a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 522a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 523584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned getMSRMask() const { 52421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach assert(Kind == k_MSRMask && "Invalid access!"); 525584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MMask.Val; 526584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 527584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 52821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocNum() const { return Kind == k_CoprocNum; } 52921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCoprocReg() const { return Kind == k_CoprocReg; } 5309b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach bool isCoprocOption() const { return Kind == k_CoprocOption; } 53121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCondCode() const { return Kind == k_CondCode; } 53221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isCCOut() const { return Kind == k_CCOut; } 53321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITMask() const { return Kind == k_ITCondMask; } 53421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isITCondCode() const { return Kind == k_CondCode; } 53521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isImm() const { return Kind == k_Immediate; } 53651222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach bool isFPImm() const { 53751222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach if (!isImm()) return false; 53851222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 53951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach if (!CE) return false; 54051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 54151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach return Val != -1; 54251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach } 5434050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits16() const { 5444050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5454050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5464050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5474050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5484050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 0 && Value <= 16; 5494050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 5504050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach bool isFBits32() const { 5514050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!isImm()) return false; 5524050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5534050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach if (!CE) return false; 5544050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach int64_t Value = CE->getValue(); 5554050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach return Value >= 1 && Value <= 32; 5564050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 557a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isImm8s4() const { 55821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 559a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 560a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach if (!CE) return false; 561a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach int64_t Value = CE->getValue(); 562a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 563a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 56472f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_1020s4() const { 56521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 56672f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 56772f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 56872f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 56972f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 57072f39f8436848885176943b0ba985a7171145423Jim Grosbach } 57172f39f8436848885176943b0ba985a7171145423Jim Grosbach bool isImm0_508s4() const { 57221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 57372f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 57472f39f8436848885176943b0ba985a7171145423Jim Grosbach if (!CE) return false; 57572f39f8436848885176943b0ba985a7171145423Jim Grosbach int64_t Value = CE->getValue(); 57672f39f8436848885176943b0ba985a7171145423Jim Grosbach return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 57772f39f8436848885176943b0ba985a7171145423Jim Grosbach } 5786b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isImm0_255() const { 57921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 5806b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 5816b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 5826b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 5836b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return Value >= 0 && Value < 256; 5846b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 585587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_1() const { 58621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 587587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 588587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 589587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 590587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 2; 591587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 592587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach bool isImm0_3() const { 59321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 594587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 595587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach if (!CE) return false; 596587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach int64_t Value = CE->getValue(); 597587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach return Value >= 0 && Value < 4; 598587f5062b9e4532c4f464942e593cb87c58ac153Jim Grosbach } 59983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_7() const { 60021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 60183ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 60283ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 60383ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 60483ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 8; 60583ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 60683ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach bool isImm0_15() const { 60721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 60883ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 60983ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach if (!CE) return false; 61083ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach int64_t Value = CE->getValue(); 61183ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach return Value >= 0 && Value < 16; 61283ab070fc1fbb02ca77b0a37e6ae0eacf58001e1Jim Grosbach } 6137c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach bool isImm0_31() const { 61421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6157c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6167c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach if (!CE) return false; 6177c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach int64_t Value = CE->getValue(); 6187c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach return Value >= 0 && Value < 32; 6197c6e42e9273168ba9b1273a1580d569e1bac0e91Jim Grosbach } 620730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach bool isImm0_63() const { 62121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 622730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 623730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach if (!CE) return false; 624730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach int64_t Value = CE->getValue(); 625730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach return Value >= 0 && Value < 64; 626730fe6c1b686fe71c8e549b0f955e65a6a49d3ffJim Grosbach } 6273b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm8() const { 62821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6293b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6303b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6313b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6323b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 8; 6333b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6343b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm16() const { 63521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6363b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6373b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6383b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6393b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 16; 6403b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6413b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm32() const { 64221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6433b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6443b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6453b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6463b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value == 32; 6473b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6486b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm8() const { 64921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6506b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6516b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6526b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6536b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 8; 6546b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6556b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm16() const { 65621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6576b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6586b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6596b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6606b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 16; 6616b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6626b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm32() const { 66321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6646b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6656b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6666b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6676b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 32; 6686b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6696b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach bool isShrImm64() const { 67021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6716b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6726b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach if (!CE) return false; 6736b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach int64_t Value = CE->getValue(); 6746b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach return Value > 0 && Value <= 64; 6756b044c26094a9f86da7d12945b00a47a5f07cf6dJim Grosbach } 6763b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_7() const { 67721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6783b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6793b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6803b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6813b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 8; 6823b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6833b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_15() const { 68421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6853b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6863b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6873b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6883b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 16; 6893b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 6903b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach bool isImm1_31() const { 69121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 6923b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 6933b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach if (!CE) return false; 6943b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach int64_t Value = CE->getValue(); 6953b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach return Value > 0 && Value < 32; 6963b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2Jim Grosbach } 697f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach bool isImm1_16() const { 69821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 699f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 700f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach if (!CE) return false; 701f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach int64_t Value = CE->getValue(); 702f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach return Value > 0 && Value < 17; 703f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 7044a5ffb399f841783c201c599b88d576757f1922eJim Grosbach bool isImm1_32() const { 70521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7064a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7074a5ffb399f841783c201c599b88d576757f1922eJim Grosbach if (!CE) return false; 7084a5ffb399f841783c201c599b88d576757f1922eJim Grosbach int64_t Value = CE->getValue(); 7094a5ffb399f841783c201c599b88d576757f1922eJim Grosbach return Value > 0 && Value < 33; 7104a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 711ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach bool isImm0_32() const { 71221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 713ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 714ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (!CE) return false; 715ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach int64_t Value = CE->getValue(); 716ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach return Value >= 0 && Value < 33; 717ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 718fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach bool isImm0_65535() const { 71921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 720fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 721fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach if (!CE) return false; 722fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach int64_t Value = CE->getValue(); 723fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach return Value >= 0 && Value < 65536; 724fff76ee7ef007b2bb74804f165fee475e30ead0dJim Grosbach } 725ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach bool isImm0_65535Expr() const { 72621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 727ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 728ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // If it's not a constant expression, it'll generate a fixup and be 729ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // handled later. 730ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach if (!CE) return true; 731ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach int64_t Value = CE->getValue(); 732ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Value >= 0 && Value < 65536; 733ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 734ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach bool isImm24bit() const { 73521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 736ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 737ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach if (!CE) return false; 738ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach int64_t Value = CE->getValue(); 739ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach return Value >= 0 && Value <= 0xffffff; 740ed8384806e56952c44f8a717c1ef54a8468d2c8dJim Grosbach } 74170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach bool isImmThumbSR() const { 74221bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 74370939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 74470939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach if (!CE) return false; 74570939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach int64_t Value = CE->getValue(); 74670939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach return Value > 0 && Value < 33; 74770939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach } 748f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHLSLImm() const { 74921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 750f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 751f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 752f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 753f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value >= 0 && Value < 32; 754f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 755f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach bool isPKHASRImm() const { 75621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 757f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 758f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) return false; 759f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int64_t Value = CE->getValue(); 760f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return Value > 0 && Value <= 32; 761f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 7626bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach bool isARMSOImm() const { 76321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7646bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7656bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach if (!CE) return false; 7666bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach int64_t Value = CE->getValue(); 7676bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach return ARM_AM::getSOImmVal(Value) != -1; 7686bc1dbc37695bcfc5ae23a1a9e17550ee50fe02fJim Grosbach } 769e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach bool isARMSOImmNot() const { 77021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 771e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 772e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach if (!CE) return false; 773e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach int64_t Value = CE->getValue(); 774e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach return ARM_AM::getSOImmVal(~Value) != -1; 775e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 7763bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isARMSOImmNeg() const { 77721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7783bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7793bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 7803bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 7813bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach return ARM_AM::getSOImmVal(-Value) != -1; 7823bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 7836b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach bool isT2SOImm() const { 78421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7856b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 7866b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach if (!CE) return false; 7876b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach int64_t Value = CE->getValue(); 7886b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach return ARM_AM::getT2SOImmVal(Value) != -1; 7896b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 79089a633708542de5847e807f98f86edfefc9fc019Jim Grosbach bool isT2SOImmNot() const { 79121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 79289a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 79389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach if (!CE) return false; 79489a633708542de5847e807f98f86edfefc9fc019Jim Grosbach int64_t Value = CE->getValue(); 79589a633708542de5847e807f98f86edfefc9fc019Jim Grosbach return ARM_AM::getT2SOImmVal(~Value) != -1; 79689a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 7973bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach bool isT2SOImmNeg() const { 79821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 7993bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8003bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach if (!CE) return false; 8013bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach int64_t Value = CE->getValue(); 8023bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach return ARM_AM::getT2SOImmVal(-Value) != -1; 8033bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 804c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach bool isSetEndImm() const { 80521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 806c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 807c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CE) return false; 808c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int64_t Value = CE->getValue(); 809c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Value == 1 || Value == 0; 810c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 81121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isReg() const { return Kind == k_Register; } 81221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegList() const { return Kind == k_RegisterList; } 81321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 81421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 81521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isToken() const { return Kind == k_Token; } 81621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 81721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMemory() const { return Kind == k_Memory; } 81821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isShifterImm() const { return Kind == k_ShifterImmediate; } 81921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 82021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 82121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isRotImm() const { return Kind == k_RotateImmediate; } 82221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 82321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 824f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach bool isPostIdxReg() const { 825430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 826f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 82757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isMemNoOffset(bool alignOK = false) const { 828f6c35c59f515505fa2e9b74b3d0f4ab06f8266d8Jim Grosbach if (!isMemory()) 829ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return false; 8307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // No offset of any kind. 83157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 83257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach (alignOK || Memory.Alignment == 0); 83357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 8340b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach bool isMemPCRelImm12() const { 8350b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 8360b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return false; 8370b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base register must be PC. 8380b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum != ARM::PC) 8390b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return false; 8400b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Immediate offset in range [-4095, 4095]. 8410b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (!Memory.OffsetImm) return true; 8420b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8430b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 8440b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach } 84557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach bool isAlignedMemory() const { 84657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return isMemNoOffset(true); 847ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 8487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode2() const { 84957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 851e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 8527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 853e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 854e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Val > -4096 && Val < 4096; 8567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 857039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach bool isAM2OffsetImm() const { 85821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 859039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Immediate offset in range [-4095, 4095]. 860039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 861039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (!CE) return false; 862039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int64_t Val = CE->getValue(); 863039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach return Val > -4096 && Val < 4096; 864039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 8652fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAddrMode3() const { 8662f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 8672f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 8682f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 86921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 8702f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 87157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 8722fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // No shifts are legal for AM3. 873e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::no_shift) return false; 8742fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Check for register offset. 875e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return true; 8762fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 877e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 878e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 8792fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return Val > -256 && Val < 256; 8802fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 8812fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach bool isAM3Offset() const { 88221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind != k_Immediate && Kind != k_PostIndexRegister) 8832fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return false; 88421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) 8852fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return PostIdxReg.ShiftTy == ARM_AM::no_shift; 8862fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Immediate offset in range [-255, 255]. 8872fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 8882fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (!CE) return false; 8892fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int64_t Val = CE->getValue(); 890251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Special case, #-0 is INT32_MIN. 891251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return (Val > -256 && Val < 256) || Val == INT32_MIN; 8922fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 8937ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAddrMode5() const { 894681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 895681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 896681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 89721bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 898681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return true; 89957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.Alignment != 0) return false; 9007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for register offset. 901e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.OffsetRegNum) return false; 9027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-1020, 1020] and a multiple of 4. 903e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 904e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 9050da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 906681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Val == INT32_MIN; 9077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 9087f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBB() const { 909e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 91057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 9117f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9127f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9137f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9147f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach bool isMemTBH() const { 915e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 91657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 91757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0 ) 9187f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return false; 9197f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach return true; 9207f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 9217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemRegOffset() const { 92257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 923ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return false; 924ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 925ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 926ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach bool isT2MemRegOffset() const { 92757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 92857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.Alignment != 0) 929ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 930ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach // Only lsl #{0, 1, 2, 3} allowed. 931e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType == ARM_AM::no_shift) 932ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 933e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 934ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return false; 935ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach return true; 936ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 9377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemThumbRR() const { 9387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Thumb reg+reg addressing is simple. Just two registers, a base and 9397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // an offset. No shifts, negations or any other complicating factors. 940e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 94157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 94287f4f9a946549ad93046990a364ac5190333a7ebBill Wendling return false; 943e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach return isARMLowRegister(Memory.BaseRegNum) && 944e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 94560f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 94660f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach bool isMemThumbRIs4() const { 947e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 94857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 94960f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach return false; 95060f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach // Immediate offset, multiple of 4 in range [0, 124]. 951e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 952e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 953ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 124 && (Val % 4) == 0; 954ecd858968384be029574d845eb098d357049e02eJim Grosbach } 95538466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach bool isMemThumbRIs2() const { 956e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 95757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 95838466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return false; 95938466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach // Immediate offset, multiple of 4 in range [0, 62]. 960e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 961e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 96238466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach return Val >= 0 && Val <= 62 && (Val % 2) == 0; 96338466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 96448ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach bool isMemThumbRIs1() const { 965e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 96657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 96748ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return false; 96848ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach // Immediate offset in range [0, 31]. 969e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 970e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 97148ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach return Val >= 0 && Val <= 31; 97248ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 973ecd858968384be029574d845eb098d357049e02eJim Grosbach bool isMemThumbSPI() const { 97457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || 97557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 976ecd858968384be029574d845eb098d357049e02eJim Grosbach return false; 977ecd858968384be029574d845eb098d357049e02eJim Grosbach // Immediate offset, multiple of 4 in range [0, 1020]. 978e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 979e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 980ecd858968384be029574d845eb098d357049e02eJim Grosbach return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 981505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 982a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach bool isMemImm8s4Offset() const { 9832f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 9842f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 9852f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 98621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 9872f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return true; 98857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 989a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return false; 990a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Immediate offset a multiple of 4 in range [-1020, 1020]. 991e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 992e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 993a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 994a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 995b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach bool isMemImm0_1020s4Offset() const { 99657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 997b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return false; 998b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // Immediate offset a multiple of 4 in range [0, 1020]. 999e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1000e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1001b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1002b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 10037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm8Offset() const { 100457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1005f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling return false; 10060b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base reg of PC isn't allowed for these encodings. 10070b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum == ARM::PC) return false; 10087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-255, 255]. 1009e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1010e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10114d2a00147d19b17d382644de0d6a1f0d3230e0e4Owen Anderson return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1012f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1013f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach bool isMemPosImm8Offset() const { 101457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1015f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return false; 1016f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach // Immediate offset in range [0, 255]. 1017e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1018e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1019f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach return Val >= 0 && Val < 256; 1020f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1021a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemNegImm8Offset() const { 102257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1023a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 10240b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Base reg of PC isn't allowed for these encodings. 10250b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Memory.BaseRegNum == ARM::PC) return false; 1026a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [-255, -1]. 1027df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach if (!Memory.OffsetImm) return false; 1028e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1029df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876Jim Grosbach return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1030a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1031a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach bool isMemUImm12Offset() const { 103257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1033a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return false; 1034a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Immediate offset in range [0, 4095]. 1035e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1036e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 1037a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return (Val >= 0 && Val < 4096); 1038a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 10397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isMemImm12Offset() const { 104009176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 104109176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 104209176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // and we reject it. 104321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm() && !isa<MCConstantExpr>(getImm())) 104409176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return true; 104509176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 104657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1047ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling return false; 10487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Immediate offset in range [-4095, 4095]. 1049e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetImm) return true; 1050e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm->getValue(); 10510da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 10527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 10537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isPostIdxImm8() const { 105421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 10557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1056ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling if (!CE) return false; 10577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Val = CE->getValue(); 105863553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1059ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 10602bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isPostIdxImm8s4() const { 106121bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 10622bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 10632bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (!CE) return false; 10642bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int64_t Val = CE->getValue(); 10652bd0118472de352745a2e038245fab4974f7c87eJim Grosbach return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 10662bd0118472de352745a2e038245fab4974f7c87eJim Grosbach (Val == INT32_MIN); 10672bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 10687ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 106921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isMSRMask() const { return Kind == k_MSRMask; } 107021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach bool isProcIFlags() const { return Kind == k_ProcIFlags; } 10713483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 10720e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // NEON operands. 10730aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isSingleSpacedVectorList() const { 10740aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && !VectorList.isDoubleSpaced; 10750aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 10760aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpacedVectorList() const { 10770aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return Kind == k_VectorList && VectorList.isDoubleSpaced; 10780aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 1079862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach bool isVecListOneD() const { 10800aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1081862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return VectorList.Count == 1; 1082862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1083862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 1084280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach bool isVecListTwoD() const { 10850aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1086280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach return VectorList.Count == 2; 1087280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach } 1088280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach 1089cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach bool isVecListThreeD() const { 10900aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1091cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach return VectorList.Count == 3; 1092cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach } 1093cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach 1094b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach bool isVecListFourD() const { 10950aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isSingleSpacedVectorList()) return false; 1096b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach return VectorList.Count == 4; 1097b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach } 1098b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach 10994661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach bool isVecListTwoQ() const { 11000aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!isDoubleSpacedVectorList()) return false; 11010aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return VectorList.Count == 2; 11024661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach } 11034661d4cac3ba7f480a91d0ccd35fb2d22d9692d3Jim Grosbach 1104c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach bool isVecListThreeQ() const { 1105c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach if (!isDoubleSpacedVectorList()) return false; 1106c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return VectorList.Count == 3; 1107c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 1108c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 11093471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isSingleSpacedVectorAllLanes() const { 11103471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 11113471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 11123471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpacedVectorAllLanes() const { 11133471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 11143471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 111598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach bool isVecListOneDAllLanes() const { 11163471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 111798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return VectorList.Count == 1; 111898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 111998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 112013af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach bool isVecListTwoDAllLanes() const { 11213471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isSingleSpacedVectorAllLanes()) return false; 11223471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach return VectorList.Count == 2; 11233471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach } 11243471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach 11253471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isVecListTwoQAllLanes() const { 11263471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach if (!isDoubleSpacedVectorAllLanes()) return false; 112713af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach return VectorList.Count == 2; 112813af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach } 112913af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach 113095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isSingleSpacedVectorIndexed() const { 113195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 113295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 113395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpacedVectorIndexed() const { 113495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 113595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 11367636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach bool isVecListOneDByteIndexed() const { 113795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11387636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 11397636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 11407636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1141799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDHWordIndexed() const { 114295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1143799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1144799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1145799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1146799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListOneDWordIndexed() const { 114795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1148799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1149799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1150799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 11519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach bool isVecListTwoDByteIndexed() const { 115295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 11549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 11559b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 1156799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDHWordIndexed() const { 115795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 115895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 115995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 116095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 116195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQWordIndexed() const { 116295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 116395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 116495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach } 116595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach 116695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isVecListTwoQHWordIndexed() const { 116795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 1168799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1169799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1170799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 1171799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach bool isVecListTwoDWordIndexed() const { 117295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 1173799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1174799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach } 1175799ca9d1b7cfa8910ac27f8de4929bfbd278114dJim Grosbach 11763a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeDByteIndexed() const { 11773a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11783a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 11793a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 11803a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 11813a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeDHWordIndexed() const { 11823a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11833a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 11843a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 11853a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 11863a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeQWordIndexed() const { 11873a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 11883a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 11893a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 11903a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 11913a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeQHWordIndexed() const { 11923a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isDoubleSpacedVectorIndexed()) return false; 11933a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 11943a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 11953a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 11963a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach bool isVecListThreeDWordIndexed() const { 11973a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach if (!isSingleSpacedVectorIndexed()) return false; 11983a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 11993a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 12003a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 1201460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex8() const { 1202460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1203460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 8; 1204460a90540b045c102012da2492999557e6840526Jim Grosbach } 1205460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex16() const { 1206460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1207460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 4; 1208460a90540b045c102012da2492999557e6840526Jim Grosbach } 1209460a90540b045c102012da2492999557e6840526Jim Grosbach bool isVectorIndex32() const { 1210460a90540b045c102012da2492999557e6840526Jim Grosbach if (Kind != k_VectorIndex) return false; 1211460a90540b045c102012da2492999557e6840526Jim Grosbach return VectorIndex.Val < 2; 1212460a90540b045c102012da2492999557e6840526Jim Grosbach } 1213460a90540b045c102012da2492999557e6840526Jim Grosbach 12140e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach bool isNEONi8splat() const { 121521bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12160e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12170e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Must be a constant. 12180e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!CE) return false; 12190e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach int64_t Value = CE->getValue(); 12200e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // i8 value splatted across 8 bytes. The immediate is just the 8 byte 12210e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // value. 12220e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return Value >= 0 && Value < 256; 12230e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 1224460a90540b045c102012da2492999557e6840526Jim Grosbach 1225ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach bool isNEONi16splat() const { 122621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1227ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1228ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // Must be a constant. 1229ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (!CE) return false; 1230ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach int64_t Value = CE->getValue(); 1231ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // i16 value in the range [0,255] or [0x0100, 0xff00] 1232ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1233ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1234ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 12356248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32splat() const { 123621bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12376248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12386248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 12396248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 12406248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 12416248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 12426248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 12436248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12446248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12456248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000); 12466248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 12476248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 12486248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach bool isNEONi32vmov() const { 124921bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12506248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12516248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // Must be a constant. 12526248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (!CE) return false; 12536248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach int64_t Value = CE->getValue(); 12546248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 12556248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 12566248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach return (Value >= 0 && Value < 256) || 12576248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12586248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12596248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 12606248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 12616248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 12626248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 12639b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach bool isNEONi32vmovNeg() const { 126421bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 12659b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 12669b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // Must be a constant. 12679b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (!CE) return false; 12689b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach int64_t Value = ~CE->getValue(); 12699b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 12709b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 12719b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach return (Value >= 0 && Value < 256) || 12729b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x0100 && Value <= 0xff00) || 12739b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x010000 && Value <= 0xff0000) || 12749b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01000000 && Value <= 0xff000000) || 12759b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 12769b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 12779b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 12786248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 1279f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach bool isNEONi64splat() const { 128021bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (!isImm()) return false; 1281f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1282f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // Must be a constant. 1283f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if (!CE) return false; 1284f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 1285f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // i64 value with each byte being either 0 or 0xff. 1286f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i) 1287f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1288f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach return true; 1289f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1290f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 12913483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addExpr(MCInst &Inst, const MCExpr *Expr) const { 129214b93851cc7611ae6c2000f1c162592ead954420Chris Lattner // Add as immediates when possible. Null MCExpr = 0. 129314b93851cc7611ae6c2000f1c162592ead954420Chris Lattner if (Expr == 0) 129414b93851cc7611ae6c2000f1c162592ead954420Chris Lattner Inst.addOperand(MCOperand::CreateImm(0)); 129514b93851cc7611ae6c2000f1c162592ead954420Chris Lattner else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 12963483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 12973483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar else 12983483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar Inst.addOperand(MCOperand::CreateExpr(Expr)); 12993483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar } 13003483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 13018462b30548fb5969250858036638c73c16b65b43Daniel Dunbar void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1302345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar assert(N == 2 && "Invalid number of operands!"); 13038462b30548fb5969250858036638c73c16b65b43Daniel Dunbar Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 130404f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 130504f74942f2994a7c1d8e62c207c4005ed4652b6aJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegNum)); 13068462b30548fb5969250858036638c73c16b65b43Daniel Dunbar } 13078462b30548fb5969250858036638c73c16b65b43Daniel Dunbar 1308fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1309fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1310fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1311fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1312fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 13139b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 13149b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 13159b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(getCoproc())); 13169b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 13179b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 13189b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 13199b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach assert(N == 1 && "Invalid number of operands!"); 13209b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 13219b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 13229b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 132389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITMaskOperands(MCInst &Inst, unsigned N) const { 132489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 132589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 132689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 132789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 132889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 132989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 133089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 133189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 133289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 1333d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach void addCCOutOperands(MCInst &Inst, unsigned N) const { 1334d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1335d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Inst.addOperand(MCOperand::CreateReg(getReg())); 1336d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 1337d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 1338a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby void addRegOperands(MCInst &Inst, unsigned N) const { 1339a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby assert(N == 1 && "Invalid number of operands!"); 1340a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby Inst.addOperand(MCOperand::CreateReg(getReg())); 1341a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1342a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 1343af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1344e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1345430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedReg() && 1346430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedRegOperands() on non RegShiftedReg!"); 1347af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1348af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1349e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Inst.addOperand(MCOperand::CreateImm( 1350af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1351e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 1352e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 1353af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1354152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(N == 2 && "Invalid number of operands!"); 1355430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach assert(isRegShiftedImm() && 1356430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach "addRegShiftedImmOperands() on non RegShiftedImm!"); 1357af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 135892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Inst.addOperand(MCOperand::CreateImm( 1359af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 136092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 136192a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 1362580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach void addShifterImmOperands(MCInst &Inst, unsigned N) const { 13630082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(N == 1 && "Invalid number of operands!"); 1364580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1365580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach ShifterImm.Imm)); 13660082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 13670082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 136887f4f9a946549ad93046990a364ac5190333a7ebBill Wendling void addRegListOperands(MCInst &Inst, unsigned N) const { 13697729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling assert(N == 1 && "Invalid number of operands!"); 13705fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 13715fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 13727729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ++I) 13737729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling Inst.addOperand(MCOperand::CreateReg(*I)); 137487f4f9a946549ad93046990a364ac5190333a7ebBill Wendling } 137587f4f9a946549ad93046990a364ac5190333a7ebBill Wendling 13760f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 13770f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 13780f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 13790f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 13800f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 13810f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling addRegListOperands(Inst, N); 13820f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling } 13830f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 13847e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach void addRotImmOperands(MCInst &Inst, unsigned N) const { 13857e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 13867e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Encoded as val>>3. The printer handles display as 8, 16, 24. 13877e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 13887e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 13897e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 1390293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1391293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1392293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Munge the lsb/width into a bitfield mask. 1393293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned lsb = Bitfield.LSB; 1394293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach unsigned width = Bitfield.Width; 1395293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1396293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1397293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach (32 - (lsb + width))); 1398293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Mask)); 1399293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 1400293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 14013483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar void addImmOperands(MCInst &Inst, unsigned N) const { 14026b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 14036b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach addExpr(Inst, getImm()); 14046b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach } 14056b8f1e35eacba34a11e2a7d5f614efc47b43d2e3Jim Grosbach 14064050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits16Operands(MCInst &Inst, unsigned N) const { 14074050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 14084050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14094050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 14104050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 14114050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 14124050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach void addFBits32Operands(MCInst &Inst, unsigned N) const { 14134050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 14144050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14154050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 14164050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach } 14174050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 14189d39036f62674606565217a10db28171b9594bc7Jim Grosbach void addFPImmOperands(MCInst &Inst, unsigned N) const { 14199d39036f62674606565217a10db28171b9594bc7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 142051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 142151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 142251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 14239d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 14249d39036f62674606565217a10db28171b9594bc7Jim Grosbach 1425a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1426a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1427a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // FIXME: We really want to scale the value here, but the LDRD/STRD 1428a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // instruction don't encode operands that way yet. 1429a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1430a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1431a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1432a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 143372f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 143472f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 143572f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 143672f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 143772f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 143872f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 143972f39f8436848885176943b0ba985a7171145423Jim Grosbach } 144072f39f8436848885176943b0ba985a7171145423Jim Grosbach 144172f39f8436848885176943b0ba985a7171145423Jim Grosbach void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 144272f39f8436848885176943b0ba985a7171145423Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 144372f39f8436848885176943b0ba985a7171145423Jim Grosbach // The immediate is scaled by four in the encoding and is stored 144472f39f8436848885176943b0ba985a7171145423Jim Grosbach // in the MCInst as such. Lop off the low two bits here. 144572f39f8436848885176943b0ba985a7171145423Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 144672f39f8436848885176943b0ba985a7171145423Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 144772f39f8436848885176943b0ba985a7171145423Jim Grosbach } 144872f39f8436848885176943b0ba985a7171145423Jim Grosbach 1449f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1450f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1451f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 1452f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach // the bits as encoded, so subtract off one here. 1453f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1454f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1455f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach } 1456f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach 14574a5ffb399f841783c201c599b88d576757f1922eJim Grosbach void addImm1_32Operands(MCInst &Inst, unsigned N) const { 14584a5ffb399f841783c201c599b88d576757f1922eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14594a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // The constant encodes as the immediate-1, and we store in the instruction 14604a5ffb399f841783c201c599b88d576757f1922eJim Grosbach // the bits as encoded, so subtract off one here. 14614a5ffb399f841783c201c599b88d576757f1922eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14624a5ffb399f841783c201c599b88d576757f1922eJim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 14634a5ffb399f841783c201c599b88d576757f1922eJim Grosbach } 14644a5ffb399f841783c201c599b88d576757f1922eJim Grosbach 146570939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 146670939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 146770939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // The constant encodes as the immediate, except for 32, which encodes as 146870939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach // zero. 146970939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 147070939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach unsigned Imm = CE->getValue(); 147170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1472ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 1473ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 1474f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1475f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1476f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // An ASR value of 32 encodes as 0, so that's how we want to add it to 1477f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // the instruction as well. 1478f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1479f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 1480f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1481f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 1482f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 148389a633708542de5847e807f98f86edfefc9fc019Jim Grosbach void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 148489a633708542de5847e807f98f86edfefc9fc019Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 148589a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // The operand is actually a t2_so_imm, but we have its bitwise 148689a633708542de5847e807f98f86edfefc9fc019Jim Grosbach // negation in the assembly source, so twiddle it here. 148789a633708542de5847e807f98f86edfefc9fc019Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 148889a633708542de5847e807f98f86edfefc9fc019Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 148989a633708542de5847e807f98f86edfefc9fc019Jim Grosbach } 149089a633708542de5847e807f98f86edfefc9fc019Jim Grosbach 14913bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 14923bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 14933bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a t2_so_imm, but we have its 14943bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 14953bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 14963bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 14973bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 14983bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 1499e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1500e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1501e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // The operand is actually a so_imm, but we have its bitwise 1502e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach // negation in the assembly source, so twiddle it here. 1503e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1504e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1505e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach } 1506e70ec8463720b5990f0d1ab8d9b6ab56ca1d01c3Jim Grosbach 15073bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 15083bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 15093bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // The operand is actually a so_imm, but we have its 15103bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach // negation in the assembly source, so twiddle it here. 15113bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 15123bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 15133bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach } 15143bc8a3d3afe3ddda884a681002e24850099b719eJim Grosbach 1515706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1516706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1517706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1518706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 1519706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 15207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 15217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1522e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1523505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes } 1524505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes 15250b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 15260b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach assert(N == 1 && "Invalid number of operands!"); 15270b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach int32_t Imm = Memory.OffsetImm->getValue(); 15280b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // FIXME: Handle #-0 15290b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach if (Imm == INT32_MIN) Imm = 0; 15300b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 15310b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach } 15320b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach 153357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 153457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 153557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 153657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 153757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 153857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 15397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 15407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1541e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1542e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 15437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 15457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 15467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 15477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 15487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else { 15497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // For register offset, we encode the shift type and negation flag 15507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // here. 1551e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1552e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Memory.ShiftImm, Memory.ShiftType); 1553ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1554e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1555e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 15567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1557ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 1558ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 1559039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1560039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1561039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1562039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach assert(CE && "non-constant AM2OffsetImm operand!"); 1563039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach int32_t Val = CE->getValue(); 1564039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1565039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach // Special case for #-0 1566039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val == INT32_MIN) Val = 0; 1567039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach if (Val < 0) Val = -Val; 1568039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1569039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 1570039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1571039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach } 1572039c2e19c4237fb484315a62e95222ac28640bb7Jim Grosbach 15732fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 15742fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 15752f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 15762f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 15772f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 15782f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 15792f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 15802f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 15812f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 15822f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 15832f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 15842f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1585e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1586e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach if (!Memory.OffsetRegNum) { 15872fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 15882fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 15892fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 15902fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 15912fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 15922fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } else { 15932fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // For register offset, we encode the shift type and negation flag 15942fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // here. 1595e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 15962fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 1597e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1598e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 15992fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 16002fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 16012fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 16022fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 16032fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 160421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach if (Kind == k_PostIndexRegister) { 16052fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = 16062fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 16072fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 16082fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1609251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return; 16102fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 16112fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 16122fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Constant offset. 16132fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 16142fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach int32_t Val = CE->getValue(); 16152fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 16162fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Special case for #-0 16172fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val == INT32_MIN) Val = 0; 16182fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach if (Val < 0) Val = -Val; 1619251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = ARM_AM::getAM3Opc(AddSub, Val); 16202fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 16212fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 16222fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach } 16232fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 16247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 16257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1626681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // If we have an immediate that's not a constant, treat it as a label 1627681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // reference needing a fixup. If it is a constant, it's something else 1628681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach // and we reject it. 1629681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach if (isImm()) { 1630681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 1631681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1632681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach return; 1633681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach } 1634681460f954e9c13ffd2f02f27bba048ccf90abafJim Grosbach 16357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1636e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 16377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 16387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Special case for #-0 16397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val == INT32_MIN) Val = 0; 16407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Val < 0) Val = -Val; 16417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Val = ARM_AM::getAM5Opc(AddSub, Val); 1642e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 16437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 16447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 16457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 1646a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1647a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 16482f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // If we have an immediate that's not a constant, treat it as a label 16492f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // reference needing a fixup. If it is a constant, it's something else 16502f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach // and we reject it. 16512f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (isImm()) { 16522f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateExpr(getImm())); 16532f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 16542f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 16552f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 16562f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 1657e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1658e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1659a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1660a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach } 1661a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 1662b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1663b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1664b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach // The lower two bits are always zero and as such are not encoded. 1665e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1666e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1667b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1668b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach } 1669b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 16707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 16717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1672e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1673e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 16747ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1675ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 1676ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 1677f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1678f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1679f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach } 1680f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach 1681a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1682f0eee6eca8c39b11b6a41d9b04eba8985655df77Jim Grosbach addMemImm8OffsetOperands(Inst, N); 1683a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1684a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1685a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1686a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1687a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // If this is an immediate, it's a label reference. 168821bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 1689a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach addExpr(Inst, getImm()); 1690a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 1691a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach return; 1692a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1693a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 1694a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1695e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1696e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1697a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1698a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach } 1699a8307dd1c9279cbde1f3497e530d2ed9d014a0c5Jim Grosbach 17007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 17017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 170209176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // If this is an immediate, it's a label reference. 170321bcca81f4597f1c7d939e5d69067539ff804e6dJim Grosbach if (isImm()) { 170409176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach addExpr(Inst, getImm()); 170509176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 170609176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach return; 170709176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach } 170809176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach 170909176e10dbe575b0f4c68803695c47ccb4b81f81Jim Grosbach // Otherwise, it's a normal memory reg+offset. 1710e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1711e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 17127ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 17137ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 171492b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling 17157f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBBOperands(MCInst &Inst, unsigned N) const { 17167f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1717e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1718e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 17197f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 17207f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 17217f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach void addMemTBHOperands(MCInst &Inst, unsigned N) const { 17227f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1723e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1724e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 17257f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach } 17267f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 17277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 17287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 3 && "Invalid number of operands!"); 1729430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach unsigned Val = 1730430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1731430052b084de7ab4eb6162b9f1a6a16bfb2a80adJim Grosbach Memory.ShiftImm, Memory.ShiftType); 1732e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1733e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 17347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 17357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 1736d3df5f32c059b3ac111f1c08571d5493aa1d48c6Daniel Dunbar 1737ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1738ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach assert(N == 3 && "Invalid number of operands!"); 1739e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1740e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1741e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1742ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach } 1743ab899c1bcca7f1cc85342c3a686464ba4af035dfJim Grosbach 17447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 17457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1746e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1747e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 174814b93851cc7611ae6c2000f1c162592ead954420Chris Lattner } 17493483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 175060f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 175160f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1752e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1753e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 175460f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 175548ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach } 175648ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach 175738466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 175838466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1759e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1760e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 176138466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 176238466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach } 176338466309d5c8ce408f05567fa47aeaa3b5826080Jim Grosbach 176448ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 176548ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1766e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1767e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 176848ff5ffe9e2a90f853ce3645b1b97ea7885eccf1Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 176960f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach } 177060f91a3d9518617e29da18477ae433b8f0069304Jim Grosbach 1771ecd858968384be029574d845eb098d357049e02eJim Grosbach void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1772ecd858968384be029574d845eb098d357049e02eJim Grosbach assert(N == 2 && "Invalid number of operands!"); 1773e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1774e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1775ecd858968384be029574d845eb098d357049e02eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Val)); 1776ecd858968384be029574d845eb098d357049e02eJim Grosbach } 1777ecd858968384be029574d845eb098d357049e02eJim Grosbach 17787ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 17797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 17807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 17817ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(CE && "non-constant post-idx-imm8 operand!"); 17827ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Imm = CE->getValue(); 17837ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isAdd = Imm >= 0; 178463553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson if (Imm == INT32_MIN) Imm = 0; 17857ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 17867ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1787f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 1788ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 17892bd0118472de352745a2e038245fab4974f7c87eJim Grosbach void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 17902bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(N == 1 && "Invalid number of operands!"); 17912bd0118472de352745a2e038245fab4974f7c87eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 17922bd0118472de352745a2e038245fab4974f7c87eJim Grosbach assert(CE && "non-constant post-idx-imm8s4 operand!"); 17932bd0118472de352745a2e038245fab4974f7c87eJim Grosbach int Imm = CE->getValue(); 17942bd0118472de352745a2e038245fab4974f7c87eJim Grosbach bool isAdd = Imm >= 0; 17952bd0118472de352745a2e038245fab4974f7c87eJim Grosbach if (Imm == INT32_MIN) Imm = 0; 17962bd0118472de352745a2e038245fab4974f7c87eJim Grosbach // Immediate is scaled by 4. 17972bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 17982bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 17992bd0118472de352745a2e038245fab4974f7c87eJim Grosbach } 18002bd0118472de352745a2e038245fab4974f7c87eJim Grosbach 18017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 18027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 18037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1804f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1805f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 1806f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 1807f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1808f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 1809f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1810f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // The sign, shift type, and shift amount are encoded in a single operand 1811f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // using the AM2 encoding helpers. 1812f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1813f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1814f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach PostIdxReg.ShiftTy); 1815f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm)); 1816ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling } 1817ef4a68badbde372faac9ca47efb9001def57a43dBill Wendling 1818584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1819584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1820584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1821584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 1822584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 1823a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1824a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes assert(N == 1 && "Invalid number of operands!"); 1825a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1826a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 1827a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 18286029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach void addVecListOperands(MCInst &Inst, unsigned N) const { 1829862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1830862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1831862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 1832862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 18337636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 18347636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach assert(N == 2 && "Invalid number of operands!"); 18357636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 18367636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 18377636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 18387636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 1839460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1840460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1841460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1842460a90540b045c102012da2492999557e6840526Jim Grosbach } 1843460a90540b045c102012da2492999557e6840526Jim Grosbach 1844460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1845460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1846460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1847460a90540b045c102012da2492999557e6840526Jim Grosbach } 1848460a90540b045c102012da2492999557e6840526Jim Grosbach 1849460a90540b045c102012da2492999557e6840526Jim Grosbach void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1850460a90540b045c102012da2492999557e6840526Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1851460a90540b045c102012da2492999557e6840526Jim Grosbach Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1852460a90540b045c102012da2492999557e6840526Jim Grosbach } 1853460a90540b045c102012da2492999557e6840526Jim Grosbach 18540e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 18550e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18560e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // The immediate encodes the type of constant as well as the value. 18570e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Mask in that this is an i8 splat. 18580e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18590e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 18600e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach } 18610e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 1862ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1863ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach assert(N == 1 && "Invalid number of operands!"); 1864ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach // The immediate encodes the type of constant as well as the value. 1865ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1866ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach unsigned Value = CE->getValue(); 1867ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach if (Value >= 256) 1868ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value = (Value >> 8) | 0xa00; 1869ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach else 1870ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Value |= 0x800; 1871ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 1872ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach } 1873ea46110f57b293844a314aec3b8092adf21ff63fJim Grosbach 18746248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 18756248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18766248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 18776248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18786248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 18796248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xff00) 18806248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | 0x200; 18816248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xff0000) 18826248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | 0x400; 18836248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 18846248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 18856248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 18866248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 18876248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 18886248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 18896248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 18906248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach // The immediate encodes the type of constant as well as the value. 18916248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 18926248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach unsigned Value = CE->getValue(); 18936248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach if (Value >= 256 && Value <= 0xffff) 18946248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 18956248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 18966248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 18976248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach else if (Value > 0xffffff) 18986248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Value = (Value >> 24) | 0x600; 18999b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 19009b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach } 19019b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach 19029b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 19039b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 19049b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach // The immediate encodes the type of constant as well as the value. 19059b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 19069b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach unsigned Value = ~CE->getValue(); 19079b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach if (Value >= 256 && Value <= 0xffff) 19089b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 19099b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffff && Value <= 0xffffff) 19109b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 19119b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach else if (Value > 0xffffff) 19129b0878512fb57ee4b0bc483509e4d9f4f0b9e426Jim Grosbach Value = (Value >> 24) | 0x600; 19136248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Value)); 19146248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach } 19156248a546f23e7ffa84c171dc364b922e28467275Jim Grosbach 1916f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 1917f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach assert(N == 1 && "Invalid number of operands!"); 1918f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach // The immediate encodes the type of constant as well as the value. 1919f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1920f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach uint64_t Value = CE->getValue(); 1921f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach unsigned Imm = 0; 1922f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 1923f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Imm |= (Value & 1) << i; 1924f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1925f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 1926f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach } 1927f2f5bc60f61acf0490d856ddd09e461bf93c5459Jim Grosbach 1928b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbach virtual void print(raw_ostream &OS) const; 1929b3cb6967949493a2e1b10d015ac08b746736764eDaniel Dunbar 193089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 193121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ITCondMask); 193289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->ITMask.Mask = Mask; 193389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->StartLoc = S; 193489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Op->EndLoc = S; 193589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return Op; 193689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 193789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 19383a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 193921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CondCode); 1940345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->CC.Val = CC; 1941345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->StartLoc = S; 1942345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar Op->EndLoc = S; 19433a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1944345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar } 1945345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 1946fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 194721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocNum); 1948fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 1949fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 1950fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 1951fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 1952fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1953fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 1954fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 195521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocReg); 1956fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->Cop.Val = CopVal; 1957fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->StartLoc = S; 1958fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Op->EndLoc = S; 1959fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return Op; 1960fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes } 1961fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 19629b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 19639b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach ARMOperand *Op = new ARMOperand(k_CoprocOption); 19649b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->Cop.Val = Val; 19659b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->StartLoc = S; 19669b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Op->EndLoc = E; 19679b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return Op; 19689b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 19699b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 1970d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 197121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_CCOut); 1972d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->Reg.RegNum = RegNum; 1973d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->StartLoc = S; 1974d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach Op->EndLoc = S; 1975d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach return Op; 1976d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach } 1977d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach 19783a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 197921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Token); 1980762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Data = Str.data(); 1981762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Tok.Length = Str.size(); 1982762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 1983762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = S; 19843a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1985a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1986a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 198750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 198821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Register); 1989762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Reg.RegNum = RegNum; 1990762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 1991762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 19923a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 1993a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 1994a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 1995e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1996e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned SrcReg, 1997e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftReg, 1998e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach unsigned ShiftImm, 1999e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc S, SMLoc E) { 200021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2001af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftTy = ShTy; 2002af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.SrcReg = SrcReg; 2003af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftReg = ShiftReg; 2004af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedReg.ShiftImm = ShiftImm; 2005e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->StartLoc = S; 2006e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Op->EndLoc = E; 2007e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Op; 2008e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2009e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 201092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 201192a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned SrcReg, 201292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson unsigned ShiftImm, 201392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson SMLoc S, SMLoc E) { 201421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2015af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftTy = ShTy; 2016af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.SrcReg = SrcReg; 2017af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach Op->RegShiftedImm.ShiftImm = ShiftImm; 201892a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->StartLoc = S; 201992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Op->EndLoc = E; 202092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson return Op; 202192a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson } 202292a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson 2023580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 20240082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S, SMLoc E) { 202521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2026580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.isASR = isASR; 2027580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Op->ShifterImm.Imm = Imm; 20280082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->StartLoc = S; 20290082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson Op->EndLoc = E; 20300082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return Op; 20310082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson } 20320082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 20337e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 203421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_RotateImmediate); 20357e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->RotImm.Imm = Imm; 20367e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->StartLoc = S; 20377e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Op->EndLoc = E; 20387e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return Op; 20397e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 20407e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 2041293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2042293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S, SMLoc E) { 204321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2044293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.LSB = LSB; 2045293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->Bitfield.Width = Width; 2046293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->StartLoc = S; 2047293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Op->EndLoc = E; 2048293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return Op; 2049293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 2050293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 20517729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling static ARMOperand * 20525fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2053cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay SMLoc StartLoc, SMLoc EndLoc) { 205421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach KindTy Kind = k_RegisterList; 20550f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 2056d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 205721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_DPRRegisterList; 2058d300b94e51cf8c91928a66478c387c1c3d76faabJim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2059275944afb55086d0b4b20d4d831de7c1c7507925Evan Cheng contains(Regs.front().first)) 206021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach Kind = k_SPRRegisterList; 20610f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling 20620f6307561359fac4425a0b9e512931cf96c1ec5bBill Wendling ARMOperand *Op = new ARMOperand(Kind); 20635fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 20647729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = Regs.begin(), E = Regs.end(); I != E; ++I) 206524d22d27640e9de954a5ac26f51a45cc96bb9135Bill Wendling Op->Registers.push_back(I->first); 2066cb21d1c9fd1cf53f063183f7eb28af7fa4052ef0Bill Wendling array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2067cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->StartLoc = StartLoc; 2068cc8d10e1a8a8555fa63f33e36e3c1ed2fb24389dMatt Beaumont-Gay Op->EndLoc = EndLoc; 20698d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling return Op; 20708d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 20718d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 2072862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 20730aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach bool isDoubleSpaced, SMLoc S, SMLoc E) { 2074862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorList); 2075862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.RegNum = RegNum; 2076862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->VectorList.Count = Count; 20770aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2078862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->StartLoc = S; 2079862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Op->EndLoc = E; 2080862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return Op; 2081862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 2082862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 208398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 20843471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach bool isDoubleSpaced, 208598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc S, SMLoc E) { 208698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 208798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.RegNum = RegNum; 208898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->VectorList.Count = Count; 20893471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 209098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->StartLoc = S; 209198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Op->EndLoc = E; 209298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Op; 209398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 209498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 20957636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 209695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Index, 209795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach bool isDoubleSpaced, 209895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach SMLoc S, SMLoc E) { 20997636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 21007636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.RegNum = RegNum; 21017636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.Count = Count; 21027636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->VectorList.LaneIndex = Index; 210395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Op->VectorList.isDoubleSpaced = isDoubleSpaced; 21047636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->StartLoc = S; 21057636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Op->EndLoc = E; 21067636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return Op; 21077636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 21087636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 2109460a90540b045c102012da2492999557e6840526Jim Grosbach static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2110460a90540b045c102012da2492999557e6840526Jim Grosbach MCContext &Ctx) { 2111460a90540b045c102012da2492999557e6840526Jim Grosbach ARMOperand *Op = new ARMOperand(k_VectorIndex); 2112460a90540b045c102012da2492999557e6840526Jim Grosbach Op->VectorIndex.Val = Idx; 2113460a90540b045c102012da2492999557e6840526Jim Grosbach Op->StartLoc = S; 2114460a90540b045c102012da2492999557e6840526Jim Grosbach Op->EndLoc = E; 2115460a90540b045c102012da2492999557e6840526Jim Grosbach return Op; 2116460a90540b045c102012da2492999557e6840526Jim Grosbach } 2117460a90540b045c102012da2492999557e6840526Jim Grosbach 21183a69756e392942bc522193f38d7f33958ed3b131Chris Lattner static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 211921ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Immediate); 2120762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->Imm.Val = Val; 2121762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2122762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 21233a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2124cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby } 2125cfe072401658bbe9336b200b79526b65c5213b74Kevin Enderby 21267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach static ARMOperand *CreateMem(unsigned BaseRegNum, 21277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *OffsetImm, 21287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OffsetRegNum, 21297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType, 21300d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm, 213157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Alignment, 21327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative, 21333a69756e392942bc522193f38d7f33958ed3b131Chris Lattner SMLoc S, SMLoc E) { 213421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_Memory); 2135e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.BaseRegNum = BaseRegNum; 2136e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetImm = OffsetImm; 2137e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.OffsetRegNum = OffsetRegNum; 2138e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftType = ShiftType; 2139e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.ShiftImm = ShiftImm; 214057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Op->Memory.Alignment = Alignment; 2141e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach Op->Memory.isNegative = isNegative; 21427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->StartLoc = S; 21437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->EndLoc = E; 21447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Op; 21457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 214616c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2147f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2148f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy, 2149f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm, 21507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S, SMLoc E) { 215121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 21527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Op->PostIdxReg.RegNum = RegNum; 2153f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.isAdd = isAdd; 2154f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftTy = ShiftTy; 2155f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Op->PostIdxReg.ShiftImm = ShiftImm; 2156762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->StartLoc = S; 2157762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan Op->EndLoc = E; 21583a69756e392942bc522193f38d7f33958ed3b131Chris Lattner return Op; 2159a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 2160706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 2161706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 216221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2163706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->MBOpt.Val = Opt; 2164706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->StartLoc = S; 2165706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Op->EndLoc = S; 2166706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes return Op; 2167706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes } 2168a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 2169a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 217021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2171a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->IFlags.Val = IFlags; 2172a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->StartLoc = S; 2173a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Op->EndLoc = S; 2174a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return Op; 2175a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 2176584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 2177584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 217821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach ARMOperand *Op = new ARMOperand(k_MSRMask); 2179584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->MMask.Val = MMask; 2180584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->StartLoc = S; 2181584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Op->EndLoc = S; 2182584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return Op; 2183584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 2184a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby}; 2185a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2186a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} // end anonymous namespace. 2187a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2188b7f689bab98777236a2bf600f299d232d246bb61Jim Grosbachvoid ARMOperand::print(raw_ostream &OS) const { 2189fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar switch (Kind) { 219021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CondCode: 21916a5c22ed89c8bb73034a70105340acf6539dc58bDaniel Dunbar OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2192fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 219321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CCOut: 2194d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach OS << "<ccout " << getReg() << ">"; 2195d67641b6f804110505a69aaed5479f446bbbb34eJim Grosbach break; 219621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ITCondMask: { 21971a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer static const char *MaskStr[] = { 21981a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 21991a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 22001a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer }; 220189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert((ITMask.Mask & 0xf) == ITMask.Mask); 220289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 220389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 220489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 220521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocNum: 2206fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor number: " << getCoproc() << ">"; 2207fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 220821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_CoprocReg: 2209fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes OS << "<coprocessor register: " << getCoproc() << ">"; 2210fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes break; 22119b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach case k_CoprocOption: 22129b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach OS << "<coprocessor option: " << CoprocOption.Val << ">"; 22139b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach break; 221421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MSRMask: 2215584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes OS << "<mask: " << getMSRMask() << ">"; 2216584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes break; 221721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Immediate: 2218fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar getImm()->print(OS); 2219fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 222021ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_MemBarrierOpt: 2221706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2222706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes break; 222321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Memory: 22246ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << "<memory " 2225e53c87b302b3ae07c781405572170b0b6641b524Jim Grosbach << " base:" << Memory.BaseRegNum; 22266ec56204f372df73e4a27085b188a72548b867acDaniel Dunbar OS << ">"; 2227fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 222821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_PostIndexRegister: 2229f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2230f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.RegNum; 2231f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2232f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2233f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach << PostIdxReg.ShiftImm; 2234f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach OS << ">"; 22357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach break; 223621ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ProcIFlags: { 2237a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << "<ARM_PROC::"; 2238a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = getProcIFlags(); 2239a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes for (int i=2; i >= 0; --i) 2240a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IFlags & (1 << i)) 2241a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ARM_PROC::IFlagsToString(1 << i); 2242a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes OS << ">"; 2243a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes break; 2244a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 224521ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Register: 224650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling OS << "<register " << getReg() << ">"; 2247fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 224821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShifterImmediate: 2249580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2250580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach << " #" << ShifterImm.Imm << ">"; 2251e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach break; 225221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedRegister: 225392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_reg " 2254efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedReg.SrcReg << " " 2255efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2256efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " " << RegShiftedReg.ShiftReg << ">"; 22570082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson break; 225821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_ShiftedImmediate: 225992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson OS << "<so_reg_imm " 2260efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << RegShiftedImm.SrcReg << " " 2261efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2262efed3d1f58f69ec0a9bbe74e2ce5cc9b939a3805Jim Grosbach << " #" << RegShiftedImm.ShiftImm << ">"; 226392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson break; 226421ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RotateImmediate: 22657e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 22667e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach break; 226721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_BitfieldDescriptor: 2268293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach OS << "<bitfield " << "lsb: " << Bitfield.LSB 2269293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach << ", width: " << Bitfield.Width << ">"; 2270293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach break; 227121ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_RegisterList: 227221ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_DPRRegisterList: 227321ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_SPRRegisterList: { 22748d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << "<register_list "; 22758d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 22765fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling const SmallVectorImpl<unsigned> &RegList = getRegList(); 22775fa22a19750c082ff161db1702ebe96dd2a787e7Bill Wendling for (SmallVectorImpl<unsigned>::const_iterator 22787729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling I = RegList.begin(), E = RegList.end(); I != E; ) { 22797729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling OS << *I; 22807729e06c128be01fc564870d5ea3d22d236dddb5Bill Wendling if (++I < E) OS << ", "; 22818d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 22828d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling 22838d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling OS << ">"; 22848d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling break; 22858d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7Bill Wendling } 2286862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach case k_VectorList: 2287862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach OS << "<vector_list " << VectorList.Count << " * " 2288862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach << VectorList.RegNum << ">"; 2289862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach break; 229098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case k_VectorListAllLanes: 229198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach OS << "<vector_list(all lanes) " << VectorList.Count << " * " 229298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach << VectorList.RegNum << ">"; 229398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 22947636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case k_VectorListIndexed: 22957636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 22967636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach << VectorList.Count << " * " << VectorList.RegNum << ">"; 22977636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 229821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach case k_Token: 2299fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar OS << "'" << getToken() << "'"; 2300fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar break; 2301460a90540b045c102012da2492999557e6840526Jim Grosbach case k_VectorIndex: 2302460a90540b045c102012da2492999557e6840526Jim Grosbach OS << "<vectorindex " << getVectorIndex() << ">"; 2303460a90540b045c102012da2492999557e6840526Jim Grosbach break; 2304fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar } 2305fa315de8f44ddb318a7c6ff913e80d71d7c68859Daniel Dunbar} 23063483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 23073483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// @name Auto-generated Match Functions 23083483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// { 23093483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 23103483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbarstatic unsigned MatchRegisterName(StringRef Name); 23113483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 23123483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar/// } 23133483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 231469df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilsonbool ARMAsmParser::ParseRegister(unsigned &RegNo, 231569df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson SMLoc &StartLoc, SMLoc &EndLoc) { 2316a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach StartLoc = Parser.getTok().getLoc(); 23171355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach RegNo = tryParseRegister(); 2318a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach EndLoc = Parser.getTok().getLoc(); 2319bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 2320bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky return (RegNo == (unsigned)-1); 2321bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky} 2322bf7553210ae44f05e7460edeae1ee499d8a22dcbRoman Divacky 23239c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Try to parse a register name. The token must be an Identifier when called, 2324e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// and if it is a register name the token is eaten and the register number is 2325e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// returned. Otherwise return -1. 23263a69756e392942bc522193f38d7f33958ed3b131Chris Lattner/// 23271355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachint ARMAsmParser::tryParseRegister() { 232818b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 23297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) return -1; 2330d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 2331590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 23320c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson unsigned RegNum = MatchRegisterName(lowerCase); 23330c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson if (!RegNum) { 23340c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson RegNum = StringSwitch<unsigned>(lowerCase) 23350c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r13", ARM::SP) 23360c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r14", ARM::LR) 23370c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("r15", ARM::PC) 23380c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Case("ip", ARM::R12) 233940e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach // Additional register name aliases for 'gas' compatibility. 234040e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a1", ARM::R0) 234140e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a2", ARM::R1) 234240e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a3", ARM::R2) 234340e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("a4", ARM::R3) 234440e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v1", ARM::R4) 234540e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v2", ARM::R5) 234640e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v3", ARM::R6) 234740e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v4", ARM::R7) 234840e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v5", ARM::R8) 234940e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v6", ARM::R9) 235040e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v7", ARM::R10) 235140e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("v8", ARM::R11) 235240e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sb", ARM::R9) 235340e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("sl", ARM::R10) 235440e285554773c51f6dd6eb8d076256e557fab9c3Jim Grosbach .Case("fp", ARM::R11) 23550c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson .Default(0); 23560c9f250d54ed59108fffe5ce2f7df7bc8448915cOwen Anderson } 2357a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (!RegNum) { 2358aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // Check for aliases registered via .req. Canonicalize to lower case. 2359aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // That's more consistent since register names are case insensitive, and 2360aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach // it's how the original entry was passed in from MC/MCParser/AsmParser. 2361aee718beac4fada5914d773db38002d95cae5e0dJim Grosbach StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2362a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // If no match, return failure. 2363a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Entry == RegisterReqs.end()) 2364a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return -1; 2365a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat identifier token. 2366a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Entry->getValue(); 2367a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 236869df72367f45c0414541196efaf7c13b1ccd3f08Bob Wilson 2369b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat identifier token. 2370460a90540b045c102012da2492999557e6840526Jim Grosbach 2371e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner return RegNum; 2372e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner} 2373d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 237419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 237519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// If a recoverable error occurs, return 1. If an irrecoverable error 237619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// occurs, return -1. An irrecoverable error is one where tokens have been 237719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// consumed in the process of trying to parse the shifter (i.e., when it is 237819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach// indeed a shifter operand, but malformed). 23790d87ec21d79c8622733b8367aa41067169602480Jim Grosbachint ARMAsmParser::tryParseShiftRegister( 23800082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 23810082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 23820082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson const AsmToken &Tok = Parser.getTok(); 23830082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 23840082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2385590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string lowerCase = Tok.getString().lower(); 23860082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2387af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach .Case("asl", ARM_AM::lsl) 23880082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsl", ARM_AM::lsl) 23890082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("lsr", ARM_AM::lsr) 23900082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("asr", ARM_AM::asr) 23910082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("ror", ARM_AM::ror) 23920082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Case("rrx", ARM_AM::rrx) 23930082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson .Default(ARM_AM::no_shift); 23940082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 23950082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson if (ShiftTy == ARM_AM::no_shift) 239619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 1; 23970082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 2398e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat the operator. 2399e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 2400e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The source register for the shift has already been added to the 2401e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // operand list, so we need to pop it off and combine it into the shifted 2402e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // register operand instead. 2403eac0796542d098caa371856d545faa6cdab5aad3Benjamin Kramer OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2404e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (!PrevOp->isReg()) 2405e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2406e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int SrcReg = PrevOp->getReg(); 2407e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int64_t Imm = 0; 2408e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach int ShiftReg = 0; 2409e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (ShiftTy == ARM_AM::rrx) { 2410e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // RRX Doesn't have an explicit shift amount. The encoder expects 2411e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // the shift register to be the same as the source register. Seems odd, 2412e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // but OK. 2413e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ShiftReg = SrcReg; 2414e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else { 2415e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Figure out if this is shifted by a constant or a register (for non-RRX). 24168a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 24178a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 2418e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Parser.Lex(); // Eat hash. 2419e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc ImmLoc = Parser.getTok().getLoc(); 2420e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCExpr *ShiftExpr = 0; 242119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (getParser().ParseExpression(ShiftExpr)) { 242219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 242319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 242419906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2425e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // The expression must be evaluatable as an immediate. 2426e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 242719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (!CE) { 242819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "invalid immediate shift value"); 242919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 243019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2431e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // Range check the immediate. 2432e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsl, ror: 0 <= imm <= 31 2433e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach // lsr, asr: 0 <= imm <= 32 2434e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach Imm = CE->getValue(); 2435e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (Imm < 0 || 2436e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2437e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 243819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error(ImmLoc, "immediate shift value out of range"); 243919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 2440e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2441de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // shift by zero is a nop. Always send it through as lsl. 2442de626ad8726677328e10dbdc15011254214437d7Jim Grosbach // ('as' compatibility) 2443de626ad8726677328e10dbdc15011254214437d7Jim Grosbach if (Imm == 0) 2444de626ad8726677328e10dbdc15011254214437d7Jim Grosbach ShiftTy = ARM_AM::lsl; 2445e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } else if (Parser.getTok().is(AsmToken::Identifier)) { 24461355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach ShiftReg = tryParseRegister(); 2447e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach SMLoc L = Parser.getTok().getLoc(); 244819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (ShiftReg == -1) { 244919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (L, "expected immediate or register in shift operand"); 245019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 245119906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 245219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } else { 245319906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach Error (Parser.getTok().getLoc(), 2454e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach "expected immediate or register in shift operand"); 245519906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return -1; 245619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 2457e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach } 2458e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach 245992a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson if (ShiftReg && ShiftTy != ARM_AM::rrx) 246092a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2461af6981f2f59f0d825ad973e0bed8fff5d302196fJim Grosbach ShiftReg, Imm, 24620082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson S, Parser.getTok().getLoc())); 246392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson else 246492a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 246592a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson S, Parser.getTok().getLoc())); 24660082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 246719906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return 0; 24680082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson} 24690082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 24700082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson 247150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// Try to parse a register name. The token must be an Identifier when called. 247250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// If it's a register, an AsmOperand is created. Another AsmOperand is created 247350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling/// if there is a "writeback". 'true' if it's not a register. 2474e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// 2475e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// TODO this is likely to change to allow different register types and or to 2476e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner/// parse for a specific register type. 247750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 24781355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachtryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2479e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner SMLoc S = Parser.getTok().getLoc(); 24801355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int RegNo = tryParseRegister(); 2481e717610f53e0465cde198536561a3c00ce29d59fBill Wendling if (RegNo == -1) 248250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 2483d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 248450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2485a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2486e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner const AsmToken &ExclaimTok = Parser.getTok(); 2487e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner if (ExclaimTok.is(AsmToken::Exclaim)) { 248850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 248950d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling ExclaimTok.getLoc())); 2490e5658fa15ebb733e0786a96c1852c7cf590d5b24Chris Lattner Parser.Lex(); // Eat exclaim token 2491460a90540b045c102012da2492999557e6840526Jim Grosbach return false; 2492460a90540b045c102012da2492999557e6840526Jim Grosbach } 2493460a90540b045c102012da2492999557e6840526Jim Grosbach 2494460a90540b045c102012da2492999557e6840526Jim Grosbach // Also check for an index operand. This is only legal for vector registers, 2495460a90540b045c102012da2492999557e6840526Jim Grosbach // but that'll get caught OK in operand matching, so we don't need to 2496460a90540b045c102012da2492999557e6840526Jim Grosbach // explicitly filter everything else out here. 2497460a90540b045c102012da2492999557e6840526Jim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 2498460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc SIdx = Parser.getTok().getLoc(); 2499460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat left bracket token. 2500460a90540b045c102012da2492999557e6840526Jim Grosbach 2501460a90540b045c102012da2492999557e6840526Jim Grosbach const MCExpr *ImmVal; 2502460a90540b045c102012da2492999557e6840526Jim Grosbach if (getParser().ParseExpression(ImmVal)) 2503460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2504460a90540b045c102012da2492999557e6840526Jim Grosbach const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2505460a90540b045c102012da2492999557e6840526Jim Grosbach if (!MCE) { 2506460a90540b045c102012da2492999557e6840526Jim Grosbach TokError("immediate value expected for vector index"); 2507460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2508460a90540b045c102012da2492999557e6840526Jim Grosbach } 2509460a90540b045c102012da2492999557e6840526Jim Grosbach 2510460a90540b045c102012da2492999557e6840526Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2511460a90540b045c102012da2492999557e6840526Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) { 2512460a90540b045c102012da2492999557e6840526Jim Grosbach Error(E, "']' expected"); 2513460a90540b045c102012da2492999557e6840526Jim Grosbach return MatchOperand_ParseFail; 2514460a90540b045c102012da2492999557e6840526Jim Grosbach } 2515460a90540b045c102012da2492999557e6840526Jim Grosbach 2516460a90540b045c102012da2492999557e6840526Jim Grosbach Parser.Lex(); // Eat right bracket token. 2517460a90540b045c102012da2492999557e6840526Jim Grosbach 2518460a90540b045c102012da2492999557e6840526Jim Grosbach Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2519460a90540b045c102012da2492999557e6840526Jim Grosbach SIdx, E, 2520460a90540b045c102012da2492999557e6840526Jim Grosbach getContext())); 252199e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby } 252299e6d4e8392497d950d48b03f45c79b7dd131327Kevin Enderby 252350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2524a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 2525a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 2526fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2527fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2528fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// "c5", ... 2529fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopesstatic int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2530e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Use the same layout as the tablegen'erated register name matcher. Ugly, 2531e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // but efficient. 2532e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name.size()) { 25334d6ccb5f68cd7c6418a209f1fa4dbade569e4493David Blaikie default: return -1; 2534e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 2: 2535fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp) 2536e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2537e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[1]) { 2538e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2539e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 0; 2540e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 1; 2541e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 2; 2542e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 3; 2543e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 4; 2544e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 5; 2545e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '6': return 6; 2546e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '7': return 7; 2547e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '8': return 8; 2548e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '9': return 9; 2549e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2550e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case 3: 2551fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Name[0] != CoprocOp || Name[1] != '1') 2552e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson return -1; 2553e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson switch (Name[2]) { 2554e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson default: return -1; 2555e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '0': return 10; 2556e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '1': return 11; 2557e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '2': return 12; 2558e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '3': return 13; 2559e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '4': return 14; 2560e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson case '5': return 15; 2561e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2562e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson } 2563e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2564e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 256589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach/// parseITCondCode - Try to parse a condition code for an IT instruction. 256689df996ab20609676ecc8823f58414d598b09b46Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 256789df996ab20609676ecc8823f58414d598b09b46Jim GrosbachparseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 256889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 256989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach const AsmToken &Tok = Parser.getTok(); 257089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (!Tok.is(AsmToken::Identifier)) 257189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 257289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned CC = StringSwitch<unsigned>(Tok.getString()) 257389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("eq", ARMCC::EQ) 257489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ne", ARMCC::NE) 257589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hs", ARMCC::HS) 257689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cs", ARMCC::HS) 257789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lo", ARMCC::LO) 257889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("cc", ARMCC::LO) 257989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("mi", ARMCC::MI) 258089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("pl", ARMCC::PL) 258189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vs", ARMCC::VS) 258289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("vc", ARMCC::VC) 258389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("hi", ARMCC::HI) 258489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ls", ARMCC::LS) 258589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("ge", ARMCC::GE) 258689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("lt", ARMCC::LT) 258789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("gt", ARMCC::GT) 258889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("le", ARMCC::LE) 258989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Case("al", ARMCC::AL) 259089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach .Default(~0U); 259189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (CC == ~0U) 259289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_NoMatch; 259389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.Lex(); // Eat the token. 259489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 259589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 259689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 259789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach return MatchOperand_Success; 259889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach} 259989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 260043904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2601fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2602fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2603f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 260443904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2605e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson SMLoc S = Parser.getTok().getLoc(); 2606e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson const AsmToken &Tok = Parser.getTok(); 2607c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2608c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2609e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2610fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2611e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson if (Num == -1) 2612f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2613e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 2614e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson Parser.Lex(); // Eat identifier token. 2615fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2616f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2617fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes} 2618fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 261943904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2620fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// token must be an Identifier when called, and if it is a coprocessor 2621fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes/// number, the token is eaten and the operand is added to the operand list. 2622f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 262343904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2624fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 2625fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 2626c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) 2627c66e7afcf2810a2c1ebf08514eaf45c478e5ff67Jim Grosbach return MatchOperand_NoMatch; 2628fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2629fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2630fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes if (Reg == -1) 2631f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 2632fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 2633fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 2634fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2635f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 2636e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 2637e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 26389b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 26399b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach/// coproc_option : '{' imm0_255 '}' 26409b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 26419b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim GrosbachparseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 26429b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc S = Parser.getTok().getLoc(); 26439b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26449b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // If this isn't a '{', this isn't a coprocessor immediate operand. 26459b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 26469b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_NoMatch; 26479b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '{' 26489b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26499b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCExpr *Expr; 26509b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 26519b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (getParser().ParseExpression(Expr)) { 26529b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "illegal expression"); 26539b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26549b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 26559b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 26569b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 26579b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 26589b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26599b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach } 26609b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach int Val = CE->getValue(); 26619b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26629b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach // Check for and consume the closing '}' 26639b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 26649b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_ParseFail; 26659b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach SMLoc E = Parser.getTok().getLoc(); 26669b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Parser.Lex(); // Eat the '}' 26679b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 26689b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 26699b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach return MatchOperand_Success; 26709b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach} 26719b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 2672d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// For register list parsing, we need to map from raw GPR register numbering 2673d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// to the enumeration values. The enumeration values aren't sorted by 2674d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach// register number due to our using "sp", "lr" and "pc" as canonical names. 2675d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbachstatic unsigned getNextRegister(unsigned Reg) { 2676d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If this is a GPR, we need to do it manually, otherwise we can rely 2677d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // on the sort ordering of the enumeration since the other reg-classes 2678d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // are sane. 2679d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2680d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Reg + 1; 2681d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach switch(Reg) { 2682d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach default: assert(0 && "Invalid GPR number!"); 2683d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2684d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2685d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2686d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2687d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2688d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2689d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2690d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2691d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2692d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach} 2693d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2694ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach// Return the low-subreg of a given Q register. 2695ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbachstatic unsigned getDRegFromQReg(unsigned QReg) { 2696ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach switch (QReg) { 2697ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach default: llvm_unreachable("expected a Q register!"); 2698ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q0: return ARM::D0; 2699ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q1: return ARM::D2; 2700ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q2: return ARM::D4; 2701ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q3: return ARM::D6; 2702ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q4: return ARM::D8; 2703ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q5: return ARM::D10; 2704ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q6: return ARM::D12; 2705ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q7: return ARM::D14; 2706ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q8: return ARM::D16; 270725e0a87e9190cdca62aee5ac95cfc8ef44f35e92Jim Grosbach case ARM::Q9: return ARM::D18; 2708ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q10: return ARM::D20; 2709ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q11: return ARM::D22; 2710ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q12: return ARM::D24; 2711ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q13: return ARM::D26; 2712ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q14: return ARM::D28; 2713ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach case ARM::Q15: return ARM::D30; 2714ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2715ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach} 2716ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2717d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach/// Parse a register list. 271850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 27191355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachparseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 272018b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LCurly) && 2721a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Curly Brace"); 2722e717610f53e0465cde198536561a3c00ce29d59fBill Wendling SMLoc S = Parser.getTok().getLoc(); 2723d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '{' token. 2724d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 272516c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 2726d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Check the first register in the list to see what register class 2727d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // this is a list of. 2728d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int Reg = tryParseRegister(); 2729d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 2730d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "register expected"); 2731d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2732ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // The reglist instructions have at most 16 registers, so reserve 2733ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // space for that many. 2734ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2735ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach 2736ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2737ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2738ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2739ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2740ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach ++Reg; 2741ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 27421a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCRegisterClass *RC; 2743d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2744d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2745d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2746d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2747d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2748d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2749d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach else 2750d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2751e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 2752ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Store the register. 2753d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2754d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2755d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // This starts immediately after the first register token in the list, 2756d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // so we can see either a comma or a minus (range separator) as a legal 2757d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // next token. 2758d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 2759d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 2760d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 2761e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 2762d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 2763d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int EndReg = tryParseRegister(); 2764d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (EndReg == -1) 2765d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "register expected"); 2766ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2767ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2768ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 2769d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // If the register is the same as the start reg, there's nothing 2770d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // more to do. 2771d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == EndReg) 2772d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2773d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2774d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(EndReg)) 2775d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "invalid register in register list"); 2776d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Ranges must go from low to high. 2777d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2778d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(EndLoc, "bad range in register list"); 2779d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2780d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // Add all the registers in the range to the register list. 2781d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach while (Reg != EndReg) { 2782d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = getNextRegister(Reg); 2783d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2784d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2785d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach continue; 2786d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2787d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat the comma. 2788d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach RegLoc = Parser.getTok().getLoc(); 2789d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach int OldReg = Reg; 2790a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach const AsmToken RegTok = Parser.getTok(); 2791d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg = tryParseRegister(); 2792d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Reg == -1) 27932d539691a1e4b9d61853aa99d1a5580dc88595dbJim Grosbach return Error(RegLoc, "register expected"); 2794ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2795ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach bool isQReg = false; 2796ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2797ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Reg = getDRegFromQReg(Reg); 2798ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach isQReg = true; 2799ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach } 2800d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // The register must be in the same register class as the first. 2801d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (!RC->contains(Reg)) 2802d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "invalid register in register list"); 2803d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // List must be monotonically increasing. 2804a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) 2805d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "register list not in ascending order"); 2806a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) { 2807a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2808a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach ") in register list"); 2809a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach continue; 2810a62d11ea942ab99ba74589f74d390138654b6197Jim Grosbach } 2811d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register lists must also be contiguous. 2812d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // It's OK to use the enumeration values directly here rather, as the 2813d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach // VFP register classes have the enum sorted properly. 2814d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2815d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Reg != OldReg + 1) 2816d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(RegLoc, "non-contiguous register range"); 2817d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2818ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach if (isQReg) 2819ce485e7f70faed6d19daafff91bb20509403d432Jim Grosbach Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2820d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach } 2821d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach 2822d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 2823d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) 2824d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach return Error(E, "'}' expected"); 2825d0588e2a2ed1f7570f13b78c2042855dc4afae10Jim Grosbach Parser.Lex(); // Eat '}' token. 2826e717610f53e0465cde198536561a3c00ce29d59fBill Wendling 282727debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // Push the register list operand. 282850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 282927debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 283027debd60a152d39e421c57bce511f16d8439a670Jim Grosbach // The ARM system instruction variants for LDM/STM have a '^' token here. 283127debd60a152d39e421c57bce511f16d8439a670Jim Grosbach if (Parser.getTok().is(AsmToken::Caret)) { 283227debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 283327debd60a152d39e421c57bce511f16d8439a670Jim Grosbach Parser.Lex(); // Eat '^' token. 283427debd60a152d39e421c57bce511f16d8439a670Jim Grosbach } 283527debd60a152d39e421c57bce511f16d8439a670Jim Grosbach 283650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 2837d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby} 2838d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby 283998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach// Helper function to parse the lane index for vector lists. 284098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 28417636bf6530fd83bf7356ae3894246a4e558741a4Jim GrosbachparseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 28427636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Index = 0; // Always return a defined index value. 284398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::LBrac)) { 284498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the '['. 284598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Parser.getTok().is(AsmToken::RBrac)) { 284698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // "Dn[]" is the 'all lanes' syntax. 284798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = AllLanes; 284898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Parser.Lex(); // Eat the ']'. 284998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 285098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 2851c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCExpr *LaneIndex; 2852c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 2853c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (getParser().ParseExpression(LaneIndex)) { 2854c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "illegal expression"); 2855c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 28567636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 2857c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 2858c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (!CE) { 2859c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Loc, "lane index must be empty or an integer"); 2860c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2861c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2862c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) { 2863c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "']' expected"); 2864c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2865c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2866c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Parser.Lex(); // Eat the ']'. 2867c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach int64_t Val = CE->getValue(); 2868c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach 2869c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach // FIXME: Make this range check context sensitive for .8, .16, .32. 2870c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach if (Val < 0 || Val > 7) { 2871c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Error(Parser.getTok().getLoc(), "lane index out of range"); 2872c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_ParseFail; 2873c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach } 2874c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach Index = Val; 2875c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach LaneKind = IndexedLane; 2876c931325d99a93c273844c38d3c762705c454ae93Jim Grosbach return MatchOperand_Success; 287798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 287898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach LaneKind = NoLanes; 287998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_Success; 288098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach} 288198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 2882862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach// parse a vector register list 2883862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2884862019c37f5b5d76e34eeb0d5686e617d544059fJim GrosbachparseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 288598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy LaneKind; 28867636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned LaneIndex; 28875c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc S = Parser.getTok().getLoc(); 28885c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // As an extension (to match gas), support a plain D register or Q register 28895c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // (without encosing curly braces) as a single or double entry list, 28905c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach // respectively. 28915c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) { 28925c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach int Reg = tryParseRegister(); 28935c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Reg == -1) 28945c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_NoMatch; 28955c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 28965c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 28977636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 289898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 289998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 290098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 290198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 290298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 29030aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 290498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 290598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 290698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 29073471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 29083471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 290998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 29107636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 29117636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 291295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 291395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 29147636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 291598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 29165c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 29175c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29185c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 29195c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Reg = getDRegFromQReg(Reg); 29207636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 292198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach if (Res != MatchOperand_Success) 292298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return Res; 292398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 292498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 292598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 29260aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 292798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 292898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 292998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach E = Parser.getTok().getLoc(); 29303471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 29313471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach S, E)); 293298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 29337636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 29347636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 293595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 293695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach false, S, E)); 29377636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 293898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 29395c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_Success; 29405c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29415c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach Error(S, "vector register expected"); 29425c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach return MatchOperand_ParseFail; 29435c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach } 29445c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach 29455c984e451d604e3ff3cfdc5db7c0b6ca6be7a14fJim Grosbach if (Parser.getTok().isNot(AsmToken::LCurly)) 2946862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_NoMatch; 2947862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 2948862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '{' token. 2949862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc RegLoc = Parser.getTok().getLoc(); 2950862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 2951862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int Reg = tryParseRegister(); 2952862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 2953862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 2954862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 2955862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 2956862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach unsigned Count = 1; 2957276ed0344c05822617934fa4a6a9920d864193a5Jim Grosbach int Spacing = 0; 2958c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach unsigned FirstReg = Reg; 2959c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 2960c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 2961c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2962c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach FirstReg = Reg = getDRegFromQReg(Reg); 29630aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // double-spacing requires explicit D registers, otherwise 29640aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // it's ambiguous with four-register single spaced. 2965c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 2966c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Count; 2967c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 29687636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 296998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 2970c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach 2971e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach while (Parser.getTok().is(AsmToken::Comma) || 2972e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.getTok().is(AsmToken::Minus)) { 2973e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 29740aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 29750aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 29760aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 29770aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(Parser.getTok().getLoc(), 29780aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "sequential registers in double spaced list"); 29790aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 29800aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 2981e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Parser.Lex(); // Eat the minus. 2982e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 2983e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach int EndReg = tryParseRegister(); 2984e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (EndReg == -1) { 2985e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "register expected"); 2986e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2987e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 2988e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Allow Q regs and just interpret them as the two D sub-registers. 2989e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2990e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach EndReg = getDRegFromQReg(EndReg) + 1; 2991e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // If the register is the same as the start reg, there's nothing 2992e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // more to do. 2993e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg == EndReg) 2994e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 2995e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // The register must be in the same register class as the first. 2996e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 2997e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "invalid register in register list"); 2998e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 2999e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 3000e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Ranges must go from low to high. 3001e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach if (Reg > EndReg) { 3002e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Error(EndLoc, "bad range in register list"); 3003e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach return MatchOperand_ParseFail; 3004e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 300598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 300698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 30077636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 30087636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 300998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30107636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 301198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 301298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 301398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 301498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach EndLoc = Parser.getTok().getLoc(); 3015e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach 3016e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach // Add all the registers in the range to the register list. 3017e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Count += EndReg - Reg; 3018e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach Reg = EndReg; 3019e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach continue; 3020e43862b6a6130ec29ee4e9e6c6c30b5607c9a728Jim Grosbach } 3021862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat the comma. 3022862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach RegLoc = Parser.getTok().getLoc(); 3023862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach int OldReg = Reg; 3024862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Reg = tryParseRegister(); 3025862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Reg == -1) { 3026862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "register expected"); 3027862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3028862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3029c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // vector register lists must be contiguous. 3030862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // It's OK to use the enumeration values directly here rather, as the 3031862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach // VFP register classes have the enum sorted properly. 3032c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // 3033c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // The list is of D registers, but we also allow Q regs and just interpret 3034c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach // them as the two D sub-registers. 3035c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 30360aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 30370aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1; // Register range implies a single spaced list. 30380aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach else if (Spacing == 2) { 30390aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Error(RegLoc, 30400aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach "invalid register in double-spaced list (must be 'D' register')"); 30410aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach return MatchOperand_ParseFail; 30420aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach } 3043c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Reg = getDRegFromQReg(Reg); 3044c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach if (Reg != OldReg + 1) { 3045c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Error(RegLoc, "non-contiguous register range"); 3046c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach return MatchOperand_ParseFail; 3047c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 3048c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach ++Reg; 3049c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach Count += 2; 305098b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 305198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 30527636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 305398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 30547636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 305598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30567636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 305798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 305898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 305998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3060c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach continue; 3061c73d73eb881ebe7493e934c00ca1c474ffd0ed2dJim Grosbach } 30620aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Normal D register. 30630aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Figure out the register spacing (single or double) of the list if 30640aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // we don't know it already. 30650aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (!Spacing) 30660aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Spacing = 1 + (Reg == OldReg + 2); 30670aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach 30680aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach // Just check that it's contiguous and keep going. 30690aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach if (Reg != OldReg + Spacing) { 3070862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(RegLoc, "non-contiguous register range"); 3071862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3072862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3073862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach ++Count; 307498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach // Parse the lane specifier if present. 307598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach VectorLaneTy NextLaneKind; 30767636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach unsigned NextLaneIndex; 307798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach SMLoc EndLoc = Parser.getTok().getLoc(); 30787636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 307998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 30807636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 308198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Error(EndLoc, "mismatched lane index in register list"); 308298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach return MatchOperand_ParseFail; 308398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3084862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3085862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 3086862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3087862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach if (Parser.getTok().isNot(AsmToken::RCurly)) { 3088862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Error(E, "'}' expected"); 3089862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_ParseFail; 3090862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach } 3091862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach Parser.Lex(); // Eat '}' token. 3092862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 309398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach switch (LaneKind) { 309498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case NoLanes: 30950aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 30960aaf4cd9b34454eb381e1694f520504779c6b7f8Jim Grosbach (Spacing == 2), S, E)); 309798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 309898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach case AllLanes: 309998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 31003471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach (Spacing == 2), 310198b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach S, E)); 310298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach break; 31037636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach case IndexedLane: 31047636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 310595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach LaneIndex, 310695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach (Spacing == 2), 310795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach S, E)); 31087636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach break; 310998b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach } 3110862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach return MatchOperand_Success; 3111862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach} 3112862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 311343904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3114f922c47143d247cbae14b294a0bada139bcd35f6Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 311543904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3116706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3117706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3118706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3119706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes StringRef OptStr = Tok.getString(); 3120706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3121706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 3122706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("sy", ARM_MB::SY) 3123706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("st", ARM_MB::ST) 3124032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("sh", ARM_MB::ISH) 3125706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ish", ARM_MB::ISH) 3126032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("shst", ARM_MB::ISHST) 3127706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("ishst", ARM_MB::ISHST) 3128706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nsh", ARM_MB::NSH) 3129032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("un", ARM_MB::NSH) 3130706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("nshst", ARM_MB::NSHST) 3131032434d622b6cd030a60bb9045a520c93b0d7d68Jim Grosbach .Case("unst", ARM_MB::NSHST) 3132706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("osh", ARM_MB::OSH) 3133706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Case("oshst", ARM_MB::OSHST) 3134706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes .Default(~0U); 3135706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3136706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes if (Opt == ~0U) 3137f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_NoMatch; 3138706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 3139706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3140706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3141f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return MatchOperand_Success; 3142706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes} 3143706d946cfe44fa93f482c3a56ed42d52ca81b257Bruno Cardoso Lopes 314443904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3145a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 314643904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3147a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3148a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3149a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3150a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef IFlagsStr = Tok.getString(); 3151a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 31522dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // An iflags string of "none" is interpreted to mean that none of the AIF 31532dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // bits are set. Not a terribly useful instruction, but a valid encoding. 3154a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = 0; 31552dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (IFlagsStr != "none") { 31562dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 31572dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 31582dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("a", ARM_PROC::A) 31592dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("i", ARM_PROC::I) 31602dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Case("f", ARM_PROC::F) 31612dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson .Default(~0U); 31622dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 31632dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // If some specific iflag is already set, it means that some letter is 31642dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson // present more than once, this is not acceptable. 31652dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (Flag == ~0U || (IFlags & Flag)) 31662dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson return MatchOperand_NoMatch; 31672dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 31682dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson IFlags |= Flag; 31692dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson } 3170a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 3171a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3172a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3173a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3174a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes return MatchOperand_Success; 3175584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes} 3176584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 317743904299b05bdf579415749041f77c4490fe5f5bJim Grosbach/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3178584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso LopesARMAsmParser::OperandMatchResultTy ARMAsmParser:: 317943904299b05bdf579415749041f77c4490fe5f5bJim GrosbachparseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3180584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes SMLoc S = Parser.getTok().getLoc(); 3181584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes const AsmToken &Tok = Parser.getTok(); 3182584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3183584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Mask = Tok.getString(); 3184584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3185acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (isMClass()) { 3186acad68da50581de905a994ed3c6b9c197bcea687James Molloy // See ARMv6-M 10.1.1 3187acad68da50581de905a994ed3c6b9c197bcea687James Molloy unsigned FlagsVal = StringSwitch<unsigned>(Mask) 3188acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("apsr", 0) 3189acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("iapsr", 1) 3190acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("eapsr", 2) 3191acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("xpsr", 3) 3192acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("ipsr", 5) 3193acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("epsr", 6) 3194acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("iepsr", 7) 3195acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("msp", 8) 3196acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("psp", 9) 3197acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("primask", 16) 3198acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("basepri", 17) 3199acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("basepri_max", 18) 3200acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("faultmask", 19) 3201acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Case("control", 20) 3202acad68da50581de905a994ed3c6b9c197bcea687James Molloy .Default(~0U); 320318c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3204acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (FlagsVal == ~0U) 3205acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 3206acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3207acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) 3208acad68da50581de905a994ed3c6b9c197bcea687James Molloy // basepri, basepri_max and faultmask only valid for V7m. 3209acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_NoMatch; 321018c8d12dea944086ef0ce2f674ca8a34de2bbd74Jim Grosbach 3211acad68da50581de905a994ed3c6b9c197bcea687James Molloy Parser.Lex(); // Eat identifier token. 3212acad68da50581de905a994ed3c6b9c197bcea687James Molloy Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3213acad68da50581de905a994ed3c6b9c197bcea687James Molloy return MatchOperand_Success; 3214acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 3215acad68da50581de905a994ed3c6b9c197bcea687James Molloy 3216584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3217584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes size_t Start = 0, Next = Mask.find('_'); 3218584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes StringRef Flags = ""; 3219590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string SpecReg = Mask.slice(Start, Next).lower(); 3220584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (Next != StringRef::npos) 3221584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Flags = Mask.slice(Next+1, Mask.size()); 3222584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3223584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // FlagsVal contains the complete mask: 3224584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 3-0: Mask 3225584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3226584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned FlagsVal = 0; 3227584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3228584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "apsr") { 3229584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal = StringSwitch<unsigned>(Flags) 3230b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach .Case("nzcvq", 0x8) // same as CPSR_f 3231584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("g", 0x4) // same as CPSR_s 3232584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("nzcvqg", 0xc) // same as CPSR_fs 3233584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3234584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 32354b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger if (FlagsVal == ~0U) { 3236584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (!Flags.empty()) 3237584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3238584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes else 3239bf841cf3360558d2939c9f1a244a7a7296f846dfJim Grosbach FlagsVal = 8; // No flag 32404b19c9865ee94367d7b3594c36e59e4c15ba82ccJoerg Sonnenberger } 3241584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 324256926a39619bd644c83c4128f0b55189e52707d7Bruno Cardoso Lopes if (Flags == "all") // cpsr_all is an alias for cpsr_fc 324356926a39619bd644c83c4128f0b55189e52707d7Bruno Cardoso Lopes Flags = "fc"; 3244584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes for (int i = 0, e = Flags.size(); i != e; ++i) { 3245584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3246584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("c", 1) 3247584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("x", 2) 3248584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("s", 4) 3249584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Case("f", 8) 3250584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes .Default(~0U); 3251584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3252584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // If some specific flag is already set, it means that some letter is 3253584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // present more than once, this is not acceptable. 3254584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (FlagsVal == ~0U || (FlagsVal & Flag)) 3255584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3256584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= Flag; 3257584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } 3258584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes } else // No match for special register. 3259584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_NoMatch; 3260584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 32617784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // Special register without flags is NOT equivalent to "fc" flags. 32627784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // NOTE: This is a divergence from gas' behavior. Uncommenting the following 32637784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // two lines would enable gas compatibility at the expense of breaking 32647784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // round-tripping. 32657784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // 32667784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // if (!FlagsVal) 32677784f1d2d8b76a7eb9dd9b3fef7213770605532dOwen Anderson // FlagsVal = 0x9; 3268584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3269584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3270584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecReg == "spsr") 3271584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes FlagsVal |= 16; 3272584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 3273584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Parser.Lex(); // Eat identifier token. 3274584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3275584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes return MatchOperand_Success; 3276a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes} 3277a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 3278f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3279f6c0525d421cb48119423a96e23289b473eddbd7Jim GrosbachparsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3280f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Low, int High) { 3281f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3282f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3283f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3284f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3285f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3286f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach StringRef ShiftName = Tok.getString(); 3287590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string LowerOp = Op.lower(); 3288590853667345d6fb191764b9d0bd2ff13589e3a3Benjamin Kramer std::string UpperOp = Op.upper(); 3289f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (ShiftName != LowerOp && ShiftName != UpperOp) { 3290f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), Op + " operand expected."); 3291f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3292f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3293f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat shift type token. 3294f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3295f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach // There must be a '#' and a shift amount. 32968a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 32978a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3298f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3299f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3300f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3301f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Parser.Lex(); // Eat hash token. 3302f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3303f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCExpr *ShiftAmount; 3304f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 3305f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3306f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "illegal expression"); 3307f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3308f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3309f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3310f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (!CE) { 3311f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "constant expression expected"); 3312f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3313f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3314f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach int Val = CE->getValue(); 3315f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach if (Val < Low || Val > High) { 3316f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Error(Loc, "immediate value out of range"); 3317f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_ParseFail; 3318f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach } 3319f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3320f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3321f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3322f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach return MatchOperand_Success; 3323f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach} 3324f6c0525d421cb48119423a96e23289b473eddbd7Jim Grosbach 3325c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3326c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim GrosbachparseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3327c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach const AsmToken &Tok = Parser.getTok(); 3328c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach SMLoc S = Tok.getLoc(); 3329c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3330c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3331c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3332c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3333c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach int Val = StringSwitch<int>(Tok.getString()) 3334c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("be", 1) 3335c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Case("le", 0) 3336c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach .Default(-1); 3337c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.Lex(); // Eat the token. 3338c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3339c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (Val == -1) { 3340c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3341c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_ParseFail; 3342c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 3343c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3344c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach getContext()), 3345c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach S, Parser.getTok().getLoc())); 3346c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return MatchOperand_Success; 3347c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach} 3348c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach 3349580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3350580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// instructions. Legal values are: 3351580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// lsl #n 'n' in [0,31] 3352580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// asr #n 'n' in [1,32] 3353580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach/// n == 32 encoded as n == 0. 3354580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3355580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim GrosbachparseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3356580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const AsmToken &Tok = Parser.getTok(); 3357580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc S = Tok.getLoc(); 3358580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) { 3359580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3360580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3361580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3362580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach StringRef ShiftName = Tok.getString(); 3363580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR; 3364580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL") 3365580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = false; 3366580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else if (ShiftName == "asr" || ShiftName == "ASR") 3367580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach isASR = true; 3368580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else { 3369580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(S, "shift operator 'asr' or 'lsl' expected"); 3370580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3371580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3372580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat the operator. 3373580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3374580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // A '#' and a shift amount. 33758a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 33768a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3377580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3378580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3379580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3380580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Parser.Lex(); // Eat hash token. 3381580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3382580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCExpr *ShiftAmount; 3383580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach SMLoc E = Parser.getTok().getLoc(); 3384580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 3385580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "malformed shift expression"); 3386580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3387580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3388580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3389580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (!CE) { 3390580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "shift amount must be an immediate"); 3391580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3392580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3393580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3394580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach int64_t Val = CE->getValue(); 3395580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (isASR) { 3396580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3397580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 1 || Val > 32) { 3398580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'asr' shift amount must be in range [1,32]"); 3399580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3400580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 34010afa0094afdfe589f407feb76948f273b414b278Owen Anderson // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 34020afa0094afdfe589f407feb76948f273b414b278Owen Anderson if (isThumb() && Val == 32) { 34030afa0094afdfe589f407feb76948f273b414b278Owen Anderson Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 34040afa0094afdfe589f407feb76948f273b414b278Owen Anderson return MatchOperand_ParseFail; 34050afa0094afdfe589f407feb76948f273b414b278Owen Anderson } 3406580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val == 32) Val = 0; 3407580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } else { 3408580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach // Shift amount must be in [1,32] 3409580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (Val < 0 || Val > 31) { 3410580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Error(E, "'lsr' shift amount must be in range [0,31]"); 3411580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_ParseFail; 3412580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3413580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach } 3414580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3415580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach E = Parser.getTok().getLoc(); 3416580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3417580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 3418580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach return MatchOperand_Success; 3419580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach} 3420580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach 34217e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 34227e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// of instructions. Legal values are: 34237e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach/// ror #n 'n' in {0, 8, 16, 24} 34247e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 34257e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim GrosbachparseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 34267e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const AsmToken &Tok = Parser.getTok(); 34277e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc S = Tok.getLoc(); 3428326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (Tok.isNot(AsmToken::Identifier)) 3429326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 34307e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach StringRef ShiftName = Tok.getString(); 3431326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (ShiftName != "ror" && ShiftName != "ROR") 3432326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach return MatchOperand_NoMatch; 34337e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat the operator. 34347e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34357e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // A '#' and a rotate amount. 34368a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34378a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 34387e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 34397e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34407e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34417e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Parser.Lex(); // Eat hash token. 34427e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34437e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCExpr *ShiftAmount; 34447e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 34457e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (getParser().ParseExpression(ShiftAmount)) { 34467e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "malformed rotate expression"); 34477e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34487e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34497e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 34507e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (!CE) { 34517e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "rotate amount must be an immediate"); 34527e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34537e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34547e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34557e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach int64_t Val = CE->getValue(); 34567e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 34577e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // normally, zero is represented in asm by omitting the rotate operand 34587e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach // entirely. 34597e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 34607e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Error(E, "'ror' rotate amount must be 8, 16, or 24"); 34617e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_ParseFail; 34627e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach } 34637e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34647e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach E = Parser.getTok().getLoc(); 34657e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 34667e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 34677e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach return MatchOperand_Success; 34687e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach} 34697e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0Jim Grosbach 3470293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3471293a2ee3063953bb6f5bc828831f985f054782a3Jim GrosbachparseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3472293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 3473293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The bitfield descriptor is really two operands, the LSB and the width. 34748a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 34758a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3476293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3477293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3478293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3479293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3480293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3481293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *LSBExpr; 3482293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3483293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(LSBExpr)) { 3484293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3485293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3486293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3487293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3488293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3489293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be an immediate"); 3490293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3491293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3492293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3493293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t LSB = CE->getValue(); 3494293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [0,31] 3495293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (LSB < 0 || LSB > 31) { 3496293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'lsb' operand must be in the range [0,31]"); 3497293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3498293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3499293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3500293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3501293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // Expect another immediate operand. 3502293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Parser.getTok().isNot(AsmToken::Comma)) { 3503293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "too few operands"); 3504293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3505293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3506293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 35078a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 35088a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) { 3509293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(Parser.getTok().getLoc(), "'#' expected"); 3510293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3511293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3512293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Parser.Lex(); // Eat hash token. 3513293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3514293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach const MCExpr *WidthExpr; 3515293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (getParser().ParseExpression(WidthExpr)) { 3516293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "malformed immediate expression"); 3517293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3518293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3519293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach CE = dyn_cast<MCConstantExpr>(WidthExpr); 3520293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (!CE) { 3521293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be an immediate"); 3522293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3523293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3524293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3525293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach int64_t Width = CE->getValue(); 3526293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach // The LSB must be in the range [1,32-lsb] 3527293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach if (Width < 1 || Width > 32 - LSB) { 3528293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Error(E, "'width' operand must be in the range [1,32-lsb]"); 3529293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_ParseFail; 3530293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach } 3531293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach E = Parser.getTok().getLoc(); 3532293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3533293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3534293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 3535293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach return MatchOperand_Success; 3536293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach} 3537293a2ee3063953bb6f5bc828831f985f054782a3Jim Grosbach 35387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 35397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 35407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3541f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // postidx_reg := '+' register {, shift} 3542f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | '-' register {, shift} 3543f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // | register {, shift} 35447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 35457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 35467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // in the case where there is no match, as other alternatives take other 35477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // parse methods. 35487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach AsmToken Tok = Parser.getTok(); 35497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc S = Tok.getLoc(); 35507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool haveEaten = false; 355116578b50889329eb62774148091ba0f38b681a09Jim Grosbach bool isAdd = true; 35527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int Reg = -1; 35537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::Plus)) { 35547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+' token. 35557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 35567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 35577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-' token. 355816578b50889329eb62774148091ba0f38b681a09Jim Grosbach isAdd = false; 35597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach haveEaten = true; 35607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 35617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 35627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Reg = tryParseRegister(); 35637ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Reg == -1) { 35647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!haveEaten) 35657ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_NoMatch; 35667ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 35677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_ParseFail; 35687ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 35697ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 35707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3571f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3572f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach unsigned ShiftImm = 0; 35730d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 35740d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach Parser.Lex(); // Eat the ','. 35750d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 35760d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach return MatchOperand_ParseFail; 35770d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach } 3578f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach 3579f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3580f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach ShiftImm, S, E)); 35817ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 35827ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return MatchOperand_Success; 35837ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 35847ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 3585251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3586251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim GrosbachparseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3587251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Check for a post-index addressing register operand. Specifically: 3588251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // am3offset := '+' register 3589251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | '-' register 3590251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | register 3591251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # imm 3592251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # + imm 3593251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // | # - imm 3594251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3595251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // This method must return MatchOperand_NoMatch without consuming any tokens 3596251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // in the case where there is no match, as other alternatives take other 3597251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // parse methods. 3598251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach AsmToken Tok = Parser.getTok(); 3599251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc S = Tok.getLoc(); 3600251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3601251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Do immediates first, as we always parse those if we have a '#'. 36028a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 36038a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar)) { 3604251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '#'. 3605251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Explicitly look for a '-', as we need to encode negative zero 3606251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // differently. 3607251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isNegative = Parser.getTok().is(AsmToken::Minus); 3608251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCExpr *Offset; 3609251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (getParser().ParseExpression(Offset)) 3610251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3611251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3612251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!CE) { 3613251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(S, "constant expression expected"); 3614251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3615251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3616251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Tok.getLoc(); 3617251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach // Negative zero is encoded as the flag value INT32_MIN. 3618251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int32_t Val = CE->getValue(); 3619251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (isNegative && Val == 0) 3620251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Val = INT32_MIN; 3621251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3622251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back( 3623251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3624251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3625251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3626251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3627251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3628251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3629251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool haveEaten = false; 3630251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach bool isAdd = true; 3631251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach int Reg = -1; 3632251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Tok.is(AsmToken::Plus)) { 3633251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '+' token. 3634251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3635251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } else if (Tok.is(AsmToken::Minus)) { 3636251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Parser.Lex(); // Eat the '-' token. 3637251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach isAdd = false; 3638251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach haveEaten = true; 3639251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3640251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier)) 3641251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Reg = tryParseRegister(); 3642251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (Reg == -1) { 3643251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach if (!haveEaten) 3644251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_NoMatch; 3645251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Error(Parser.getTok().getLoc(), "register expected"); 3646251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_ParseFail; 3647251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach } 3648251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach SMLoc E = Parser.getTok().getLoc(); 3649251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3650251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3651251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 0, S, E)); 3652251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3653251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach return MatchOperand_Success; 3654251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach} 3655251bf25e7ee9702fed2a66deeb404ce473f7bac1Jim Grosbach 3656a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2LdrdPre - Convert parsed operands to MCInst. 3657a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3658a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3659a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3660a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3661a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3662a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3663a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3664a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3665a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3666a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3667a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3668a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3669a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3670a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3671a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3672a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3673a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3674a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// cvtT2StrdPre - Convert parsed operands to MCInst. 3675a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3676a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3677a77295db19527503d6b290e4f34f273d0a789365Jim Grosbachbool ARMAsmParser:: 3678a77295db19527503d6b290e4f34f273d0a789365Jim GrosbachcvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3679a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3680a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Create a writeback register dummy placeholder. 3681a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); 3682a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // Rt, Rt2 3683a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3684a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3685a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // addr 3686a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3687a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach // pred 3688a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3689a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach return true; 3690a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach} 3691a77295db19527503d6b290e4f34f273d0a789365Jim Grosbach 3692eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3693eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3694eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3695eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbachbool ARMAsmParser:: 3696eeec025cf5a2236ee9527a3312496a6ea42100c6Jim GrosbachcvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3697eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3698eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3699eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3700eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach // Create a writeback register dummy placeholder. 3701eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3702eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3703eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3704eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3705eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach return true; 3706eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach} 3707eeec025cf5a2236ee9527a3312496a6ea42100c6Jim Grosbach 3708ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3709ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3710ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3711ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbachbool ARMAsmParser:: 3712ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim GrosbachcvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3713ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3714ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach // Create a writeback register dummy placeholder. 3715ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3716ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3717ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3718ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3719ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach return true; 3720ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach} 3721ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7Jim Grosbach 37221355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3723ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3724ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3725ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 37261355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3727ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3728ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3729ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 3730ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3731ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3732ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 37337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3734ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3735ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3736ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3737ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 37389ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 37399ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37409ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson/// when they refer multiple MIOperands inside a single one. 37419ab0f25fc194b4315db1b87d38d4024054120bf6Owen Andersonbool ARMAsmParser:: 37429ab0f25fc194b4315db1b87d38d4024054120bf6Owen AndersoncvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 37439ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37449ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37459ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37469ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson // Create a writeback register dummy placeholder. 37479ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson Inst.addOperand(MCOperand::CreateImm(0)); 37489ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37499ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 37509ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37519ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson return true; 37529ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson} 37539ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 37549ab0f25fc194b4315db1b87d38d4024054120bf6Owen Anderson 3755548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3756548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3757548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3758548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbachbool ARMAsmParser:: 3759548340c4bfa596b602f286dfd3a8782817859d95Jim GrosbachcvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3760548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3761548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach // Create a writeback register dummy placeholder. 3762548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3763548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3764548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3765548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3766548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach return true; 3767548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach} 3768548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach 37691355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3770ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3771ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3772ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesbool ARMAsmParser:: 37731355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachcvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3774ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3775ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // Create a writeback register dummy placeholder. 3776ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 3777548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3778548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3779548340c4bfa596b602f286dfd3a8782817859d95Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 37817ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 37827ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 37837b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 37847b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37857b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach/// when they refer multiple MIOperands inside a single one. 37867b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbachbool ARMAsmParser:: 37877b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim GrosbachcvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 37887b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 37897b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach // Create a writeback register dummy placeholder. 37907b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 37917b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 37927b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 37937b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 37947b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach return true; 37957b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach} 37967b8f46cf9e31d730acc25be771462e2a6a1a1dfbJim Grosbach 37977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 37987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 37997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 38007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 38017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 38027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3804ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 38067ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 38077ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38087ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38097ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38107ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 38117ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3812ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3813ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return true; 3814ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 3815ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 38167ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 3817ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3818ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3819ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 38207ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 38217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3823aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3824ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 3825ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 38267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 38307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 38317ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 38327ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 38337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 3834aa3402e2800e85107a8f803be2942633b1c8c384Owen Anderson 38357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 38367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 38377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// when they refer multiple MIOperands inside a single one. 38387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser:: 38397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 38407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Create a writeback register dummy placeholder. 38427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 38437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 38447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 38497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3850ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3851ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 3852ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 3853ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 38547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 3855ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3856ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes/// when they refer multiple MIOperands inside a single one. 3857ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesbool ARMAsmParser:: 38587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachcvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 38597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3860ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // Create a writeback register dummy placeholder. 3861ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes Inst.addOperand(MCOperand::CreateImm(0)); 38627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Rt 3863ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38647ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // addr 38657ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 38667ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // offset 38677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 38687ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // pred 3869ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3870ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return true; 3871ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 3872ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 38732fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// cvtLdrdPre - Convert parsed operands to MCInst. 38742fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 38752fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach/// when they refer multiple MIOperands inside a single one. 38762fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbachbool ARMAsmParser:: 38772fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim GrosbachcvtLdrdPre(MCInst &Inst, unsigned Opcode, 38782fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 38792fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Rt, Rt2 38802fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 38812fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 38822fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // Create a writeback register dummy placeholder. 38832fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 38842fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // addr 38852fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 38862fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach // pred 38872fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 38882fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach return true; 38892fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach} 38902fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach 389114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// cvtStrdPre - Convert parsed operands to MCInst. 389214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 389314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach/// when they refer multiple MIOperands inside a single one. 389414605d1a679d55ff25875656e100ff455194ee17Jim Grosbachbool ARMAsmParser:: 389514605d1a679d55ff25875656e100ff455194ee17Jim GrosbachcvtStrdPre(MCInst &Inst, unsigned Opcode, 389614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 389714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Create a writeback register dummy placeholder. 389814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 389914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt, Rt2 390014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 390114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 390214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // addr 390314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 390414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // pred 390514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 390614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return true; 390714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach} 390814605d1a679d55ff25875656e100ff455194ee17Jim Grosbach 3909623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3910623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3911623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach/// when they refer multiple MIOperands inside a single one. 3912623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbachbool ARMAsmParser:: 3913623a454b0f5c300e69a19984d7855a1e976c3d09Jim GrosbachcvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3914623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3915623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3916623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach // Create a writeback register dummy placeholder. 3917623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 3918623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3919623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3920623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach return true; 3921623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach} 3922623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 392388ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// cvtThumbMultiple- Convert parsed operands to MCInst. 392488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// Needed here because the Asm Gen Matcher can't handle properly tied operands 392588ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach/// when they refer multiple MIOperands inside a single one. 392688ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbachbool ARMAsmParser:: 392788ae2bc6d53bbf58422ff74729da18a53e155b4aJim GrosbachcvtThumbMultiply(MCInst &Inst, unsigned Opcode, 392888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 392988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // The second source operand must be the same register as the destination 393088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // operand. 393188ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach if (Operands.size() == 6 && 39327a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 39337a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[5])->getReg()) && 39347a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach (((ARMOperand*)Operands[3])->getReg() != 39357a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach ((ARMOperand*)Operands[4])->getReg())) { 393688ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach Error(Operands[3]->getStartLoc(), 39377a010694209ce46c4f415c0b42c3bc03dc094a5cJim Grosbach "destination register must match source register"); 393888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return false; 393988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach } 394088ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 394188ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 39421b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // If we have a three-operand form, make sure to set Rn to be the operand 39431b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach // that isn't the same as Rd. 39441b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach unsigned RegOp = 4; 39451b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach if (Operands.size() == 6 && 39461b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[4])->getReg() == 39471b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[3])->getReg()) 39481b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach RegOp = 5; 39491b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 39501b332860aef0121cf4591f4377a7201ce0ef8366Jim Grosbach Inst.addOperand(Inst.getOperand(0)); 395188ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 395288ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach 395388ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 395488ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach} 3955623a454b0f5c300e69a19984d7855a1e976c3d09Jim Grosbach 395612431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 395712431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 395812431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 395912431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 39606029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 396112431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 396212431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 396312431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 396412431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 396512431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 396612431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 396712431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 396812431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 396912431329d617064d6e72dd040a58c1635cc261abJim Grosbach 397012431329d617064d6e72dd040a58c1635cc261abJim Grosbachbool ARMAsmParser:: 397112431329d617064d6e72dd040a58c1635cc261abJim GrosbachcvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 397212431329d617064d6e72dd040a58c1635cc261abJim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 397312431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vd 39746029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 397512431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Create a writeback register dummy placeholder. 397612431329d617064d6e72dd040a58c1635cc261abJim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 397712431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vn 397812431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 397912431329d617064d6e72dd040a58c1635cc261abJim Grosbach // Vm 398012431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 398112431329d617064d6e72dd040a58c1635cc261abJim Grosbach // pred 398212431329d617064d6e72dd040a58c1635cc261abJim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 398312431329d617064d6e72dd040a58c1635cc261abJim Grosbach return true; 398412431329d617064d6e72dd040a58c1635cc261abJim Grosbach} 398512431329d617064d6e72dd040a58c1635cc261abJim Grosbach 39864334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 39874334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 39884334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 39894334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 39904334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 39914334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 39924334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 39934334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 39946029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 39954334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 39964334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 39974334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 39984334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 39994334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 40004334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbachbool ARMAsmParser:: 40014334e032525d6c9038605f3871b945e8cbe6fab7Jim GrosbachcvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 40024334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 40034334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Create a writeback register dummy placeholder. 40044334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach Inst.addOperand(MCOperand::CreateImm(0)); 40054334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vn 40064334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 40074334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vm 40084334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 40094334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // Vt 40106029b6ddafad45791c9e9d8e8ddd96978294beefJim Grosbach ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 40114334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach // pred 40124334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 40134334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach return true; 40144334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach} 40154334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach 4016e717610f53e0465cde198536561a3c00ce29d59fBill Wendling/// Parse an ARM memory expression, return false if successful else return true 40179c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// or an error. The first token must be a '[' when called. 401850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendlingbool ARMAsmParser:: 40197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim GrosbachparseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4020762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 402118b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan assert(Parser.getTok().is(AsmToken::LBrac) && 4022a60f157b7c6fb60b33598fa5143ed8cb91aa5107Bill Wendling "Token is not a Left Bracket"); 4023762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4024b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat left bracket token. 4025a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 402618b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &BaseRegTok = Parser.getTok(); 40271355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach int BaseRegNum = tryParseRegister(); 40287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (BaseRegNum == -1) 40297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(BaseRegTok.getLoc(), "register expected"); 4030a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 40310571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar // The next token must either be a comma or a closing bracket. 40320571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar const AsmToken &Tok = Parser.getTok(); 40330571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 40347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Tok.getLoc(), "malformed memory operand"); 40350571093f4cf0414724674448fe6b973c0fa705b3Daniel Dunbar 40367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Tok.is(AsmToken::RBrac)) { 4037762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = Tok.getLoc(); 4038b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat right bracket token. 4039a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 40407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 404157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 0, 0, false, S, E)); 404203f44a04e63ff77af12df33e10ffdc473609dfe2Jim Grosbach 4043fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4044fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach // operand. It's rather odd, but syntactically valid. 4045fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4046fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4047fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach Parser.Lex(); // Eat the '!'. 4048fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach } 4049fb12f35545481e8b42bd547bc37d220ffee77f86Jim Grosbach 40507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 40517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 405250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 40537ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 40547ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the comma. 405550d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 405657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a ':', it's an alignment specifier. 405757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Colon)) { 405857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the ':'. 405957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 406057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 406157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCExpr *Expr; 406257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (getParser().ParseExpression(Expr)) 406357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return true; 406457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 406557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // The expression has to be a constant. Memory references with relocations 406657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // don't come through here, as they use the <label> forms of the relevant 406757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // instructions. 406857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 406957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (!CE) 407057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error (E, "constant expression expected"); 407157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 407257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach unsigned Align = 0; 407357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach switch (CE->getValue()) { 407457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach default: 4075eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach return Error(E, 4076eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4077eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 16: Align = 2; break; 4078eeaf1c1636c664c707fd9ecc96916fd20ddf137aJim Grosbach case 32: Align = 4; break; 407957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 64: Align = 8; break; 408057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 128: Align = 16; break; 408157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach case 256: Align = 32; break; 408257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 408357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 408457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Now we should have the closing ']' 408557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach E = Parser.getTok().getLoc(); 408657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 408757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return Error(E, "']' expected"); 408857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat right bracket token. 408957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 409057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // Don't worry about range checking the value here. That's handled by 409157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // the is*() predicates. 409257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 409357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, Align, 409457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 409557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 409657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 409757dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // operand. 409857dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 409957dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 410057dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach Parser.Lex(); // Eat the '!'. 410157dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 410257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 410357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach return false; 410457dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach } 410557dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach 410657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach // If we have a '#', it's an immediate offset, else assume it's a register 41076cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // offset. Be friendly and also accept a plain integer (without a leading 41086cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach // hash) for gas compatibility. 41096cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach if (Parser.getTok().is(AsmToken::Hash) || 41108a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().is(AsmToken::Dollar) || 41116cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.getTok().is(AsmToken::Integer)) { 41128a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Integer)) 41136cb4b081829880ba97a729bcf33fd59517ca5450Jim Grosbach Parser.Lex(); // Eat the '#'. 41147ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 411550d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling 41160da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson bool isNegative = getParser().getTok().is(AsmToken::Minus); 41177ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Offset; 41187ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Offset)) 41197ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 412005d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 41217ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The expression has to be a constant. Memory references with relocations 41227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // don't come through here, as they use the <label> forms of the relevant 41237ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // instructions. 41247ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 41257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 41267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error (E, "constant expression expected"); 41277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41280da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson // If the constant was #-0, represent it as INT32_MIN. 41290da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson int32_t Val = CE->getValue(); 41300da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson if (isNegative && Val == 0) 41310da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson CE = MCConstantExpr::Create(INT32_MIN, getContext()); 41320da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson 41337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 41347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41357ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 41367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 41377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 413805d8b71424316ad7b014adbbb316f78c5bd46861Daniel Dunbar 41397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Don't worry about range checking the value here. That's handled by 41407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // the is*() predicates. 41417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 414257dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ARM_AM::no_shift, 0, 0, 414357dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach false, S, E)); 4144a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 41457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 41467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // operand. 41477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 41487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 41497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '!'. 4150762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan } 41517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41527ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return false; 41539c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 4154d4462a5a4feae0293ca14376ff25d8bb72dd12a9Jim Grosbach 41557ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // The register offset is optionally preceded by a '+' or '-' 41567ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach bool isNegative = false; 41577ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 41587ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach isNegative = true; 41597ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '-'. 41607ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } else if (Parser.getTok().is(AsmToken::Plus)) { 41617ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Nothing to do. 41627ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the '+'. 41637ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 41649c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41657ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41667ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int OffsetRegNum = tryParseRegister(); 41677ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (OffsetRegNum == -1) 41687ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "register expected"); 41697ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41707ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // If there's a shift operator, handle it. 41717ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 41720d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach unsigned ShiftImm = 0; 41737ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().is(AsmToken::Comma)) { 41747ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat the ','. 41750d6fac36eda6b65f0e396b24c5bce582f89f7992Jim Grosbach if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 41767ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 41779c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby } 417816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 41797ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Now we should have the closing ']' 41807ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach E = Parser.getTok().getLoc(); 41817ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Parser.getTok().isNot(AsmToken::RBrac)) 41827ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(E, "']' expected"); 41837ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat right bracket token. 41847ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 41857ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 418657dcb85a30133a9bc008f0b9ead81be03a23521eJim Grosbach ShiftType, ShiftImm, 0, isNegative, 41877ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach S, E)); 41887ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 4189f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // If there's a pre-indexing writeback marker, '!', just add it as a token 4190f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach // operand. 4191f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach if (Parser.getTok().is(AsmToken::Exclaim)) { 4192f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4193f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach Parser.Lex(); // Eat the '!'. 4194f4fa3d6e463e88743983ccfa027a7555a8720917Jim Grosbach } 41959c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41969c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby return false; 41979c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby} 41989c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 41997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// parseMemRegOffsetShift - one of these two: 4200a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// ( lsl | lsr | asr | ror ) , # shift_amount 4201a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby/// rrx 42027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach/// return true if it parses a shift otherwise it returns false. 42037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachbool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 42047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned &Amount) { 42057ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach SMLoc Loc = Parser.getTok().getLoc(); 420618b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 4207a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby if (Tok.isNot(AsmToken::Identifier)) 4208a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return true; 420938e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef ShiftName = Tok.getString(); 4210af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach if (ShiftName == "lsl" || ShiftName == "LSL" || 4211af4edea67b007592f9474e07d27182956e37f7f5Jim Grosbach ShiftName == "asl" || ShiftName == "ASL") 42120082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsl; 4213a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "lsr" || ShiftName == "LSR") 42140082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::lsr; 4215a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "asr" || ShiftName == "ASR") 42160082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::asr; 4217a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "ror" || ShiftName == "ROR") 42180082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::ror; 4219a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else if (ShiftName == "rrx" || ShiftName == "RRX") 42200082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson St = ARM_AM::rrx; 4221a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby else 42227ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "illegal shift operator"); 4223b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat shift type token. 4224a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 42257ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // rrx stands alone. 42267ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = 0; 42277ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (St != ARM_AM::rrx) { 42287ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Loc = Parser.getTok().getLoc(); 42297ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // A '#' and a shift amount. 42307ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const AsmToken &HashTok = Parser.getTok(); 42318a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (HashTok.isNot(AsmToken::Hash) && 42328a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach HashTok.isNot(AsmToken::Dollar)) 42337ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(HashTok.getLoc(), "'#' expected"); 42347ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Parser.Lex(); // Eat hash token. 42359c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby 42367ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCExpr *Expr; 42377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (getParser().ParseExpression(Expr)) 42387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return true; 42397ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // Range check the immediate. 42407ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsl, ror: 0 <= imm <= 31 42417ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach // lsr, asr: 0 <= imm <= 32 42427ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 42437ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (!CE) 42447ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "shift amount must be an immediate"); 42457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach int64_t Imm = CE->getValue(); 42467ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach if (Imm < 0 || 42477ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 42487ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 42497ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach return Error(Loc, "immediate shift value out of range"); 42507ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach Amount = Imm; 42517ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach } 4252a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4253a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby return false; 4254a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4255a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 42569d39036f62674606565217a10db28171b9594bc7Jim Grosbach/// parseFPImm - A floating point immediate expression operand. 42579d39036f62674606565217a10db28171b9594bc7Jim GrosbachARMAsmParser::OperandMatchResultTy ARMAsmParser:: 42589d39036f62674606565217a10db28171b9594bc7Jim GrosbachparseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 425951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // Anything that can accept a floating point constant as an operand 426051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // needs to go through here, as the regular ParseExpression is 426151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // integer only. 426251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // 426351222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // This routine still creates a generic Immediate operand, containing 426451222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // a bitcast of the 64-bit floating point value. The various operands 426551222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // that accept floats can check whether the value is valid for them 426651222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // via the standard is*() predicates. 426751222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach 42689d39036f62674606565217a10db28171b9594bc7Jim Grosbach SMLoc S = Parser.getTok().getLoc(); 42699d39036f62674606565217a10db28171b9594bc7Jim Grosbach 42708a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach if (Parser.getTok().isNot(AsmToken::Hash) && 42718a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach Parser.getTok().isNot(AsmToken::Dollar)) 42729d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_NoMatch; 42730e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 42740e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // Disambiguate the VMOV forms that can accept an FP immediate. 42750e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <sreg>, #imm 42760e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f64 <dreg>, #imm 42770e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <dreg>, #imm @ vector f32x2 42780e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.f32 <qreg>, #imm @ vector f32x4 42790e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // 42800e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // There are also the NEON VMOV instructions which expect an 42810e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // integer constant. Make sure we don't try to parse an FPImm 42820e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // for these: 42830e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach // vmov.i{8|16|32|64} <dreg|qreg>, #imm 42840e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 42850e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 42860e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach TyOp->getToken() != ".f64")) 42870e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach return MatchOperand_NoMatch; 42880e387b2877e4eebeedfcb26b08253f9c1b946035Jim Grosbach 42899d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the '#'. 42909d39036f62674606565217a10db28171b9594bc7Jim Grosbach 42919d39036f62674606565217a10db28171b9594bc7Jim Grosbach // Handle negation, as that still comes through as a separate token. 42929d39036f62674606565217a10db28171b9594bc7Jim Grosbach bool isNegative = false; 42939d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Parser.getTok().is(AsmToken::Minus)) { 42949d39036f62674606565217a10db28171b9594bc7Jim Grosbach isNegative = true; 42959d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); 42969d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 42979d39036f62674606565217a10db28171b9594bc7Jim Grosbach const AsmToken &Tok = Parser.getTok(); 4298ae69f703d59410fc96f04be3c1afeaa1c17a45ceJim Grosbach SMLoc Loc = Tok.getLoc(); 42999d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Real)) { 430051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 43019d39036f62674606565217a10db28171b9594bc7Jim Grosbach uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 43029d39036f62674606565217a10db28171b9594bc7Jim Grosbach // If we had a '-' in front, toggle the sign bit. 430351222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach IntVal ^= (uint64_t)isNegative << 31; 43049d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 430551222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Operands.push_back(ARMOperand::CreateImm( 430651222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach MCConstantExpr::Create(IntVal, getContext()), 430751222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach S, Parser.getTok().getLoc())); 43089d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 43099d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 431051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // Also handle plain integers. Instructions which allow floating point 431151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach // immediates also allow a raw encoded 8-bit value. 43129d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Tok.is(AsmToken::Integer)) { 43139d39036f62674606565217a10db28171b9594bc7Jim Grosbach int64_t Val = Tok.getIntVal(); 43149d39036f62674606565217a10db28171b9594bc7Jim Grosbach Parser.Lex(); // Eat the token. 43159d39036f62674606565217a10db28171b9594bc7Jim Grosbach if (Val > 255 || Val < 0) { 4316ae69f703d59410fc96f04be3c1afeaa1c17a45ceJim Grosbach Error(Loc, "encoded floating point value out of range"); 43179d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 43189d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 431951222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach double RealVal = ARM_AM::getFPImmFloat(Val); 432051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 432151222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Operands.push_back(ARMOperand::CreateImm( 432251222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach MCConstantExpr::Create(Val, getContext()), S, 432351222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach Parser.getTok().getLoc())); 43249d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_Success; 43259d39036f62674606565217a10db28171b9594bc7Jim Grosbach } 43269d39036f62674606565217a10db28171b9594bc7Jim Grosbach 4327ae69f703d59410fc96f04be3c1afeaa1c17a45ceJim Grosbach Error(Loc, "invalid floating point immediate"); 43289d39036f62674606565217a10db28171b9594bc7Jim Grosbach return MatchOperand_ParseFail; 43299d39036f62674606565217a10db28171b9594bc7Jim Grosbach} 433051222d1551383dd7b95ba356b1a5ed89df69e789Jim Grosbach 43319c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Parse a arm instruction operand. For now this parses the operand regardless 43329c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// of the mnemonic. 43331355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4334fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes StringRef Mnemonic) { 4335762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan SMLoc S, E; 4336fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4337fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // Check if the current operand has a custom associated parser, if so, try to 4338fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes // custom parse the operand, or fallback to the general approach. 4339f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4340f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_Success) 4341fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes return false; 4342f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // If there wasn't a custom match, try the generic matcher below. Otherwise, 4343f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // there was a match, but an error occurred, in which case, just return that 4344f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach // the operand parsing failed. 4345f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach if (ResTy == MatchOperand_ParseFail) 4346f922c47143d247cbae14b294a0bada139bcd35f6Jim Grosbach return true; 4347fafde7f0b7c70e08de719d9e33ce9f6fdaefc984Bruno Cardoso Lopes 4348a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby switch (getLexer().getKind()) { 4349146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling default: 4350146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling Error(Parser.getTok().getLoc(), "unexpected token in operand"); 435150d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 435219906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach case AsmToken::Identifier: { 43531355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (!tryParseRegisterWithWriteBack(Operands)) 435450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 43550d87ec21d79c8622733b8367aa41067169602480Jim Grosbach int Res = tryParseShiftRegister(Operands); 435619906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach if (Res == 0) // success 43570082830cb26248178fe5cc9bbdbd00881556c33dOwen Anderson return false; 435819906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach else if (Res == -1) // irrecoverable error 435919906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach return true; 43603cbe43fe69680df772d83947ced97ca445861213Jim Grosbach // If this is VMRS, check for the apsr_nzcv operand. 43615cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { 43625cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach S = Parser.getTok().getLoc(); 43635cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach Parser.Lex(); 43645cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S)); 43655cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach return false; 43665cd5ac6ad455880395e34ac647f1e962a83763a0Jim Grosbach } 4367e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 4368e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // Fall though for the Identifier case that is not a register or a 4369e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson // special name. 437019906729a490744ce3071d20e3d514cadc12e6c5Jim Grosbach } 4371758a519a22b469ce8e2b8d0bf7a72813e87710d4Jim Grosbach case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 437267b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Integer: // things like 1f and 2b as a branch targets 43736284afc293c8f6e84dffab8731aa9e679d437745Jim Grosbach case AsmToken::String: // quoted label names. 437467b212e03b77e921e2b9780059681125a45d15a7Kevin Enderby case AsmToken::Dot: { // . as a branch target 4375515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // This was not a register so parse other operands that start with an 4376515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // identifier (like labels) as expressions and create them as immediates. 4377515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby const MCExpr *IdVal; 4378762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4379515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getParser().ParseExpression(IdVal)) 438050d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 4381762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 438250d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 438350d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 438450d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling } 4385a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby case AsmToken::LBrac: 43861355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseMemory(Operands); 4387d7894f105a3c397a3d7f5c5136eee39f5865e64bKevin Enderby case AsmToken::LCurly: 43881355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseRegisterList(Operands); 43898a12e3b5df13b279eff3cfc29e0d7808ff86aa44Jim Grosbach case AsmToken::Dollar: 439063553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson case AsmToken::Hash: { 4391079469f649d8da3923b9f747d7062c84e01cc4aeKevin Enderby // #42 -> immediate. 4392079469f649d8da3923b9f747d7062c84e01cc4aeKevin Enderby // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 4393762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan S = Parser.getTok().getLoc(); 4394b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 439563553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson bool isNegative = Parser.getTok().is(AsmToken::Minus); 4396515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby const MCExpr *ImmVal; 4397515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getParser().ParseExpression(ImmVal)) 439850d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return true; 439963553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4400ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach if (CE) { 4401ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach int32_t Val = CE->getValue(); 4402ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach if (isNegative && Val == 0) 4403ed6a0c5243f4dc13169edc8e342c679f1bfc201cJim Grosbach ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 440463553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 4405762647673379dbcff6bbba6167b0b1b0d658ba9dSean Callanan E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 440650d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 440750d0f5894448aff6eb02ad63da55ecf26b54aeb8Bill Wendling return false; 440863553c77cd1cf3b204d955fb65350db087aaff1dOwen Anderson } 44099081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim case AsmToken::Colon: { 44109081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // ":lower16:" and ":upper16:" expression prefixes 44117597212abced110723f2fee985a7d60557c092ecEvan Cheng // FIXME: Check it's an expression prefix, 44127597212abced110723f2fee985a7d60557c092ecEvan Cheng // e.g. (FOO - :lower16:BAR) isn't legal. 44137597212abced110723f2fee985a7d60557c092ecEvan Cheng ARMMCExpr::VariantKind RefKind; 44141355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parsePrefix(RefKind)) 44159081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44169081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44177597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *SubExprVal; 44187597212abced110723f2fee985a7d60557c092ecEvan Cheng if (getParser().ParseExpression(SubExprVal)) 44199081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44209081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44217597212abced110723f2fee985a7d60557c092ecEvan Cheng const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 44227597212abced110723f2fee985a7d60557c092ecEvan Cheng getContext()); 44239081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 44247597212abced110723f2fee985a7d60557c092ecEvan Cheng Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 44259081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 44269081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 4427a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 4428a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby} 4429a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 44301355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 44317597212abced110723f2fee985a7d60557c092ecEvan Cheng// :lower16: and :upper16:. 44321355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 44337597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_None; 44349081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44359081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim // :lower16: and :upper16: modifiers 44368a8696db6b6f6e735bb9de630876af83946b45f9Jason W Kim assert(getLexer().is(AsmToken::Colon) && "expected a :"); 44379081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat ':' 44389081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44399081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Identifier)) { 44409081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 44419081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44429081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44439081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44449081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim StringRef IDVal = Parser.getTok().getIdentifier(); 44459081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (IDVal == "lower16") { 44467597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_LO16; 44479081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else if (IDVal == "upper16") { 44487597212abced110723f2fee985a7d60557c092ecEvan Cheng RefKind = ARMMCExpr::VK_ARM_HI16; 44499081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } else { 44509081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 44519081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44529081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44539081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); 44549081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 44559081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim if (getLexer().isNot(AsmToken::Colon)) { 44569081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 44579081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return true; 44589081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim } 44599081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim Parser.Lex(); // Eat the last ':' 44609081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim return false; 44619081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim} 44629081b4b4cf89a161246e037f4817c69de2fcdf82Jason W Kim 4463352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// \brief Given a mnemonic, split out possible predication code and carry 4464352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar/// setting letters to form a canonical mnemonic and flags. 4465352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar// 4466badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar// FIXME: Would be nice to autogen this. 446789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach// FIXME: This is a bit of a maze of special cases. 44681355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachStringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 44695f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach unsigned &PredicationCode, 44705f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach bool &CarrySetting, 447189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned &ProcessorIMod, 447289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef &ITMask) { 4473352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar PredicationCode = ARMCC::AL; 4474352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = false; 4475a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = 0; 4476352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4477badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Ignore some mnemonics we know aren't predicated forms. 4478352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // 4479352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // FIXME: Would be nice to autogen this. 44805f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach if ((Mnemonic == "movs" && isThumb()) || 44815f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 44825f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 44835f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 44845f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 44855f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 44865f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 44876849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 44886849019079794c573b72c1ec55613cb6ba1297a5Jim Grosbach Mnemonic == "fmuls") 4489352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4490badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 44913f00e317064560ad11168d22030416d853829f6eJim Grosbach // First, split out any predication code. Ignore mnemonics we know aren't 44923f00e317064560ad11168d22030416d853829f6eJim Grosbach // predicated but do have a carry-set and so weren't caught above. 4493ab40f4b737b0a87c4048a9ad2f0c02be735e3770Jim Grosbach if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 449471725a099e6d0cba24a63f9c9063f6efee3bf76eJim Grosbach Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 449504d55f1905748b0d66655e2332e1a232a3f665f4Jim Grosbach Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 44962f25d9b9334662e846460e98a8fe2dae4f233068Jim Grosbach Mnemonic != "sbcs" && Mnemonic != "rscs") { 44973f00e317064560ad11168d22030416d853829f6eJim Grosbach unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 44983f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("eq", ARMCC::EQ) 44993f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ne", ARMCC::NE) 45003f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hs", ARMCC::HS) 45013f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cs", ARMCC::HS) 45023f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lo", ARMCC::LO) 45033f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("cc", ARMCC::LO) 45043f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("mi", ARMCC::MI) 45053f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("pl", ARMCC::PL) 45063f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vs", ARMCC::VS) 45073f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("vc", ARMCC::VC) 45083f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("hi", ARMCC::HI) 45093f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ls", ARMCC::LS) 45103f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("ge", ARMCC::GE) 45113f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("lt", ARMCC::LT) 45123f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("gt", ARMCC::GT) 45133f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("le", ARMCC::LE) 45143f00e317064560ad11168d22030416d853829f6eJim Grosbach .Case("al", ARMCC::AL) 45153f00e317064560ad11168d22030416d853829f6eJim Grosbach .Default(~0U); 45163f00e317064560ad11168d22030416d853829f6eJim Grosbach if (CC != ~0U) { 45173f00e317064560ad11168d22030416d853829f6eJim Grosbach Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 45183f00e317064560ad11168d22030416d853829f6eJim Grosbach PredicationCode = CC; 45193f00e317064560ad11168d22030416d853829f6eJim Grosbach } 452052925b60f1cd4cf810524ca05b00a207a926ab9fBill Wendling } 4521345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 4522352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Next, determine if we have a carry setting bit. We explicitly ignore all 4523352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // the instructions we know end in 's'. 4524352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar if (Mnemonic.endswith("s") && 452500f5d982057574cf65a4a3f29548ff9fb0ecfbd0Jim Grosbach !(Mnemonic == "cps" || Mnemonic == "mls" || 45265f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 45275f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 45285f16057d1e4b711d492091bc555693a03d4a1b6eJim Grosbach Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 452967ca1adf822c6cbc2f2bb78b8f94eefd099a8eb6Jim Grosbach Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 453048171e7fbe58bb418f09717813779d03903d35e4Jim Grosbach Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 45319c39789c361d4fe2632f28fca74c9ea5fff3dafcJim Grosbach Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 45321aa149f5acea364aa8bc9cfc3a167f78eff2e96bJim Grosbach Mnemonic == "fmuls" || Mnemonic == "fcmps" || 4533e1cf5902ec832cecdd5a94b9701930253d410741Jim Grosbach (Mnemonic == "movs" && isThumb()))) { 4534352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4535352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar CarrySetting = true; 4536352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar } 4537352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar 4538a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // The "cps" instruction can have a interrupt mode operand which is glued into 4539a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // the mnemonic. Check if this is the case, split it and parse the imod op 4540a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (Mnemonic.startswith("cps")) { 4541a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Split out any imod code. 4542a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IMod = 4543a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4544a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("ie", ARM_PROC::IE) 4545a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Case("id", ARM_PROC::ID) 4546a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes .Default(~0U); 4547a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IMod != ~0U) { 4548a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4549a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes ProcessorIMod = IMod; 4550a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4551a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4552a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 455389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The "it" instruction has the condition mask on the end of the mnemonic. 455489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic.startswith("it")) { 455589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ITMask = Mnemonic.slice(2, Mnemonic.size()); 455689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mnemonic = Mnemonic.slice(0, 2); 455789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 455889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4559352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar return Mnemonic; 4560352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar} 45613771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 45623771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// \brief Given a canonical mnemonic, determine if the instruction ever allows 45633771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar/// inclusion of carry set or predication code operands. 45643771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// 45653771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar// FIXME: It would be nice to autogen this. 4566fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopesvoid ARMAsmParser:: 45671355cf1f76abe9699cd1c2838da132ff8b25b76bJim GrosbachgetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4568fdcee77887372dbf6589d47cc33094965b679f24Bruno Cardoso Lopes bool &CanAcceptPredicationCode) { 4569eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4570eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 45713443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach Mnemonic == "add" || Mnemonic == "adc" || 4572eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4573d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "orr" || Mnemonic == "mvn" || 4574eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4575d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 45763443ed525a3bce98bacabb5aa8e67bee6def3b09Jim Grosbach (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4577d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "mla" || Mnemonic == "smlal" || 4578d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9Jim Grosbach Mnemonic == "umlal" || Mnemonic == "umull"))) { 4579eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = true; 4580fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 4581eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar CanAcceptCarrySet = false; 45823771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 4583eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4584eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4585eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4586eb9f3f91c03c29f020ee3c25cfefe7ae2b496526Daniel Dunbar Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4587ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4588ad2dad930d450d721209531175b0cbfdc8402558Jim Grosbach (Mnemonic == "clrex" && !isThumb()) || 45890780b6303b99441fef04340b7a083006484f4743Jim Grosbach (Mnemonic == "nop" && isThumbOne()) || 45902bd0118472de352745a2e038245fab4974f7c87eJim Grosbach ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 45912bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 45922bd0118472de352745a2e038245fab4974f7c87eJim Grosbach Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 45934af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 45944af54a461fad6c98df72dd18e607bfb32bfc486fJim Grosbach !isThumb()) || 45951ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 45963771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = false; 4597fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } else 45983771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar CanAcceptPredicationCode = true; 4599fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes 4600fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach if (isThumb()) { 4601fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 460263b46faeb8acae9b7e5f865b7417dc00b9b9dad3Jim Grosbach Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4603fa5bd27fbe5188ca708ac0dda4f32d90505da9f5Bruno Cardoso Lopes CanAcceptPredicationCode = false; 4604fb9cffea4a650d7f60d2c24741656c52c2185945Jim Grosbach } 4605badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar} 4606badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4607d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbachbool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4608d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 460920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // FIXME: This is all horribly hacky. We really need a better way to deal 461020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // with optional operands like this in the matcher table. 4611d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 4612d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4613d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // another does not. Specifically, the MOVW instruction does not. So we 4614d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // special case it here and remove the defaulted (non-setting) cc_out 4615d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // operand if that's the instruction we're trying to match. 4616d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // 4617d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // We do this as post-processing of the explicit operands rather than just 4618d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // conditionally adding the cc_out in the first place because we need 4619d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // to check the type of the parsed immediate operand. 46208adf62034a874adacff158e8adc9438cb3e67c01Owen Anderson if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4621d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4622d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4623d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4624d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return true; 46253912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 46263912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 46273912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach // when there are only two register operands. 46283912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 46293912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 46303912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 46313912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 46323912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach return true; 463372f39f8436848885176943b0ba985a7171145423Jim Grosbach // Register-register 'add' for thumb does not have a cc_out operand 463420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 463520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // have to check the immediate range here since Thumb2 has a variant 463620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // that can handle a different range and has a cc_out operand. 4637f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (((isThumb() && Mnemonic == "add") || 4638f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach (isThumbTwo() && Mnemonic == "sub")) && 4639f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 464072f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 464172f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 464272f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 464320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 464420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach (static_cast<ARMOperand*>(Operands[5])->isReg() || 464520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 464672f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 4647f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // For Thumb2, add/sub immediate does not have a cc_out operand for the 4648f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // imm0_4095 variant. That's the least-preferred variant when 464920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // selecting via the generic "add" mnemonic, so to know that we 465020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // should remove the cc_out operand, we have to explicitly check that 465120ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // it's not one of the other variants. Ugh. 4652f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4653f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Operands.size() == 6 && 465420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 465520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 465620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 465720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Nest conditions rather than one big 'if' statement for readability. 465820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // 465920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If either register is a high reg, it's either one of the SP 466020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // variants (handled above) or a 32-bit encoding, so we just 466112a8863828879168ffd634df09f3aa91b0b256eeJim Grosbach // check against T3. If the second register is the PC, this is an 466212a8863828879168ffd634df09f3aa91b0b256eeJim Grosbach // alternate form of ADR, which uses encoding T4, so check for that too. 466320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 466420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 466512a8863828879168ffd634df09f3aa91b0b256eeJim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 466620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 466720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 466820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // If both registers are low, we're in an IT block, and the immediate is 466920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // in range, we should use encoding T1 instead, which has a cc_out. 467020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (inITBlock() && 467164944f48a1164c02c15ca423a53919682a89074cJim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 467220ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 467320ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 467420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return false; 467520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 467620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // Otherwise, we use encoding T4, which does not have a cc_out 467720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // operand. 467820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach return true; 467920ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach } 468020ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 468164944f48a1164c02c15ca423a53919682a89074cJim Grosbach // The thumb2 multiply instruction doesn't have a CCOut register, so 468264944f48a1164c02c15ca423a53919682a89074cJim Grosbach // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 468364944f48a1164c02c15ca423a53919682a89074cJim Grosbach // use the 16-bit encoding or not. 468464944f48a1164c02c15ca423a53919682a89074cJim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 468564944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 468664944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 468764944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 468864944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->isReg() && 468964944f48a1164c02c15ca423a53919682a89074cJim Grosbach // If the registers aren't low regs, the destination reg isn't the 469064944f48a1164c02c15ca423a53919682a89074cJim Grosbach // same as one of the source regs, or the cc_out operand is zero 469164944f48a1164c02c15ca423a53919682a89074cJim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 469264944f48a1164c02c15ca423a53919682a89074cJim Grosbach // remove the cc_out operand. 469364944f48a1164c02c15ca423a53919682a89074cJim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 469464944f48a1164c02c15ca423a53919682a89074cJim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 46951de0bd194540f8bab399fb39c4ba615a7b2381d3Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 469664944f48a1164c02c15ca423a53919682a89074cJim Grosbach !inITBlock() || 469764944f48a1164c02c15ca423a53919682a89074cJim Grosbach (static_cast<ARMOperand*>(Operands[3])->getReg() != 469864944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[5])->getReg() && 469964944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() != 470064944f48a1164c02c15ca423a53919682a89074cJim Grosbach static_cast<ARMOperand*>(Operands[4])->getReg()))) 470164944f48a1164c02c15ca423a53919682a89074cJim Grosbach return true; 470264944f48a1164c02c15ca423a53919682a89074cJim Grosbach 47037f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // Also check the 'mul' syntax variant that doesn't specify an explicit 47047f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // destination register. 47057f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 47067f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 47077f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 47087f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 47097f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // If the registers aren't low regs or the cc_out operand is zero 47107f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // outside of an IT block, we have to use the 32-bit encoding, so 47117f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach // remove the cc_out operand. 47127f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 47137f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 47147f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach !inITBlock())) 47157f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach return true; 47167f1ec9570d673aedd13c5621407085400bab8299Jim Grosbach 471764944f48a1164c02c15ca423a53919682a89074cJim Grosbach 471820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach 4719f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // Register-register 'add/sub' for thumb does not have a cc_out operand 4720f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4721f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4722f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // right, this will result in better diagnostics (which operand is off) 4723f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach // anyway. 4724f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4725f69c80403620ef38674e037ae2664f1bbe5a4f3cJim Grosbach (Operands.size() == 5 || Operands.size() == 6) && 472672f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 472772f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 472872f39f8436848885176943b0ba985a7171145423Jim Grosbach static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 472972f39f8436848885176943b0ba985a7171145423Jim Grosbach return true; 47303912b73c74dc9c928228504e9a23c577b57c4e12Jim Grosbach 4731d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach return false; 4732d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach} 4733d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach 47347aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool isDataTypeToken(StringRef Tok) { 47357aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 47367aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 47377aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 47387aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 47397aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 47407aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach Tok == ".f" || Tok == ".d"; 47417aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 47427aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 47437aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// FIXME: This bit should probably be handled via an explicit match class 47447aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// in the .td files that matches the suffix instead of having it be 47457aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach// a literal string token the way it is now. 47467aef99b677452724100145c81f76f32e494cc5a7Jim Grosbachstatic bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 47477aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 47487aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach} 47497aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 475021d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbachstatic void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4751badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar/// Parse an arm instruction mnemonic followed by its operands. 4752badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbarbool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4753badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 475421d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // Apply mnemonic aliases before doing anything else, as the destination 475521d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // mnemnonic may include suffices and we want to handle them normally. 475621d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // The generic tblgen'erated code does this later, at the start of 475721d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // MatchInstructionImpl(), but that's too late for aliases that include 475821d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach // any sort of suffix. 475921d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach unsigned AvailableFeatures = getAvailableFeatures(); 476021d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach applyMnemonicAliases(Name, AvailableFeatures); 476121d7fb814adcedc7b2f156e003d2083ad1d8ac6aJim Grosbach 4762a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // First check for the ARM-specific .req directive. 4763a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().is(AsmToken::Identifier) && 4764a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.getTok().getIdentifier() == ".req") { 4765a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach parseDirectiveReq(Name, NameLoc); 4766a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // We always return 'error' for this, as we're done with this 4767a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // statement and don't need to match the 'instruction." 4768a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return true; 4769a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 4770a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 4771badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar // Create the leading tokens for the mnemonic, split by '.' characters. 4772badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar size_t Start = 0, Next = Name.find('.'); 4773ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach StringRef Mnemonic = Name.slice(Start, Next); 4774badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 4775352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar // Split out the predication code and carry setting flag from the mnemonic. 4776352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar unsigned PredicationCode; 4777a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned ProcessorIMod; 4778352e148cbe6498a6dd31b7fc71df7cd23c4b4d10Daniel Dunbar bool CarrySetting; 477989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach StringRef ITMask; 47801355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 478189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach ProcessorIMod, ITMask); 4782badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar 47830c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach // In Thumb1, only the branch (B) instruction can be predicated. 47840c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 47850c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach Parser.EatToEndOfStatement(); 47860c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach return Error(NameLoc, "conditional execution not supported in Thumb1"); 47870c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach } 47880c49ac05cd2374a99a3126ebe6c8370490a73ca5Jim Grosbach 4789ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4790ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 479189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // Handle the IT instruction ITMask. Convert it to a bitmask. This 479289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // is the mask as it will be for the IT encoding if the conditional 479389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 479489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // where the conditional bit0 is zero, the instruction post-processing 479589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // will adjust the mask accordingly. 479689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (Mnemonic == "it") { 4797f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4798f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITMask.size() > 3) { 4799f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Parser.EatToEndOfStatement(); 4800f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "too many conditions on IT instruction"); 4801f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 480289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = 8; 480389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = ITMask.size(); i != 0; --i) { 480489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach char pos = ITMask[i - 1]; 480589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (pos != 't' && pos != 'e') { 480689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Parser.EatToEndOfStatement(); 4807f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 480889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 480989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask >>= 1; 481089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if (ITMask[i - 1] == 't') 481189df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask |= 8; 481289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 4813f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 481489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 481589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach 4816ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // FIXME: This is all a pretty gross hack. We should automatically handle 4817ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach // optional operands like this via tblgen. 48189717fa9f29696bca45ddfdf206b1c382c8b40b78Bill Wendling 48193771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Next, add the CCOut and ConditionCode operands, if needed. 48203771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // 48213771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // For mnemonics which can ever incorporate a carry setting bit or predication 48223771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // code, our matching model involves us always generating CCOut and 48233771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // ConditionCode operands to match the mnemonic "as written" and then we let 48243771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // the matcher deal with finding the right instruction or generating an 48253771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // appropriate error. 48263771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar bool CanAcceptCarrySet, CanAcceptPredicationCode; 48271355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 48283771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 482933c16a27370939de39679245c3dff72383c210bdJim Grosbach // If we had a carry-set on an instruction that can't do that, issue an 483033c16a27370939de39679245c3dff72383c210bdJim Grosbach // error. 483133c16a27370939de39679245c3dff72383c210bdJim Grosbach if (!CanAcceptCarrySet && CarrySetting) { 483233c16a27370939de39679245c3dff72383c210bdJim Grosbach Parser.EatToEndOfStatement(); 4833ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 483433c16a27370939de39679245c3dff72383c210bdJim Grosbach "' can not set flags, but 's' suffix specified"); 483533c16a27370939de39679245c3dff72383c210bdJim Grosbach } 4836c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // If we had a predication code on an instruction that can't do that, issue an 4837c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach // error. 4838c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 4839c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach Parser.EatToEndOfStatement(); 4840c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach return Error(NameLoc, "instruction '" + Mnemonic + 4841c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach "' is not predicable, but condition code specified"); 4842c27d4f9ea0cb9064d3e2cadb384d73e95e9de449Jim Grosbach } 484333c16a27370939de39679245c3dff72383c210bdJim Grosbach 48443771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the carry setting operand, if necessary. 4845f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (CanAcceptCarrySet) { 4846f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 48473771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 4848f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Loc)); 4849f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 48503771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar 48513771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar // Add the predication code operand, if necessary. 48523771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar if (CanAcceptPredicationCode) { 4853f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 4854f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CarrySetting); 48553771dd041f6a68bef08b6f685a41d1d54f4e8b9dDaniel Dunbar Operands.push_back(ARMOperand::CreateCondCode( 4856f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::CondCodes(PredicationCode), Loc)); 4857badbd2fde9b8debd6265e8ece511fb01123d1d5fDaniel Dunbar } 4858345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar 4859a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes // Add the processor imod operand, if necessary. 4860a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (ProcessorIMod) { 4861a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes Operands.push_back(ARMOperand::CreateImm( 4862a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes MCConstantExpr::Create(ProcessorIMod, getContext()), 4863a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes NameLoc, NameLoc)); 4864a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes } 4865a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 4866345a9a6269318c96f333c0492b23733e29d952dfDaniel Dunbar // Add the remaining tokens in the mnemonic. 48675747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar while (Next != StringRef::npos) { 48685747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Start = Next; 48695747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar Next = Name.find('.', Start + 1); 4870a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes StringRef ExtraToken = Name.slice(Start, Next); 4871a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 48727aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // Some NEON instructions have an optional datatype suffix that is 48737aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach // completely ignored. Check for that. 48747aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach if (isDataTypeToken(ExtraToken) && 48757aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 48767aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach continue; 48777aef99b677452724100145c81f76f32e494cc5a7Jim Grosbach 487881d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach if (ExtraToken != ".n") { 487981d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 488081d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 488181d2e3901eed4bd70f551df8935c9ff224ccef6fJim Grosbach } 48825747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar } 48835747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar 48845747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar // Read the remaining operands. 48855747b13af801d5af7cd5827c07c6a59e981bdb1aDaniel Dunbar if (getLexer().isNot(AsmToken::EndOfStatement)) { 4886a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Read the first operand. 48871355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 4888cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4889cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 4890cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4891a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4892a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby while (getLexer().is(AsmToken::Comma)) { 4893b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); // Eat the comma. 4894a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby 4895a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby // Parse and remember the operand. 48961355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach if (parseOperand(Operands, Mnemonic)) { 4897cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4898cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner return true; 4899cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4900a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 4901a7ba3a81c008142a91d799e2ec3152cfd6bbb15fKevin Enderby } 490216c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 4903cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner if (getLexer().isNot(AsmToken::EndOfStatement)) { 4904186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach SMLoc Loc = getLexer().getLoc(); 4905cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner Parser.EatToEndOfStatement(); 4906186ffac4d35c9ea669b03ac75f5e21bff1f01a7fJim Grosbach return Error(Loc, "unexpected token in argument list"); 4907cbf8a98c7c652e96967623c80cb945fef001b090Chris Lattner } 4908146018fc6414eb2a1e67b2d8798a42a2f55ec96cBill Wendling 490934e53140c2cc02ce4c9d060e48302576d3962e1cChris Lattner Parser.Lex(); // Consume the EndOfStatement 4910ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 4911d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // Some instructions, mostly Thumb, have forms for the same mnemonic that 4912d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // do and don't have a cc_out optional-def operand. With some spot-checks 4913d54b4e612aa5d2d76a62f4409f82bd409f9af297Jim Grosbach // of the operand list, we can figure out which variant we're trying to 491420ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // parse and adjust accordingly before actually matching. We shouldn't ever 491520ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // try to remove a cc_out operand that was explicitly set on the the 491620ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // mnemonic, of course (CarrySetting == true). Reason number #317 the 491720ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach // table driven matcher doesn't fit well with the ARM instruction set. 491820ed2e7939d6a8e804a51897c3af4588deb48be2Jim Grosbach if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 4919ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4920ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach Operands.erase(Operands.begin() + 1); 4921ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach delete Op; 4922ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach } 4923ffa3225e26cc1977d20f0d9649fcd6f38a3c4815Jim Grosbach 4924cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // ARM mode 'blx' need special handling, as the register operand version 4925cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // is predicable, but the label operand version is not. So, we can't rely 4926cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach // on the Mnemonic based checking to correctly figure out when to put 492721ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // a k_CondCode operand in the list. If we're trying to match the label 492821ff17ce1b57ad68ae01d6eee0ecc36b5dd318cfJim Grosbach // version, remove the k_CondCode operand here. 4929cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 4930cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach static_cast<ARMOperand*>(Operands[2])->isImm()) { 4931cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4932cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach Operands.erase(Operands.begin() + 1); 4933cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach delete Op; 4934cf121c35c484ee17210fde1cecbd896348cd654aJim Grosbach } 4935857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach 4936857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // The vector-compare-to-zero instructions have a literal token "#0" at 4937857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // the end that comes to here as an immediate operand. Convert it to a 4938857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach // token to play nicely with the matcher. 4939857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 4940857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 4941857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 4942857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4943857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4944857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach if (CE && CE->getValue() == 0) { 4945857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.erase(Operands.begin() + 5); 4946857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 494768259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach delete Op; 494868259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 494968259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach } 495068259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach // VCMP{E} does the same thing, but with a different operand count. 495168259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 495268259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isImm()) { 495368259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 495468259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 495568259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach if (CE && CE->getValue() == 0) { 495668259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.erase(Operands.begin() + 4); 495768259145d9ac1f8d4e2cc9fc73626254fcc5cf08Jim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4958857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach delete Op; 4959857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 4960857e1a7b3fcc848a6508f9205f22e8e0d293dcaeJim Grosbach } 4961934755ac040c516eac7fdd974e87590543acd16aJim Grosbach // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 496255b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // end. Convert it to a token here. Take care not to convert those 496355b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach // that should hit the Thumb2 encoding. 4964934755ac040c516eac7fdd974e87590543acd16aJim Grosbach if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 496555b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[3])->isReg() && 496655b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach static_cast<ARMOperand*>(Operands[4])->isReg() && 4967934755ac040c516eac7fdd974e87590543acd16aJim Grosbach static_cast<ARMOperand*>(Operands[5])->isImm()) { 4968934755ac040c516eac7fdd974e87590543acd16aJim Grosbach ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4969934755ac040c516eac7fdd974e87590543acd16aJim Grosbach const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 497055b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach if (CE && CE->getValue() == 0 && 497155b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isThumbOne() || 4972d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // The cc_out operand matches the IT block. 4973d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach ((inITBlock() != CarrySetting) && 4974d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach // Neither register operand is a high register. 497555b02f28c1a2960ebb88cf5019cc5b36bb2eabf4Jim Grosbach (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4976d7ea73a4909fc3200a1cecd2b420d7ace2180b70Jim Grosbach isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 4977934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.erase(Operands.begin() + 5); 4978934755ac040c516eac7fdd974e87590543acd16aJim Grosbach Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4979934755ac040c516eac7fdd974e87590543acd16aJim Grosbach delete Op; 4980934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 4981934755ac040c516eac7fdd974e87590543acd16aJim Grosbach } 4982934755ac040c516eac7fdd974e87590543acd16aJim Grosbach 49839898671a74d3fc924347e679c45edaa685b3fe6eChris Lattner return false; 4984ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 4985ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 4986189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// Validate context-sensitive operand constraints. 4987aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 4988aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// return 'true' if register list contains non-low GPR registers, 4989aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'false' otherwise. If Reg is in the register list or is HiReg, set 4990aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach// 'containsReg' to true. 4991aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbachstatic bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 4992aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned HiReg, bool &containsReg) { 4993aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = false; 4994aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 4995aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 4996aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (OpReg == Reg) 4997aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach containsReg = true; 4998aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach // Anything other than a low register isn't legal here. 4999aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5000aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return true; 5001aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach } 5002aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return false; 5003aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach} 5004aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach 500576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// Check if the specified regisgter is in the register list of the inst, 500676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach// starting at the indicated operand number. 500776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbachstatic bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 500876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 500976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned OpReg = Inst.getOperand(i).getReg(); 501076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (OpReg == Reg) 501176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return true; 501276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 501376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return false; 501476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach} 501576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach 5016f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5017f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// the ARMInsts array) instead. Getting that here requires awkward 5018f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach// API changes, though. Better way? 5019f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbachnamespace llvm { 50201a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerextern const MCInstrDesc ARMInsts[]; 5021f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 50221a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramerstatic const MCInstrDesc &getInstDesc(unsigned Opcode) { 5023f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return ARMInsts[Opcode]; 5024f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach} 5025f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 5026189610f9466686a91fb7d847b572e1645c785323Jim Grosbach// FIXME: We would really like to be able to tablegen'erate this. 5027189610f9466686a91fb7d847b572e1645c785323Jim Grosbachbool ARMAsmParser:: 5028189610f9466686a91fb7d847b572e1645c785323Jim GrosbachvalidateInstruction(MCInst &Inst, 5029189610f9466686a91fb7d847b572e1645c785323Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 50301a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5031f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc Loc = Operands[0]->getStartLoc(); 5032f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Check the IT block state first. 5033b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // NOTE: In Thumb mode, the BKPT instruction has the interesting property of 5034b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // being allowed in IT blocks, but not being predicable. It just always 5035b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson // executes. 5036b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1Owen Anderson if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { 5037f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned bit = 1; 5038f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (ITState.FirstCond) 5039f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = false; 5040f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach else 5041a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5042f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // The instruction must be predicable. 5043f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (!MCID.isPredicable()) 5044f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "instructions in IT block must be predicable"); 5045f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5046f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned ITCond = bit ? ITState.Cond : 5047f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCC::getOppositeCondition(ITState.Cond); 5048f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (Cond != ITCond) { 5049f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Find the condition code Operand to get its SMLoc information. 5050f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach SMLoc CondLoc; 5051f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach for (unsigned i = 1; i < Operands.size(); ++i) 5052f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5053f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach CondLoc = Operands[i]->getStartLoc(); 5054f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(CondLoc, "incorrect condition in IT block; got '" + 5055f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5056f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach "', but expected '" + 5057f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5058f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 5059c9a9b442853ee086492d6ad1384a2de2fea9b43bJim Grosbach // Check for non-'al' condition codes outside of the IT block. 5060f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } else if (isThumbTwo() && MCID.isPredicable() && 5061f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 506251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson ARMCC::AL && Inst.getOpcode() != ARM::tB && 506351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.getOpcode() != ARM::t2B) 5064f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(Loc, "predicated instructions must be in IT block"); 5065f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 5066189610f9466686a91fb7d847b572e1645c785323Jim Grosbach switch (Inst.getOpcode()) { 50672fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD: 50682fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_PRE: 50692fd2b87ded53f6b87eb240c17d62a23fb4964ba0Jim Grosbach case ARM::LDRD_POST: 5070189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::LDREXD: { 5071189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5072189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5073189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5074189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 5075189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return Error(Operands[3]->getStartLoc(), 5076189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "destination operands must be sequential"); 5077189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5078189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 507914605d1a679d55ff25875656e100ff455194ee17Jim Grosbach case ARM::STRD: { 508014605d1a679d55ff25875656e100ff455194ee17Jim Grosbach // Rt2 must be Rt + 1. 508114605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 508214605d1a679d55ff25875656e100ff455194ee17Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 508314605d1a679d55ff25875656e100ff455194ee17Jim Grosbach if (Rt2 != Rt + 1) 508414605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 508514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach "source operands must be sequential"); 508614605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return false; 508714605d1a679d55ff25875656e100ff455194ee17Jim Grosbach } 508853642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_PRE: 508953642c533564c41d9a85ad28efe19b12fc2305ceJim Grosbach case ARM::STRD_POST: 5090189610f9466686a91fb7d847b572e1645c785323Jim Grosbach case ARM::STREXD: { 5091189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Rt2 must be Rt + 1. 5092189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5093189610f9466686a91fb7d847b572e1645c785323Jim Grosbach unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 5094189610f9466686a91fb7d847b572e1645c785323Jim Grosbach if (Rt2 != Rt + 1) 509514605d1a679d55ff25875656e100ff455194ee17Jim Grosbach return Error(Operands[3]->getStartLoc(), 5096189610f9466686a91fb7d847b572e1645c785323Jim Grosbach "source operands must be sequential"); 5097189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5098189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5099fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::SBFX: 5100fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach case ARM::UBFX: { 5101fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach // width must be in range [1, 32-lsb] 5102fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned lsb = Inst.getOperand(2).getImm(); 5103fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach unsigned widthm1 = Inst.getOperand(3).getImm(); 5104fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach if (widthm1 >= 32 - lsb) 5105fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach return Error(Operands[5]->getStartLoc(), 5106fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach "bitfield width must be in range [1,32-lsb]"); 510700c9a518886c4f2d1cd869c174c994c20a353906Jim Grosbach return false; 5108fb8989e64024547e4ad5ab6fe4d94fe146a7899fJim Grosbach } 510993b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach case ARM::tLDMIA: { 511076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're parsing Thumb2, the .w variant is available and handles 511176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // most cases that are normally illegal for a Thumb1 LDM 511276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instruction. We'll make the transformation in processInstruction() 511376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // if necessary. 511476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 511593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // Thumb LDM instructions are writeback iff the base register is not 511693b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // in the register list. 511793b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 51187260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach bool hasWritebackToken = 51197260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 51207260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5121aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 512276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5123aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5124aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7"); 512593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach // If we should have writeback, then there should be a '!' token. 512676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 512793b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach return Error(Operands[2]->getStartLoc(), 512893b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach "writeback operator '!' expected"); 512976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we should not have writeback, there must not be a '!'. This is 513076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // true even for the 32-bit wide encodings. 5131aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach if (listContainsBase && hasWritebackToken) 51327260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach return Error(Operands[3]->getStartLoc(), 51337260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "writeback operator '!' not allowed when base register " 51347260c6a4ea19f5eb94068296c1c8e01a99f17a01Jim Grosbach "in register list"); 513593b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach 513693b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach break; 513793b3eff62322803a520e183fdc294bffd6d99bfaJim Grosbach } 513876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::t2LDMIA_UPD: { 513976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 514076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach return Error(Operands[4]->getStartLoc(), 514176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "writeback operator '!' not allowed when base register " 514276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach "in register list"); 514376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 514476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 51455402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 51465402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // so only issue a diagnostic for thumb1. The instructions will be 51475402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // switched to the t2 encodings in processInstruction() if necessary. 51486dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPOP: { 5149aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 51505402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 51515402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5152aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5153aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or pc"); 51546dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 51556dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 51566dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach case ARM::tPUSH: { 5157aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach bool listContainsBase; 51585402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 51595402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach !isThumbTwo()) 5160aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach return Error(Operands[2]->getStartLoc(), 5161aa875f8c6fdf3a7a26ccc381cf8ecd2b69678dadJim Grosbach "registers must be in range r0-r7 or lr"); 51626dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach break; 51636dcafc0d0b33bebcac28539257a9a5b250542f6aJim Grosbach } 51641e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach case ARM::tSTMIA_UPD: { 51651e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach bool listContainsBase; 51668213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 51671e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach return Error(Operands[4]->getStartLoc(), 51681e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach "registers must be in range r0-r7"); 51691e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach break; 51701e84f19337d44c04e74af4fb005550b525ef60e5Jim Grosbach } 5171189610f9466686a91fb7d847b572e1645c785323Jim Grosbach } 5172189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 5173189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return false; 5174189610f9466686a91fb7d847b572e1645c785323Jim Grosbach} 5175189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 5176d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbachstatic unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 517784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach switch(Opc) { 517884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach default: assert(0 && "unexpected opcode!"); 51799b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST1LN 51808b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: 51815b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8_UPD; 51838b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_16: 51845b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51859b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16_UPD; 51868b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: 51875b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32_UPD; 51898b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_8: 51905b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8_UPD; 51928b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_16: 51935b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16_UPD; 51958b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_32: 51965b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 51979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32_UPD; 51988b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_8: 51995b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd8; 52018b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_16: 52025b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd16; 52048b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_32: 52055b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52069b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST1LNd32; 52079b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 52089b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VST2LN 52098b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: 52105b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52119b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8_UPD; 52128b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_16: 52135b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52149b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16_UPD; 52158b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: 52165b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52179b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32_UPD; 52188b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: 52195b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52205b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16_UPD; 52218b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_fixed_Asm_32: 52225b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52235b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32_UPD; 52245b484312c66f8d125c072517947538f301c5a805Jim Grosbach 52258b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_8: 52265b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52279b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8_UPD; 52288b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_16: 52295b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16_UPD; 52318b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_32: 52325b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32_UPD; 52348b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_register_Asm_16: 52355b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52365b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16_UPD; 52378b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_register_Asm_32: 52385b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52395b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32_UPD; 52405b484312c66f8d125c072517947538f301c5a805Jim Grosbach 52418b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_8: 52425b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd8; 52448b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_16: 52455b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd16; 52478b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_32: 52485b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 1; 52499b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VST2LNd32; 52508b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqAsm_16: 52515b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52525b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq16; 52538b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqAsm_32: 52545b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing = 2; 52555b484312c66f8d125c072517947538f301c5a805Jim Grosbach return ARM::VST2LNq32; 5256d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 5257d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach // VST3 5258d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_8: 5259d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5260d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d8_UPD; 5261d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_16: 5262d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5263d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d16_UPD; 5264d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_32: 5265d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5266d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d32_UPD; 5267d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_8: 5268d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5269d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q8_UPD; 5270d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_16: 5271d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5272d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q16_UPD; 5273d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_32: 5274d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5275d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q32_UPD; 5276d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_8: 5277d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5278d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d8_UPD; 5279d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_16: 5280d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5281d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d16_UPD; 5282d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_32: 5283d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5284d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d32_UPD; 5285d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_8: 5286d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5287d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q8_UPD; 5288d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_16: 5289d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5290d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q16_UPD; 5291d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_32: 5292d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5293d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q32_UPD; 5294d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_8: 5295d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5296d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d8; 5297d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_16: 5298d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5299d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d16; 5300d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_32: 5301d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 1; 5302d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3d32; 5303d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_8: 5304d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5305d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q8; 5306d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_16: 5307d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5308d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q16; 5309d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_32: 5310d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing = 2; 5311d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return ARM::VST3q32; 531284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 531384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach} 531484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach 5315d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbachstatic unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 53167636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach switch(Opc) { 53177636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach default: assert(0 && "unexpected opcode!"); 53189b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD1LN 53198b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: 532095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53219b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8_UPD; 53228b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_16: 532395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53249b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16_UPD; 53258b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: 532695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53279b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32_UPD; 53288b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_8: 532995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8_UPD; 53318b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_16: 533295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16_UPD; 53348b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_32: 533595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53369b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32_UPD; 53378b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_8: 533895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd8; 53408b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_16: 534195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd16; 53438b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_32: 534495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD1LNd32; 53469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 53479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // VLD2LN 53488b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: 534995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8_UPD; 53518b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_16: 535295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16_UPD; 53548b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: 535595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32_UPD; 53578b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: 535895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 535995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16_UPD; 53608b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_32: 536195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 536295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32_UPD; 53638b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_8: 536495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53659b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8_UPD; 53668b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_16: 536795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16_UPD; 53698b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_32: 537095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32_UPD; 53728b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_register_Asm_16: 537395fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 537495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16_UPD; 53758b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_register_Asm_32: 537695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 537795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32_UPD; 53788b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_8: 537995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd8; 53818b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_16: 538295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd16; 53848b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_32: 538595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 1; 53869b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return ARM::VLD2LNd32; 53878b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqAsm_16: 538895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 538995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq16; 53908b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqAsm_32: 539195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing = 2; 539295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach return ARM::VLD2LNq32; 53933a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 53943a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // VLD3LN 53953a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_8: 53963a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 53973a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd8_UPD; 53983a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_16: 53993a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54003a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd16_UPD; 54013a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_32: 54023a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54033a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd32_UPD; 54043a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_fixed_Asm_16: 54053a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54063a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNq16_UPD; 54073a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_fixed_Asm_32: 54083a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 2; 54093a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNq32_UPD; 54103a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_8: 54113a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54123a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd8_UPD; 54133a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_16: 54143a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54153a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd16_UPD; 54163a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_32: 54173a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54183a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd32_UPD; 54193a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_register_Asm_16: 54203a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 2; 54213a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNq16_UPD; 54223a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_register_Asm_32: 54233a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 2; 54243a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNq32_UPD; 54253a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_8: 54263a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54273a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd8; 54283a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_16: 54293a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54303a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd16; 54313a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_32: 54323a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 1; 54333a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNd32; 54343a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqAsm_16: 54353a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 2; 54363a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNq16; 54373a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqAsm_32: 54383a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing = 2; 54393a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return ARM::VLD3LNq32; 5440c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 5441c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach // VLD3 5442c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_8: 5443c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5444c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d8_UPD; 5445c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_16: 5446c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5447c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d16_UPD; 5448c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_32: 5449c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5450c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d32_UPD; 5451c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_8: 5452c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5453c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q8_UPD; 5454c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_16: 5455c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5456c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q16_UPD; 5457c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_32: 5458c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5459c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q32_UPD; 5460c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_8: 5461c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5462c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d8_UPD; 5463c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_16: 5464c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5465c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d16_UPD; 5466c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_32: 5467c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5468c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d32_UPD; 5469c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_8: 5470c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5471c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q8_UPD; 5472c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_16: 5473c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5474c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q16_UPD; 5475c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_32: 5476c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5477c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q32_UPD; 5478c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_8: 5479c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5480c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d8; 5481c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_16: 5482c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5483c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d16; 5484c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_32: 5485c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 1; 5486c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3d32; 5487c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_8: 5488c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5489c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q8; 5490c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_16: 5491c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5492c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q16; 5493c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_32: 5494c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing = 2; 5495c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return ARM::VLD3q32; 54967636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 54977636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach} 54987636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach 549983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbachbool ARMAsmParser:: 5500f8fce711e8b756adca63044f7d122648c960ab96Jim GrosbachprocessInstruction(MCInst &Inst, 5501f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5502f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach switch (Inst.getOpcode()) { 55030b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach // Aliases for alternate PC+imm syntax of LDR instructions. 55040b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRpcrel: 55050b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRpci); 55060b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 55070b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRBpcrel: 55080b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRBpci); 55090b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 55100b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRHpcrel: 55110b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRHpci); 55120b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 55130b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRSBpcrel: 55140b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRSBpci); 55150b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 55160b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach case ARM::t2LDRSHpcrel: 55170b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach Inst.setOpcode(ARM::t2LDRSHpci); 55180b4c6738868e11ba06047a406f79489cb1db8c5aJim Grosbach return true; 55199b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VST complex aliases. 55208b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_8: 55218b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_16: 55228b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_register_Asm_32: { 552384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 552484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 552584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 55265b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5527d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 552884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 552984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 553084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 553184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 553284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 553384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 553484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 553584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 553684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 553784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 553884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 55399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 55408b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_8: 55418b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_16: 55428b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_register_Asm_32: 55438b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_register_Asm_16: 55448b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_register_Asm_32: { 55459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 55469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 55479b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 55485b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5549d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 55509b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 55519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 55529b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 55539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 55549b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 55555b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 55565b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 55579b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 55589b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 55599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 55609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 55619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 55629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 55638b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_8: 55648b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_16: 55658b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdWB_fixed_Asm_32: { 556684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 556784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 556884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 55695b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5570d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 557184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 557284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 557384defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 557484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 557584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 557684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 557784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 557884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 557984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 558084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 558184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 55829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 55838b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_8: 55848b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_16: 55858b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdWB_fixed_Asm_32: 55868b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_fixed_Asm_16: 55878b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqWB_fixed_Asm_32: { 55889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 55899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 55909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 55915b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5592d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 55939b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 55949b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 55959b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 55969b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 55979b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 55985b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 55995b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 56009b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 56019b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 56029b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 56039b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 56049b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 56059b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 56068b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_8: 56078b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_16: 56088b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST1LNdAsm_32: { 560984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach MCInst TmpInst; 561084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // Shuffle the operands around so the lane index operand is in the 561184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach // right place. 56125b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5613d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 561484defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 561584defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 561684defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 561784defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 561884defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 561984defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 562084defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach Inst = TmpInst; 562184defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach return true; 562284defb51ca183d136e08e87d95e2c907654405f9Jim Grosbach } 56239b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 56248b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_8: 56258b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_16: 56268b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNdAsm_32: 56278b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqAsm_16: 56288b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VST2LNqAsm_32: { 56299b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 56309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56319b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 56325b484312c66f8d125c072517947538f301c5a805Jim Grosbach unsigned Spacing; 5633d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 56349b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56359b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 56369b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 56375b484312c66f8d125c072517947538f301c5a805Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 56385b484312c66f8d125c072517947538f301c5a805Jim Grosbach Spacing)); 56399b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 56409b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 56419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 56429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 56439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 56449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 56459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Handle NEON VLD complex aliases. 56468b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_8: 56478b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_16: 56488b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_register_Asm_32: { 5649872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 5650872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 5651872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 565295fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5653d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5654872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5655872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5656872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 5657872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 5658872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 5659872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5660872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 5661872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5662872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 5663872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 5664872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 5665872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 56669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 56678b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_8: 56688b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_16: 56698b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_register_Asm_32: 56708b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_register_Asm_16: 56718b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_register_Asm_32: { 56729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 56739b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 56749b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 567595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5676d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 56779b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 567895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 567995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56809b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 56819b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 56829b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 56839b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 56849b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 568595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 568695fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 56879b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 56889b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 56899b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 56909b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 56919b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 56929b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 56939b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 56943a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_8: 56953a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_16: 56963a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_register_Asm_32: 56973a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_register_Asm_16: 56983a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_register_Asm_32: { 56993a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach MCInst TmpInst; 57003a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // Shuffle the operands around so the lane index operand is in the 57013a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // right place. 57023a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach unsigned Spacing; 5703d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 57043a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 57053a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 57063a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 57073a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5708c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 57093a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 57103a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57113a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57123a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rm 57133a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 57143a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 57153a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 57163a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5717c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 57183a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57193a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // CondCode 57203a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 57213a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Inst = TmpInst; 57223a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return true; 57233a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 57243a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 57258b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_8: 57268b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_16: 57278b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdWB_fixed_Asm_32: { 5728872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach MCInst TmpInst; 5729872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // Shuffle the operands around so the lane index operand is in the 5730872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach // right place. 573195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5732d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5733872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5734872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5735872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 5736872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 5737872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5738872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5739872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 5740872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5741872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 5742872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach Inst = TmpInst; 5743872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach return true; 5744872eedbb3a46618e333db42ee9c41fda34eb1e9bJim Grosbach } 57459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 57468b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_8: 57478b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_16: 57488b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdWB_fixed_Asm_32: 57498b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_16: 57508b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqWB_fixed_Asm_32: { 57519b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 57529b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 57539b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 575495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5755d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 57569b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 575795fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 575895fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57599b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 57609b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57619b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57629b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 57639b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 576495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 576595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 57669b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57679b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57689b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 57699b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 57709b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 57719b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 57729b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 57733a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_8: 57743a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_16: 57753a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdWB_fixed_Asm_32: 57763a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_fixed_Asm_16: 57773a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqWB_fixed_Asm_32: { 57783a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach MCInst TmpInst; 57793a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // Shuffle the operands around so the lane index operand is in the 57803a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // right place. 57813a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach unsigned Spacing; 5782d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 57833a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 57843a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 57853a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 57863a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5787c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 57883a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 57893a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 57903a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 57913a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 57923a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 57933a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 57943a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 57953a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5796c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 57973a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 57983a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 57993a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 58003a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Inst = TmpInst; 58013a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return true; 58023a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 58033a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 58048b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_8: 58058b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_16: 58068b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD1LNdAsm_32: { 58077636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach MCInst TmpInst; 58087636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // Shuffle the operands around so the lane index operand is in the 58097636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach // right place. 581095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5811d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 58127636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 58137636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 58147636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 58157636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 58167636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 58177636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 58187636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 58197636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach Inst = TmpInst; 58207636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach return true; 58217636bf6530fd83bf7356ae3894246a4e558741a4Jim Grosbach } 58229b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach 58238b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_8: 58248b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_16: 58258b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNdAsm_32: 58268b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqAsm_16: 58278b31f95bdde1e3809a1c9fdb6926b1840effcf9cJim Grosbach case ARM::VLD2LNqAsm_32: { 58289b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach MCInst TmpInst; 58299b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // Shuffle the operands around so the lane index operand is in the 58309b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach // right place. 583195fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach unsigned Spacing; 5832d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 58339b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 583495fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 583595fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 58369b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 58379b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 58389b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 583995fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 584095fad1c6034cdf8010428e61b71cd196ee1698adJim Grosbach Spacing)); 58419b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 58429b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 58439b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 58449b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach Inst = TmpInst; 58459b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach return true; 58469b1b3902882675e5ce35eacd639456bd648324b7Jim Grosbach } 58473a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 58483a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_8: 58493a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_16: 58503a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNdAsm_32: 58513a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqAsm_16: 58523a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach case ARM::VLD3LNqAsm_32: { 58533a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach MCInst TmpInst; 58543a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // Shuffle the operands around so the lane index operand is in the 58553a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach // right place. 58563a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach unsigned Spacing; 5857d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 58583a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 58593a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 58603a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 58613a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5862c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 58633a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rn 58643a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // alignment 58653a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 58663a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 58673a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Spacing)); 58683a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5869c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 58703a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // lane 58713a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 58723a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 58733a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach Inst = TmpInst; 58743a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach return true; 58753a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach } 58763a678af71dec76a7e1474ad85a99b3588516906dJim Grosbach 5877c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach // VLD3 multiple 3-element structure instructions. 5878c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_8: 5879c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_16: 5880c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dAsm_32: 5881c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_8: 5882c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_16: 5883c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qAsm_32: { 5884c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach MCInst TmpInst; 5885c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach unsigned Spacing; 5886d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5887c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5888c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5889c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing)); 5890c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5891c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 5892c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5893c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 5894c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5895c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 5896c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Inst = TmpInst; 5897c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return true; 5898c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 5899c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 5900c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_8: 5901c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_16: 5902c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_fixed_Asm_32: 5903c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_8: 5904c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_16: 5905c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_fixed_Asm_32: { 5906c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach MCInst TmpInst; 5907c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach unsigned Spacing; 5908d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5909c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5910c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5911c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing)); 5912c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5913c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 5914c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5915c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 5916c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 5917c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5918c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5919c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 5920c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Inst = TmpInst; 5921c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return true; 5922c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 5923c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 5924c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_8: 5925c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_16: 5926c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3dWB_register_Asm_32: 5927c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_8: 5928c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_16: 5929c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach case ARM::VLD3qWB_register_Asm_32: { 5930c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach MCInst TmpInst; 5931c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach unsigned Spacing; 5932d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5933d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5934d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5935d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing)); 5936d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5937d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing * 2)); 5938d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5939d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 5940d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 5941d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 5942d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5943d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 5944d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Inst = TmpInst; 5945d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return true; 5946d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach } 5947d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 5948d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach // VST3 multiple 3-element structure instructions. 5949d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_8: 5950d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_16: 5951d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dAsm_32: 5952d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_8: 5953d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_16: 5954d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qAsm_32: { 5955d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach MCInst TmpInst; 5956d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach unsigned Spacing; 5957d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5958d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5959d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 5960d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5961d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5962d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing)); 5963d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5964d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing * 2)); 5965d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5966d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 5967d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Inst = TmpInst; 5968d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return true; 5969d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach } 5970d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 5971d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_8: 5972d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_16: 5973d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_fixed_Asm_32: 5974d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_8: 5975d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_16: 5976d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_fixed_Asm_32: { 5977d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach MCInst TmpInst; 5978d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach unsigned Spacing; 5979d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5980d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 5981d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 5982d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 5983d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5984c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 5985c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5986c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing)); 5987c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5988c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Spacing * 2)); 5989d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5990d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 5991d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Inst = TmpInst; 5992d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach return true; 5993d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach } 5994d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach 5995d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_8: 5996d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_16: 5997d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3dWB_register_Asm_32: 5998d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_8: 5999d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_16: 6000d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach case ARM::VST3qWB_register_Asm_32: { 6001d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach MCInst TmpInst; 6002d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach unsigned Spacing; 6003d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6004c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6005c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6006c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // alignment 6007c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // Rm 6008d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Vd 6009d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6010d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing)); 6011d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6012d7433e2873706265d545edc5cdd0a728dd71ef66Jim Grosbach Spacing * 2)); 6013c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6014c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 6015c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach Inst = TmpInst; 6016c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach return true; 6017c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach } 6018c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach 6019863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the Thumb2 mode MOV complex aliases. 60202cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVsr: 60212cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM::t2MOVSsr: { 60222cc5cda464e7c936215281934193658cb799c603Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 60232cc5cda464e7c936215281934193658cb799c603Jim Grosbach // whether we're in an IT block if the register operands are low 60242cc5cda464e7c936215281934193658cb799c603Jim Grosbach // registers. 60252cc5cda464e7c936215281934193658cb799c603Jim Grosbach bool isNarrow = false; 60262cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 60272cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 60282cc5cda464e7c936215281934193658cb799c603Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg()) && 60292cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 60302cc5cda464e7c936215281934193658cb799c603Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 60312cc5cda464e7c936215281934193658cb799c603Jim Grosbach isNarrow = true; 60322cc5cda464e7c936215281934193658cb799c603Jim Grosbach MCInst TmpInst; 60332cc5cda464e7c936215281934193658cb799c603Jim Grosbach unsigned newOpc; 60342cc5cda464e7c936215281934193658cb799c603Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 60352cc5cda464e7c936215281934193658cb799c603Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 60362cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 60372cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 60382cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 60392cc5cda464e7c936215281934193658cb799c603Jim Grosbach case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 60402cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 60412cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.setOpcode(newOpc); 60422cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 60432cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (isNarrow) 60442cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 60452cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 60462cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 60472cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 60482cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // CondCode 60492cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 60502cc5cda464e7c936215281934193658cb799c603Jim Grosbach if (!isNarrow) 60512cc5cda464e7c936215281934193658cb799c603Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 60522cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 60532cc5cda464e7c936215281934193658cb799c603Jim Grosbach Inst = TmpInst; 60542cc5cda464e7c936215281934193658cb799c603Jim Grosbach return true; 60552cc5cda464e7c936215281934193658cb799c603Jim Grosbach } 6056863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVsi: 6057863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM::t2MOVSsi: { 6058863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Which instruction to expand to depends on the CCOut operand and 6059863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // whether we're in an IT block if the register operands are low 6060863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // registers. 6061863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach bool isNarrow = false; 6062863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6063863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6064863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 6065863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach isNarrow = true; 6066863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach MCInst TmpInst; 6067863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach unsigned newOpc; 6068863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 6069863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 6070863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 6071863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 6072863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 6073863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 6074520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 6075863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 6076863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 6077863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (Ammount == 32) Ammount = 0; 6078863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.setOpcode(newOpc); 6079863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 6080863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (isNarrow) 6081863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 6082863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6083863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6084520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach if (newOpc != ARM::t2RRX) 6085520dc78d92a47af5e644b09f401d278cb1d5d196Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Ammount)); 6086863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6087863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6088863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach if (!isNarrow) 6089863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg( 6090863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6091863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach Inst = TmpInst; 6092863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach return true; 6093863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach } 6094863d2af9477e331955a9bee8be1969ce658b59b5Jim Grosbach // Handle the ARM mode MOV complex aliases. 609523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: 609623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: 609723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: 609823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: { 609923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 610023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach switch(Inst.getOpcode()) { 610123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 610223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 610323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 610423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 610523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach case ARM::RORr: ShiftTy = ARM_AM::ror; break; 610623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 610723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 610823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach MCInst TmpInst; 610923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.setOpcode(ARM::MOVsr); 611023f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 611123f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 611223f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // Rm 611323f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 611423f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 611523f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 611623f220705a74685edd743e84861a3e0d6d109828Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 611723f220705a74685edd743e84861a3e0d6d109828Jim Grosbach Inst = TmpInst; 611823f220705a74685edd743e84861a3e0d6d109828Jim Grosbach return true; 611923f220705a74685edd743e84861a3e0d6d109828Jim Grosbach } 6120ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: 6121ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: 6122ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: 6123ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: { 6124ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach ARM_AM::ShiftOpc ShiftTy; 6125ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach switch(Inst.getOpcode()) { 6126ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach default: llvm_unreachable("unexpected opcode!"); 6127ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 6128ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 6129ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 6130ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach case ARM::RORi: ShiftTy = ARM_AM::ror; break; 6131ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach } 6132ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach // A shift by zero is a plain MOVr, not a MOVsi. 613348b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Amt = Inst.getOperand(2).getImm(); 6134ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6135ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 613671810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach MCInst TmpInst; 6137ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.setOpcode(Opc); 613871810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 613971810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6140ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach if (Opc == ARM::MOVsi) 6141ee10ff89a2934636570cb17b756bf31b2a38aab5Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 614271810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); // CondCode 614371810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 614471810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); // cc_out 614571810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach Inst = TmpInst; 614683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 614771810ab7c0ecd6927dde1eee0c73169642f3764dJim Grosbach } 614848b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach case ARM::RRXi: { 614948b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 615048b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach MCInst TmpInst; 615148b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.setOpcode(ARM::MOVsi); 615248b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rd 615348b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 615448b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 615548b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 615648b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 615748b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // cc_out 615848b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach Inst = TmpInst; 615948b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach return true; 616048b368bcd5fd6d1857de137230ac019b8530f1cdJim Grosbach } 61610352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2LDMIA_UPD: { 61620352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a load of a single register, then we should use 61630352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 61640352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 61650352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 61660352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 61670352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2LDR_POST); 61680352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 61690352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 61700352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 61710352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 61720352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 61730352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 61740352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 61750352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 61760352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 61770352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach case ARM::t2STMDB_UPD: { 61780352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // If this is a store of a single register, then we should use 61790352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 61800352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach if (Inst.getNumOperands() != 5) 61810352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return false; 61820352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach MCInst TmpInst; 61830352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.setOpcode(ARM::t2STR_PRE); 61840352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 61850352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 61860352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 61870352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 61880352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 61890352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 61900352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach Inst = TmpInst; 61910352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach return true; 61920352b4679e9289ded6b2d73a76a017e0d97fe70dJim Grosbach } 6193f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach case ARM::LDMIA_UPD: 6194f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // If this is a load of a single register via a 'pop', then we should use 6195f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // a post-indexed LDR instruction instead, per the ARM ARM. 6196f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 6197f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst.getNumOperands() == 5) { 6198f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach MCInst TmpInst; 6199f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.setOpcode(ARM::LDR_POST_IMM); 6200f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 6201f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6202f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // Rn 6203f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 6204f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(MCOperand::CreateImm(4)); 6205f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6206f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6207f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach Inst = TmpInst; 620883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 6209f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 6210f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach break; 6211f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach case ARM::STMDB_UPD: 6212f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // If this is a store of a single register via a 'push', then we should use 6213f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach // a pre-indexed STR instruction instead, per the ARM ARM. 6214f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 6215f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst.getNumOperands() == 5) { 6216f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach MCInst TmpInst; 6217f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.setOpcode(ARM::STR_PRE_IMM); 6218f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6219f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); // Rt 6220f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 6221f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(MCOperand::CreateImm(-4)); 6222f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6223f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6224f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach Inst = TmpInst; 6225f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach } 6226f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach break; 6227da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2ADDri12: 6228da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 6229da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "addw"), encoding T3 is preferred. 6230da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 6231da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6232da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 6233da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2ADDri); 6234da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 6235da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 6236da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach case ARM::t2SUBri12: 6237da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 6238da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach // mnemonic was used (not "subw"), encoding T3 is preferred. 6239da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 6240da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6241da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 6242da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.setOpcode(ARM::t2SUBri); 6243da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 6244da84786bee8304588a4325b15e297be1995a5d41Jim Grosbach break; 624589e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach case ARM::tADDi8: 62460f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 62470f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 62480f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 62490f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77Jim Grosbach // to encoding T1 if <Rd> is omitted." 625083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 625189e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach Inst.setOpcode(ARM::tADDi3); 625283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 625383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 625489e2aa6afd408f1b4c6b47c53bbf31d48463bcabJim Grosbach break; 6255f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach case ARM::tSUBi8: 6256f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 6257f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 6258f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T2 if <Rd> is specified and encoding T2 is preferred 6259f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach // to encoding T1 if <Rd> is omitted." 626083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 6261f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach Inst.setOpcode(ARM::tSUBi3); 626283ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 626383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 6264f67e8554bf4808ad447ffb5d2deebbb10b810391Jim Grosbach break; 6265927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach case ARM::t2ADDrr: { 6266927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // If the destination and first source operand are the same, and 6267927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // there's no setting of the flags, use encoding T2 instead of T3. 6268927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // Note that this is only for ADD, not SUB. This mirrors the system 6269927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach // 'as' behaviour. Make sure the wide encoding wasn't explicit. 6270927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 6271927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst.getOperand(5).getReg() != 0 || 6272713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 6273713c70238c6d150d2cd458b07ab35932fafe508eJim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 6274927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach break; 6275927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach MCInst TmpInst; 6276927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.setOpcode(ARM::tADDhirr); 6277927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6278927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6279927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 6280927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6281927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6282927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach Inst = TmpInst; 6283927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach return true; 6284927b9df4c678371d3fb1308be90e76ed44af72f8Jim Grosbach } 628551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::tB: 628651f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb conditional branch outside of an IT block is a tBcc. 628783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 628851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::tBcc); 628983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 629083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 629151f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 629251f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson case ARM::t2B: 629351f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 629483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 629551f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson Inst.setOpcode(ARM::t2Bcc); 629683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 629783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 629851f6a7abf27fc92c3d8904c2334feab8b498e8e9Owen Anderson break; 6299c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach case ARM::t2Bcc: 6300a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // If the conditional is AL or we're in an IT block, we really want t2B. 630183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 6302c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach Inst.setOpcode(ARM::t2B); 630383ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 630483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 6305c075510e43f768e79f0d66374f4d60529c4d3d85Jim Grosbach break; 6306395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach case ARM::tBcc: 6307395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach // If the conditional is AL, we really want tB. 630883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach if (Inst.getOperand(1).getImm() == ARMCC::AL) { 6309395b453bed53a60c559b679eb92f75d0b140b307Jim Grosbach Inst.setOpcode(ARM::tB); 631083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 631183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach } 63123ce23d3d87d1ca437acb65ac01fac1c486507280Jim Grosbach break; 631376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach case ARM::tLDMIA: { 631476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If the register list contains any high registers, or if the writeback 631576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 631676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // instead if we're in Thumb2. Otherwise, this should have generated 631776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // an error in validateInstruction(). 631876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 631976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool hasWritebackToken = 632076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (static_cast<ARMOperand*>(Operands[3])->isToken() && 632176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 632276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach bool listContainsBase; 632376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 632476ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (!listContainsBase && !hasWritebackToken) || 632576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach (listContainsBase && hasWritebackToken)) { 632676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 632776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach assert (isThumbTwo()); 632876ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 632976ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // If we're switching to the updating version, we need to insert 633076ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach // the writeback tied operand. 633176ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach if (hasWritebackToken) 633276ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach Inst.insert(Inst.begin(), 633376ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach MCOperand::CreateReg(Inst.getOperand(0).getReg())); 633483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 633576ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 633676ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach break; 633776ecc3d35b4d16afb016bb14e29e12802b968716Jim Grosbach } 63388213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach case ARM::tSTMIA_UPD: { 63398213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // If the register list contains any high registers, we need to use 63408213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 63418213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // should have generated an error in validateInstruction(). 63428213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach unsigned Rn = Inst.getOperand(0).getReg(); 63438213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach bool listContainsBase; 63448213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 63458213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 63468213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach assert (isThumbTwo()); 63478213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach Inst.setOpcode(ARM::t2STMIA_UPD); 634883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 63498213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 63508213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach break; 63518213c96655e955a0b63b05580bc2f6a55be26083Jim Grosbach } 63525402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPOP: { 63535402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 63545402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // If the register list contains any high registers, we need to use 63555402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 63565402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // should have generated an error in validateInstruction(). 63575402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 635883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 63595402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 63605402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2LDMIA_UPD); 63615402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 63625402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 63635402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 636483ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 63655402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 63665402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach case ARM::tPUSH: { 63675402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach bool listContainsBase; 63685402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 636983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 63705402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach assert (isThumbTwo()); 63715402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.setOpcode(ARM::t2STMDB_UPD); 63725402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach // Add the base register and writeback operands. 63735402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 63745402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 637583ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 63765402637ff283d7397513d5c1699cdf2274c47313Jim Grosbach } 63771ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVi: { 63781ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 63791ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 63801ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 63811ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(1).getImm() <= 255 && 6382c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 6383c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR) || 6384c2d3164ab467bdfa8508b93177e69b99626cd8e2Jim Grosbach (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 63851ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 63861ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 63871ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't in the same order for tMOVi8... 63881ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 63891ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(ARM::tMOVi8); 63901ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 63911ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 63921ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 63931ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 63941ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 63951ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 639683ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 63971ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 63981ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 63991ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 64001ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach case ARM::t2MOVr: { 64011ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 64021ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // request the 32-bit variant, transform it here. 64031ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 64041ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 64051ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(2).getImm() == ARMCC::AL && 64061ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst.getOperand(4).getReg() == ARM::CPSR && 64071ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 64081ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 64091ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach // The operands aren't the same for tMOV[S]r... (no cc_out) 64101ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach MCInst TmpInst; 64111ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 64121ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 64131ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 64141ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 64151ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 64161ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach Inst = TmpInst; 641783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 64181ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 64191ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach break; 64201ad60c2adc9ed765a968747d0c548cda53bfd384Jim Grosbach } 6421326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach case ARM::t2SXTH: 642250f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: 642350f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: 642450f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: { 6425326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // If we can use the 16-bit encoding and the user didn't explicitly 6426326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // request the 32-bit variant, transform it here. 6427326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6428326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6429326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst.getOperand(2).getImm() == 0 && 6430326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach (!static_cast<ARMOperand*>(Operands[2])->isToken() || 6431326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 643250f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach unsigned NewOpc; 643350f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach switch (Inst.getOpcode()) { 643450f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach default: llvm_unreachable("Illegal opcode!"); 643550f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 643650f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 643750f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 643850f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 643950f1c37123968b7f57068280483ec78f6ff7973eJim Grosbach } 6440326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach // The operands aren't the same for thumb1 (no rotate operand). 6441326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach MCInst TmpInst; 6442326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.setOpcode(NewOpc); 6443326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 6444326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 6445326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 6446326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 6447326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach Inst = TmpInst; 644883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return true; 6449326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 6450326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach break; 6451326efe58918d3f0a431d07938054870fcd0e240fJim Grosbach } 645204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach case ARM::MOVsi: { 645304b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 645404b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach if (SOpc == ARM_AM::rrx) return false; 645504b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 645604b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach // Shifting by zero is accepted as a vanilla 'MOVr' 645704b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach MCInst TmpInst; 645804b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.setOpcode(ARM::MOVr); 645904b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 646004b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 646104b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(3)); 646204b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 646304b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 646404b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach Inst = TmpInst; 646504b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return true; 646604b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 646704b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach return false; 646804b5d93250bef585631a583a85f6733b1bdc8c52Jim Grosbach } 64698d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: 64708d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: 64718d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: 64728d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: 64738d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: 64748d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: { 64758d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach unsigned newOpc; 64768d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 64778d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (SOpc == ARM_AM::rrx) return false; 64788d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach switch (Inst.getOpcode()) { 647919055cc2712223f6834fc3cf5b547803ba83f066Matt Beaumont-Gay default: assert(0 && "unexpected opcode!"); 64808d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 64818d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 64828d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::EORrsi: newOpc = ARM::EORrr; break; 64838d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::BICrsi: newOpc = ARM::BICrr; break; 64848d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 64858d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 64868d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 64878d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach // If the shift is by zero, use the non-shifted instruction definition. 64888d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) { 64898d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach MCInst TmpInst; 64908d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.setOpcode(newOpc); 64918d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(0)); 64928d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(1)); 64938d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(2)); 64948d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(4)); 64958d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(5)); 64968d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach TmpInst.addOperand(Inst.getOperand(6)); 64978d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach Inst = TmpInst; 64988d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return true; 64998d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 65008d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach return false; 65018d9550bde95c8d128e7bf62e9e65dec1854e2d1dJim Grosbach } 650289df996ab20609676ecc8823f58414d598b09b46Jim Grosbach case ARM::t2IT: { 650389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // The mask bits for all but the first condition are represented as 650489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // the low bit of the condition code value implies 't'. We currently 650589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // always have 1 implies 't', so XOR toggle the bits if the low bit 650689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // of the condition code is zero. The encoding also expects the low 650789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // bit of the condition to be encoded as bit 4 of the mask operand, 650889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach // so mask that in if needed 650989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MCOperand &MO = Inst.getOperand(1); 651089df996ab20609676ecc8823f58414d598b09b46Jim Grosbach unsigned Mask = MO.getImm(); 6511f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned OrigMask = Mask; 6512f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach unsigned TZ = CountTrailingZeros_32(Mask); 651389df996ab20609676ecc8823f58414d598b09b46Jim Grosbach if ((Inst.getOperand(0).getImm() & 1) == 0) { 651489df996ab20609676ecc8823f58414d598b09b46Jim Grosbach assert(Mask && TZ <= 3 && "illegal IT mask value!"); 651589df996ab20609676ecc8823f58414d598b09b46Jim Grosbach for (unsigned i = 3; i != TZ; --i) 651689df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask ^= 1 << i; 651789df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } else 651889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach Mask |= 0x10; 651989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach MO.setImm(Mask); 6520f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 6521f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // Set up the IT block state according to the IT instruction we just 6522f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach // matched. 6523f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach assert(!inITBlock() && "nested IT blocks?!"); 6524f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 6525f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.Mask = OrigMask; // Use the original mask, not the updated one. 6526f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.CurPosition = 0; 6527f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach ITState.FirstCond = true; 652889df996ab20609676ecc8823f58414d598b09b46Jim Grosbach break; 652989df996ab20609676ecc8823f58414d598b09b46Jim Grosbach } 6530f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 653183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach return false; 6532f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach} 6533f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 653447a0d52b69056250a1edaca8b28f705993094542Jim Grosbachunsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 653547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // 16-bit thumb arithmetic instructions either require or preclude the 'S' 653647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // suffix depending on whether they're in an IT block or not. 6537194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach unsigned Opc = Inst.getOpcode(); 65381a2f9886a2a60dbd41216468a240446bbfed3e76Benjamin Kramer const MCInstrDesc &MCID = getInstDesc(Opc); 653947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 654047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.hasOptionalDef() && 654147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "optionally flag setting instruction missing optional def operand"); 654247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach assert(MCID.NumOperands == Inst.getNumOperands() && 654347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach "operand count mismatch!"); 654447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // Find the optional-def operand (cc_out). 654547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach unsigned OpNo; 654647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach for (OpNo = 0; 654747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 654847a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ++OpNo) 654947a0d52b69056250a1edaca8b28f705993094542Jim Grosbach ; 655047a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb1, reject it completely. 655147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 655247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_MnemonicFail; 655347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // If we're parsing Thumb2, which form is legal depends on whether we're 655447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach // in an IT block. 6555f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 6556f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach !inITBlock()) 655747a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_RequiresITBlock; 6558f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 6559f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach inITBlock()) 6560f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Match_RequiresNotITBlock; 656147a0d52b69056250a1edaca8b28f705993094542Jim Grosbach } 6562194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Some high-register supporting Thumb1 encodings only allow both registers 6563194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // to be from r0-r7 when in Thumb2. 6564194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach else if (Opc == ARM::tADDhirr && isThumbOne() && 6565194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg()) && 6566194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(2).getReg())) 6567194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresThumb2; 6568194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach // Others only require ARMv6 or later. 65694ec6e888ec6d12b5255afd685b05c8fee1f7fc73Jim Grosbach else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 6570194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(0).getReg()) && 6571194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach isARMLowRegister(Inst.getOperand(1).getReg())) 6572194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Match_RequiresV6; 657347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Match_Success; 657447a0d52b69056250a1edaca8b28f705993094542Jim Grosbach} 657547a0d52b69056250a1edaca8b28f705993094542Jim Grosbach 6576fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattnerbool ARMAsmParser:: 6577fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris LattnerMatchAndEmitInstruction(SMLoc IDLoc, 6578fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner SmallVectorImpl<MCParsedAsmOperand*> &Operands, 6579fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCStreamer &Out) { 6580fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner MCInst Inst; 6581fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner unsigned ErrorInfo; 658219cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach unsigned MatchResult; 6583193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 6584193c3acbe5cdb60767d114016970e898c7502d7aKevin Enderby switch (MatchResult) { 658519cb7f491fbc7cb5d0bbd10e201f9d5093e6d4e5Jim Grosbach default: break; 6586e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_Success: 6587189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // Context sensitive operand constraints aren't handled by the matcher, 6588189610f9466686a91fb7d847b572e1645c785323Jim Grosbach // so check them here. 6589a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach if (validateInstruction(Inst, Operands)) { 6590a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Still progress the IT block, otherwise one wrong condition causes 6591a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // nasty cascading errors. 6592a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 6593189610f9466686a91fb7d847b572e1645c785323Jim Grosbach return true; 6594a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach } 6595189610f9466686a91fb7d847b572e1645c785323Jim Grosbach 6596f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach // Some instructions need post-processing to, for example, tweak which 659783ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // encoding is selected. Loop on it while changes happen so the 659883ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // individual transformations can chain off each other. E.g., 659983ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 660083ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach while (processInstruction(Inst, Operands)) 660183ec87755ed4d07f6650d6727fb762052bd0041cJim Grosbach ; 6602f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 6603a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // Only move forward at the very end so that everything in validate 6604a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // and process gets a consistent answer about whether we're in an IT 6605a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach // block. 6606a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach forwardITPosition(); 6607a110988b391652e3f4f85cb709a3eeb81c8cdd84Jim Grosbach 6608fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner Out.EmitInstruction(Inst); 6609fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner return false; 6610e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_MissingFeature: 6611e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 6612e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return true; 6613e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_InvalidOperand: { 6614e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner SMLoc ErrorLoc = IDLoc; 6615e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo != ~0U) { 6616e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorInfo >= Operands.size()) 6617e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(IDLoc, "too few operands for instruction"); 661816c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6619e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 6620e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 6621e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 662216c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6623e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner return Error(ErrorLoc, "invalid operand for instruction"); 6624e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner } 6625e73d4f8ec7af68fc0f67811e4e004562ab538014Chris Lattner case Match_MnemonicFail: 662647a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Error(IDLoc, "invalid instruction"); 6627b412915ff6229b3e2dffedcfb0f3fb7e85259841Daniel Dunbar case Match_ConversionFail: 662888ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach // The converter function will have already emited a diagnostic. 662988ae2bc6d53bbf58422ff74729da18a53e155b4aJim Grosbach return true; 6630f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach case Match_RequiresNotITBlock: 6631f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return Error(IDLoc, "flag setting instruction only valid outside IT block"); 663247a0d52b69056250a1edaca8b28f705993094542Jim Grosbach case Match_RequiresITBlock: 663347a0d52b69056250a1edaca8b28f705993094542Jim Grosbach return Error(IDLoc, "instruction only valid inside IT block"); 6634194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresV6: 6635194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires ARMv6 or later"); 6636194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach case Match_RequiresThumb2: 6637194bd8982936c819a4b14335a4d08f28af8f3d42Jim Grosbach return Error(IDLoc, "instruction variant requires Thumb2"); 6638fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner } 663916c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6640c223e2b10b4753a63dfe7e6980c650b179139983Eric Christopher llvm_unreachable("Implement any new match types added!"); 6641fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner} 6642fa42fad8bf7b0058ba031a275e1e8ce53b2cb1adChris Lattner 66431355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirective parses the arm specific directives 6644ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbybool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 6645ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby StringRef IDVal = DirectiveID.getIdentifier(); 6646ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (IDVal == ".word") 66471355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveWord(4, DirectiveID.getLoc()); 6648515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb") 66491355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumb(DirectiveID.getLoc()); 66509a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach else if (IDVal == ".arm") 66519a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return parseDirectiveARM(DirectiveID.getLoc()); 6652515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".thumb_func") 66531355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveThumbFunc(DirectiveID.getLoc()); 6654515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".code") 66551355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveCode(DirectiveID.getLoc()); 6656515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else if (IDVal == ".syntax") 66571355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach return parseDirectiveSyntax(DirectiveID.getLoc()); 6658a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach else if (IDVal == ".unreq") 6659a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return parseDirectiveUnreq(DirectiveID.getLoc()); 6660d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".arch") 6661d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveArch(DirectiveID.getLoc()); 6662d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim else if (IDVal == ".eabi_attribute") 6663d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return parseDirectiveEabiAttr(DirectiveID.getLoc()); 6664ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 6665ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 6666ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 66671355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveWord 6668ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby/// ::= .word [ expression (, expression)* ] 66691355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 6670ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) { 6671ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby for (;;) { 6672ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby const MCExpr *Value; 6673ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getParser().ParseExpression(Value)) 6674ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return true; 6675ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6676aaec205b87637cd0d59d4f11630db603686eb73dChris Lattner getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 6677ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6678ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().is(AsmToken::EndOfStatement)) 6679ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby break; 668016c7425cff6ac3d0a4a9c56779bdfa91b2e8e863Jim Grosbach 6681ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby // FIXME: Improve diagnostic. 6682ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby if (getLexer().isNot(AsmToken::Comma)) 6683ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return Error(L, "unexpected token in directive"); 6684b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6685ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 6686ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby } 6687ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 6688b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6689ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby return false; 6690ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 6691ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby 66921355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumb 6693515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumb 66941355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 6695515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 6696515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 6697b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6698515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 66999a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (!isThumb()) 67009a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 67019a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 67029a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return false; 67039a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach} 67049a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 67059a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// parseDirectiveARM 67069a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach/// ::= .arm 67079a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbachbool ARMAsmParser::parseDirectiveARM(SMLoc L) { 67089a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 67099a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach return Error(L, "unexpected token in directive"); 67109a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach Parser.Lex(); 67119a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach 67129a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach if (isThumb()) 67139a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach SwitchMode(); 67149a70df99ca674b288d50dbf454779ed75d6e48ddJim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 6715515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6716515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6717515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 67181355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveThumbFunc 6719515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .thumbfunc symbol_name 67201355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 67216469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 67226469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola bool isMachO = MAI.hasSubsectionsViaSymbols(); 67236469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola StringRef Name; 6724de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach bool needFuncName = true; 67256469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6726de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Darwin asm has (optionally) function name after .thumb_func direction 67276469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // ELF doesn't 67286469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola if (isMachO) { 67296469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola const AsmToken &Tok = Parser.getTok(); 6730de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::EndOfStatement)) { 6731de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 6732de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach return Error(L, "unexpected token in .thumb_func directive"); 6733de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Name = Tok.getIdentifier(); 6734de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); // Consume the identifier token. 6735de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach needFuncName = false; 6736de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach } 67376469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 67386469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6739de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (getLexer().isNot(AsmToken::EndOfStatement)) 6740515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in directive"); 6741de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach 6742de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // Eat the end of statement and any blank lines that follow. 6743de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach while (getLexer().is(AsmToken::EndOfStatement)) 6744de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach Parser.Lex(); 6745515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 67466469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola // FIXME: assuming function name will be the line following .thumb_func 6747de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // We really should be checking the next symbol definition even if there's 6748de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach // stuff in between. 6749de4d83943a5206690fbe1e39dd33770f5ab29595Jim Grosbach if (needFuncName) { 6750d475f8612b1c7959dbf50242c8fa9d4aea1ee1a9Jim Grosbach Name = Parser.getTok().getIdentifier(); 67516469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola } 67526469540adf63d94a876c2b623cb4ca70479647f7Rafael Espindola 6753642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach // Mark symbol as a thumb symbol. 6754642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 6755642fc9c24ba7c43a4a962c6c05cfffce713d7de7Jim Grosbach getParser().getStreamer().EmitThumbFunc(Func); 6756515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6757515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6758515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 67591355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveSyntax 6760515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .syntax unified | divided 67611355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 676218b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 6763515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Identifier)) 6764515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .syntax directive"); 676538e59891ee4417a9be2f8146ce0ba3269e38ac21Benjamin Kramer StringRef Mode = Tok.getString(); 676658c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Mode == "unified" || Mode == "UNIFIED") 6767b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 676858c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Mode == "divided" || Mode == "DIVIDED") 67699e56fb12c504c82c92947fe9c46287fc60116b91Kevin Enderby return Error(L, "'.syntax divided' arm asssembly not supported"); 6770515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 6771515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unrecognized syntax mode in .syntax directive"); 6772515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6773515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 677418b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 6775b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6776515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6777515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // TODO tell the MC streamer the mode 6778515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby // getParser().getStreamer().Emit???(); 6779515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6780515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6781515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 67821355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbach/// parseDirectiveCode 6783515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby/// ::= .code 16 | 32 67841355cf1f76abe9699cd1c2838da132ff8b25b76bJim Grosbachbool ARMAsmParser::parseDirectiveCode(SMLoc L) { 678518b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan const AsmToken &Tok = Parser.getTok(); 6786515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (Tok.isNot(AsmToken::Integer)) 6787515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "unexpected token in .code directive"); 678818b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan int64_t Val = Parser.getTok().getIntVal(); 678958c86910b31c569a5709466c82e2fabae2014a56Duncan Sands if (Val == 16) 6790b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 679158c86910b31c569a5709466c82e2fabae2014a56Duncan Sands else if (Val == 32) 6792b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6793515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby else 6794515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return Error(L, "invalid operand to .code directive"); 6795515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6796515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby if (getLexer().isNot(AsmToken::EndOfStatement)) 679718b8323de70e3461b5d035e3f9e4f6dfaf5e674bSean Callanan return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 6798b9a25b7744ed12b80031426978decce3d4cebbd7Sean Callanan Parser.Lex(); 6799515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 680032869205052430f45d598fba25ab878d8b29da2dEvan Cheng if (Val == 16) { 680198447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (!isThumb()) 6802ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 680398447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 680432869205052430f45d598fba25ab878d8b29da2dEvan Cheng } else { 680598447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach if (isThumb()) 6806ffc0e73046f737d75e0a62b3a83ef19bcef111e3Evan Cheng SwitchMode(); 680798447daa9559d5bf7816f084581b5ca073d316f6Jim Grosbach getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 6808eb0caa115491019f7f7fe45fc70ad47682244187Evan Cheng } 68092a301704ea76535f0485d5c3b75664b323249bdbJim Grosbach 6810515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby return false; 6811515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby} 6812515d509360d81946247fd0f937034cdf1f237c72Kevin Enderby 6813a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveReq 6814a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= name .req registername 6815a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 6816a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the '.req' token. 6817a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach unsigned Reg; 6818a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach SMLoc SRegLoc, ERegLoc; 6819a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 6820a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6821a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "register name expected"); 6822a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6823a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6824a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach // Shouldn't be anything else. 6825a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 6826a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6827a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(Parser.getTok().getLoc(), 6828a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "unexpected input in .req directive."); 6829a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6830a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6831a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Consume the EndOfStatement 6832a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6833a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 6834a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(SRegLoc, "redefinition of '" + Name + 6835a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach "' does not match original."); 6836a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6837a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 6838a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 6839a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6840a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// parseDirectiveUneq 6841a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach/// ::= .unreq registername 6842a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbachbool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 6843a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach if (Parser.getTok().isNot(AsmToken::Identifier)) { 6844a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.EatToEndOfStatement(); 6845a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return Error(L, "unexpected input in .unreq directive."); 6846a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach } 6847a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach RegisterReqs.erase(Parser.getTok().getIdentifier()); 6848a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach Parser.Lex(); // Eat the identifier. 6849a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach return false; 6850a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach} 6851a39cda7aff2d379ad9c15500319ab037baa48747Jim Grosbach 6852d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveArch 6853d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .arch token 6854d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveArch(SMLoc L) { 6855d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 6856d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 6857d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 6858d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// parseDirectiveEabiAttr 6859d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim/// ::= .eabi_attribute int, int 6860d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kimbool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 6861d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim return true; 6862d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim} 6863d7c9e08b6bcf15655919960e214b9b91677cdde9Jason W Kim 686490b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callananextern "C" void LLVMInitializeARMAsmLexer(); 686590b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan 68669c41fa87eac369d84f8bfc2245084cd39f281ee4Kevin Enderby/// Force static initialization. 6867ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderbyextern "C" void LLVMInitializeARMAsmParser() { 686894b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 686994b9550a32d189704a8eae55505edf62662c0534Evan Cheng RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 687090b7097f92f6b4f6b27cd88c7c88a21b777f5795Sean Callanan LLVMInitializeARMAsmLexer(); 6871ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70Kevin Enderby} 68723483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar 68730692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_REGISTER_MATCHER 68740692ee676f8cdad25ad09a868bf597af4115c9d9Chris Lattner#define GET_MATCHER_IMPLEMENTATION 68753483acabf012b847b13b969ebd9ce5c4d16d9eb7Daniel Dunbar#include "ARMGenAsmMatcher.inc" 6876