ARMAsmParser.cpp revision 11e03e7c2d0c163e54b911ad1e665616dc0bcc8c 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MCTargetAsmParser.h"
24#include "llvm/Target/TargetRegistry.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/ADT/BitVector.h"
28#include "llvm/ADT/OwningPtr.h"
29#include "llvm/ADT/STLExtras.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/ADT/StringExtras.h"
32#include "llvm/ADT/StringSwitch.h"
33#include "llvm/ADT/Twine.h"
34
35using namespace llvm;
36
37namespace {
38
39class ARMOperand;
40
41class ARMAsmParser : public MCTargetAsmParser {
42  MCSubtargetInfo &STI;
43  MCAsmParser &Parser;
44
45  MCAsmParser &getParser() const { return Parser; }
46  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47
48  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
49  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50
51  int tryParseRegister();
52  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
53  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
56  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
57  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
58  const MCExpr *applyPrefixToExpr(const MCExpr *E,
59                                  MCSymbolRefExpr::VariantKind Variant);
60
61
62  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
63                              unsigned &ShiftAmount);
64  bool parseDirectiveWord(unsigned Size, SMLoc L);
65  bool parseDirectiveThumb(SMLoc L);
66  bool parseDirectiveThumbFunc(SMLoc L);
67  bool parseDirectiveCode(SMLoc L);
68  bool parseDirectiveSyntax(SMLoc L);
69
70  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
71                          bool &CarrySetting, unsigned &ProcessorIMod);
72  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
73                             bool &CanAcceptPredicationCode);
74
75  bool isThumb() const {
76    // FIXME: Can tablegen auto-generate this?
77    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
78  }
79  bool isThumbOne() const {
80    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
81  }
82  bool isThumbTwo() const {
83    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
84  }
85  bool hasV6Ops() const {
86    return STI.getFeatureBits() & ARM::HasV6Ops;
87  }
88  void SwitchMode() {
89    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
90    setAvailableFeatures(FB);
91  }
92
93  /// @name Auto-generated Match Functions
94  /// {
95
96#define GET_ASSEMBLER_HEADER
97#include "ARMGenAsmMatcher.inc"
98
99  /// }
100
101  OperandMatchResultTy parseCoprocNumOperand(
102    SmallVectorImpl<MCParsedAsmOperand*>&);
103  OperandMatchResultTy parseCoprocRegOperand(
104    SmallVectorImpl<MCParsedAsmOperand*>&);
105  OperandMatchResultTy parseMemBarrierOptOperand(
106    SmallVectorImpl<MCParsedAsmOperand*>&);
107  OperandMatchResultTy parseProcIFlagsOperand(
108    SmallVectorImpl<MCParsedAsmOperand*>&);
109  OperandMatchResultTy parseMSRMaskOperand(
110    SmallVectorImpl<MCParsedAsmOperand*>&);
111  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
112                                   StringRef Op, int Low, int High);
113  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
114    return parsePKHImm(O, "lsl", 0, 31);
115  }
116  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
117    return parsePKHImm(O, "asr", 1, 32);
118  }
119  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
120  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
122  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
123  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
124  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
125
126  // Asm Match Converter Methods
127  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
128                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
129  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
130                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
131  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
132                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
133  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
134                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
135  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
136                             const SmallVectorImpl<MCParsedAsmOperand*> &);
137  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
138                             const SmallVectorImpl<MCParsedAsmOperand*> &);
139  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
140                             const SmallVectorImpl<MCParsedAsmOperand*> &);
141  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
142                             const SmallVectorImpl<MCParsedAsmOperand*> &);
143  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
144                  const SmallVectorImpl<MCParsedAsmOperand*> &);
145  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
146                  const SmallVectorImpl<MCParsedAsmOperand*> &);
147  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
148                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
149  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
150                        const SmallVectorImpl<MCParsedAsmOperand*> &);
151
152  bool validateInstruction(MCInst &Inst,
153                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
154  void processInstruction(MCInst &Inst,
155                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
156  bool shouldOmitCCOutOperand(StringRef Mnemonic,
157                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
158
159public:
160  enum ARMMatchResultTy {
161    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
162    Match_RequiresV6,
163    Match_RequiresThumb2
164  };
165
166  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
167    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
168    MCAsmParserExtension::Initialize(_Parser);
169
170    // Initialize the set of available features.
171    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
172  }
173
174  // Implementation of the MCTargetAsmParser interface:
175  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
176  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
177                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
178  bool ParseDirective(AsmToken DirectiveID);
179
180  unsigned checkTargetMatchPredicate(MCInst &Inst);
181
182  bool MatchAndEmitInstruction(SMLoc IDLoc,
183                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
184                               MCStreamer &Out);
185};
186} // end anonymous namespace
187
188namespace {
189
190/// ARMOperand - Instances of this class represent a parsed ARM machine
191/// instruction.
192class ARMOperand : public MCParsedAsmOperand {
193  enum KindTy {
194    CondCode,
195    CCOut,
196    CoprocNum,
197    CoprocReg,
198    Immediate,
199    MemBarrierOpt,
200    Memory,
201    PostIndexRegister,
202    MSRMask,
203    ProcIFlags,
204    Register,
205    RegisterList,
206    DPRRegisterList,
207    SPRRegisterList,
208    ShiftedRegister,
209    ShiftedImmediate,
210    ShifterImmediate,
211    RotateImmediate,
212    BitfieldDescriptor,
213    Token
214  } Kind;
215
216  SMLoc StartLoc, EndLoc;
217  SmallVector<unsigned, 8> Registers;
218
219  union {
220    struct {
221      ARMCC::CondCodes Val;
222    } CC;
223
224    struct {
225      ARM_MB::MemBOpt Val;
226    } MBOpt;
227
228    struct {
229      unsigned Val;
230    } Cop;
231
232    struct {
233      ARM_PROC::IFlags Val;
234    } IFlags;
235
236    struct {
237      unsigned Val;
238    } MMask;
239
240    struct {
241      const char *Data;
242      unsigned Length;
243    } Tok;
244
245    struct {
246      unsigned RegNum;
247    } Reg;
248
249    struct {
250      const MCExpr *Val;
251    } Imm;
252
253    /// Combined record for all forms of ARM address expressions.
254    struct {
255      unsigned BaseRegNum;
256      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
257      // was specified.
258      const MCConstantExpr *OffsetImm;  // Offset immediate value
259      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
260      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
261      unsigned ShiftImm;      // shift for OffsetReg.
262      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
263    } Mem;
264
265    struct {
266      unsigned RegNum;
267      bool isAdd;
268      ARM_AM::ShiftOpc ShiftTy;
269      unsigned ShiftImm;
270    } PostIdxReg;
271
272    struct {
273      bool isASR;
274      unsigned Imm;
275    } ShifterImm;
276    struct {
277      ARM_AM::ShiftOpc ShiftTy;
278      unsigned SrcReg;
279      unsigned ShiftReg;
280      unsigned ShiftImm;
281    } RegShiftedReg;
282    struct {
283      ARM_AM::ShiftOpc ShiftTy;
284      unsigned SrcReg;
285      unsigned ShiftImm;
286    } RegShiftedImm;
287    struct {
288      unsigned Imm;
289    } RotImm;
290    struct {
291      unsigned LSB;
292      unsigned Width;
293    } Bitfield;
294  };
295
296  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
297public:
298  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
299    Kind = o.Kind;
300    StartLoc = o.StartLoc;
301    EndLoc = o.EndLoc;
302    switch (Kind) {
303    case CondCode:
304      CC = o.CC;
305      break;
306    case Token:
307      Tok = o.Tok;
308      break;
309    case CCOut:
310    case Register:
311      Reg = o.Reg;
312      break;
313    case RegisterList:
314    case DPRRegisterList:
315    case SPRRegisterList:
316      Registers = o.Registers;
317      break;
318    case CoprocNum:
319    case CoprocReg:
320      Cop = o.Cop;
321      break;
322    case Immediate:
323      Imm = o.Imm;
324      break;
325    case MemBarrierOpt:
326      MBOpt = o.MBOpt;
327      break;
328    case Memory:
329      Mem = o.Mem;
330      break;
331    case PostIndexRegister:
332      PostIdxReg = o.PostIdxReg;
333      break;
334    case MSRMask:
335      MMask = o.MMask;
336      break;
337    case ProcIFlags:
338      IFlags = o.IFlags;
339      break;
340    case ShifterImmediate:
341      ShifterImm = o.ShifterImm;
342      break;
343    case ShiftedRegister:
344      RegShiftedReg = o.RegShiftedReg;
345      break;
346    case ShiftedImmediate:
347      RegShiftedImm = o.RegShiftedImm;
348      break;
349    case RotateImmediate:
350      RotImm = o.RotImm;
351      break;
352    case BitfieldDescriptor:
353      Bitfield = o.Bitfield;
354      break;
355    }
356  }
357
358  /// getStartLoc - Get the location of the first token of this operand.
359  SMLoc getStartLoc() const { return StartLoc; }
360  /// getEndLoc - Get the location of the last token of this operand.
361  SMLoc getEndLoc() const { return EndLoc; }
362
363  ARMCC::CondCodes getCondCode() const {
364    assert(Kind == CondCode && "Invalid access!");
365    return CC.Val;
366  }
367
368  unsigned getCoproc() const {
369    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
370    return Cop.Val;
371  }
372
373  StringRef getToken() const {
374    assert(Kind == Token && "Invalid access!");
375    return StringRef(Tok.Data, Tok.Length);
376  }
377
378  unsigned getReg() const {
379    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
380    return Reg.RegNum;
381  }
382
383  const SmallVectorImpl<unsigned> &getRegList() const {
384    assert((Kind == RegisterList || Kind == DPRRegisterList ||
385            Kind == SPRRegisterList) && "Invalid access!");
386    return Registers;
387  }
388
389  const MCExpr *getImm() const {
390    assert(Kind == Immediate && "Invalid access!");
391    return Imm.Val;
392  }
393
394  ARM_MB::MemBOpt getMemBarrierOpt() const {
395    assert(Kind == MemBarrierOpt && "Invalid access!");
396    return MBOpt.Val;
397  }
398
399  ARM_PROC::IFlags getProcIFlags() const {
400    assert(Kind == ProcIFlags && "Invalid access!");
401    return IFlags.Val;
402  }
403
404  unsigned getMSRMask() const {
405    assert(Kind == MSRMask && "Invalid access!");
406    return MMask.Val;
407  }
408
409  bool isCoprocNum() const { return Kind == CoprocNum; }
410  bool isCoprocReg() const { return Kind == CoprocReg; }
411  bool isCondCode() const { return Kind == CondCode; }
412  bool isCCOut() const { return Kind == CCOut; }
413  bool isImm() const { return Kind == Immediate; }
414  bool isImm0_255() const {
415    if (Kind != Immediate)
416      return false;
417    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
418    if (!CE) return false;
419    int64_t Value = CE->getValue();
420    return Value >= 0 && Value < 256;
421  }
422  bool isImm0_7() const {
423    if (Kind != Immediate)
424      return false;
425    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
426    if (!CE) return false;
427    int64_t Value = CE->getValue();
428    return Value >= 0 && Value < 8;
429  }
430  bool isImm0_15() const {
431    if (Kind != Immediate)
432      return false;
433    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
434    if (!CE) return false;
435    int64_t Value = CE->getValue();
436    return Value >= 0 && Value < 16;
437  }
438  bool isImm0_31() const {
439    if (Kind != Immediate)
440      return false;
441    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
442    if (!CE) return false;
443    int64_t Value = CE->getValue();
444    return Value >= 0 && Value < 32;
445  }
446  bool isImm1_16() const {
447    if (Kind != Immediate)
448      return false;
449    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
450    if (!CE) return false;
451    int64_t Value = CE->getValue();
452    return Value > 0 && Value < 17;
453  }
454  bool isImm1_32() const {
455    if (Kind != Immediate)
456      return false;
457    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
458    if (!CE) return false;
459    int64_t Value = CE->getValue();
460    return Value > 0 && Value < 33;
461  }
462  bool isImm0_65535() const {
463    if (Kind != Immediate)
464      return false;
465    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
466    if (!CE) return false;
467    int64_t Value = CE->getValue();
468    return Value >= 0 && Value < 65536;
469  }
470  bool isImm0_65535Expr() const {
471    if (Kind != Immediate)
472      return false;
473    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474    // If it's not a constant expression, it'll generate a fixup and be
475    // handled later.
476    if (!CE) return true;
477    int64_t Value = CE->getValue();
478    return Value >= 0 && Value < 65536;
479  }
480  bool isImm24bit() const {
481    if (Kind != Immediate)
482      return false;
483    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
484    if (!CE) return false;
485    int64_t Value = CE->getValue();
486    return Value >= 0 && Value <= 0xffffff;
487  }
488  bool isImmThumbSR() const {
489    if (Kind != Immediate)
490      return false;
491    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
492    if (!CE) return false;
493    int64_t Value = CE->getValue();
494    return Value > 0 && Value < 33;
495  }
496  bool isPKHLSLImm() const {
497    if (Kind != Immediate)
498      return false;
499    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
500    if (!CE) return false;
501    int64_t Value = CE->getValue();
502    return Value >= 0 && Value < 32;
503  }
504  bool isPKHASRImm() const {
505    if (Kind != Immediate)
506      return false;
507    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
508    if (!CE) return false;
509    int64_t Value = CE->getValue();
510    return Value > 0 && Value <= 32;
511  }
512  bool isARMSOImm() const {
513    if (Kind != Immediate)
514      return false;
515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516    if (!CE) return false;
517    int64_t Value = CE->getValue();
518    return ARM_AM::getSOImmVal(Value) != -1;
519  }
520  bool isT2SOImm() const {
521    if (Kind != Immediate)
522      return false;
523    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
524    if (!CE) return false;
525    int64_t Value = CE->getValue();
526    return ARM_AM::getT2SOImmVal(Value) != -1;
527  }
528  bool isSetEndImm() const {
529    if (Kind != Immediate)
530      return false;
531    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
532    if (!CE) return false;
533    int64_t Value = CE->getValue();
534    return Value == 1 || Value == 0;
535  }
536  bool isReg() const { return Kind == Register; }
537  bool isRegList() const { return Kind == RegisterList; }
538  bool isDPRRegList() const { return Kind == DPRRegisterList; }
539  bool isSPRRegList() const { return Kind == SPRRegisterList; }
540  bool isToken() const { return Kind == Token; }
541  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
542  bool isMemory() const { return Kind == Memory; }
543  bool isShifterImm() const { return Kind == ShifterImmediate; }
544  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
545  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
546  bool isRotImm() const { return Kind == RotateImmediate; }
547  bool isBitfield() const { return Kind == BitfieldDescriptor; }
548  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
549  bool isPostIdxReg() const {
550    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
551  }
552  bool isMemNoOffset() const {
553    if (Kind != Memory)
554      return false;
555    // No offset of any kind.
556    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
557  }
558  bool isAddrMode2() const {
559    if (Kind != Memory)
560      return false;
561    // Check for register offset.
562    if (Mem.OffsetRegNum) return true;
563    // Immediate offset in range [-4095, 4095].
564    if (!Mem.OffsetImm) return true;
565    int64_t Val = Mem.OffsetImm->getValue();
566    return Val > -4096 && Val < 4096;
567  }
568  bool isAM2OffsetImm() const {
569    if (Kind != Immediate)
570      return false;
571    // Immediate offset in range [-4095, 4095].
572    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
573    if (!CE) return false;
574    int64_t Val = CE->getValue();
575    return Val > -4096 && Val < 4096;
576  }
577  bool isAddrMode3() const {
578    if (Kind != Memory)
579      return false;
580    // No shifts are legal for AM3.
581    if (Mem.ShiftType != ARM_AM::no_shift) return false;
582    // Check for register offset.
583    if (Mem.OffsetRegNum) return true;
584    // Immediate offset in range [-255, 255].
585    if (!Mem.OffsetImm) return true;
586    int64_t Val = Mem.OffsetImm->getValue();
587    return Val > -256 && Val < 256;
588  }
589  bool isAM3Offset() const {
590    if (Kind != Immediate && Kind != PostIndexRegister)
591      return false;
592    if (Kind == PostIndexRegister)
593      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
594    // Immediate offset in range [-255, 255].
595    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596    if (!CE) return false;
597    int64_t Val = CE->getValue();
598    // Special case, #-0 is INT32_MIN.
599    return (Val > -256 && Val < 256) || Val == INT32_MIN;
600  }
601  bool isAddrMode5() const {
602    if (Kind != Memory)
603      return false;
604    // Check for register offset.
605    if (Mem.OffsetRegNum) return false;
606    // Immediate offset in range [-1020, 1020] and a multiple of 4.
607    if (!Mem.OffsetImm) return true;
608    int64_t Val = Mem.OffsetImm->getValue();
609    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
610  }
611  bool isMemRegOffset() const {
612    if (Kind != Memory || !Mem.OffsetRegNum)
613      return false;
614    return true;
615  }
616  bool isMemThumbRR() const {
617    // Thumb reg+reg addressing is simple. Just two registers, a base and
618    // an offset. No shifts, negations or any other complicating factors.
619    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
620        Mem.ShiftType != ARM_AM::no_shift)
621      return false;
622    return isARMLowRegister(Mem.BaseRegNum) &&
623      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
624  }
625  bool isMemThumbRIs4() const {
626    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
627        !isARMLowRegister(Mem.BaseRegNum))
628      return false;
629    // Immediate offset, multiple of 4 in range [0, 124].
630    if (!Mem.OffsetImm) return true;
631    int64_t Val = Mem.OffsetImm->getValue();
632    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
633  }
634  bool isMemThumbRIs2() const {
635    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
636        !isARMLowRegister(Mem.BaseRegNum))
637      return false;
638    // Immediate offset, multiple of 4 in range [0, 62].
639    if (!Mem.OffsetImm) return true;
640    int64_t Val = Mem.OffsetImm->getValue();
641    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
642  }
643  bool isMemThumbRIs1() const {
644    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
645        !isARMLowRegister(Mem.BaseRegNum))
646      return false;
647    // Immediate offset in range [0, 31].
648    if (!Mem.OffsetImm) return true;
649    int64_t Val = Mem.OffsetImm->getValue();
650    return Val >= 0 && Val <= 31;
651  }
652  bool isMemThumbSPI() const {
653    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
654      return false;
655    // Immediate offset, multiple of 4 in range [0, 1020].
656    if (!Mem.OffsetImm) return true;
657    int64_t Val = Mem.OffsetImm->getValue();
658    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
659  }
660  bool isMemImm8Offset() const {
661    if (Kind != Memory || Mem.OffsetRegNum != 0)
662      return false;
663    // Immediate offset in range [-255, 255].
664    if (!Mem.OffsetImm) return true;
665    int64_t Val = Mem.OffsetImm->getValue();
666    return Val > -256 && Val < 256;
667  }
668  bool isMemImm12Offset() const {
669    // If we have an immediate that's not a constant, treat it as a label
670    // reference needing a fixup. If it is a constant, it's something else
671    // and we reject it.
672    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
673      return true;
674
675    if (Kind != Memory || Mem.OffsetRegNum != 0)
676      return false;
677    // Immediate offset in range [-4095, 4095].
678    if (!Mem.OffsetImm) return true;
679    int64_t Val = Mem.OffsetImm->getValue();
680    return Val > -4096 && Val < 4096;
681  }
682  bool isPostIdxImm8() const {
683    if (Kind != Immediate)
684      return false;
685    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
686    if (!CE) return false;
687    int64_t Val = CE->getValue();
688    return Val > -256 && Val < 256;
689  }
690
691  bool isMSRMask() const { return Kind == MSRMask; }
692  bool isProcIFlags() const { return Kind == ProcIFlags; }
693
694  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
695    // Add as immediates when possible.  Null MCExpr = 0.
696    if (Expr == 0)
697      Inst.addOperand(MCOperand::CreateImm(0));
698    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
699      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
700    else
701      Inst.addOperand(MCOperand::CreateExpr(Expr));
702  }
703
704  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
705    assert(N == 2 && "Invalid number of operands!");
706    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
707    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
708    Inst.addOperand(MCOperand::CreateReg(RegNum));
709  }
710
711  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
712    assert(N == 1 && "Invalid number of operands!");
713    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
714  }
715
716  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
717    assert(N == 1 && "Invalid number of operands!");
718    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
719  }
720
721  void addCCOutOperands(MCInst &Inst, unsigned N) const {
722    assert(N == 1 && "Invalid number of operands!");
723    Inst.addOperand(MCOperand::CreateReg(getReg()));
724  }
725
726  void addRegOperands(MCInst &Inst, unsigned N) const {
727    assert(N == 1 && "Invalid number of operands!");
728    Inst.addOperand(MCOperand::CreateReg(getReg()));
729  }
730
731  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
732    assert(N == 3 && "Invalid number of operands!");
733    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
734    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
735    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
736    Inst.addOperand(MCOperand::CreateImm(
737      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
738  }
739
740  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
741    assert(N == 2 && "Invalid number of operands!");
742    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
743    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
744    Inst.addOperand(MCOperand::CreateImm(
745      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
746  }
747
748
749  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
750    assert(N == 1 && "Invalid number of operands!");
751    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
752                                         ShifterImm.Imm));
753  }
754
755  void addRegListOperands(MCInst &Inst, unsigned N) const {
756    assert(N == 1 && "Invalid number of operands!");
757    const SmallVectorImpl<unsigned> &RegList = getRegList();
758    for (SmallVectorImpl<unsigned>::const_iterator
759           I = RegList.begin(), E = RegList.end(); I != E; ++I)
760      Inst.addOperand(MCOperand::CreateReg(*I));
761  }
762
763  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
764    addRegListOperands(Inst, N);
765  }
766
767  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
768    addRegListOperands(Inst, N);
769  }
770
771  void addRotImmOperands(MCInst &Inst, unsigned N) const {
772    assert(N == 1 && "Invalid number of operands!");
773    // Encoded as val>>3. The printer handles display as 8, 16, 24.
774    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
775  }
776
777  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
778    assert(N == 1 && "Invalid number of operands!");
779    // Munge the lsb/width into a bitfield mask.
780    unsigned lsb = Bitfield.LSB;
781    unsigned width = Bitfield.Width;
782    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
783    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
784                      (32 - (lsb + width)));
785    Inst.addOperand(MCOperand::CreateImm(Mask));
786  }
787
788  void addImmOperands(MCInst &Inst, unsigned N) const {
789    assert(N == 1 && "Invalid number of operands!");
790    addExpr(Inst, getImm());
791  }
792
793  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
794    assert(N == 1 && "Invalid number of operands!");
795    addExpr(Inst, getImm());
796  }
797
798  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
799    assert(N == 1 && "Invalid number of operands!");
800    addExpr(Inst, getImm());
801  }
802
803  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
804    assert(N == 1 && "Invalid number of operands!");
805    addExpr(Inst, getImm());
806  }
807
808  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
809    assert(N == 1 && "Invalid number of operands!");
810    addExpr(Inst, getImm());
811  }
812
813  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
814    assert(N == 1 && "Invalid number of operands!");
815    // The constant encodes as the immediate-1, and we store in the instruction
816    // the bits as encoded, so subtract off one here.
817    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
819  }
820
821  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
822    assert(N == 1 && "Invalid number of operands!");
823    // The constant encodes as the immediate-1, and we store in the instruction
824    // the bits as encoded, so subtract off one here.
825    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
826    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
827  }
828
829  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
830    assert(N == 1 && "Invalid number of operands!");
831    addExpr(Inst, getImm());
832  }
833
834  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
835    assert(N == 1 && "Invalid number of operands!");
836    addExpr(Inst, getImm());
837  }
838
839  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
840    assert(N == 1 && "Invalid number of operands!");
841    addExpr(Inst, getImm());
842  }
843
844  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
845    assert(N == 1 && "Invalid number of operands!");
846    // The constant encodes as the immediate, except for 32, which encodes as
847    // zero.
848    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
849    unsigned Imm = CE->getValue();
850    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
851  }
852
853  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
854    assert(N == 1 && "Invalid number of operands!");
855    addExpr(Inst, getImm());
856  }
857
858  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
859    assert(N == 1 && "Invalid number of operands!");
860    // An ASR value of 32 encodes as 0, so that's how we want to add it to
861    // the instruction as well.
862    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
863    int Val = CE->getValue();
864    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
865  }
866
867  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
868    assert(N == 1 && "Invalid number of operands!");
869    addExpr(Inst, getImm());
870  }
871
872  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
873    assert(N == 1 && "Invalid number of operands!");
874    addExpr(Inst, getImm());
875  }
876
877  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
878    assert(N == 1 && "Invalid number of operands!");
879    addExpr(Inst, getImm());
880  }
881
882  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
883    assert(N == 1 && "Invalid number of operands!");
884    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
885  }
886
887  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
888    assert(N == 1 && "Invalid number of operands!");
889    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
890  }
891
892  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
893    assert(N == 3 && "Invalid number of operands!");
894    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
895    if (!Mem.OffsetRegNum) {
896      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
897      // Special case for #-0
898      if (Val == INT32_MIN) Val = 0;
899      if (Val < 0) Val = -Val;
900      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
901    } else {
902      // For register offset, we encode the shift type and negation flag
903      // here.
904      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
905                              Mem.ShiftImm, Mem.ShiftType);
906    }
907    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
908    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
909    Inst.addOperand(MCOperand::CreateImm(Val));
910  }
911
912  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
913    assert(N == 2 && "Invalid number of operands!");
914    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
915    assert(CE && "non-constant AM2OffsetImm operand!");
916    int32_t Val = CE->getValue();
917    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
918    // Special case for #-0
919    if (Val == INT32_MIN) Val = 0;
920    if (Val < 0) Val = -Val;
921    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
922    Inst.addOperand(MCOperand::CreateReg(0));
923    Inst.addOperand(MCOperand::CreateImm(Val));
924  }
925
926  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
927    assert(N == 3 && "Invalid number of operands!");
928    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
929    if (!Mem.OffsetRegNum) {
930      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
931      // Special case for #-0
932      if (Val == INT32_MIN) Val = 0;
933      if (Val < 0) Val = -Val;
934      Val = ARM_AM::getAM3Opc(AddSub, Val);
935    } else {
936      // For register offset, we encode the shift type and negation flag
937      // here.
938      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
939    }
940    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
941    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
942    Inst.addOperand(MCOperand::CreateImm(Val));
943  }
944
945  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
946    assert(N == 2 && "Invalid number of operands!");
947    if (Kind == PostIndexRegister) {
948      int32_t Val =
949        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
950      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
951      Inst.addOperand(MCOperand::CreateImm(Val));
952      return;
953    }
954
955    // Constant offset.
956    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
957    int32_t Val = CE->getValue();
958    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
959    // Special case for #-0
960    if (Val == INT32_MIN) Val = 0;
961    if (Val < 0) Val = -Val;
962    Val = ARM_AM::getAM3Opc(AddSub, Val);
963    Inst.addOperand(MCOperand::CreateReg(0));
964    Inst.addOperand(MCOperand::CreateImm(Val));
965  }
966
967  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
968    assert(N == 2 && "Invalid number of operands!");
969    // The lower two bits are always zero and as such are not encoded.
970    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
971    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
972    // Special case for #-0
973    if (Val == INT32_MIN) Val = 0;
974    if (Val < 0) Val = -Val;
975    Val = ARM_AM::getAM5Opc(AddSub, Val);
976    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
977    Inst.addOperand(MCOperand::CreateImm(Val));
978  }
979
980  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
981    assert(N == 2 && "Invalid number of operands!");
982    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
983    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
984    Inst.addOperand(MCOperand::CreateImm(Val));
985  }
986
987  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
988    assert(N == 2 && "Invalid number of operands!");
989    // If this is an immediate, it's a label reference.
990    if (Kind == Immediate) {
991      addExpr(Inst, getImm());
992      Inst.addOperand(MCOperand::CreateImm(0));
993      return;
994    }
995
996    // Otherwise, it's a normal memory reg+offset.
997    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
998    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
999    Inst.addOperand(MCOperand::CreateImm(Val));
1000  }
1001
1002  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1003    assert(N == 3 && "Invalid number of operands!");
1004    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1005                                     Mem.ShiftImm, Mem.ShiftType);
1006    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1007    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1008    Inst.addOperand(MCOperand::CreateImm(Val));
1009  }
1010
1011  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1012    assert(N == 2 && "Invalid number of operands!");
1013    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1014    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1015  }
1016
1017  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1018    assert(N == 2 && "Invalid number of operands!");
1019    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1020    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1021    Inst.addOperand(MCOperand::CreateImm(Val));
1022  }
1023
1024  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1025    assert(N == 2 && "Invalid number of operands!");
1026    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1027    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1028    Inst.addOperand(MCOperand::CreateImm(Val));
1029  }
1030
1031  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1032    assert(N == 2 && "Invalid number of operands!");
1033    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1034    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1035    Inst.addOperand(MCOperand::CreateImm(Val));
1036  }
1037
1038  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1039    assert(N == 2 && "Invalid number of operands!");
1040    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1041    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1042    Inst.addOperand(MCOperand::CreateImm(Val));
1043  }
1044
1045  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1046    assert(N == 1 && "Invalid number of operands!");
1047    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048    assert(CE && "non-constant post-idx-imm8 operand!");
1049    int Imm = CE->getValue();
1050    bool isAdd = Imm >= 0;
1051    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1052    Inst.addOperand(MCOperand::CreateImm(Imm));
1053  }
1054
1055  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1056    assert(N == 2 && "Invalid number of operands!");
1057    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1058    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1059  }
1060
1061  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1062    assert(N == 2 && "Invalid number of operands!");
1063    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1064    // The sign, shift type, and shift amount are encoded in a single operand
1065    // using the AM2 encoding helpers.
1066    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1067    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1068                                     PostIdxReg.ShiftTy);
1069    Inst.addOperand(MCOperand::CreateImm(Imm));
1070  }
1071
1072  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1073    assert(N == 1 && "Invalid number of operands!");
1074    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1075  }
1076
1077  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1078    assert(N == 1 && "Invalid number of operands!");
1079    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1080  }
1081
1082  virtual void print(raw_ostream &OS) const;
1083
1084  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1085    ARMOperand *Op = new ARMOperand(CondCode);
1086    Op->CC.Val = CC;
1087    Op->StartLoc = S;
1088    Op->EndLoc = S;
1089    return Op;
1090  }
1091
1092  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1093    ARMOperand *Op = new ARMOperand(CoprocNum);
1094    Op->Cop.Val = CopVal;
1095    Op->StartLoc = S;
1096    Op->EndLoc = S;
1097    return Op;
1098  }
1099
1100  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1101    ARMOperand *Op = new ARMOperand(CoprocReg);
1102    Op->Cop.Val = CopVal;
1103    Op->StartLoc = S;
1104    Op->EndLoc = S;
1105    return Op;
1106  }
1107
1108  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1109    ARMOperand *Op = new ARMOperand(CCOut);
1110    Op->Reg.RegNum = RegNum;
1111    Op->StartLoc = S;
1112    Op->EndLoc = S;
1113    return Op;
1114  }
1115
1116  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1117    ARMOperand *Op = new ARMOperand(Token);
1118    Op->Tok.Data = Str.data();
1119    Op->Tok.Length = Str.size();
1120    Op->StartLoc = S;
1121    Op->EndLoc = S;
1122    return Op;
1123  }
1124
1125  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1126    ARMOperand *Op = new ARMOperand(Register);
1127    Op->Reg.RegNum = RegNum;
1128    Op->StartLoc = S;
1129    Op->EndLoc = E;
1130    return Op;
1131  }
1132
1133  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1134                                           unsigned SrcReg,
1135                                           unsigned ShiftReg,
1136                                           unsigned ShiftImm,
1137                                           SMLoc S, SMLoc E) {
1138    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1139    Op->RegShiftedReg.ShiftTy = ShTy;
1140    Op->RegShiftedReg.SrcReg = SrcReg;
1141    Op->RegShiftedReg.ShiftReg = ShiftReg;
1142    Op->RegShiftedReg.ShiftImm = ShiftImm;
1143    Op->StartLoc = S;
1144    Op->EndLoc = E;
1145    return Op;
1146  }
1147
1148  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1149                                            unsigned SrcReg,
1150                                            unsigned ShiftImm,
1151                                            SMLoc S, SMLoc E) {
1152    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1153    Op->RegShiftedImm.ShiftTy = ShTy;
1154    Op->RegShiftedImm.SrcReg = SrcReg;
1155    Op->RegShiftedImm.ShiftImm = ShiftImm;
1156    Op->StartLoc = S;
1157    Op->EndLoc = E;
1158    return Op;
1159  }
1160
1161  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1162                                   SMLoc S, SMLoc E) {
1163    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1164    Op->ShifterImm.isASR = isASR;
1165    Op->ShifterImm.Imm = Imm;
1166    Op->StartLoc = S;
1167    Op->EndLoc = E;
1168    return Op;
1169  }
1170
1171  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1172    ARMOperand *Op = new ARMOperand(RotateImmediate);
1173    Op->RotImm.Imm = Imm;
1174    Op->StartLoc = S;
1175    Op->EndLoc = E;
1176    return Op;
1177  }
1178
1179  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1180                                    SMLoc S, SMLoc E) {
1181    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1182    Op->Bitfield.LSB = LSB;
1183    Op->Bitfield.Width = Width;
1184    Op->StartLoc = S;
1185    Op->EndLoc = E;
1186    return Op;
1187  }
1188
1189  static ARMOperand *
1190  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1191                SMLoc StartLoc, SMLoc EndLoc) {
1192    KindTy Kind = RegisterList;
1193
1194    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1195        contains(Regs.front().first))
1196      Kind = DPRRegisterList;
1197    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1198             contains(Regs.front().first))
1199      Kind = SPRRegisterList;
1200
1201    ARMOperand *Op = new ARMOperand(Kind);
1202    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1203           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1204      Op->Registers.push_back(I->first);
1205    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1206    Op->StartLoc = StartLoc;
1207    Op->EndLoc = EndLoc;
1208    return Op;
1209  }
1210
1211  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1212    ARMOperand *Op = new ARMOperand(Immediate);
1213    Op->Imm.Val = Val;
1214    Op->StartLoc = S;
1215    Op->EndLoc = E;
1216    return Op;
1217  }
1218
1219  static ARMOperand *CreateMem(unsigned BaseRegNum,
1220                               const MCConstantExpr *OffsetImm,
1221                               unsigned OffsetRegNum,
1222                               ARM_AM::ShiftOpc ShiftType,
1223                               unsigned ShiftImm,
1224                               bool isNegative,
1225                               SMLoc S, SMLoc E) {
1226    ARMOperand *Op = new ARMOperand(Memory);
1227    Op->Mem.BaseRegNum = BaseRegNum;
1228    Op->Mem.OffsetImm = OffsetImm;
1229    Op->Mem.OffsetRegNum = OffsetRegNum;
1230    Op->Mem.ShiftType = ShiftType;
1231    Op->Mem.ShiftImm = ShiftImm;
1232    Op->Mem.isNegative = isNegative;
1233    Op->StartLoc = S;
1234    Op->EndLoc = E;
1235    return Op;
1236  }
1237
1238  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1239                                      ARM_AM::ShiftOpc ShiftTy,
1240                                      unsigned ShiftImm,
1241                                      SMLoc S, SMLoc E) {
1242    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1243    Op->PostIdxReg.RegNum = RegNum;
1244    Op->PostIdxReg.isAdd = isAdd;
1245    Op->PostIdxReg.ShiftTy = ShiftTy;
1246    Op->PostIdxReg.ShiftImm = ShiftImm;
1247    Op->StartLoc = S;
1248    Op->EndLoc = E;
1249    return Op;
1250  }
1251
1252  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1253    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1254    Op->MBOpt.Val = Opt;
1255    Op->StartLoc = S;
1256    Op->EndLoc = S;
1257    return Op;
1258  }
1259
1260  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1261    ARMOperand *Op = new ARMOperand(ProcIFlags);
1262    Op->IFlags.Val = IFlags;
1263    Op->StartLoc = S;
1264    Op->EndLoc = S;
1265    return Op;
1266  }
1267
1268  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1269    ARMOperand *Op = new ARMOperand(MSRMask);
1270    Op->MMask.Val = MMask;
1271    Op->StartLoc = S;
1272    Op->EndLoc = S;
1273    return Op;
1274  }
1275};
1276
1277} // end anonymous namespace.
1278
1279void ARMOperand::print(raw_ostream &OS) const {
1280  switch (Kind) {
1281  case CondCode:
1282    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1283    break;
1284  case CCOut:
1285    OS << "<ccout " << getReg() << ">";
1286    break;
1287  case CoprocNum:
1288    OS << "<coprocessor number: " << getCoproc() << ">";
1289    break;
1290  case CoprocReg:
1291    OS << "<coprocessor register: " << getCoproc() << ">";
1292    break;
1293  case MSRMask:
1294    OS << "<mask: " << getMSRMask() << ">";
1295    break;
1296  case Immediate:
1297    getImm()->print(OS);
1298    break;
1299  case MemBarrierOpt:
1300    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1301    break;
1302  case Memory:
1303    OS << "<memory "
1304       << " base:" << Mem.BaseRegNum;
1305    OS << ">";
1306    break;
1307  case PostIndexRegister:
1308    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1309       << PostIdxReg.RegNum;
1310    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1311      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1312         << PostIdxReg.ShiftImm;
1313    OS << ">";
1314    break;
1315  case ProcIFlags: {
1316    OS << "<ARM_PROC::";
1317    unsigned IFlags = getProcIFlags();
1318    for (int i=2; i >= 0; --i)
1319      if (IFlags & (1 << i))
1320        OS << ARM_PROC::IFlagsToString(1 << i);
1321    OS << ">";
1322    break;
1323  }
1324  case Register:
1325    OS << "<register " << getReg() << ">";
1326    break;
1327  case ShifterImmediate:
1328    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1329       << " #" << ShifterImm.Imm << ">";
1330    break;
1331  case ShiftedRegister:
1332    OS << "<so_reg_reg "
1333       << RegShiftedReg.SrcReg
1334       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1335       << ", " << RegShiftedReg.ShiftReg << ", "
1336       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1337       << ">";
1338    break;
1339  case ShiftedImmediate:
1340    OS << "<so_reg_imm "
1341       << RegShiftedImm.SrcReg
1342       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1343       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1344       << ">";
1345    break;
1346  case RotateImmediate:
1347    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1348    break;
1349  case BitfieldDescriptor:
1350    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1351       << ", width: " << Bitfield.Width << ">";
1352    break;
1353  case RegisterList:
1354  case DPRRegisterList:
1355  case SPRRegisterList: {
1356    OS << "<register_list ";
1357
1358    const SmallVectorImpl<unsigned> &RegList = getRegList();
1359    for (SmallVectorImpl<unsigned>::const_iterator
1360           I = RegList.begin(), E = RegList.end(); I != E; ) {
1361      OS << *I;
1362      if (++I < E) OS << ", ";
1363    }
1364
1365    OS << ">";
1366    break;
1367  }
1368  case Token:
1369    OS << "'" << getToken() << "'";
1370    break;
1371  }
1372}
1373
1374/// @name Auto-generated Match Functions
1375/// {
1376
1377static unsigned MatchRegisterName(StringRef Name);
1378
1379/// }
1380
1381bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1382                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1383  RegNo = tryParseRegister();
1384
1385  return (RegNo == (unsigned)-1);
1386}
1387
1388/// Try to parse a register name.  The token must be an Identifier when called,
1389/// and if it is a register name the token is eaten and the register number is
1390/// returned.  Otherwise return -1.
1391///
1392int ARMAsmParser::tryParseRegister() {
1393  const AsmToken &Tok = Parser.getTok();
1394  if (Tok.isNot(AsmToken::Identifier)) return -1;
1395
1396  // FIXME: Validate register for the current architecture; we have to do
1397  // validation later, so maybe there is no need for this here.
1398  std::string upperCase = Tok.getString().str();
1399  std::string lowerCase = LowercaseString(upperCase);
1400  unsigned RegNum = MatchRegisterName(lowerCase);
1401  if (!RegNum) {
1402    RegNum = StringSwitch<unsigned>(lowerCase)
1403      .Case("r13", ARM::SP)
1404      .Case("r14", ARM::LR)
1405      .Case("r15", ARM::PC)
1406      .Case("ip", ARM::R12)
1407      .Default(0);
1408  }
1409  if (!RegNum) return -1;
1410
1411  Parser.Lex(); // Eat identifier token.
1412  return RegNum;
1413}
1414
1415// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1416// If a recoverable error occurs, return 1. If an irrecoverable error
1417// occurs, return -1. An irrecoverable error is one where tokens have been
1418// consumed in the process of trying to parse the shifter (i.e., when it is
1419// indeed a shifter operand, but malformed).
1420int ARMAsmParser::tryParseShiftRegister(
1421                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1422  SMLoc S = Parser.getTok().getLoc();
1423  const AsmToken &Tok = Parser.getTok();
1424  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1425
1426  std::string upperCase = Tok.getString().str();
1427  std::string lowerCase = LowercaseString(upperCase);
1428  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1429      .Case("lsl", ARM_AM::lsl)
1430      .Case("lsr", ARM_AM::lsr)
1431      .Case("asr", ARM_AM::asr)
1432      .Case("ror", ARM_AM::ror)
1433      .Case("rrx", ARM_AM::rrx)
1434      .Default(ARM_AM::no_shift);
1435
1436  if (ShiftTy == ARM_AM::no_shift)
1437    return 1;
1438
1439  Parser.Lex(); // Eat the operator.
1440
1441  // The source register for the shift has already been added to the
1442  // operand list, so we need to pop it off and combine it into the shifted
1443  // register operand instead.
1444  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1445  if (!PrevOp->isReg())
1446    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1447  int SrcReg = PrevOp->getReg();
1448  int64_t Imm = 0;
1449  int ShiftReg = 0;
1450  if (ShiftTy == ARM_AM::rrx) {
1451    // RRX Doesn't have an explicit shift amount. The encoder expects
1452    // the shift register to be the same as the source register. Seems odd,
1453    // but OK.
1454    ShiftReg = SrcReg;
1455  } else {
1456    // Figure out if this is shifted by a constant or a register (for non-RRX).
1457    if (Parser.getTok().is(AsmToken::Hash)) {
1458      Parser.Lex(); // Eat hash.
1459      SMLoc ImmLoc = Parser.getTok().getLoc();
1460      const MCExpr *ShiftExpr = 0;
1461      if (getParser().ParseExpression(ShiftExpr)) {
1462        Error(ImmLoc, "invalid immediate shift value");
1463        return -1;
1464      }
1465      // The expression must be evaluatable as an immediate.
1466      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1467      if (!CE) {
1468        Error(ImmLoc, "invalid immediate shift value");
1469        return -1;
1470      }
1471      // Range check the immediate.
1472      // lsl, ror: 0 <= imm <= 31
1473      // lsr, asr: 0 <= imm <= 32
1474      Imm = CE->getValue();
1475      if (Imm < 0 ||
1476          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1477          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1478        Error(ImmLoc, "immediate shift value out of range");
1479        return -1;
1480      }
1481    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1482      ShiftReg = tryParseRegister();
1483      SMLoc L = Parser.getTok().getLoc();
1484      if (ShiftReg == -1) {
1485        Error (L, "expected immediate or register in shift operand");
1486        return -1;
1487      }
1488    } else {
1489      Error (Parser.getTok().getLoc(),
1490                    "expected immediate or register in shift operand");
1491      return -1;
1492    }
1493  }
1494
1495  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1496    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1497                                                         ShiftReg, Imm,
1498                                               S, Parser.getTok().getLoc()));
1499  else
1500    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1501                                               S, Parser.getTok().getLoc()));
1502
1503  return 0;
1504}
1505
1506
1507/// Try to parse a register name.  The token must be an Identifier when called.
1508/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1509/// if there is a "writeback". 'true' if it's not a register.
1510///
1511/// TODO this is likely to change to allow different register types and or to
1512/// parse for a specific register type.
1513bool ARMAsmParser::
1514tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1515  SMLoc S = Parser.getTok().getLoc();
1516  int RegNo = tryParseRegister();
1517  if (RegNo == -1)
1518    return true;
1519
1520  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1521
1522  const AsmToken &ExclaimTok = Parser.getTok();
1523  if (ExclaimTok.is(AsmToken::Exclaim)) {
1524    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1525                                               ExclaimTok.getLoc()));
1526    Parser.Lex(); // Eat exclaim token
1527  }
1528
1529  return false;
1530}
1531
1532/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1533/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1534/// "c5", ...
1535static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1536  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1537  // but efficient.
1538  switch (Name.size()) {
1539  default: break;
1540  case 2:
1541    if (Name[0] != CoprocOp)
1542      return -1;
1543    switch (Name[1]) {
1544    default:  return -1;
1545    case '0': return 0;
1546    case '1': return 1;
1547    case '2': return 2;
1548    case '3': return 3;
1549    case '4': return 4;
1550    case '5': return 5;
1551    case '6': return 6;
1552    case '7': return 7;
1553    case '8': return 8;
1554    case '9': return 9;
1555    }
1556    break;
1557  case 3:
1558    if (Name[0] != CoprocOp || Name[1] != '1')
1559      return -1;
1560    switch (Name[2]) {
1561    default:  return -1;
1562    case '0': return 10;
1563    case '1': return 11;
1564    case '2': return 12;
1565    case '3': return 13;
1566    case '4': return 14;
1567    case '5': return 15;
1568    }
1569    break;
1570  }
1571
1572  return -1;
1573}
1574
1575/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1576/// token must be an Identifier when called, and if it is a coprocessor
1577/// number, the token is eaten and the operand is added to the operand list.
1578ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1579parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1580  SMLoc S = Parser.getTok().getLoc();
1581  const AsmToken &Tok = Parser.getTok();
1582  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1583
1584  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1585  if (Num == -1)
1586    return MatchOperand_NoMatch;
1587
1588  Parser.Lex(); // Eat identifier token.
1589  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1590  return MatchOperand_Success;
1591}
1592
1593/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1594/// token must be an Identifier when called, and if it is a coprocessor
1595/// number, the token is eaten and the operand is added to the operand list.
1596ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1597parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1598  SMLoc S = Parser.getTok().getLoc();
1599  const AsmToken &Tok = Parser.getTok();
1600  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1601
1602  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1603  if (Reg == -1)
1604    return MatchOperand_NoMatch;
1605
1606  Parser.Lex(); // Eat identifier token.
1607  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1608  return MatchOperand_Success;
1609}
1610
1611/// Parse a register list, return it if successful else return null.  The first
1612/// token must be a '{' when called.
1613bool ARMAsmParser::
1614parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1615  assert(Parser.getTok().is(AsmToken::LCurly) &&
1616         "Token is not a Left Curly Brace");
1617  SMLoc S = Parser.getTok().getLoc();
1618
1619  // Read the rest of the registers in the list.
1620  unsigned PrevRegNum = 0;
1621  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1622
1623  do {
1624    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1625    Parser.Lex(); // Eat non-identifier token.
1626
1627    const AsmToken &RegTok = Parser.getTok();
1628    SMLoc RegLoc = RegTok.getLoc();
1629    if (RegTok.isNot(AsmToken::Identifier)) {
1630      Error(RegLoc, "register expected");
1631      return true;
1632    }
1633
1634    int RegNum = tryParseRegister();
1635    if (RegNum == -1) {
1636      Error(RegLoc, "register expected");
1637      return true;
1638    }
1639
1640    if (IsRange) {
1641      int Reg = PrevRegNum;
1642      do {
1643        ++Reg;
1644        Registers.push_back(std::make_pair(Reg, RegLoc));
1645      } while (Reg != RegNum);
1646    } else {
1647      Registers.push_back(std::make_pair(RegNum, RegLoc));
1648    }
1649
1650    PrevRegNum = RegNum;
1651  } while (Parser.getTok().is(AsmToken::Comma) ||
1652           Parser.getTok().is(AsmToken::Minus));
1653
1654  // Process the right curly brace of the list.
1655  const AsmToken &RCurlyTok = Parser.getTok();
1656  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1657    Error(RCurlyTok.getLoc(), "'}' expected");
1658    return true;
1659  }
1660
1661  SMLoc E = RCurlyTok.getLoc();
1662  Parser.Lex(); // Eat right curly brace token.
1663
1664  // Verify the register list.
1665  bool EmittedWarning = false;
1666  unsigned HighRegNum = 0;
1667  BitVector RegMap(32);
1668  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1669    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1670    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1671
1672    if (RegMap[Reg]) {
1673      Error(RegInfo.second, "register duplicated in register list");
1674      return true;
1675    }
1676
1677    if (!EmittedWarning && Reg < HighRegNum)
1678      Warning(RegInfo.second,
1679              "register not in ascending order in register list");
1680
1681    RegMap.set(Reg);
1682    HighRegNum = std::max(Reg, HighRegNum);
1683  }
1684
1685  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1686  return false;
1687}
1688
1689/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1690ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1691parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1692  SMLoc S = Parser.getTok().getLoc();
1693  const AsmToken &Tok = Parser.getTok();
1694  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1695  StringRef OptStr = Tok.getString();
1696
1697  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1698    .Case("sy",    ARM_MB::SY)
1699    .Case("st",    ARM_MB::ST)
1700    .Case("sh",    ARM_MB::ISH)
1701    .Case("ish",   ARM_MB::ISH)
1702    .Case("shst",  ARM_MB::ISHST)
1703    .Case("ishst", ARM_MB::ISHST)
1704    .Case("nsh",   ARM_MB::NSH)
1705    .Case("un",    ARM_MB::NSH)
1706    .Case("nshst", ARM_MB::NSHST)
1707    .Case("unst",  ARM_MB::NSHST)
1708    .Case("osh",   ARM_MB::OSH)
1709    .Case("oshst", ARM_MB::OSHST)
1710    .Default(~0U);
1711
1712  if (Opt == ~0U)
1713    return MatchOperand_NoMatch;
1714
1715  Parser.Lex(); // Eat identifier token.
1716  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1717  return MatchOperand_Success;
1718}
1719
1720/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1721ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1722parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1723  SMLoc S = Parser.getTok().getLoc();
1724  const AsmToken &Tok = Parser.getTok();
1725  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1726  StringRef IFlagsStr = Tok.getString();
1727
1728  unsigned IFlags = 0;
1729  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1730    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1731    .Case("a", ARM_PROC::A)
1732    .Case("i", ARM_PROC::I)
1733    .Case("f", ARM_PROC::F)
1734    .Default(~0U);
1735
1736    // If some specific iflag is already set, it means that some letter is
1737    // present more than once, this is not acceptable.
1738    if (Flag == ~0U || (IFlags & Flag))
1739      return MatchOperand_NoMatch;
1740
1741    IFlags |= Flag;
1742  }
1743
1744  Parser.Lex(); // Eat identifier token.
1745  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1746  return MatchOperand_Success;
1747}
1748
1749/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1750ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1751parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1752  SMLoc S = Parser.getTok().getLoc();
1753  const AsmToken &Tok = Parser.getTok();
1754  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1755  StringRef Mask = Tok.getString();
1756
1757  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1758  size_t Start = 0, Next = Mask.find('_');
1759  StringRef Flags = "";
1760  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1761  if (Next != StringRef::npos)
1762    Flags = Mask.slice(Next+1, Mask.size());
1763
1764  // FlagsVal contains the complete mask:
1765  // 3-0: Mask
1766  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1767  unsigned FlagsVal = 0;
1768
1769  if (SpecReg == "apsr") {
1770    FlagsVal = StringSwitch<unsigned>(Flags)
1771    .Case("nzcvq",  0x8) // same as CPSR_f
1772    .Case("g",      0x4) // same as CPSR_s
1773    .Case("nzcvqg", 0xc) // same as CPSR_fs
1774    .Default(~0U);
1775
1776    if (FlagsVal == ~0U) {
1777      if (!Flags.empty())
1778        return MatchOperand_NoMatch;
1779      else
1780        FlagsVal = 0; // No flag
1781    }
1782  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1783    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1784      Flags = "fc";
1785    for (int i = 0, e = Flags.size(); i != e; ++i) {
1786      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1787      .Case("c", 1)
1788      .Case("x", 2)
1789      .Case("s", 4)
1790      .Case("f", 8)
1791      .Default(~0U);
1792
1793      // If some specific flag is already set, it means that some letter is
1794      // present more than once, this is not acceptable.
1795      if (FlagsVal == ~0U || (FlagsVal & Flag))
1796        return MatchOperand_NoMatch;
1797      FlagsVal |= Flag;
1798    }
1799  } else // No match for special register.
1800    return MatchOperand_NoMatch;
1801
1802  // Special register without flags are equivalent to "fc" flags.
1803  if (!FlagsVal)
1804    FlagsVal = 0x9;
1805
1806  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1807  if (SpecReg == "spsr")
1808    FlagsVal |= 16;
1809
1810  Parser.Lex(); // Eat identifier token.
1811  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1812  return MatchOperand_Success;
1813}
1814
1815ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1816parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1817            int Low, int High) {
1818  const AsmToken &Tok = Parser.getTok();
1819  if (Tok.isNot(AsmToken::Identifier)) {
1820    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1821    return MatchOperand_ParseFail;
1822  }
1823  StringRef ShiftName = Tok.getString();
1824  std::string LowerOp = LowercaseString(Op);
1825  std::string UpperOp = UppercaseString(Op);
1826  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1827    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1828    return MatchOperand_ParseFail;
1829  }
1830  Parser.Lex(); // Eat shift type token.
1831
1832  // There must be a '#' and a shift amount.
1833  if (Parser.getTok().isNot(AsmToken::Hash)) {
1834    Error(Parser.getTok().getLoc(), "'#' expected");
1835    return MatchOperand_ParseFail;
1836  }
1837  Parser.Lex(); // Eat hash token.
1838
1839  const MCExpr *ShiftAmount;
1840  SMLoc Loc = Parser.getTok().getLoc();
1841  if (getParser().ParseExpression(ShiftAmount)) {
1842    Error(Loc, "illegal expression");
1843    return MatchOperand_ParseFail;
1844  }
1845  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1846  if (!CE) {
1847    Error(Loc, "constant expression expected");
1848    return MatchOperand_ParseFail;
1849  }
1850  int Val = CE->getValue();
1851  if (Val < Low || Val > High) {
1852    Error(Loc, "immediate value out of range");
1853    return MatchOperand_ParseFail;
1854  }
1855
1856  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1857
1858  return MatchOperand_Success;
1859}
1860
1861ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1862parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1863  const AsmToken &Tok = Parser.getTok();
1864  SMLoc S = Tok.getLoc();
1865  if (Tok.isNot(AsmToken::Identifier)) {
1866    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1867    return MatchOperand_ParseFail;
1868  }
1869  int Val = StringSwitch<int>(Tok.getString())
1870    .Case("be", 1)
1871    .Case("le", 0)
1872    .Default(-1);
1873  Parser.Lex(); // Eat the token.
1874
1875  if (Val == -1) {
1876    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1877    return MatchOperand_ParseFail;
1878  }
1879  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1880                                                                  getContext()),
1881                                           S, Parser.getTok().getLoc()));
1882  return MatchOperand_Success;
1883}
1884
1885/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1886/// instructions. Legal values are:
1887///     lsl #n  'n' in [0,31]
1888///     asr #n  'n' in [1,32]
1889///             n == 32 encoded as n == 0.
1890ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1891parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1892  const AsmToken &Tok = Parser.getTok();
1893  SMLoc S = Tok.getLoc();
1894  if (Tok.isNot(AsmToken::Identifier)) {
1895    Error(S, "shift operator 'asr' or 'lsl' expected");
1896    return MatchOperand_ParseFail;
1897  }
1898  StringRef ShiftName = Tok.getString();
1899  bool isASR;
1900  if (ShiftName == "lsl" || ShiftName == "LSL")
1901    isASR = false;
1902  else if (ShiftName == "asr" || ShiftName == "ASR")
1903    isASR = true;
1904  else {
1905    Error(S, "shift operator 'asr' or 'lsl' expected");
1906    return MatchOperand_ParseFail;
1907  }
1908  Parser.Lex(); // Eat the operator.
1909
1910  // A '#' and a shift amount.
1911  if (Parser.getTok().isNot(AsmToken::Hash)) {
1912    Error(Parser.getTok().getLoc(), "'#' expected");
1913    return MatchOperand_ParseFail;
1914  }
1915  Parser.Lex(); // Eat hash token.
1916
1917  const MCExpr *ShiftAmount;
1918  SMLoc E = Parser.getTok().getLoc();
1919  if (getParser().ParseExpression(ShiftAmount)) {
1920    Error(E, "malformed shift expression");
1921    return MatchOperand_ParseFail;
1922  }
1923  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1924  if (!CE) {
1925    Error(E, "shift amount must be an immediate");
1926    return MatchOperand_ParseFail;
1927  }
1928
1929  int64_t Val = CE->getValue();
1930  if (isASR) {
1931    // Shift amount must be in [1,32]
1932    if (Val < 1 || Val > 32) {
1933      Error(E, "'asr' shift amount must be in range [1,32]");
1934      return MatchOperand_ParseFail;
1935    }
1936    // asr #32 encoded as asr #0.
1937    if (Val == 32) Val = 0;
1938  } else {
1939    // Shift amount must be in [1,32]
1940    if (Val < 0 || Val > 31) {
1941      Error(E, "'lsr' shift amount must be in range [0,31]");
1942      return MatchOperand_ParseFail;
1943    }
1944  }
1945
1946  E = Parser.getTok().getLoc();
1947  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1948
1949  return MatchOperand_Success;
1950}
1951
1952/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1953/// of instructions. Legal values are:
1954///     ror #n  'n' in {0, 8, 16, 24}
1955ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1956parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1957  const AsmToken &Tok = Parser.getTok();
1958  SMLoc S = Tok.getLoc();
1959  if (Tok.isNot(AsmToken::Identifier)) {
1960    Error(S, "rotate operator 'ror' expected");
1961    return MatchOperand_ParseFail;
1962  }
1963  StringRef ShiftName = Tok.getString();
1964  if (ShiftName != "ror" && ShiftName != "ROR") {
1965    Error(S, "rotate operator 'ror' expected");
1966    return MatchOperand_ParseFail;
1967  }
1968  Parser.Lex(); // Eat the operator.
1969
1970  // A '#' and a rotate amount.
1971  if (Parser.getTok().isNot(AsmToken::Hash)) {
1972    Error(Parser.getTok().getLoc(), "'#' expected");
1973    return MatchOperand_ParseFail;
1974  }
1975  Parser.Lex(); // Eat hash token.
1976
1977  const MCExpr *ShiftAmount;
1978  SMLoc E = Parser.getTok().getLoc();
1979  if (getParser().ParseExpression(ShiftAmount)) {
1980    Error(E, "malformed rotate expression");
1981    return MatchOperand_ParseFail;
1982  }
1983  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1984  if (!CE) {
1985    Error(E, "rotate amount must be an immediate");
1986    return MatchOperand_ParseFail;
1987  }
1988
1989  int64_t Val = CE->getValue();
1990  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1991  // normally, zero is represented in asm by omitting the rotate operand
1992  // entirely.
1993  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1994    Error(E, "'ror' rotate amount must be 8, 16, or 24");
1995    return MatchOperand_ParseFail;
1996  }
1997
1998  E = Parser.getTok().getLoc();
1999  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2000
2001  return MatchOperand_Success;
2002}
2003
2004ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2005parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2006  SMLoc S = Parser.getTok().getLoc();
2007  // The bitfield descriptor is really two operands, the LSB and the width.
2008  if (Parser.getTok().isNot(AsmToken::Hash)) {
2009    Error(Parser.getTok().getLoc(), "'#' expected");
2010    return MatchOperand_ParseFail;
2011  }
2012  Parser.Lex(); // Eat hash token.
2013
2014  const MCExpr *LSBExpr;
2015  SMLoc E = Parser.getTok().getLoc();
2016  if (getParser().ParseExpression(LSBExpr)) {
2017    Error(E, "malformed immediate expression");
2018    return MatchOperand_ParseFail;
2019  }
2020  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2021  if (!CE) {
2022    Error(E, "'lsb' operand must be an immediate");
2023    return MatchOperand_ParseFail;
2024  }
2025
2026  int64_t LSB = CE->getValue();
2027  // The LSB must be in the range [0,31]
2028  if (LSB < 0 || LSB > 31) {
2029    Error(E, "'lsb' operand must be in the range [0,31]");
2030    return MatchOperand_ParseFail;
2031  }
2032  E = Parser.getTok().getLoc();
2033
2034  // Expect another immediate operand.
2035  if (Parser.getTok().isNot(AsmToken::Comma)) {
2036    Error(Parser.getTok().getLoc(), "too few operands");
2037    return MatchOperand_ParseFail;
2038  }
2039  Parser.Lex(); // Eat hash token.
2040  if (Parser.getTok().isNot(AsmToken::Hash)) {
2041    Error(Parser.getTok().getLoc(), "'#' expected");
2042    return MatchOperand_ParseFail;
2043  }
2044  Parser.Lex(); // Eat hash token.
2045
2046  const MCExpr *WidthExpr;
2047  if (getParser().ParseExpression(WidthExpr)) {
2048    Error(E, "malformed immediate expression");
2049    return MatchOperand_ParseFail;
2050  }
2051  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2052  if (!CE) {
2053    Error(E, "'width' operand must be an immediate");
2054    return MatchOperand_ParseFail;
2055  }
2056
2057  int64_t Width = CE->getValue();
2058  // The LSB must be in the range [1,32-lsb]
2059  if (Width < 1 || Width > 32 - LSB) {
2060    Error(E, "'width' operand must be in the range [1,32-lsb]");
2061    return MatchOperand_ParseFail;
2062  }
2063  E = Parser.getTok().getLoc();
2064
2065  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2066
2067  return MatchOperand_Success;
2068}
2069
2070ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2071parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2072  // Check for a post-index addressing register operand. Specifically:
2073  // postidx_reg := '+' register {, shift}
2074  //              | '-' register {, shift}
2075  //              | register {, shift}
2076
2077  // This method must return MatchOperand_NoMatch without consuming any tokens
2078  // in the case where there is no match, as other alternatives take other
2079  // parse methods.
2080  AsmToken Tok = Parser.getTok();
2081  SMLoc S = Tok.getLoc();
2082  bool haveEaten = false;
2083  bool isAdd = true;
2084  int Reg = -1;
2085  if (Tok.is(AsmToken::Plus)) {
2086    Parser.Lex(); // Eat the '+' token.
2087    haveEaten = true;
2088  } else if (Tok.is(AsmToken::Minus)) {
2089    Parser.Lex(); // Eat the '-' token.
2090    isAdd = false;
2091    haveEaten = true;
2092  }
2093  if (Parser.getTok().is(AsmToken::Identifier))
2094    Reg = tryParseRegister();
2095  if (Reg == -1) {
2096    if (!haveEaten)
2097      return MatchOperand_NoMatch;
2098    Error(Parser.getTok().getLoc(), "register expected");
2099    return MatchOperand_ParseFail;
2100  }
2101  SMLoc E = Parser.getTok().getLoc();
2102
2103  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2104  unsigned ShiftImm = 0;
2105  if (Parser.getTok().is(AsmToken::Comma)) {
2106    Parser.Lex(); // Eat the ','.
2107    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2108      return MatchOperand_ParseFail;
2109  }
2110
2111  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2112                                                  ShiftImm, S, E));
2113
2114  return MatchOperand_Success;
2115}
2116
2117ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2118parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2119  // Check for a post-index addressing register operand. Specifically:
2120  // am3offset := '+' register
2121  //              | '-' register
2122  //              | register
2123  //              | # imm
2124  //              | # + imm
2125  //              | # - imm
2126
2127  // This method must return MatchOperand_NoMatch without consuming any tokens
2128  // in the case where there is no match, as other alternatives take other
2129  // parse methods.
2130  AsmToken Tok = Parser.getTok();
2131  SMLoc S = Tok.getLoc();
2132
2133  // Do immediates first, as we always parse those if we have a '#'.
2134  if (Parser.getTok().is(AsmToken::Hash)) {
2135    Parser.Lex(); // Eat the '#'.
2136    // Explicitly look for a '-', as we need to encode negative zero
2137    // differently.
2138    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2139    const MCExpr *Offset;
2140    if (getParser().ParseExpression(Offset))
2141      return MatchOperand_ParseFail;
2142    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2143    if (!CE) {
2144      Error(S, "constant expression expected");
2145      return MatchOperand_ParseFail;
2146    }
2147    SMLoc E = Tok.getLoc();
2148    // Negative zero is encoded as the flag value INT32_MIN.
2149    int32_t Val = CE->getValue();
2150    if (isNegative && Val == 0)
2151      Val = INT32_MIN;
2152
2153    Operands.push_back(
2154      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2155
2156    return MatchOperand_Success;
2157  }
2158
2159
2160  bool haveEaten = false;
2161  bool isAdd = true;
2162  int Reg = -1;
2163  if (Tok.is(AsmToken::Plus)) {
2164    Parser.Lex(); // Eat the '+' token.
2165    haveEaten = true;
2166  } else if (Tok.is(AsmToken::Minus)) {
2167    Parser.Lex(); // Eat the '-' token.
2168    isAdd = false;
2169    haveEaten = true;
2170  }
2171  if (Parser.getTok().is(AsmToken::Identifier))
2172    Reg = tryParseRegister();
2173  if (Reg == -1) {
2174    if (!haveEaten)
2175      return MatchOperand_NoMatch;
2176    Error(Parser.getTok().getLoc(), "register expected");
2177    return MatchOperand_ParseFail;
2178  }
2179  SMLoc E = Parser.getTok().getLoc();
2180
2181  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2182                                                  0, S, E));
2183
2184  return MatchOperand_Success;
2185}
2186
2187/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2188/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2189/// when they refer multiple MIOperands inside a single one.
2190bool ARMAsmParser::
2191cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2192                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2193  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2194
2195  // Create a writeback register dummy placeholder.
2196  Inst.addOperand(MCOperand::CreateImm(0));
2197
2198  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2199  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2200  return true;
2201}
2202
2203/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2204/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2205/// when they refer multiple MIOperands inside a single one.
2206bool ARMAsmParser::
2207cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2208                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2209  // Create a writeback register dummy placeholder.
2210  Inst.addOperand(MCOperand::CreateImm(0));
2211  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2212  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2213  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2214  return true;
2215}
2216
2217/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2218/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2219/// when they refer multiple MIOperands inside a single one.
2220bool ARMAsmParser::
2221cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2222                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2223  // Create a writeback register dummy placeholder.
2224  Inst.addOperand(MCOperand::CreateImm(0));
2225  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2226  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2227  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2228  return true;
2229}
2230
2231/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2232/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2233/// when they refer multiple MIOperands inside a single one.
2234bool ARMAsmParser::
2235cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2236                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2237  // Create a writeback register dummy placeholder.
2238  Inst.addOperand(MCOperand::CreateImm(0));
2239  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2240  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2241  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2242  return true;
2243}
2244
2245/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2246/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2247/// when they refer multiple MIOperands inside a single one.
2248bool ARMAsmParser::
2249cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2250                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2251  // Rt
2252  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2253  // Create a writeback register dummy placeholder.
2254  Inst.addOperand(MCOperand::CreateImm(0));
2255  // addr
2256  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2257  // offset
2258  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2259  // pred
2260  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2261  return true;
2262}
2263
2264/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2265/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2266/// when they refer multiple MIOperands inside a single one.
2267bool ARMAsmParser::
2268cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2269                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2270  // Rt
2271  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2272  // Create a writeback register dummy placeholder.
2273  Inst.addOperand(MCOperand::CreateImm(0));
2274  // addr
2275  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2276  // offset
2277  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2278  // pred
2279  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2280  return true;
2281}
2282
2283/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2284/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2285/// when they refer multiple MIOperands inside a single one.
2286bool ARMAsmParser::
2287cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2288                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2289  // Create a writeback register dummy placeholder.
2290  Inst.addOperand(MCOperand::CreateImm(0));
2291  // Rt
2292  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2293  // addr
2294  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2295  // offset
2296  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2297  // pred
2298  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2299  return true;
2300}
2301
2302/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2303/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2304/// when they refer multiple MIOperands inside a single one.
2305bool ARMAsmParser::
2306cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2307                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2308  // Create a writeback register dummy placeholder.
2309  Inst.addOperand(MCOperand::CreateImm(0));
2310  // Rt
2311  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2312  // addr
2313  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2314  // offset
2315  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2316  // pred
2317  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2318  return true;
2319}
2320
2321/// cvtLdrdPre - Convert parsed operands to MCInst.
2322/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2323/// when they refer multiple MIOperands inside a single one.
2324bool ARMAsmParser::
2325cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2326           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2327  // Rt, Rt2
2328  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2329  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2330  // Create a writeback register dummy placeholder.
2331  Inst.addOperand(MCOperand::CreateImm(0));
2332  // addr
2333  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2334  // pred
2335  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2336  return true;
2337}
2338
2339/// cvtStrdPre - Convert parsed operands to MCInst.
2340/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2341/// when they refer multiple MIOperands inside a single one.
2342bool ARMAsmParser::
2343cvtStrdPre(MCInst &Inst, unsigned Opcode,
2344           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2345  // Create a writeback register dummy placeholder.
2346  Inst.addOperand(MCOperand::CreateImm(0));
2347  // Rt, Rt2
2348  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2349  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2350  // addr
2351  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2352  // pred
2353  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2354  return true;
2355}
2356
2357/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2358/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2359/// when they refer multiple MIOperands inside a single one.
2360bool ARMAsmParser::
2361cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2362                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2363  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2364  // Create a writeback register dummy placeholder.
2365  Inst.addOperand(MCOperand::CreateImm(0));
2366  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2367  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2368  return true;
2369}
2370
2371/// cvtThumbMultiple- Convert parsed operands to MCInst.
2372/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2373/// when they refer multiple MIOperands inside a single one.
2374bool ARMAsmParser::
2375cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2376           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2377  // The second source operand must be the same register as the destination
2378  // operand.
2379  if (Operands.size() == 6 &&
2380      (((ARMOperand*)Operands[3])->getReg() !=
2381       ((ARMOperand*)Operands[5])->getReg()) &&
2382      (((ARMOperand*)Operands[3])->getReg() !=
2383       ((ARMOperand*)Operands[4])->getReg())) {
2384    Error(Operands[3]->getStartLoc(),
2385          "destination register must match source register");
2386    return false;
2387  }
2388  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2389  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2390  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2391  // If we have a three-operand form, use that, else the second source operand
2392  // is just the destination operand again.
2393  if (Operands.size() == 6)
2394    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2395  else
2396    Inst.addOperand(Inst.getOperand(0));
2397  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2398
2399  return true;
2400}
2401
2402/// Parse an ARM memory expression, return false if successful else return true
2403/// or an error.  The first token must be a '[' when called.
2404bool ARMAsmParser::
2405parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2406  SMLoc S, E;
2407  assert(Parser.getTok().is(AsmToken::LBrac) &&
2408         "Token is not a Left Bracket");
2409  S = Parser.getTok().getLoc();
2410  Parser.Lex(); // Eat left bracket token.
2411
2412  const AsmToken &BaseRegTok = Parser.getTok();
2413  int BaseRegNum = tryParseRegister();
2414  if (BaseRegNum == -1)
2415    return Error(BaseRegTok.getLoc(), "register expected");
2416
2417  // The next token must either be a comma or a closing bracket.
2418  const AsmToken &Tok = Parser.getTok();
2419  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2420    return Error(Tok.getLoc(), "malformed memory operand");
2421
2422  if (Tok.is(AsmToken::RBrac)) {
2423    E = Tok.getLoc();
2424    Parser.Lex(); // Eat right bracket token.
2425
2426    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2427                                             0, false, S, E));
2428
2429    return false;
2430  }
2431
2432  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2433  Parser.Lex(); // Eat the comma.
2434
2435  // If we have a '#' it's an immediate offset, else assume it's a register
2436  // offset.
2437  if (Parser.getTok().is(AsmToken::Hash)) {
2438    Parser.Lex(); // Eat the '#'.
2439    E = Parser.getTok().getLoc();
2440
2441    // FIXME: Special case #-0 so we can correctly set the U bit.
2442
2443    const MCExpr *Offset;
2444    if (getParser().ParseExpression(Offset))
2445     return true;
2446
2447    // The expression has to be a constant. Memory references with relocations
2448    // don't come through here, as they use the <label> forms of the relevant
2449    // instructions.
2450    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2451    if (!CE)
2452      return Error (E, "constant expression expected");
2453
2454    // Now we should have the closing ']'
2455    E = Parser.getTok().getLoc();
2456    if (Parser.getTok().isNot(AsmToken::RBrac))
2457      return Error(E, "']' expected");
2458    Parser.Lex(); // Eat right bracket token.
2459
2460    // Don't worry about range checking the value here. That's handled by
2461    // the is*() predicates.
2462    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2463                                             ARM_AM::no_shift, 0, false, S,E));
2464
2465    // If there's a pre-indexing writeback marker, '!', just add it as a token
2466    // operand.
2467    if (Parser.getTok().is(AsmToken::Exclaim)) {
2468      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2469      Parser.Lex(); // Eat the '!'.
2470    }
2471
2472    return false;
2473  }
2474
2475  // The register offset is optionally preceded by a '+' or '-'
2476  bool isNegative = false;
2477  if (Parser.getTok().is(AsmToken::Minus)) {
2478    isNegative = true;
2479    Parser.Lex(); // Eat the '-'.
2480  } else if (Parser.getTok().is(AsmToken::Plus)) {
2481    // Nothing to do.
2482    Parser.Lex(); // Eat the '+'.
2483  }
2484
2485  E = Parser.getTok().getLoc();
2486  int OffsetRegNum = tryParseRegister();
2487  if (OffsetRegNum == -1)
2488    return Error(E, "register expected");
2489
2490  // If there's a shift operator, handle it.
2491  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2492  unsigned ShiftImm = 0;
2493  if (Parser.getTok().is(AsmToken::Comma)) {
2494    Parser.Lex(); // Eat the ','.
2495    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2496      return true;
2497  }
2498
2499  // Now we should have the closing ']'
2500  E = Parser.getTok().getLoc();
2501  if (Parser.getTok().isNot(AsmToken::RBrac))
2502    return Error(E, "']' expected");
2503  Parser.Lex(); // Eat right bracket token.
2504
2505  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2506                                           ShiftType, ShiftImm, isNegative,
2507                                           S, E));
2508
2509  // If there's a pre-indexing writeback marker, '!', just add it as a token
2510  // operand.
2511  if (Parser.getTok().is(AsmToken::Exclaim)) {
2512    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2513    Parser.Lex(); // Eat the '!'.
2514  }
2515
2516  return false;
2517}
2518
2519/// parseMemRegOffsetShift - one of these two:
2520///   ( lsl | lsr | asr | ror ) , # shift_amount
2521///   rrx
2522/// return true if it parses a shift otherwise it returns false.
2523bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2524                                          unsigned &Amount) {
2525  SMLoc Loc = Parser.getTok().getLoc();
2526  const AsmToken &Tok = Parser.getTok();
2527  if (Tok.isNot(AsmToken::Identifier))
2528    return true;
2529  StringRef ShiftName = Tok.getString();
2530  if (ShiftName == "lsl" || ShiftName == "LSL")
2531    St = ARM_AM::lsl;
2532  else if (ShiftName == "lsr" || ShiftName == "LSR")
2533    St = ARM_AM::lsr;
2534  else if (ShiftName == "asr" || ShiftName == "ASR")
2535    St = ARM_AM::asr;
2536  else if (ShiftName == "ror" || ShiftName == "ROR")
2537    St = ARM_AM::ror;
2538  else if (ShiftName == "rrx" || ShiftName == "RRX")
2539    St = ARM_AM::rrx;
2540  else
2541    return Error(Loc, "illegal shift operator");
2542  Parser.Lex(); // Eat shift type token.
2543
2544  // rrx stands alone.
2545  Amount = 0;
2546  if (St != ARM_AM::rrx) {
2547    Loc = Parser.getTok().getLoc();
2548    // A '#' and a shift amount.
2549    const AsmToken &HashTok = Parser.getTok();
2550    if (HashTok.isNot(AsmToken::Hash))
2551      return Error(HashTok.getLoc(), "'#' expected");
2552    Parser.Lex(); // Eat hash token.
2553
2554    const MCExpr *Expr;
2555    if (getParser().ParseExpression(Expr))
2556      return true;
2557    // Range check the immediate.
2558    // lsl, ror: 0 <= imm <= 31
2559    // lsr, asr: 0 <= imm <= 32
2560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2561    if (!CE)
2562      return Error(Loc, "shift amount must be an immediate");
2563    int64_t Imm = CE->getValue();
2564    if (Imm < 0 ||
2565        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2566        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2567      return Error(Loc, "immediate shift value out of range");
2568    Amount = Imm;
2569  }
2570
2571  return false;
2572}
2573
2574/// Parse a arm instruction operand.  For now this parses the operand regardless
2575/// of the mnemonic.
2576bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2577                                StringRef Mnemonic) {
2578  SMLoc S, E;
2579
2580  // Check if the current operand has a custom associated parser, if so, try to
2581  // custom parse the operand, or fallback to the general approach.
2582  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2583  if (ResTy == MatchOperand_Success)
2584    return false;
2585  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2586  // there was a match, but an error occurred, in which case, just return that
2587  // the operand parsing failed.
2588  if (ResTy == MatchOperand_ParseFail)
2589    return true;
2590
2591  switch (getLexer().getKind()) {
2592  default:
2593    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2594    return true;
2595  case AsmToken::Identifier: {
2596    if (!tryParseRegisterWithWriteBack(Operands))
2597      return false;
2598    int Res = tryParseShiftRegister(Operands);
2599    if (Res == 0) // success
2600      return false;
2601    else if (Res == -1) // irrecoverable error
2602      return true;
2603
2604    // Fall though for the Identifier case that is not a register or a
2605    // special name.
2606  }
2607  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2608  case AsmToken::Dot: {   // . as a branch target
2609    // This was not a register so parse other operands that start with an
2610    // identifier (like labels) as expressions and create them as immediates.
2611    const MCExpr *IdVal;
2612    S = Parser.getTok().getLoc();
2613    if (getParser().ParseExpression(IdVal))
2614      return true;
2615    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2616    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2617    return false;
2618  }
2619  case AsmToken::LBrac:
2620    return parseMemory(Operands);
2621  case AsmToken::LCurly:
2622    return parseRegisterList(Operands);
2623  case AsmToken::Hash:
2624    // #42 -> immediate.
2625    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2626    S = Parser.getTok().getLoc();
2627    Parser.Lex();
2628    const MCExpr *ImmVal;
2629    if (getParser().ParseExpression(ImmVal))
2630      return true;
2631    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2632    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2633    return false;
2634  case AsmToken::Colon: {
2635    // ":lower16:" and ":upper16:" expression prefixes
2636    // FIXME: Check it's an expression prefix,
2637    // e.g. (FOO - :lower16:BAR) isn't legal.
2638    ARMMCExpr::VariantKind RefKind;
2639    if (parsePrefix(RefKind))
2640      return true;
2641
2642    const MCExpr *SubExprVal;
2643    if (getParser().ParseExpression(SubExprVal))
2644      return true;
2645
2646    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2647                                                   getContext());
2648    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2649    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2650    return false;
2651  }
2652  }
2653}
2654
2655// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2656//  :lower16: and :upper16:.
2657bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2658  RefKind = ARMMCExpr::VK_ARM_None;
2659
2660  // :lower16: and :upper16: modifiers
2661  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2662  Parser.Lex(); // Eat ':'
2663
2664  if (getLexer().isNot(AsmToken::Identifier)) {
2665    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2666    return true;
2667  }
2668
2669  StringRef IDVal = Parser.getTok().getIdentifier();
2670  if (IDVal == "lower16") {
2671    RefKind = ARMMCExpr::VK_ARM_LO16;
2672  } else if (IDVal == "upper16") {
2673    RefKind = ARMMCExpr::VK_ARM_HI16;
2674  } else {
2675    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2676    return true;
2677  }
2678  Parser.Lex();
2679
2680  if (getLexer().isNot(AsmToken::Colon)) {
2681    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2682    return true;
2683  }
2684  Parser.Lex(); // Eat the last ':'
2685  return false;
2686}
2687
2688const MCExpr *
2689ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2690                                MCSymbolRefExpr::VariantKind Variant) {
2691  // Recurse over the given expression, rebuilding it to apply the given variant
2692  // to the leftmost symbol.
2693  if (Variant == MCSymbolRefExpr::VK_None)
2694    return E;
2695
2696  switch (E->getKind()) {
2697  case MCExpr::Target:
2698    llvm_unreachable("Can't handle target expr yet");
2699  case MCExpr::Constant:
2700    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2701
2702  case MCExpr::SymbolRef: {
2703    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2704
2705    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2706      return 0;
2707
2708    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2709  }
2710
2711  case MCExpr::Unary:
2712    llvm_unreachable("Can't handle unary expressions yet");
2713
2714  case MCExpr::Binary: {
2715    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2716    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2717    const MCExpr *RHS = BE->getRHS();
2718    if (!LHS)
2719      return 0;
2720
2721    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2722  }
2723  }
2724
2725  assert(0 && "Invalid expression kind!");
2726  return 0;
2727}
2728
2729/// \brief Given a mnemonic, split out possible predication code and carry
2730/// setting letters to form a canonical mnemonic and flags.
2731//
2732// FIXME: Would be nice to autogen this.
2733StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2734                                      unsigned &PredicationCode,
2735                                      bool &CarrySetting,
2736                                      unsigned &ProcessorIMod) {
2737  PredicationCode = ARMCC::AL;
2738  CarrySetting = false;
2739  ProcessorIMod = 0;
2740
2741  // Ignore some mnemonics we know aren't predicated forms.
2742  //
2743  // FIXME: Would be nice to autogen this.
2744  if ((Mnemonic == "movs" && isThumb()) ||
2745      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2746      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2747      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2748      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2749      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2750      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2751      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2752    return Mnemonic;
2753
2754  // First, split out any predication code. Ignore mnemonics we know aren't
2755  // predicated but do have a carry-set and so weren't caught above.
2756  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2757      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2758      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls") {
2759    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2760      .Case("eq", ARMCC::EQ)
2761      .Case("ne", ARMCC::NE)
2762      .Case("hs", ARMCC::HS)
2763      .Case("cs", ARMCC::HS)
2764      .Case("lo", ARMCC::LO)
2765      .Case("cc", ARMCC::LO)
2766      .Case("mi", ARMCC::MI)
2767      .Case("pl", ARMCC::PL)
2768      .Case("vs", ARMCC::VS)
2769      .Case("vc", ARMCC::VC)
2770      .Case("hi", ARMCC::HI)
2771      .Case("ls", ARMCC::LS)
2772      .Case("ge", ARMCC::GE)
2773      .Case("lt", ARMCC::LT)
2774      .Case("gt", ARMCC::GT)
2775      .Case("le", ARMCC::LE)
2776      .Case("al", ARMCC::AL)
2777      .Default(~0U);
2778    if (CC != ~0U) {
2779      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2780      PredicationCode = CC;
2781    }
2782  }
2783
2784  // Next, determine if we have a carry setting bit. We explicitly ignore all
2785  // the instructions we know end in 's'.
2786  if (Mnemonic.endswith("s") &&
2787      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2788        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2789        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2790        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2791        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2792        (Mnemonic == "movs" && isThumb()))) {
2793    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2794    CarrySetting = true;
2795  }
2796
2797  // The "cps" instruction can have a interrupt mode operand which is glued into
2798  // the mnemonic. Check if this is the case, split it and parse the imod op
2799  if (Mnemonic.startswith("cps")) {
2800    // Split out any imod code.
2801    unsigned IMod =
2802      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2803      .Case("ie", ARM_PROC::IE)
2804      .Case("id", ARM_PROC::ID)
2805      .Default(~0U);
2806    if (IMod != ~0U) {
2807      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2808      ProcessorIMod = IMod;
2809    }
2810  }
2811
2812  return Mnemonic;
2813}
2814
2815/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2816/// inclusion of carry set or predication code operands.
2817//
2818// FIXME: It would be nice to autogen this.
2819void ARMAsmParser::
2820getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2821                      bool &CanAcceptPredicationCode) {
2822  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2823      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2824      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2825      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2826      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2827      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2828      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2829      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2830      // FIXME: We need a better way. This really confused Thumb2
2831      // parsing for 'mov'.
2832      (Mnemonic == "mov" && !isThumbOne())) {
2833    CanAcceptCarrySet = true;
2834  } else {
2835    CanAcceptCarrySet = false;
2836  }
2837
2838  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2839      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2840      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2841      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2842      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2843      Mnemonic == "setend" ||
2844      (Mnemonic == "nop" && isThumbOne()) ||
2845      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2846      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2847        && !isThumb()) ||
2848      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2849    CanAcceptPredicationCode = false;
2850  } else {
2851    CanAcceptPredicationCode = true;
2852  }
2853
2854  if (isThumb())
2855    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2856        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2857      CanAcceptPredicationCode = false;
2858}
2859
2860bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2861                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2862
2863  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2864  // another does not. Specifically, the MOVW instruction does not. So we
2865  // special case it here and remove the defaulted (non-setting) cc_out
2866  // operand if that's the instruction we're trying to match.
2867  //
2868  // We do this as post-processing of the explicit operands rather than just
2869  // conditionally adding the cc_out in the first place because we need
2870  // to check the type of the parsed immediate operand.
2871  if (Mnemonic == "mov" && Operands.size() > 4 &&
2872      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2873      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2874      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2875    return true;
2876
2877  // Register-register 'add' for thumb does not have a cc_out operand
2878  // when there are only two register operands.
2879  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2880      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2881      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2882      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2883    return true;
2884
2885  return false;
2886}
2887
2888/// Parse an arm instruction mnemonic followed by its operands.
2889bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2890                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2891  // Create the leading tokens for the mnemonic, split by '.' characters.
2892  size_t Start = 0, Next = Name.find('.');
2893  StringRef Mnemonic = Name.slice(Start, Next);
2894
2895  // Split out the predication code and carry setting flag from the mnemonic.
2896  unsigned PredicationCode;
2897  unsigned ProcessorIMod;
2898  bool CarrySetting;
2899  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2900                           ProcessorIMod);
2901
2902  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2903
2904  // FIXME: This is all a pretty gross hack. We should automatically handle
2905  // optional operands like this via tblgen.
2906
2907  // Next, add the CCOut and ConditionCode operands, if needed.
2908  //
2909  // For mnemonics which can ever incorporate a carry setting bit or predication
2910  // code, our matching model involves us always generating CCOut and
2911  // ConditionCode operands to match the mnemonic "as written" and then we let
2912  // the matcher deal with finding the right instruction or generating an
2913  // appropriate error.
2914  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2915  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2916
2917  // If we had a carry-set on an instruction that can't do that, issue an
2918  // error.
2919  if (!CanAcceptCarrySet && CarrySetting) {
2920    Parser.EatToEndOfStatement();
2921    return Error(NameLoc, "instruction '" + Mnemonic +
2922                 "' can not set flags, but 's' suffix specified");
2923  }
2924  // If we had a predication code on an instruction that can't do that, issue an
2925  // error.
2926  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2927    Parser.EatToEndOfStatement();
2928    return Error(NameLoc, "instruction '" + Mnemonic +
2929                 "' is not predicable, but condition code specified");
2930  }
2931
2932  // Add the carry setting operand, if necessary.
2933  //
2934  // FIXME: It would be awesome if we could somehow invent a location such that
2935  // match errors on this operand would print a nice diagnostic about how the
2936  // 's' character in the mnemonic resulted in a CCOut operand.
2937  if (CanAcceptCarrySet)
2938    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2939                                               NameLoc));
2940
2941  // Add the predication code operand, if necessary.
2942  if (CanAcceptPredicationCode) {
2943    Operands.push_back(ARMOperand::CreateCondCode(
2944                         ARMCC::CondCodes(PredicationCode), NameLoc));
2945  }
2946
2947  // Add the processor imod operand, if necessary.
2948  if (ProcessorIMod) {
2949    Operands.push_back(ARMOperand::CreateImm(
2950          MCConstantExpr::Create(ProcessorIMod, getContext()),
2951                                 NameLoc, NameLoc));
2952  } else {
2953    // This mnemonic can't ever accept a imod, but the user wrote
2954    // one (or misspelled another mnemonic).
2955
2956    // FIXME: Issue a nice error.
2957  }
2958
2959  // Add the remaining tokens in the mnemonic.
2960  while (Next != StringRef::npos) {
2961    Start = Next;
2962    Next = Name.find('.', Start + 1);
2963    StringRef ExtraToken = Name.slice(Start, Next);
2964
2965    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2966  }
2967
2968  // Read the remaining operands.
2969  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2970    // Read the first operand.
2971    if (parseOperand(Operands, Mnemonic)) {
2972      Parser.EatToEndOfStatement();
2973      return true;
2974    }
2975
2976    while (getLexer().is(AsmToken::Comma)) {
2977      Parser.Lex();  // Eat the comma.
2978
2979      // Parse and remember the operand.
2980      if (parseOperand(Operands, Mnemonic)) {
2981        Parser.EatToEndOfStatement();
2982        return true;
2983      }
2984    }
2985  }
2986
2987  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2988    Parser.EatToEndOfStatement();
2989    return TokError("unexpected token in argument list");
2990  }
2991
2992  Parser.Lex(); // Consume the EndOfStatement
2993
2994  // Some instructions, mostly Thumb, have forms for the same mnemonic that
2995  // do and don't have a cc_out optional-def operand. With some spot-checks
2996  // of the operand list, we can figure out which variant we're trying to
2997  // parse and adjust accordingly before actually matching. Reason number
2998  // #317 the table driven matcher doesn't fit well with the ARM instruction
2999  // set.
3000  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3001    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3002    Operands.erase(Operands.begin() + 1);
3003    delete Op;
3004  }
3005
3006  // ARM mode 'blx' need special handling, as the register operand version
3007  // is predicable, but the label operand version is not. So, we can't rely
3008  // on the Mnemonic based checking to correctly figure out when to put
3009  // a CondCode operand in the list. If we're trying to match the label
3010  // version, remove the CondCode operand here.
3011  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3012      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3013    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3014    Operands.erase(Operands.begin() + 1);
3015    delete Op;
3016  }
3017
3018  // The vector-compare-to-zero instructions have a literal token "#0" at
3019  // the end that comes to here as an immediate operand. Convert it to a
3020  // token to play nicely with the matcher.
3021  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3022      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3023      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3024    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3025    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3026    if (CE && CE->getValue() == 0) {
3027      Operands.erase(Operands.begin() + 5);
3028      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3029      delete Op;
3030    }
3031  }
3032  return false;
3033}
3034
3035// Validate context-sensitive operand constraints.
3036// FIXME: We would really like to be able to tablegen'erate this.
3037bool ARMAsmParser::
3038validateInstruction(MCInst &Inst,
3039                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3040  switch (Inst.getOpcode()) {
3041  case ARM::LDRD:
3042  case ARM::LDRD_PRE:
3043  case ARM::LDRD_POST:
3044  case ARM::LDREXD: {
3045    // Rt2 must be Rt + 1.
3046    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3047    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3048    if (Rt2 != Rt + 1)
3049      return Error(Operands[3]->getStartLoc(),
3050                   "destination operands must be sequential");
3051    return false;
3052  }
3053  case ARM::STRD: {
3054    // Rt2 must be Rt + 1.
3055    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3056    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3057    if (Rt2 != Rt + 1)
3058      return Error(Operands[3]->getStartLoc(),
3059                   "source operands must be sequential");
3060    return false;
3061  }
3062  case ARM::STRD_PRE:
3063  case ARM::STRD_POST:
3064  case ARM::STREXD: {
3065    // Rt2 must be Rt + 1.
3066    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3067    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3068    if (Rt2 != Rt + 1)
3069      return Error(Operands[3]->getStartLoc(),
3070                   "source operands must be sequential");
3071    return false;
3072  }
3073  case ARM::SBFX:
3074  case ARM::UBFX: {
3075    // width must be in range [1, 32-lsb]
3076    unsigned lsb = Inst.getOperand(2).getImm();
3077    unsigned widthm1 = Inst.getOperand(3).getImm();
3078    if (widthm1 >= 32 - lsb)
3079      return Error(Operands[5]->getStartLoc(),
3080                   "bitfield width must be in range [1,32-lsb]");
3081    return false;
3082  }
3083  case ARM::tLDMIA: {
3084    // Thumb LDM instructions are writeback iff the base register is not
3085    // in the register list.
3086    unsigned Rn = Inst.getOperand(0).getReg();
3087    bool doesWriteback = true;
3088    for (unsigned i = 3; i < Inst.getNumOperands(); ++i) {
3089      unsigned Reg = Inst.getOperand(i).getReg();
3090      if (Reg == Rn)
3091        doesWriteback = false;
3092      // Anything other than a low register isn't legal here.
3093      if (!isARMLowRegister(Reg))
3094        return Error(Operands[4]->getStartLoc(),
3095                     "registers must be in range r0-r7");
3096    }
3097    // If we should have writeback, then there should be a '!' token.
3098    if (doesWriteback &&
3099        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
3100         static_cast<ARMOperand*>(Operands[3])->getToken() != "!"))
3101      return Error(Operands[2]->getStartLoc(),
3102                   "writeback operator '!' expected");
3103
3104    break;
3105  }
3106  }
3107
3108  return false;
3109}
3110
3111void ARMAsmParser::
3112processInstruction(MCInst &Inst,
3113                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3114  switch (Inst.getOpcode()) {
3115  case ARM::LDMIA_UPD:
3116    // If this is a load of a single register via a 'pop', then we should use
3117    // a post-indexed LDR instruction instead, per the ARM ARM.
3118    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3119        Inst.getNumOperands() == 5) {
3120      MCInst TmpInst;
3121      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3122      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3123      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3124      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3125      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3126      TmpInst.addOperand(MCOperand::CreateImm(4));
3127      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3128      TmpInst.addOperand(Inst.getOperand(3));
3129      Inst = TmpInst;
3130    }
3131    break;
3132  case ARM::STMDB_UPD:
3133    // If this is a store of a single register via a 'push', then we should use
3134    // a pre-indexed STR instruction instead, per the ARM ARM.
3135    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3136        Inst.getNumOperands() == 5) {
3137      MCInst TmpInst;
3138      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3139      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3140      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3141      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3142      TmpInst.addOperand(MCOperand::CreateImm(-4));
3143      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3144      TmpInst.addOperand(Inst.getOperand(3));
3145      Inst = TmpInst;
3146    }
3147    break;
3148  case ARM::tADDi8:
3149    // If the immediate is in the range 0-7, we really wanted tADDi3.
3150    if (Inst.getOperand(3).getImm() < 8)
3151      Inst.setOpcode(ARM::tADDi3);
3152    break;
3153  case ARM::tBcc:
3154    // If the conditional is AL, we really want tB.
3155    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3156      Inst.setOpcode(ARM::tB);
3157    break;
3158  }
3159}
3160
3161// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3162// the ARMInsts array) instead. Getting that here requires awkward
3163// API changes, though. Better way?
3164namespace llvm {
3165extern MCInstrDesc ARMInsts[];
3166}
3167static MCInstrDesc &getInstDesc(unsigned Opcode) {
3168  return ARMInsts[Opcode];
3169}
3170
3171unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3172  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3173  // suffix depending on whether they're in an IT block or not.
3174  unsigned Opc = Inst.getOpcode();
3175  MCInstrDesc &MCID = getInstDesc(Opc);
3176  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3177    assert(MCID.hasOptionalDef() &&
3178           "optionally flag setting instruction missing optional def operand");
3179    assert(MCID.NumOperands == Inst.getNumOperands() &&
3180           "operand count mismatch!");
3181    // Find the optional-def operand (cc_out).
3182    unsigned OpNo;
3183    for (OpNo = 0;
3184         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3185         ++OpNo)
3186      ;
3187    // If we're parsing Thumb1, reject it completely.
3188    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3189      return Match_MnemonicFail;
3190    // If we're parsing Thumb2, which form is legal depends on whether we're
3191    // in an IT block.
3192    // FIXME: We don't yet do IT blocks, so just always consider it to be
3193    // that we aren't in one until we do.
3194    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3195      return Match_RequiresITBlock;
3196  }
3197  // Some high-register supporting Thumb1 encodings only allow both registers
3198  // to be from r0-r7 when in Thumb2.
3199  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3200           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3201           isARMLowRegister(Inst.getOperand(2).getReg()))
3202    return Match_RequiresThumb2;
3203  // Others only require ARMv6 or later.
3204  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3205           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3206           isARMLowRegister(Inst.getOperand(1).getReg()))
3207    return Match_RequiresV6;
3208  return Match_Success;
3209}
3210
3211bool ARMAsmParser::
3212MatchAndEmitInstruction(SMLoc IDLoc,
3213                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3214                        MCStreamer &Out) {
3215  MCInst Inst;
3216  unsigned ErrorInfo;
3217  unsigned MatchResult;
3218  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3219  switch (MatchResult) {
3220  default: break;
3221  case Match_Success:
3222    // Context sensitive operand constraints aren't handled by the matcher,
3223    // so check them here.
3224    if (validateInstruction(Inst, Operands))
3225      return true;
3226
3227    // Some instructions need post-processing to, for example, tweak which
3228    // encoding is selected.
3229    processInstruction(Inst, Operands);
3230
3231    Out.EmitInstruction(Inst);
3232    return false;
3233  case Match_MissingFeature:
3234    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3235    return true;
3236  case Match_InvalidOperand: {
3237    SMLoc ErrorLoc = IDLoc;
3238    if (ErrorInfo != ~0U) {
3239      if (ErrorInfo >= Operands.size())
3240        return Error(IDLoc, "too few operands for instruction");
3241
3242      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3243      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3244    }
3245
3246    return Error(ErrorLoc, "invalid operand for instruction");
3247  }
3248  case Match_MnemonicFail:
3249    return Error(IDLoc, "invalid instruction");
3250  case Match_ConversionFail:
3251    // The converter function will have already emited a diagnostic.
3252    return true;
3253  case Match_RequiresITBlock:
3254    return Error(IDLoc, "instruction only valid inside IT block");
3255  case Match_RequiresV6:
3256    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3257  case Match_RequiresThumb2:
3258    return Error(IDLoc, "instruction variant requires Thumb2");
3259  }
3260
3261  llvm_unreachable("Implement any new match types added!");
3262  return true;
3263}
3264
3265/// parseDirective parses the arm specific directives
3266bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3267  StringRef IDVal = DirectiveID.getIdentifier();
3268  if (IDVal == ".word")
3269    return parseDirectiveWord(4, DirectiveID.getLoc());
3270  else if (IDVal == ".thumb")
3271    return parseDirectiveThumb(DirectiveID.getLoc());
3272  else if (IDVal == ".thumb_func")
3273    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3274  else if (IDVal == ".code")
3275    return parseDirectiveCode(DirectiveID.getLoc());
3276  else if (IDVal == ".syntax")
3277    return parseDirectiveSyntax(DirectiveID.getLoc());
3278  return true;
3279}
3280
3281/// parseDirectiveWord
3282///  ::= .word [ expression (, expression)* ]
3283bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3284  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3285    for (;;) {
3286      const MCExpr *Value;
3287      if (getParser().ParseExpression(Value))
3288        return true;
3289
3290      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3291
3292      if (getLexer().is(AsmToken::EndOfStatement))
3293        break;
3294
3295      // FIXME: Improve diagnostic.
3296      if (getLexer().isNot(AsmToken::Comma))
3297        return Error(L, "unexpected token in directive");
3298      Parser.Lex();
3299    }
3300  }
3301
3302  Parser.Lex();
3303  return false;
3304}
3305
3306/// parseDirectiveThumb
3307///  ::= .thumb
3308bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3309  if (getLexer().isNot(AsmToken::EndOfStatement))
3310    return Error(L, "unexpected token in directive");
3311  Parser.Lex();
3312
3313  // TODO: set thumb mode
3314  // TODO: tell the MC streamer the mode
3315  // getParser().getStreamer().Emit???();
3316  return false;
3317}
3318
3319/// parseDirectiveThumbFunc
3320///  ::= .thumbfunc symbol_name
3321bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3322  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3323  bool isMachO = MAI.hasSubsectionsViaSymbols();
3324  StringRef Name;
3325
3326  // Darwin asm has function name after .thumb_func direction
3327  // ELF doesn't
3328  if (isMachO) {
3329    const AsmToken &Tok = Parser.getTok();
3330    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3331      return Error(L, "unexpected token in .thumb_func directive");
3332    Name = Tok.getString();
3333    Parser.Lex(); // Consume the identifier token.
3334  }
3335
3336  if (getLexer().isNot(AsmToken::EndOfStatement))
3337    return Error(L, "unexpected token in directive");
3338  Parser.Lex();
3339
3340  // FIXME: assuming function name will be the line following .thumb_func
3341  if (!isMachO) {
3342    Name = Parser.getTok().getString();
3343  }
3344
3345  // Mark symbol as a thumb symbol.
3346  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3347  getParser().getStreamer().EmitThumbFunc(Func);
3348  return false;
3349}
3350
3351/// parseDirectiveSyntax
3352///  ::= .syntax unified | divided
3353bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3354  const AsmToken &Tok = Parser.getTok();
3355  if (Tok.isNot(AsmToken::Identifier))
3356    return Error(L, "unexpected token in .syntax directive");
3357  StringRef Mode = Tok.getString();
3358  if (Mode == "unified" || Mode == "UNIFIED")
3359    Parser.Lex();
3360  else if (Mode == "divided" || Mode == "DIVIDED")
3361    return Error(L, "'.syntax divided' arm asssembly not supported");
3362  else
3363    return Error(L, "unrecognized syntax mode in .syntax directive");
3364
3365  if (getLexer().isNot(AsmToken::EndOfStatement))
3366    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3367  Parser.Lex();
3368
3369  // TODO tell the MC streamer the mode
3370  // getParser().getStreamer().Emit???();
3371  return false;
3372}
3373
3374/// parseDirectiveCode
3375///  ::= .code 16 | 32
3376bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3377  const AsmToken &Tok = Parser.getTok();
3378  if (Tok.isNot(AsmToken::Integer))
3379    return Error(L, "unexpected token in .code directive");
3380  int64_t Val = Parser.getTok().getIntVal();
3381  if (Val == 16)
3382    Parser.Lex();
3383  else if (Val == 32)
3384    Parser.Lex();
3385  else
3386    return Error(L, "invalid operand to .code directive");
3387
3388  if (getLexer().isNot(AsmToken::EndOfStatement))
3389    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3390  Parser.Lex();
3391
3392  if (Val == 16) {
3393    if (!isThumb()) {
3394      SwitchMode();
3395      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3396    }
3397  } else {
3398    if (isThumb()) {
3399      SwitchMode();
3400      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3401    }
3402  }
3403
3404  return false;
3405}
3406
3407extern "C" void LLVMInitializeARMAsmLexer();
3408
3409/// Force static initialization.
3410extern "C" void LLVMInitializeARMAsmParser() {
3411  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3412  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3413  LLVMInitializeARMAsmLexer();
3414}
3415
3416#define GET_REGISTER_MATCHER
3417#define GET_MATCHER_IMPLEMENTATION
3418#include "ARMGenAsmMatcher.inc"
3419