ARMAsmParser.cpp revision 194bd8982936c819a4b14335a4d08f28af8f3d42 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MCTargetAsmParser.h"
24#include "llvm/Target/TargetRegistry.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/ADT/OwningPtr.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringExtras.h"
31#include "llvm/ADT/StringSwitch.h"
32#include "llvm/ADT/Twine.h"
33
34using namespace llvm;
35
36namespace {
37
38class ARMOperand;
39
40class ARMAsmParser : public MCTargetAsmParser {
41  MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43
44  MCAsmParser &getParser() const { return Parser; }
45  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
46
47  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
49
50  int tryParseRegister();
51  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57  const MCExpr *applyPrefixToExpr(const MCExpr *E,
58                                  MCSymbolRefExpr::VariantKind Variant);
59
60
61  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62                              unsigned &ShiftAmount);
63  bool parseDirectiveWord(unsigned Size, SMLoc L);
64  bool parseDirectiveThumb(SMLoc L);
65  bool parseDirectiveThumbFunc(SMLoc L);
66  bool parseDirectiveCode(SMLoc L);
67  bool parseDirectiveSyntax(SMLoc L);
68
69  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70                          bool &CarrySetting, unsigned &ProcessorIMod);
71  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72                             bool &CanAcceptPredicationCode);
73
74  bool isThumb() const {
75    // FIXME: Can tablegen auto-generate this?
76    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
77  }
78  bool isThumbOne() const {
79    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
80  }
81  bool isThumbTwo() const {
82    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
83  }
84  bool hasV6Ops() const {
85    return STI.getFeatureBits() & ARM::HasV6Ops;
86  }
87  void SwitchMode() {
88    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
89    setAvailableFeatures(FB);
90  }
91
92  /// @name Auto-generated Match Functions
93  /// {
94
95#define GET_ASSEMBLER_HEADER
96#include "ARMGenAsmMatcher.inc"
97
98  /// }
99
100  OperandMatchResultTy parseCoprocNumOperand(
101    SmallVectorImpl<MCParsedAsmOperand*>&);
102  OperandMatchResultTy parseCoprocRegOperand(
103    SmallVectorImpl<MCParsedAsmOperand*>&);
104  OperandMatchResultTy parseMemBarrierOptOperand(
105    SmallVectorImpl<MCParsedAsmOperand*>&);
106  OperandMatchResultTy parseProcIFlagsOperand(
107    SmallVectorImpl<MCParsedAsmOperand*>&);
108  OperandMatchResultTy parseMSRMaskOperand(
109    SmallVectorImpl<MCParsedAsmOperand*>&);
110  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
111                                   StringRef Op, int Low, int High);
112  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
113    return parsePKHImm(O, "lsl", 0, 31);
114  }
115  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
116    return parsePKHImm(O, "asr", 1, 32);
117  }
118  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
119  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
120  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
122  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
123  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
124
125  // Asm Match Converter Methods
126  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
127                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
128  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
129                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
130  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
131                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
132  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
133                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
134  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
135                             const SmallVectorImpl<MCParsedAsmOperand*> &);
136  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
137                             const SmallVectorImpl<MCParsedAsmOperand*> &);
138  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139                             const SmallVectorImpl<MCParsedAsmOperand*> &);
140  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141                             const SmallVectorImpl<MCParsedAsmOperand*> &);
142  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
143                  const SmallVectorImpl<MCParsedAsmOperand*> &);
144  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
145                  const SmallVectorImpl<MCParsedAsmOperand*> &);
146  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
147                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
148
149  bool validateInstruction(MCInst &Inst,
150                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
151  void processInstruction(MCInst &Inst,
152                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
153  bool shouldOmitCCOutOperand(StringRef Mnemonic,
154                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
155
156public:
157  enum ARMMatchResultTy {
158    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
159    Match_RequiresV6,
160    Match_RequiresThumb2
161  };
162
163  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
164    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
165    MCAsmParserExtension::Initialize(_Parser);
166
167    // Initialize the set of available features.
168    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
169  }
170
171  // Implementation of the MCTargetAsmParser interface:
172  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
173  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
174                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
175  bool ParseDirective(AsmToken DirectiveID);
176
177  unsigned checkTargetMatchPredicate(MCInst &Inst);
178
179  bool MatchAndEmitInstruction(SMLoc IDLoc,
180                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
181                               MCStreamer &Out);
182};
183} // end anonymous namespace
184
185namespace {
186
187/// ARMOperand - Instances of this class represent a parsed ARM machine
188/// instruction.
189class ARMOperand : public MCParsedAsmOperand {
190  enum KindTy {
191    CondCode,
192    CCOut,
193    CoprocNum,
194    CoprocReg,
195    Immediate,
196    MemBarrierOpt,
197    Memory,
198    PostIndexRegister,
199    MSRMask,
200    ProcIFlags,
201    Register,
202    RegisterList,
203    DPRRegisterList,
204    SPRRegisterList,
205    ShiftedRegister,
206    ShiftedImmediate,
207    ShifterImmediate,
208    RotateImmediate,
209    BitfieldDescriptor,
210    Token
211  } Kind;
212
213  SMLoc StartLoc, EndLoc;
214  SmallVector<unsigned, 8> Registers;
215
216  union {
217    struct {
218      ARMCC::CondCodes Val;
219    } CC;
220
221    struct {
222      ARM_MB::MemBOpt Val;
223    } MBOpt;
224
225    struct {
226      unsigned Val;
227    } Cop;
228
229    struct {
230      ARM_PROC::IFlags Val;
231    } IFlags;
232
233    struct {
234      unsigned Val;
235    } MMask;
236
237    struct {
238      const char *Data;
239      unsigned Length;
240    } Tok;
241
242    struct {
243      unsigned RegNum;
244    } Reg;
245
246    struct {
247      const MCExpr *Val;
248    } Imm;
249
250    /// Combined record for all forms of ARM address expressions.
251    struct {
252      unsigned BaseRegNum;
253      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
254      // was specified.
255      const MCConstantExpr *OffsetImm;  // Offset immediate value
256      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
257      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
258      unsigned ShiftImm;      // shift for OffsetReg.
259      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
260    } Mem;
261
262    struct {
263      unsigned RegNum;
264      bool isAdd;
265      ARM_AM::ShiftOpc ShiftTy;
266      unsigned ShiftImm;
267    } PostIdxReg;
268
269    struct {
270      bool isASR;
271      unsigned Imm;
272    } ShifterImm;
273    struct {
274      ARM_AM::ShiftOpc ShiftTy;
275      unsigned SrcReg;
276      unsigned ShiftReg;
277      unsigned ShiftImm;
278    } RegShiftedReg;
279    struct {
280      ARM_AM::ShiftOpc ShiftTy;
281      unsigned SrcReg;
282      unsigned ShiftImm;
283    } RegShiftedImm;
284    struct {
285      unsigned Imm;
286    } RotImm;
287    struct {
288      unsigned LSB;
289      unsigned Width;
290    } Bitfield;
291  };
292
293  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
294public:
295  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
296    Kind = o.Kind;
297    StartLoc = o.StartLoc;
298    EndLoc = o.EndLoc;
299    switch (Kind) {
300    case CondCode:
301      CC = o.CC;
302      break;
303    case Token:
304      Tok = o.Tok;
305      break;
306    case CCOut:
307    case Register:
308      Reg = o.Reg;
309      break;
310    case RegisterList:
311    case DPRRegisterList:
312    case SPRRegisterList:
313      Registers = o.Registers;
314      break;
315    case CoprocNum:
316    case CoprocReg:
317      Cop = o.Cop;
318      break;
319    case Immediate:
320      Imm = o.Imm;
321      break;
322    case MemBarrierOpt:
323      MBOpt = o.MBOpt;
324      break;
325    case Memory:
326      Mem = o.Mem;
327      break;
328    case PostIndexRegister:
329      PostIdxReg = o.PostIdxReg;
330      break;
331    case MSRMask:
332      MMask = o.MMask;
333      break;
334    case ProcIFlags:
335      IFlags = o.IFlags;
336      break;
337    case ShifterImmediate:
338      ShifterImm = o.ShifterImm;
339      break;
340    case ShiftedRegister:
341      RegShiftedReg = o.RegShiftedReg;
342      break;
343    case ShiftedImmediate:
344      RegShiftedImm = o.RegShiftedImm;
345      break;
346    case RotateImmediate:
347      RotImm = o.RotImm;
348      break;
349    case BitfieldDescriptor:
350      Bitfield = o.Bitfield;
351      break;
352    }
353  }
354
355  /// getStartLoc - Get the location of the first token of this operand.
356  SMLoc getStartLoc() const { return StartLoc; }
357  /// getEndLoc - Get the location of the last token of this operand.
358  SMLoc getEndLoc() const { return EndLoc; }
359
360  ARMCC::CondCodes getCondCode() const {
361    assert(Kind == CondCode && "Invalid access!");
362    return CC.Val;
363  }
364
365  unsigned getCoproc() const {
366    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
367    return Cop.Val;
368  }
369
370  StringRef getToken() const {
371    assert(Kind == Token && "Invalid access!");
372    return StringRef(Tok.Data, Tok.Length);
373  }
374
375  unsigned getReg() const {
376    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
377    return Reg.RegNum;
378  }
379
380  const SmallVectorImpl<unsigned> &getRegList() const {
381    assert((Kind == RegisterList || Kind == DPRRegisterList ||
382            Kind == SPRRegisterList) && "Invalid access!");
383    return Registers;
384  }
385
386  const MCExpr *getImm() const {
387    assert(Kind == Immediate && "Invalid access!");
388    return Imm.Val;
389  }
390
391  ARM_MB::MemBOpt getMemBarrierOpt() const {
392    assert(Kind == MemBarrierOpt && "Invalid access!");
393    return MBOpt.Val;
394  }
395
396  ARM_PROC::IFlags getProcIFlags() const {
397    assert(Kind == ProcIFlags && "Invalid access!");
398    return IFlags.Val;
399  }
400
401  unsigned getMSRMask() const {
402    assert(Kind == MSRMask && "Invalid access!");
403    return MMask.Val;
404  }
405
406  bool isCoprocNum() const { return Kind == CoprocNum; }
407  bool isCoprocReg() const { return Kind == CoprocReg; }
408  bool isCondCode() const { return Kind == CondCode; }
409  bool isCCOut() const { return Kind == CCOut; }
410  bool isImm() const { return Kind == Immediate; }
411  bool isImm0_255() const {
412    if (Kind != Immediate)
413      return false;
414    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
415    if (!CE) return false;
416    int64_t Value = CE->getValue();
417    return Value >= 0 && Value < 256;
418  }
419  bool isImm0_7() const {
420    if (Kind != Immediate)
421      return false;
422    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
423    if (!CE) return false;
424    int64_t Value = CE->getValue();
425    return Value >= 0 && Value < 8;
426  }
427  bool isImm0_15() const {
428    if (Kind != Immediate)
429      return false;
430    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
431    if (!CE) return false;
432    int64_t Value = CE->getValue();
433    return Value >= 0 && Value < 16;
434  }
435  bool isImm0_31() const {
436    if (Kind != Immediate)
437      return false;
438    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
439    if (!CE) return false;
440    int64_t Value = CE->getValue();
441    return Value >= 0 && Value < 32;
442  }
443  bool isImm1_16() const {
444    if (Kind != Immediate)
445      return false;
446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
447    if (!CE) return false;
448    int64_t Value = CE->getValue();
449    return Value > 0 && Value < 17;
450  }
451  bool isImm1_32() const {
452    if (Kind != Immediate)
453      return false;
454    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
455    if (!CE) return false;
456    int64_t Value = CE->getValue();
457    return Value > 0 && Value < 33;
458  }
459  bool isImm0_65535() const {
460    if (Kind != Immediate)
461      return false;
462    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
463    if (!CE) return false;
464    int64_t Value = CE->getValue();
465    return Value >= 0 && Value < 65536;
466  }
467  bool isImm0_65535Expr() const {
468    if (Kind != Immediate)
469      return false;
470    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
471    // If it's not a constant expression, it'll generate a fixup and be
472    // handled later.
473    if (!CE) return true;
474    int64_t Value = CE->getValue();
475    return Value >= 0 && Value < 65536;
476  }
477  bool isImm24bit() const {
478    if (Kind != Immediate)
479      return false;
480    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
481    if (!CE) return false;
482    int64_t Value = CE->getValue();
483    return Value >= 0 && Value <= 0xffffff;
484  }
485  bool isPKHLSLImm() const {
486    if (Kind != Immediate)
487      return false;
488    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
489    if (!CE) return false;
490    int64_t Value = CE->getValue();
491    return Value >= 0 && Value < 32;
492  }
493  bool isPKHASRImm() const {
494    if (Kind != Immediate)
495      return false;
496    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
497    if (!CE) return false;
498    int64_t Value = CE->getValue();
499    return Value > 0 && Value <= 32;
500  }
501  bool isARMSOImm() const {
502    if (Kind != Immediate)
503      return false;
504    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
505    if (!CE) return false;
506    int64_t Value = CE->getValue();
507    return ARM_AM::getSOImmVal(Value) != -1;
508  }
509  bool isT2SOImm() const {
510    if (Kind != Immediate)
511      return false;
512    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
513    if (!CE) return false;
514    int64_t Value = CE->getValue();
515    return ARM_AM::getT2SOImmVal(Value) != -1;
516  }
517  bool isSetEndImm() const {
518    if (Kind != Immediate)
519      return false;
520    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
521    if (!CE) return false;
522    int64_t Value = CE->getValue();
523    return Value == 1 || Value == 0;
524  }
525  bool isReg() const { return Kind == Register; }
526  bool isRegList() const { return Kind == RegisterList; }
527  bool isDPRRegList() const { return Kind == DPRRegisterList; }
528  bool isSPRRegList() const { return Kind == SPRRegisterList; }
529  bool isToken() const { return Kind == Token; }
530  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
531  bool isMemory() const { return Kind == Memory; }
532  bool isShifterImm() const { return Kind == ShifterImmediate; }
533  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
534  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
535  bool isRotImm() const { return Kind == RotateImmediate; }
536  bool isBitfield() const { return Kind == BitfieldDescriptor; }
537  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
538  bool isPostIdxReg() const {
539    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
540  }
541  bool isMemNoOffset() const {
542    if (Kind != Memory)
543      return false;
544    // No offset of any kind.
545    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
546  }
547  bool isAddrMode2() const {
548    if (Kind != Memory)
549      return false;
550    // Check for register offset.
551    if (Mem.OffsetRegNum) return true;
552    // Immediate offset in range [-4095, 4095].
553    if (!Mem.OffsetImm) return true;
554    int64_t Val = Mem.OffsetImm->getValue();
555    return Val > -4096 && Val < 4096;
556  }
557  bool isAM2OffsetImm() const {
558    if (Kind != Immediate)
559      return false;
560    // Immediate offset in range [-4095, 4095].
561    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562    if (!CE) return false;
563    int64_t Val = CE->getValue();
564    return Val > -4096 && Val < 4096;
565  }
566  bool isAddrMode3() const {
567    if (Kind != Memory)
568      return false;
569    // No shifts are legal for AM3.
570    if (Mem.ShiftType != ARM_AM::no_shift) return false;
571    // Check for register offset.
572    if (Mem.OffsetRegNum) return true;
573    // Immediate offset in range [-255, 255].
574    if (!Mem.OffsetImm) return true;
575    int64_t Val = Mem.OffsetImm->getValue();
576    return Val > -256 && Val < 256;
577  }
578  bool isAM3Offset() const {
579    if (Kind != Immediate && Kind != PostIndexRegister)
580      return false;
581    if (Kind == PostIndexRegister)
582      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
583    // Immediate offset in range [-255, 255].
584    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585    if (!CE) return false;
586    int64_t Val = CE->getValue();
587    // Special case, #-0 is INT32_MIN.
588    return (Val > -256 && Val < 256) || Val == INT32_MIN;
589  }
590  bool isAddrMode5() const {
591    if (Kind != Memory)
592      return false;
593    // Check for register offset.
594    if (Mem.OffsetRegNum) return false;
595    // Immediate offset in range [-1020, 1020] and a multiple of 4.
596    if (!Mem.OffsetImm) return true;
597    int64_t Val = Mem.OffsetImm->getValue();
598    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
599  }
600  bool isMemRegOffset() const {
601    if (Kind != Memory || !Mem.OffsetRegNum)
602      return false;
603    return true;
604  }
605  bool isMemThumbRR() const {
606    // Thumb reg+reg addressing is simple. Just two registers, a base and
607    // an offset. No shifts, negations or any other complicating factors.
608    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
609        Mem.ShiftType != ARM_AM::no_shift)
610      return false;
611    return true;
612  }
613  bool isMemImm8Offset() const {
614    if (Kind != Memory || Mem.OffsetRegNum != 0)
615      return false;
616    // Immediate offset in range [-255, 255].
617    if (!Mem.OffsetImm) return true;
618    int64_t Val = Mem.OffsetImm->getValue();
619    return Val > -256 && Val < 256;
620  }
621  bool isMemImm12Offset() const {
622    // If we have an immediate that's not a constant, treat it as a label
623    // reference needing a fixup. If it is a constant, it's something else
624    // and we reject it.
625    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
626      return true;
627
628    if (Kind != Memory || Mem.OffsetRegNum != 0)
629      return false;
630    // Immediate offset in range [-4095, 4095].
631    if (!Mem.OffsetImm) return true;
632    int64_t Val = Mem.OffsetImm->getValue();
633    return Val > -4096 && Val < 4096;
634  }
635  bool isPostIdxImm8() const {
636    if (Kind != Immediate)
637      return false;
638    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639    if (!CE) return false;
640    int64_t Val = CE->getValue();
641    return Val > -256 && Val < 256;
642  }
643
644  bool isMSRMask() const { return Kind == MSRMask; }
645  bool isProcIFlags() const { return Kind == ProcIFlags; }
646
647  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
648    // Add as immediates when possible.  Null MCExpr = 0.
649    if (Expr == 0)
650      Inst.addOperand(MCOperand::CreateImm(0));
651    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
652      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
653    else
654      Inst.addOperand(MCOperand::CreateExpr(Expr));
655  }
656
657  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
658    assert(N == 2 && "Invalid number of operands!");
659    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
660    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
661    Inst.addOperand(MCOperand::CreateReg(RegNum));
662  }
663
664  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
665    assert(N == 1 && "Invalid number of operands!");
666    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
667  }
668
669  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
670    assert(N == 1 && "Invalid number of operands!");
671    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
672  }
673
674  void addCCOutOperands(MCInst &Inst, unsigned N) const {
675    assert(N == 1 && "Invalid number of operands!");
676    Inst.addOperand(MCOperand::CreateReg(getReg()));
677  }
678
679  void addRegOperands(MCInst &Inst, unsigned N) const {
680    assert(N == 1 && "Invalid number of operands!");
681    Inst.addOperand(MCOperand::CreateReg(getReg()));
682  }
683
684  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
685    assert(N == 3 && "Invalid number of operands!");
686    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
687    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
688    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
689    Inst.addOperand(MCOperand::CreateImm(
690      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
691  }
692
693  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
694    assert(N == 2 && "Invalid number of operands!");
695    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
696    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
697    Inst.addOperand(MCOperand::CreateImm(
698      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
699  }
700
701
702  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
703    assert(N == 1 && "Invalid number of operands!");
704    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
705                                         ShifterImm.Imm));
706  }
707
708  void addRegListOperands(MCInst &Inst, unsigned N) const {
709    assert(N == 1 && "Invalid number of operands!");
710    const SmallVectorImpl<unsigned> &RegList = getRegList();
711    for (SmallVectorImpl<unsigned>::const_iterator
712           I = RegList.begin(), E = RegList.end(); I != E; ++I)
713      Inst.addOperand(MCOperand::CreateReg(*I));
714  }
715
716  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
717    addRegListOperands(Inst, N);
718  }
719
720  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
721    addRegListOperands(Inst, N);
722  }
723
724  void addRotImmOperands(MCInst &Inst, unsigned N) const {
725    assert(N == 1 && "Invalid number of operands!");
726    // Encoded as val>>3. The printer handles display as 8, 16, 24.
727    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
728  }
729
730  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
731    assert(N == 1 && "Invalid number of operands!");
732    // Munge the lsb/width into a bitfield mask.
733    unsigned lsb = Bitfield.LSB;
734    unsigned width = Bitfield.Width;
735    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
736    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
737                      (32 - (lsb + width)));
738    Inst.addOperand(MCOperand::CreateImm(Mask));
739  }
740
741  void addImmOperands(MCInst &Inst, unsigned N) const {
742    assert(N == 1 && "Invalid number of operands!");
743    addExpr(Inst, getImm());
744  }
745
746  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
747    assert(N == 1 && "Invalid number of operands!");
748    addExpr(Inst, getImm());
749  }
750
751  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
752    assert(N == 1 && "Invalid number of operands!");
753    addExpr(Inst, getImm());
754  }
755
756  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
757    assert(N == 1 && "Invalid number of operands!");
758    addExpr(Inst, getImm());
759  }
760
761  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
762    assert(N == 1 && "Invalid number of operands!");
763    addExpr(Inst, getImm());
764  }
765
766  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
767    assert(N == 1 && "Invalid number of operands!");
768    // The constant encodes as the immediate-1, and we store in the instruction
769    // the bits as encoded, so subtract off one here.
770    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
772  }
773
774  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
775    assert(N == 1 && "Invalid number of operands!");
776    // The constant encodes as the immediate-1, and we store in the instruction
777    // the bits as encoded, so subtract off one here.
778    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
780  }
781
782  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
783    assert(N == 1 && "Invalid number of operands!");
784    addExpr(Inst, getImm());
785  }
786
787  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
788    assert(N == 1 && "Invalid number of operands!");
789    addExpr(Inst, getImm());
790  }
791
792  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
793    assert(N == 1 && "Invalid number of operands!");
794    addExpr(Inst, getImm());
795  }
796
797  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
798    assert(N == 1 && "Invalid number of operands!");
799    addExpr(Inst, getImm());
800  }
801
802  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
803    assert(N == 1 && "Invalid number of operands!");
804    // An ASR value of 32 encodes as 0, so that's how we want to add it to
805    // the instruction as well.
806    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807    int Val = CE->getValue();
808    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
809  }
810
811  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
812    assert(N == 1 && "Invalid number of operands!");
813    addExpr(Inst, getImm());
814  }
815
816  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
817    assert(N == 1 && "Invalid number of operands!");
818    addExpr(Inst, getImm());
819  }
820
821  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
822    assert(N == 1 && "Invalid number of operands!");
823    addExpr(Inst, getImm());
824  }
825
826  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
827    assert(N == 1 && "Invalid number of operands!");
828    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
829  }
830
831  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
832    assert(N == 1 && "Invalid number of operands!");
833    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
834  }
835
836  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
837    assert(N == 3 && "Invalid number of operands!");
838    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
839    if (!Mem.OffsetRegNum) {
840      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
841      // Special case for #-0
842      if (Val == INT32_MIN) Val = 0;
843      if (Val < 0) Val = -Val;
844      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
845    } else {
846      // For register offset, we encode the shift type and negation flag
847      // here.
848      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
849                              Mem.ShiftImm, Mem.ShiftType);
850    }
851    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
852    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
853    Inst.addOperand(MCOperand::CreateImm(Val));
854  }
855
856  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
857    assert(N == 2 && "Invalid number of operands!");
858    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859    assert(CE && "non-constant AM2OffsetImm operand!");
860    int32_t Val = CE->getValue();
861    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
862    // Special case for #-0
863    if (Val == INT32_MIN) Val = 0;
864    if (Val < 0) Val = -Val;
865    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
866    Inst.addOperand(MCOperand::CreateReg(0));
867    Inst.addOperand(MCOperand::CreateImm(Val));
868  }
869
870  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
871    assert(N == 3 && "Invalid number of operands!");
872    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
873    if (!Mem.OffsetRegNum) {
874      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
875      // Special case for #-0
876      if (Val == INT32_MIN) Val = 0;
877      if (Val < 0) Val = -Val;
878      Val = ARM_AM::getAM3Opc(AddSub, Val);
879    } else {
880      // For register offset, we encode the shift type and negation flag
881      // here.
882      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
883    }
884    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
885    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
886    Inst.addOperand(MCOperand::CreateImm(Val));
887  }
888
889  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
890    assert(N == 2 && "Invalid number of operands!");
891    if (Kind == PostIndexRegister) {
892      int32_t Val =
893        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
894      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
895      Inst.addOperand(MCOperand::CreateImm(Val));
896      return;
897    }
898
899    // Constant offset.
900    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
901    int32_t Val = CE->getValue();
902    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
903    // Special case for #-0
904    if (Val == INT32_MIN) Val = 0;
905    if (Val < 0) Val = -Val;
906    Val = ARM_AM::getAM3Opc(AddSub, Val);
907    Inst.addOperand(MCOperand::CreateReg(0));
908    Inst.addOperand(MCOperand::CreateImm(Val));
909  }
910
911  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
912    assert(N == 2 && "Invalid number of operands!");
913    // The lower two bits are always zero and as such are not encoded.
914    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
915    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
916    // Special case for #-0
917    if (Val == INT32_MIN) Val = 0;
918    if (Val < 0) Val = -Val;
919    Val = ARM_AM::getAM5Opc(AddSub, Val);
920    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
921    Inst.addOperand(MCOperand::CreateImm(Val));
922  }
923
924  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
925    assert(N == 2 && "Invalid number of operands!");
926    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
927    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
928    Inst.addOperand(MCOperand::CreateImm(Val));
929  }
930
931  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
932    assert(N == 2 && "Invalid number of operands!");
933    // If this is an immediate, it's a label reference.
934    if (Kind == Immediate) {
935      addExpr(Inst, getImm());
936      Inst.addOperand(MCOperand::CreateImm(0));
937      return;
938    }
939
940    // Otherwise, it's a normal memory reg+offset.
941    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
942    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
943    Inst.addOperand(MCOperand::CreateImm(Val));
944  }
945
946  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
947    assert(N == 3 && "Invalid number of operands!");
948    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
949                                     Mem.ShiftImm, Mem.ShiftType);
950    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
951    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
952    Inst.addOperand(MCOperand::CreateImm(Val));
953  }
954
955  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
956    assert(N == 2 && "Invalid number of operands!");
957    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
958    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
959  }
960
961  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
962    assert(N == 1 && "Invalid number of operands!");
963    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964    assert(CE && "non-constant post-idx-imm8 operand!");
965    int Imm = CE->getValue();
966    bool isAdd = Imm >= 0;
967    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
968    Inst.addOperand(MCOperand::CreateImm(Imm));
969  }
970
971  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
972    assert(N == 2 && "Invalid number of operands!");
973    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
974    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
975  }
976
977  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
978    assert(N == 2 && "Invalid number of operands!");
979    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
980    // The sign, shift type, and shift amount are encoded in a single operand
981    // using the AM2 encoding helpers.
982    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
983    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
984                                     PostIdxReg.ShiftTy);
985    Inst.addOperand(MCOperand::CreateImm(Imm));
986  }
987
988  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
989    assert(N == 1 && "Invalid number of operands!");
990    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
991  }
992
993  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
994    assert(N == 1 && "Invalid number of operands!");
995    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
996  }
997
998  virtual void print(raw_ostream &OS) const;
999
1000  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1001    ARMOperand *Op = new ARMOperand(CondCode);
1002    Op->CC.Val = CC;
1003    Op->StartLoc = S;
1004    Op->EndLoc = S;
1005    return Op;
1006  }
1007
1008  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1009    ARMOperand *Op = new ARMOperand(CoprocNum);
1010    Op->Cop.Val = CopVal;
1011    Op->StartLoc = S;
1012    Op->EndLoc = S;
1013    return Op;
1014  }
1015
1016  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1017    ARMOperand *Op = new ARMOperand(CoprocReg);
1018    Op->Cop.Val = CopVal;
1019    Op->StartLoc = S;
1020    Op->EndLoc = S;
1021    return Op;
1022  }
1023
1024  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1025    ARMOperand *Op = new ARMOperand(CCOut);
1026    Op->Reg.RegNum = RegNum;
1027    Op->StartLoc = S;
1028    Op->EndLoc = S;
1029    return Op;
1030  }
1031
1032  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1033    ARMOperand *Op = new ARMOperand(Token);
1034    Op->Tok.Data = Str.data();
1035    Op->Tok.Length = Str.size();
1036    Op->StartLoc = S;
1037    Op->EndLoc = S;
1038    return Op;
1039  }
1040
1041  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1042    ARMOperand *Op = new ARMOperand(Register);
1043    Op->Reg.RegNum = RegNum;
1044    Op->StartLoc = S;
1045    Op->EndLoc = E;
1046    return Op;
1047  }
1048
1049  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1050                                           unsigned SrcReg,
1051                                           unsigned ShiftReg,
1052                                           unsigned ShiftImm,
1053                                           SMLoc S, SMLoc E) {
1054    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1055    Op->RegShiftedReg.ShiftTy = ShTy;
1056    Op->RegShiftedReg.SrcReg = SrcReg;
1057    Op->RegShiftedReg.ShiftReg = ShiftReg;
1058    Op->RegShiftedReg.ShiftImm = ShiftImm;
1059    Op->StartLoc = S;
1060    Op->EndLoc = E;
1061    return Op;
1062  }
1063
1064  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1065                                            unsigned SrcReg,
1066                                            unsigned ShiftImm,
1067                                            SMLoc S, SMLoc E) {
1068    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1069    Op->RegShiftedImm.ShiftTy = ShTy;
1070    Op->RegShiftedImm.SrcReg = SrcReg;
1071    Op->RegShiftedImm.ShiftImm = ShiftImm;
1072    Op->StartLoc = S;
1073    Op->EndLoc = E;
1074    return Op;
1075  }
1076
1077  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1078                                   SMLoc S, SMLoc E) {
1079    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1080    Op->ShifterImm.isASR = isASR;
1081    Op->ShifterImm.Imm = Imm;
1082    Op->StartLoc = S;
1083    Op->EndLoc = E;
1084    return Op;
1085  }
1086
1087  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1088    ARMOperand *Op = new ARMOperand(RotateImmediate);
1089    Op->RotImm.Imm = Imm;
1090    Op->StartLoc = S;
1091    Op->EndLoc = E;
1092    return Op;
1093  }
1094
1095  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1096                                    SMLoc S, SMLoc E) {
1097    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1098    Op->Bitfield.LSB = LSB;
1099    Op->Bitfield.Width = Width;
1100    Op->StartLoc = S;
1101    Op->EndLoc = E;
1102    return Op;
1103  }
1104
1105  static ARMOperand *
1106  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1107                SMLoc StartLoc, SMLoc EndLoc) {
1108    KindTy Kind = RegisterList;
1109
1110    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1111        contains(Regs.front().first))
1112      Kind = DPRRegisterList;
1113    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1114             contains(Regs.front().first))
1115      Kind = SPRRegisterList;
1116
1117    ARMOperand *Op = new ARMOperand(Kind);
1118    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1119           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1120      Op->Registers.push_back(I->first);
1121    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1122    Op->StartLoc = StartLoc;
1123    Op->EndLoc = EndLoc;
1124    return Op;
1125  }
1126
1127  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1128    ARMOperand *Op = new ARMOperand(Immediate);
1129    Op->Imm.Val = Val;
1130    Op->StartLoc = S;
1131    Op->EndLoc = E;
1132    return Op;
1133  }
1134
1135  static ARMOperand *CreateMem(unsigned BaseRegNum,
1136                               const MCConstantExpr *OffsetImm,
1137                               unsigned OffsetRegNum,
1138                               ARM_AM::ShiftOpc ShiftType,
1139                               unsigned ShiftImm,
1140                               bool isNegative,
1141                               SMLoc S, SMLoc E) {
1142    ARMOperand *Op = new ARMOperand(Memory);
1143    Op->Mem.BaseRegNum = BaseRegNum;
1144    Op->Mem.OffsetImm = OffsetImm;
1145    Op->Mem.OffsetRegNum = OffsetRegNum;
1146    Op->Mem.ShiftType = ShiftType;
1147    Op->Mem.ShiftImm = ShiftImm;
1148    Op->Mem.isNegative = isNegative;
1149    Op->StartLoc = S;
1150    Op->EndLoc = E;
1151    return Op;
1152  }
1153
1154  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1155                                      ARM_AM::ShiftOpc ShiftTy,
1156                                      unsigned ShiftImm,
1157                                      SMLoc S, SMLoc E) {
1158    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1159    Op->PostIdxReg.RegNum = RegNum;
1160    Op->PostIdxReg.isAdd = isAdd;
1161    Op->PostIdxReg.ShiftTy = ShiftTy;
1162    Op->PostIdxReg.ShiftImm = ShiftImm;
1163    Op->StartLoc = S;
1164    Op->EndLoc = E;
1165    return Op;
1166  }
1167
1168  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1169    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1170    Op->MBOpt.Val = Opt;
1171    Op->StartLoc = S;
1172    Op->EndLoc = S;
1173    return Op;
1174  }
1175
1176  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1177    ARMOperand *Op = new ARMOperand(ProcIFlags);
1178    Op->IFlags.Val = IFlags;
1179    Op->StartLoc = S;
1180    Op->EndLoc = S;
1181    return Op;
1182  }
1183
1184  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1185    ARMOperand *Op = new ARMOperand(MSRMask);
1186    Op->MMask.Val = MMask;
1187    Op->StartLoc = S;
1188    Op->EndLoc = S;
1189    return Op;
1190  }
1191};
1192
1193} // end anonymous namespace.
1194
1195void ARMOperand::print(raw_ostream &OS) const {
1196  switch (Kind) {
1197  case CondCode:
1198    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1199    break;
1200  case CCOut:
1201    OS << "<ccout " << getReg() << ">";
1202    break;
1203  case CoprocNum:
1204    OS << "<coprocessor number: " << getCoproc() << ">";
1205    break;
1206  case CoprocReg:
1207    OS << "<coprocessor register: " << getCoproc() << ">";
1208    break;
1209  case MSRMask:
1210    OS << "<mask: " << getMSRMask() << ">";
1211    break;
1212  case Immediate:
1213    getImm()->print(OS);
1214    break;
1215  case MemBarrierOpt:
1216    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1217    break;
1218  case Memory:
1219    OS << "<memory "
1220       << " base:" << Mem.BaseRegNum;
1221    OS << ">";
1222    break;
1223  case PostIndexRegister:
1224    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1225       << PostIdxReg.RegNum;
1226    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1227      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1228         << PostIdxReg.ShiftImm;
1229    OS << ">";
1230    break;
1231  case ProcIFlags: {
1232    OS << "<ARM_PROC::";
1233    unsigned IFlags = getProcIFlags();
1234    for (int i=2; i >= 0; --i)
1235      if (IFlags & (1 << i))
1236        OS << ARM_PROC::IFlagsToString(1 << i);
1237    OS << ">";
1238    break;
1239  }
1240  case Register:
1241    OS << "<register " << getReg() << ">";
1242    break;
1243  case ShifterImmediate:
1244    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1245       << " #" << ShifterImm.Imm << ">";
1246    break;
1247  case ShiftedRegister:
1248    OS << "<so_reg_reg "
1249       << RegShiftedReg.SrcReg
1250       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1251       << ", " << RegShiftedReg.ShiftReg << ", "
1252       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1253       << ">";
1254    break;
1255  case ShiftedImmediate:
1256    OS << "<so_reg_imm "
1257       << RegShiftedImm.SrcReg
1258       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1259       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1260       << ">";
1261    break;
1262  case RotateImmediate:
1263    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1264    break;
1265  case BitfieldDescriptor:
1266    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1267       << ", width: " << Bitfield.Width << ">";
1268    break;
1269  case RegisterList:
1270  case DPRRegisterList:
1271  case SPRRegisterList: {
1272    OS << "<register_list ";
1273
1274    const SmallVectorImpl<unsigned> &RegList = getRegList();
1275    for (SmallVectorImpl<unsigned>::const_iterator
1276           I = RegList.begin(), E = RegList.end(); I != E; ) {
1277      OS << *I;
1278      if (++I < E) OS << ", ";
1279    }
1280
1281    OS << ">";
1282    break;
1283  }
1284  case Token:
1285    OS << "'" << getToken() << "'";
1286    break;
1287  }
1288}
1289
1290/// @name Auto-generated Match Functions
1291/// {
1292
1293static unsigned MatchRegisterName(StringRef Name);
1294
1295/// }
1296
1297bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1298                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1299  RegNo = tryParseRegister();
1300
1301  return (RegNo == (unsigned)-1);
1302}
1303
1304/// Try to parse a register name.  The token must be an Identifier when called,
1305/// and if it is a register name the token is eaten and the register number is
1306/// returned.  Otherwise return -1.
1307///
1308int ARMAsmParser::tryParseRegister() {
1309  const AsmToken &Tok = Parser.getTok();
1310  if (Tok.isNot(AsmToken::Identifier)) return -1;
1311
1312  // FIXME: Validate register for the current architecture; we have to do
1313  // validation later, so maybe there is no need for this here.
1314  std::string upperCase = Tok.getString().str();
1315  std::string lowerCase = LowercaseString(upperCase);
1316  unsigned RegNum = MatchRegisterName(lowerCase);
1317  if (!RegNum) {
1318    RegNum = StringSwitch<unsigned>(lowerCase)
1319      .Case("r13", ARM::SP)
1320      .Case("r14", ARM::LR)
1321      .Case("r15", ARM::PC)
1322      .Case("ip", ARM::R12)
1323      .Default(0);
1324  }
1325  if (!RegNum) return -1;
1326
1327  Parser.Lex(); // Eat identifier token.
1328  return RegNum;
1329}
1330
1331// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1332// If a recoverable error occurs, return 1. If an irrecoverable error
1333// occurs, return -1. An irrecoverable error is one where tokens have been
1334// consumed in the process of trying to parse the shifter (i.e., when it is
1335// indeed a shifter operand, but malformed).
1336int ARMAsmParser::tryParseShiftRegister(
1337                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1338  SMLoc S = Parser.getTok().getLoc();
1339  const AsmToken &Tok = Parser.getTok();
1340  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1341
1342  std::string upperCase = Tok.getString().str();
1343  std::string lowerCase = LowercaseString(upperCase);
1344  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1345      .Case("lsl", ARM_AM::lsl)
1346      .Case("lsr", ARM_AM::lsr)
1347      .Case("asr", ARM_AM::asr)
1348      .Case("ror", ARM_AM::ror)
1349      .Case("rrx", ARM_AM::rrx)
1350      .Default(ARM_AM::no_shift);
1351
1352  if (ShiftTy == ARM_AM::no_shift)
1353    return 1;
1354
1355  Parser.Lex(); // Eat the operator.
1356
1357  // The source register for the shift has already been added to the
1358  // operand list, so we need to pop it off and combine it into the shifted
1359  // register operand instead.
1360  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1361  if (!PrevOp->isReg())
1362    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1363  int SrcReg = PrevOp->getReg();
1364  int64_t Imm = 0;
1365  int ShiftReg = 0;
1366  if (ShiftTy == ARM_AM::rrx) {
1367    // RRX Doesn't have an explicit shift amount. The encoder expects
1368    // the shift register to be the same as the source register. Seems odd,
1369    // but OK.
1370    ShiftReg = SrcReg;
1371  } else {
1372    // Figure out if this is shifted by a constant or a register (for non-RRX).
1373    if (Parser.getTok().is(AsmToken::Hash)) {
1374      Parser.Lex(); // Eat hash.
1375      SMLoc ImmLoc = Parser.getTok().getLoc();
1376      const MCExpr *ShiftExpr = 0;
1377      if (getParser().ParseExpression(ShiftExpr)) {
1378        Error(ImmLoc, "invalid immediate shift value");
1379        return -1;
1380      }
1381      // The expression must be evaluatable as an immediate.
1382      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1383      if (!CE) {
1384        Error(ImmLoc, "invalid immediate shift value");
1385        return -1;
1386      }
1387      // Range check the immediate.
1388      // lsl, ror: 0 <= imm <= 31
1389      // lsr, asr: 0 <= imm <= 32
1390      Imm = CE->getValue();
1391      if (Imm < 0 ||
1392          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1393          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1394        Error(ImmLoc, "immediate shift value out of range");
1395        return -1;
1396      }
1397    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1398      ShiftReg = tryParseRegister();
1399      SMLoc L = Parser.getTok().getLoc();
1400      if (ShiftReg == -1) {
1401        Error (L, "expected immediate or register in shift operand");
1402        return -1;
1403      }
1404    } else {
1405      Error (Parser.getTok().getLoc(),
1406                    "expected immediate or register in shift operand");
1407      return -1;
1408    }
1409  }
1410
1411  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1412    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1413                                                         ShiftReg, Imm,
1414                                               S, Parser.getTok().getLoc()));
1415  else
1416    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1417                                               S, Parser.getTok().getLoc()));
1418
1419  return 0;
1420}
1421
1422
1423/// Try to parse a register name.  The token must be an Identifier when called.
1424/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1425/// if there is a "writeback". 'true' if it's not a register.
1426///
1427/// TODO this is likely to change to allow different register types and or to
1428/// parse for a specific register type.
1429bool ARMAsmParser::
1430tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1431  SMLoc S = Parser.getTok().getLoc();
1432  int RegNo = tryParseRegister();
1433  if (RegNo == -1)
1434    return true;
1435
1436  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1437
1438  const AsmToken &ExclaimTok = Parser.getTok();
1439  if (ExclaimTok.is(AsmToken::Exclaim)) {
1440    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1441                                               ExclaimTok.getLoc()));
1442    Parser.Lex(); // Eat exclaim token
1443  }
1444
1445  return false;
1446}
1447
1448/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1449/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1450/// "c5", ...
1451static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1452  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1453  // but efficient.
1454  switch (Name.size()) {
1455  default: break;
1456  case 2:
1457    if (Name[0] != CoprocOp)
1458      return -1;
1459    switch (Name[1]) {
1460    default:  return -1;
1461    case '0': return 0;
1462    case '1': return 1;
1463    case '2': return 2;
1464    case '3': return 3;
1465    case '4': return 4;
1466    case '5': return 5;
1467    case '6': return 6;
1468    case '7': return 7;
1469    case '8': return 8;
1470    case '9': return 9;
1471    }
1472    break;
1473  case 3:
1474    if (Name[0] != CoprocOp || Name[1] != '1')
1475      return -1;
1476    switch (Name[2]) {
1477    default:  return -1;
1478    case '0': return 10;
1479    case '1': return 11;
1480    case '2': return 12;
1481    case '3': return 13;
1482    case '4': return 14;
1483    case '5': return 15;
1484    }
1485    break;
1486  }
1487
1488  return -1;
1489}
1490
1491/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1492/// token must be an Identifier when called, and if it is a coprocessor
1493/// number, the token is eaten and the operand is added to the operand list.
1494ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1495parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1496  SMLoc S = Parser.getTok().getLoc();
1497  const AsmToken &Tok = Parser.getTok();
1498  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1499
1500  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1501  if (Num == -1)
1502    return MatchOperand_NoMatch;
1503
1504  Parser.Lex(); // Eat identifier token.
1505  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1506  return MatchOperand_Success;
1507}
1508
1509/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1510/// token must be an Identifier when called, and if it is a coprocessor
1511/// number, the token is eaten and the operand is added to the operand list.
1512ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1513parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1514  SMLoc S = Parser.getTok().getLoc();
1515  const AsmToken &Tok = Parser.getTok();
1516  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1517
1518  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1519  if (Reg == -1)
1520    return MatchOperand_NoMatch;
1521
1522  Parser.Lex(); // Eat identifier token.
1523  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1524  return MatchOperand_Success;
1525}
1526
1527/// Parse a register list, return it if successful else return null.  The first
1528/// token must be a '{' when called.
1529bool ARMAsmParser::
1530parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1531  assert(Parser.getTok().is(AsmToken::LCurly) &&
1532         "Token is not a Left Curly Brace");
1533  SMLoc S = Parser.getTok().getLoc();
1534
1535  // Read the rest of the registers in the list.
1536  unsigned PrevRegNum = 0;
1537  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1538
1539  do {
1540    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1541    Parser.Lex(); // Eat non-identifier token.
1542
1543    const AsmToken &RegTok = Parser.getTok();
1544    SMLoc RegLoc = RegTok.getLoc();
1545    if (RegTok.isNot(AsmToken::Identifier)) {
1546      Error(RegLoc, "register expected");
1547      return true;
1548    }
1549
1550    int RegNum = tryParseRegister();
1551    if (RegNum == -1) {
1552      Error(RegLoc, "register expected");
1553      return true;
1554    }
1555
1556    if (IsRange) {
1557      int Reg = PrevRegNum;
1558      do {
1559        ++Reg;
1560        Registers.push_back(std::make_pair(Reg, RegLoc));
1561      } while (Reg != RegNum);
1562    } else {
1563      Registers.push_back(std::make_pair(RegNum, RegLoc));
1564    }
1565
1566    PrevRegNum = RegNum;
1567  } while (Parser.getTok().is(AsmToken::Comma) ||
1568           Parser.getTok().is(AsmToken::Minus));
1569
1570  // Process the right curly brace of the list.
1571  const AsmToken &RCurlyTok = Parser.getTok();
1572  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1573    Error(RCurlyTok.getLoc(), "'}' expected");
1574    return true;
1575  }
1576
1577  SMLoc E = RCurlyTok.getLoc();
1578  Parser.Lex(); // Eat right curly brace token.
1579
1580  // Verify the register list.
1581  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1582    RI = Registers.begin(), RE = Registers.end();
1583
1584  unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1585  bool EmittedWarning = false;
1586
1587  DenseMap<unsigned, bool> RegMap;
1588  RegMap[HighRegNum] = true;
1589
1590  for (++RI; RI != RE; ++RI) {
1591    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1592    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1593
1594    if (RegMap[Reg]) {
1595      Error(RegInfo.second, "register duplicated in register list");
1596      return true;
1597    }
1598
1599    if (!EmittedWarning && Reg < HighRegNum)
1600      Warning(RegInfo.second,
1601              "register not in ascending order in register list");
1602
1603    RegMap[Reg] = true;
1604    HighRegNum = std::max(Reg, HighRegNum);
1605  }
1606
1607  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1608  return false;
1609}
1610
1611/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1612ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1613parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1614  SMLoc S = Parser.getTok().getLoc();
1615  const AsmToken &Tok = Parser.getTok();
1616  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1617  StringRef OptStr = Tok.getString();
1618
1619  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1620    .Case("sy",    ARM_MB::SY)
1621    .Case("st",    ARM_MB::ST)
1622    .Case("sh",    ARM_MB::ISH)
1623    .Case("ish",   ARM_MB::ISH)
1624    .Case("shst",  ARM_MB::ISHST)
1625    .Case("ishst", ARM_MB::ISHST)
1626    .Case("nsh",   ARM_MB::NSH)
1627    .Case("un",    ARM_MB::NSH)
1628    .Case("nshst", ARM_MB::NSHST)
1629    .Case("unst",  ARM_MB::NSHST)
1630    .Case("osh",   ARM_MB::OSH)
1631    .Case("oshst", ARM_MB::OSHST)
1632    .Default(~0U);
1633
1634  if (Opt == ~0U)
1635    return MatchOperand_NoMatch;
1636
1637  Parser.Lex(); // Eat identifier token.
1638  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1639  return MatchOperand_Success;
1640}
1641
1642/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1643ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1644parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1645  SMLoc S = Parser.getTok().getLoc();
1646  const AsmToken &Tok = Parser.getTok();
1647  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1648  StringRef IFlagsStr = Tok.getString();
1649
1650  unsigned IFlags = 0;
1651  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1652    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1653    .Case("a", ARM_PROC::A)
1654    .Case("i", ARM_PROC::I)
1655    .Case("f", ARM_PROC::F)
1656    .Default(~0U);
1657
1658    // If some specific iflag is already set, it means that some letter is
1659    // present more than once, this is not acceptable.
1660    if (Flag == ~0U || (IFlags & Flag))
1661      return MatchOperand_NoMatch;
1662
1663    IFlags |= Flag;
1664  }
1665
1666  Parser.Lex(); // Eat identifier token.
1667  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1668  return MatchOperand_Success;
1669}
1670
1671/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1672ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1673parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1674  SMLoc S = Parser.getTok().getLoc();
1675  const AsmToken &Tok = Parser.getTok();
1676  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1677  StringRef Mask = Tok.getString();
1678
1679  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1680  size_t Start = 0, Next = Mask.find('_');
1681  StringRef Flags = "";
1682  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1683  if (Next != StringRef::npos)
1684    Flags = Mask.slice(Next+1, Mask.size());
1685
1686  // FlagsVal contains the complete mask:
1687  // 3-0: Mask
1688  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1689  unsigned FlagsVal = 0;
1690
1691  if (SpecReg == "apsr") {
1692    FlagsVal = StringSwitch<unsigned>(Flags)
1693    .Case("nzcvq",  0x8) // same as CPSR_f
1694    .Case("g",      0x4) // same as CPSR_s
1695    .Case("nzcvqg", 0xc) // same as CPSR_fs
1696    .Default(~0U);
1697
1698    if (FlagsVal == ~0U) {
1699      if (!Flags.empty())
1700        return MatchOperand_NoMatch;
1701      else
1702        FlagsVal = 0; // No flag
1703    }
1704  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1705    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1706      Flags = "fc";
1707    for (int i = 0, e = Flags.size(); i != e; ++i) {
1708      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1709      .Case("c", 1)
1710      .Case("x", 2)
1711      .Case("s", 4)
1712      .Case("f", 8)
1713      .Default(~0U);
1714
1715      // If some specific flag is already set, it means that some letter is
1716      // present more than once, this is not acceptable.
1717      if (FlagsVal == ~0U || (FlagsVal & Flag))
1718        return MatchOperand_NoMatch;
1719      FlagsVal |= Flag;
1720    }
1721  } else // No match for special register.
1722    return MatchOperand_NoMatch;
1723
1724  // Special register without flags are equivalent to "fc" flags.
1725  if (!FlagsVal)
1726    FlagsVal = 0x9;
1727
1728  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1729  if (SpecReg == "spsr")
1730    FlagsVal |= 16;
1731
1732  Parser.Lex(); // Eat identifier token.
1733  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1734  return MatchOperand_Success;
1735}
1736
1737ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1738parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1739            int Low, int High) {
1740  const AsmToken &Tok = Parser.getTok();
1741  if (Tok.isNot(AsmToken::Identifier)) {
1742    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1743    return MatchOperand_ParseFail;
1744  }
1745  StringRef ShiftName = Tok.getString();
1746  std::string LowerOp = LowercaseString(Op);
1747  std::string UpperOp = UppercaseString(Op);
1748  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1749    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1750    return MatchOperand_ParseFail;
1751  }
1752  Parser.Lex(); // Eat shift type token.
1753
1754  // There must be a '#' and a shift amount.
1755  if (Parser.getTok().isNot(AsmToken::Hash)) {
1756    Error(Parser.getTok().getLoc(), "'#' expected");
1757    return MatchOperand_ParseFail;
1758  }
1759  Parser.Lex(); // Eat hash token.
1760
1761  const MCExpr *ShiftAmount;
1762  SMLoc Loc = Parser.getTok().getLoc();
1763  if (getParser().ParseExpression(ShiftAmount)) {
1764    Error(Loc, "illegal expression");
1765    return MatchOperand_ParseFail;
1766  }
1767  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1768  if (!CE) {
1769    Error(Loc, "constant expression expected");
1770    return MatchOperand_ParseFail;
1771  }
1772  int Val = CE->getValue();
1773  if (Val < Low || Val > High) {
1774    Error(Loc, "immediate value out of range");
1775    return MatchOperand_ParseFail;
1776  }
1777
1778  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1779
1780  return MatchOperand_Success;
1781}
1782
1783ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1784parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1785  const AsmToken &Tok = Parser.getTok();
1786  SMLoc S = Tok.getLoc();
1787  if (Tok.isNot(AsmToken::Identifier)) {
1788    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1789    return MatchOperand_ParseFail;
1790  }
1791  int Val = StringSwitch<int>(Tok.getString())
1792    .Case("be", 1)
1793    .Case("le", 0)
1794    .Default(-1);
1795  Parser.Lex(); // Eat the token.
1796
1797  if (Val == -1) {
1798    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1799    return MatchOperand_ParseFail;
1800  }
1801  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1802                                                                  getContext()),
1803                                           S, Parser.getTok().getLoc()));
1804  return MatchOperand_Success;
1805}
1806
1807/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1808/// instructions. Legal values are:
1809///     lsl #n  'n' in [0,31]
1810///     asr #n  'n' in [1,32]
1811///             n == 32 encoded as n == 0.
1812ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1813parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1814  const AsmToken &Tok = Parser.getTok();
1815  SMLoc S = Tok.getLoc();
1816  if (Tok.isNot(AsmToken::Identifier)) {
1817    Error(S, "shift operator 'asr' or 'lsl' expected");
1818    return MatchOperand_ParseFail;
1819  }
1820  StringRef ShiftName = Tok.getString();
1821  bool isASR;
1822  if (ShiftName == "lsl" || ShiftName == "LSL")
1823    isASR = false;
1824  else if (ShiftName == "asr" || ShiftName == "ASR")
1825    isASR = true;
1826  else {
1827    Error(S, "shift operator 'asr' or 'lsl' expected");
1828    return MatchOperand_ParseFail;
1829  }
1830  Parser.Lex(); // Eat the operator.
1831
1832  // A '#' and a shift amount.
1833  if (Parser.getTok().isNot(AsmToken::Hash)) {
1834    Error(Parser.getTok().getLoc(), "'#' expected");
1835    return MatchOperand_ParseFail;
1836  }
1837  Parser.Lex(); // Eat hash token.
1838
1839  const MCExpr *ShiftAmount;
1840  SMLoc E = Parser.getTok().getLoc();
1841  if (getParser().ParseExpression(ShiftAmount)) {
1842    Error(E, "malformed shift expression");
1843    return MatchOperand_ParseFail;
1844  }
1845  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1846  if (!CE) {
1847    Error(E, "shift amount must be an immediate");
1848    return MatchOperand_ParseFail;
1849  }
1850
1851  int64_t Val = CE->getValue();
1852  if (isASR) {
1853    // Shift amount must be in [1,32]
1854    if (Val < 1 || Val > 32) {
1855      Error(E, "'asr' shift amount must be in range [1,32]");
1856      return MatchOperand_ParseFail;
1857    }
1858    // asr #32 encoded as asr #0.
1859    if (Val == 32) Val = 0;
1860  } else {
1861    // Shift amount must be in [1,32]
1862    if (Val < 0 || Val > 31) {
1863      Error(E, "'lsr' shift amount must be in range [0,31]");
1864      return MatchOperand_ParseFail;
1865    }
1866  }
1867
1868  E = Parser.getTok().getLoc();
1869  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1870
1871  return MatchOperand_Success;
1872}
1873
1874/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1875/// of instructions. Legal values are:
1876///     ror #n  'n' in {0, 8, 16, 24}
1877ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1878parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1879  const AsmToken &Tok = Parser.getTok();
1880  SMLoc S = Tok.getLoc();
1881  if (Tok.isNot(AsmToken::Identifier)) {
1882    Error(S, "rotate operator 'ror' expected");
1883    return MatchOperand_ParseFail;
1884  }
1885  StringRef ShiftName = Tok.getString();
1886  if (ShiftName != "ror" && ShiftName != "ROR") {
1887    Error(S, "rotate operator 'ror' expected");
1888    return MatchOperand_ParseFail;
1889  }
1890  Parser.Lex(); // Eat the operator.
1891
1892  // A '#' and a rotate amount.
1893  if (Parser.getTok().isNot(AsmToken::Hash)) {
1894    Error(Parser.getTok().getLoc(), "'#' expected");
1895    return MatchOperand_ParseFail;
1896  }
1897  Parser.Lex(); // Eat hash token.
1898
1899  const MCExpr *ShiftAmount;
1900  SMLoc E = Parser.getTok().getLoc();
1901  if (getParser().ParseExpression(ShiftAmount)) {
1902    Error(E, "malformed rotate expression");
1903    return MatchOperand_ParseFail;
1904  }
1905  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1906  if (!CE) {
1907    Error(E, "rotate amount must be an immediate");
1908    return MatchOperand_ParseFail;
1909  }
1910
1911  int64_t Val = CE->getValue();
1912  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1913  // normally, zero is represented in asm by omitting the rotate operand
1914  // entirely.
1915  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1916    Error(E, "'ror' rotate amount must be 8, 16, or 24");
1917    return MatchOperand_ParseFail;
1918  }
1919
1920  E = Parser.getTok().getLoc();
1921  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
1922
1923  return MatchOperand_Success;
1924}
1925
1926ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1927parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1928  SMLoc S = Parser.getTok().getLoc();
1929  // The bitfield descriptor is really two operands, the LSB and the width.
1930  if (Parser.getTok().isNot(AsmToken::Hash)) {
1931    Error(Parser.getTok().getLoc(), "'#' expected");
1932    return MatchOperand_ParseFail;
1933  }
1934  Parser.Lex(); // Eat hash token.
1935
1936  const MCExpr *LSBExpr;
1937  SMLoc E = Parser.getTok().getLoc();
1938  if (getParser().ParseExpression(LSBExpr)) {
1939    Error(E, "malformed immediate expression");
1940    return MatchOperand_ParseFail;
1941  }
1942  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
1943  if (!CE) {
1944    Error(E, "'lsb' operand must be an immediate");
1945    return MatchOperand_ParseFail;
1946  }
1947
1948  int64_t LSB = CE->getValue();
1949  // The LSB must be in the range [0,31]
1950  if (LSB < 0 || LSB > 31) {
1951    Error(E, "'lsb' operand must be in the range [0,31]");
1952    return MatchOperand_ParseFail;
1953  }
1954  E = Parser.getTok().getLoc();
1955
1956  // Expect another immediate operand.
1957  if (Parser.getTok().isNot(AsmToken::Comma)) {
1958    Error(Parser.getTok().getLoc(), "too few operands");
1959    return MatchOperand_ParseFail;
1960  }
1961  Parser.Lex(); // Eat hash token.
1962  if (Parser.getTok().isNot(AsmToken::Hash)) {
1963    Error(Parser.getTok().getLoc(), "'#' expected");
1964    return MatchOperand_ParseFail;
1965  }
1966  Parser.Lex(); // Eat hash token.
1967
1968  const MCExpr *WidthExpr;
1969  if (getParser().ParseExpression(WidthExpr)) {
1970    Error(E, "malformed immediate expression");
1971    return MatchOperand_ParseFail;
1972  }
1973  CE = dyn_cast<MCConstantExpr>(WidthExpr);
1974  if (!CE) {
1975    Error(E, "'width' operand must be an immediate");
1976    return MatchOperand_ParseFail;
1977  }
1978
1979  int64_t Width = CE->getValue();
1980  // The LSB must be in the range [1,32-lsb]
1981  if (Width < 1 || Width > 32 - LSB) {
1982    Error(E, "'width' operand must be in the range [1,32-lsb]");
1983    return MatchOperand_ParseFail;
1984  }
1985  E = Parser.getTok().getLoc();
1986
1987  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
1988
1989  return MatchOperand_Success;
1990}
1991
1992ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1993parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1994  // Check for a post-index addressing register operand. Specifically:
1995  // postidx_reg := '+' register {, shift}
1996  //              | '-' register {, shift}
1997  //              | register {, shift}
1998
1999  // This method must return MatchOperand_NoMatch without consuming any tokens
2000  // in the case where there is no match, as other alternatives take other
2001  // parse methods.
2002  AsmToken Tok = Parser.getTok();
2003  SMLoc S = Tok.getLoc();
2004  bool haveEaten = false;
2005  bool isAdd = true;
2006  int Reg = -1;
2007  if (Tok.is(AsmToken::Plus)) {
2008    Parser.Lex(); // Eat the '+' token.
2009    haveEaten = true;
2010  } else if (Tok.is(AsmToken::Minus)) {
2011    Parser.Lex(); // Eat the '-' token.
2012    isAdd = false;
2013    haveEaten = true;
2014  }
2015  if (Parser.getTok().is(AsmToken::Identifier))
2016    Reg = tryParseRegister();
2017  if (Reg == -1) {
2018    if (!haveEaten)
2019      return MatchOperand_NoMatch;
2020    Error(Parser.getTok().getLoc(), "register expected");
2021    return MatchOperand_ParseFail;
2022  }
2023  SMLoc E = Parser.getTok().getLoc();
2024
2025  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2026  unsigned ShiftImm = 0;
2027  if (Parser.getTok().is(AsmToken::Comma)) {
2028    Parser.Lex(); // Eat the ','.
2029    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2030      return MatchOperand_ParseFail;
2031  }
2032
2033  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2034                                                  ShiftImm, S, E));
2035
2036  return MatchOperand_Success;
2037}
2038
2039ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2040parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2041  // Check for a post-index addressing register operand. Specifically:
2042  // am3offset := '+' register
2043  //              | '-' register
2044  //              | register
2045  //              | # imm
2046  //              | # + imm
2047  //              | # - imm
2048
2049  // This method must return MatchOperand_NoMatch without consuming any tokens
2050  // in the case where there is no match, as other alternatives take other
2051  // parse methods.
2052  AsmToken Tok = Parser.getTok();
2053  SMLoc S = Tok.getLoc();
2054
2055  // Do immediates first, as we always parse those if we have a '#'.
2056  if (Parser.getTok().is(AsmToken::Hash)) {
2057    Parser.Lex(); // Eat the '#'.
2058    // Explicitly look for a '-', as we need to encode negative zero
2059    // differently.
2060    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2061    const MCExpr *Offset;
2062    if (getParser().ParseExpression(Offset))
2063      return MatchOperand_ParseFail;
2064    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2065    if (!CE) {
2066      Error(S, "constant expression expected");
2067      return MatchOperand_ParseFail;
2068    }
2069    SMLoc E = Tok.getLoc();
2070    // Negative zero is encoded as the flag value INT32_MIN.
2071    int32_t Val = CE->getValue();
2072    if (isNegative && Val == 0)
2073      Val = INT32_MIN;
2074
2075    Operands.push_back(
2076      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2077
2078    return MatchOperand_Success;
2079  }
2080
2081
2082  bool haveEaten = false;
2083  bool isAdd = true;
2084  int Reg = -1;
2085  if (Tok.is(AsmToken::Plus)) {
2086    Parser.Lex(); // Eat the '+' token.
2087    haveEaten = true;
2088  } else if (Tok.is(AsmToken::Minus)) {
2089    Parser.Lex(); // Eat the '-' token.
2090    isAdd = false;
2091    haveEaten = true;
2092  }
2093  if (Parser.getTok().is(AsmToken::Identifier))
2094    Reg = tryParseRegister();
2095  if (Reg == -1) {
2096    if (!haveEaten)
2097      return MatchOperand_NoMatch;
2098    Error(Parser.getTok().getLoc(), "register expected");
2099    return MatchOperand_ParseFail;
2100  }
2101  SMLoc E = Parser.getTok().getLoc();
2102
2103  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2104                                                  0, S, E));
2105
2106  return MatchOperand_Success;
2107}
2108
2109/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2110/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2111/// when they refer multiple MIOperands inside a single one.
2112bool ARMAsmParser::
2113cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2114                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2115  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2116
2117  // Create a writeback register dummy placeholder.
2118  Inst.addOperand(MCOperand::CreateImm(0));
2119
2120  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2121  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2122  return true;
2123}
2124
2125/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2126/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2127/// when they refer multiple MIOperands inside a single one.
2128bool ARMAsmParser::
2129cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2130                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2131  // Create a writeback register dummy placeholder.
2132  Inst.addOperand(MCOperand::CreateImm(0));
2133  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2134  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2135  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2136  return true;
2137}
2138
2139/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2140/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2141/// when they refer multiple MIOperands inside a single one.
2142bool ARMAsmParser::
2143cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2144                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2145  // Create a writeback register dummy placeholder.
2146  Inst.addOperand(MCOperand::CreateImm(0));
2147  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2148  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2149  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2150  return true;
2151}
2152
2153/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2154/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2155/// when they refer multiple MIOperands inside a single one.
2156bool ARMAsmParser::
2157cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2158                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2159  // Create a writeback register dummy placeholder.
2160  Inst.addOperand(MCOperand::CreateImm(0));
2161  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2162  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2163  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2164  return true;
2165}
2166
2167/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2168/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2169/// when they refer multiple MIOperands inside a single one.
2170bool ARMAsmParser::
2171cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2172                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2173  // Rt
2174  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2175  // Create a writeback register dummy placeholder.
2176  Inst.addOperand(MCOperand::CreateImm(0));
2177  // addr
2178  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2179  // offset
2180  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2181  // pred
2182  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2183  return true;
2184}
2185
2186/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2187/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2188/// when they refer multiple MIOperands inside a single one.
2189bool ARMAsmParser::
2190cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2191                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2192  // Rt
2193  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2194  // Create a writeback register dummy placeholder.
2195  Inst.addOperand(MCOperand::CreateImm(0));
2196  // addr
2197  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2198  // offset
2199  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2200  // pred
2201  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2202  return true;
2203}
2204
2205/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2206/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2207/// when they refer multiple MIOperands inside a single one.
2208bool ARMAsmParser::
2209cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2210                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2211  // Create a writeback register dummy placeholder.
2212  Inst.addOperand(MCOperand::CreateImm(0));
2213  // Rt
2214  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2215  // addr
2216  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2217  // offset
2218  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2219  // pred
2220  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2221  return true;
2222}
2223
2224/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2225/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2226/// when they refer multiple MIOperands inside a single one.
2227bool ARMAsmParser::
2228cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2229                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2230  // Create a writeback register dummy placeholder.
2231  Inst.addOperand(MCOperand::CreateImm(0));
2232  // Rt
2233  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2234  // addr
2235  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2236  // offset
2237  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2238  // pred
2239  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2240  return true;
2241}
2242
2243/// cvtLdrdPre - Convert parsed operands to MCInst.
2244/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2245/// when they refer multiple MIOperands inside a single one.
2246bool ARMAsmParser::
2247cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2248           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2249  // Rt, Rt2
2250  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2251  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2252  // Create a writeback register dummy placeholder.
2253  Inst.addOperand(MCOperand::CreateImm(0));
2254  // addr
2255  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2256  // pred
2257  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2258  return true;
2259}
2260
2261/// cvtStrdPre - Convert parsed operands to MCInst.
2262/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2263/// when they refer multiple MIOperands inside a single one.
2264bool ARMAsmParser::
2265cvtStrdPre(MCInst &Inst, unsigned Opcode,
2266           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2267  // Create a writeback register dummy placeholder.
2268  Inst.addOperand(MCOperand::CreateImm(0));
2269  // Rt, Rt2
2270  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2271  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2272  // addr
2273  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2274  // pred
2275  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2276  return true;
2277}
2278
2279/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2280/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2281/// when they refer multiple MIOperands inside a single one.
2282bool ARMAsmParser::
2283cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2284                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2285  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2286  // Create a writeback register dummy placeholder.
2287  Inst.addOperand(MCOperand::CreateImm(0));
2288  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2289  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2290  return true;
2291}
2292
2293
2294/// Parse an ARM memory expression, return false if successful else return true
2295/// or an error.  The first token must be a '[' when called.
2296bool ARMAsmParser::
2297parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2298  SMLoc S, E;
2299  assert(Parser.getTok().is(AsmToken::LBrac) &&
2300         "Token is not a Left Bracket");
2301  S = Parser.getTok().getLoc();
2302  Parser.Lex(); // Eat left bracket token.
2303
2304  const AsmToken &BaseRegTok = Parser.getTok();
2305  int BaseRegNum = tryParseRegister();
2306  if (BaseRegNum == -1)
2307    return Error(BaseRegTok.getLoc(), "register expected");
2308
2309  // The next token must either be a comma or a closing bracket.
2310  const AsmToken &Tok = Parser.getTok();
2311  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2312    return Error(Tok.getLoc(), "malformed memory operand");
2313
2314  if (Tok.is(AsmToken::RBrac)) {
2315    E = Tok.getLoc();
2316    Parser.Lex(); // Eat right bracket token.
2317
2318    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2319                                             0, false, S, E));
2320
2321    return false;
2322  }
2323
2324  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2325  Parser.Lex(); // Eat the comma.
2326
2327  // If we have a '#' it's an immediate offset, else assume it's a register
2328  // offset.
2329  if (Parser.getTok().is(AsmToken::Hash)) {
2330    Parser.Lex(); // Eat the '#'.
2331    E = Parser.getTok().getLoc();
2332
2333    // FIXME: Special case #-0 so we can correctly set the U bit.
2334
2335    const MCExpr *Offset;
2336    if (getParser().ParseExpression(Offset))
2337     return true;
2338
2339    // The expression has to be a constant. Memory references with relocations
2340    // don't come through here, as they use the <label> forms of the relevant
2341    // instructions.
2342    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2343    if (!CE)
2344      return Error (E, "constant expression expected");
2345
2346    // Now we should have the closing ']'
2347    E = Parser.getTok().getLoc();
2348    if (Parser.getTok().isNot(AsmToken::RBrac))
2349      return Error(E, "']' expected");
2350    Parser.Lex(); // Eat right bracket token.
2351
2352    // Don't worry about range checking the value here. That's handled by
2353    // the is*() predicates.
2354    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2355                                             ARM_AM::no_shift, 0, false, S,E));
2356
2357    // If there's a pre-indexing writeback marker, '!', just add it as a token
2358    // operand.
2359    if (Parser.getTok().is(AsmToken::Exclaim)) {
2360      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2361      Parser.Lex(); // Eat the '!'.
2362    }
2363
2364    return false;
2365  }
2366
2367  // The register offset is optionally preceded by a '+' or '-'
2368  bool isNegative = false;
2369  if (Parser.getTok().is(AsmToken::Minus)) {
2370    isNegative = true;
2371    Parser.Lex(); // Eat the '-'.
2372  } else if (Parser.getTok().is(AsmToken::Plus)) {
2373    // Nothing to do.
2374    Parser.Lex(); // Eat the '+'.
2375  }
2376
2377  E = Parser.getTok().getLoc();
2378  int OffsetRegNum = tryParseRegister();
2379  if (OffsetRegNum == -1)
2380    return Error(E, "register expected");
2381
2382  // If there's a shift operator, handle it.
2383  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2384  unsigned ShiftImm = 0;
2385  if (Parser.getTok().is(AsmToken::Comma)) {
2386    Parser.Lex(); // Eat the ','.
2387    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2388      return true;
2389  }
2390
2391  // Now we should have the closing ']'
2392  E = Parser.getTok().getLoc();
2393  if (Parser.getTok().isNot(AsmToken::RBrac))
2394    return Error(E, "']' expected");
2395  Parser.Lex(); // Eat right bracket token.
2396
2397  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2398                                           ShiftType, ShiftImm, isNegative,
2399                                           S, E));
2400
2401  // If there's a pre-indexing writeback marker, '!', just add it as a token
2402  // operand.
2403  if (Parser.getTok().is(AsmToken::Exclaim)) {
2404    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2405    Parser.Lex(); // Eat the '!'.
2406  }
2407
2408  return false;
2409}
2410
2411/// parseMemRegOffsetShift - one of these two:
2412///   ( lsl | lsr | asr | ror ) , # shift_amount
2413///   rrx
2414/// return true if it parses a shift otherwise it returns false.
2415bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2416                                          unsigned &Amount) {
2417  SMLoc Loc = Parser.getTok().getLoc();
2418  const AsmToken &Tok = Parser.getTok();
2419  if (Tok.isNot(AsmToken::Identifier))
2420    return true;
2421  StringRef ShiftName = Tok.getString();
2422  if (ShiftName == "lsl" || ShiftName == "LSL")
2423    St = ARM_AM::lsl;
2424  else if (ShiftName == "lsr" || ShiftName == "LSR")
2425    St = ARM_AM::lsr;
2426  else if (ShiftName == "asr" || ShiftName == "ASR")
2427    St = ARM_AM::asr;
2428  else if (ShiftName == "ror" || ShiftName == "ROR")
2429    St = ARM_AM::ror;
2430  else if (ShiftName == "rrx" || ShiftName == "RRX")
2431    St = ARM_AM::rrx;
2432  else
2433    return Error(Loc, "illegal shift operator");
2434  Parser.Lex(); // Eat shift type token.
2435
2436  // rrx stands alone.
2437  Amount = 0;
2438  if (St != ARM_AM::rrx) {
2439    Loc = Parser.getTok().getLoc();
2440    // A '#' and a shift amount.
2441    const AsmToken &HashTok = Parser.getTok();
2442    if (HashTok.isNot(AsmToken::Hash))
2443      return Error(HashTok.getLoc(), "'#' expected");
2444    Parser.Lex(); // Eat hash token.
2445
2446    const MCExpr *Expr;
2447    if (getParser().ParseExpression(Expr))
2448      return true;
2449    // Range check the immediate.
2450    // lsl, ror: 0 <= imm <= 31
2451    // lsr, asr: 0 <= imm <= 32
2452    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2453    if (!CE)
2454      return Error(Loc, "shift amount must be an immediate");
2455    int64_t Imm = CE->getValue();
2456    if (Imm < 0 ||
2457        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2458        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2459      return Error(Loc, "immediate shift value out of range");
2460    Amount = Imm;
2461  }
2462
2463  return false;
2464}
2465
2466/// Parse a arm instruction operand.  For now this parses the operand regardless
2467/// of the mnemonic.
2468bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2469                                StringRef Mnemonic) {
2470  SMLoc S, E;
2471
2472  // Check if the current operand has a custom associated parser, if so, try to
2473  // custom parse the operand, or fallback to the general approach.
2474  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2475  if (ResTy == MatchOperand_Success)
2476    return false;
2477  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2478  // there was a match, but an error occurred, in which case, just return that
2479  // the operand parsing failed.
2480  if (ResTy == MatchOperand_ParseFail)
2481    return true;
2482
2483  switch (getLexer().getKind()) {
2484  default:
2485    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2486    return true;
2487  case AsmToken::Identifier: {
2488    if (!tryParseRegisterWithWriteBack(Operands))
2489      return false;
2490    int Res = tryParseShiftRegister(Operands);
2491    if (Res == 0) // success
2492      return false;
2493    else if (Res == -1) // irrecoverable error
2494      return true;
2495
2496    // Fall though for the Identifier case that is not a register or a
2497    // special name.
2498  }
2499  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2500  case AsmToken::Dot: {   // . as a branch target
2501    // This was not a register so parse other operands that start with an
2502    // identifier (like labels) as expressions and create them as immediates.
2503    const MCExpr *IdVal;
2504    S = Parser.getTok().getLoc();
2505    if (getParser().ParseExpression(IdVal))
2506      return true;
2507    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2508    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2509    return false;
2510  }
2511  case AsmToken::LBrac:
2512    return parseMemory(Operands);
2513  case AsmToken::LCurly:
2514    return parseRegisterList(Operands);
2515  case AsmToken::Hash:
2516    // #42 -> immediate.
2517    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2518    S = Parser.getTok().getLoc();
2519    Parser.Lex();
2520    const MCExpr *ImmVal;
2521    if (getParser().ParseExpression(ImmVal))
2522      return true;
2523    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2524    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2525    return false;
2526  case AsmToken::Colon: {
2527    // ":lower16:" and ":upper16:" expression prefixes
2528    // FIXME: Check it's an expression prefix,
2529    // e.g. (FOO - :lower16:BAR) isn't legal.
2530    ARMMCExpr::VariantKind RefKind;
2531    if (parsePrefix(RefKind))
2532      return true;
2533
2534    const MCExpr *SubExprVal;
2535    if (getParser().ParseExpression(SubExprVal))
2536      return true;
2537
2538    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2539                                                   getContext());
2540    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2541    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2542    return false;
2543  }
2544  }
2545}
2546
2547// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2548//  :lower16: and :upper16:.
2549bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2550  RefKind = ARMMCExpr::VK_ARM_None;
2551
2552  // :lower16: and :upper16: modifiers
2553  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2554  Parser.Lex(); // Eat ':'
2555
2556  if (getLexer().isNot(AsmToken::Identifier)) {
2557    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2558    return true;
2559  }
2560
2561  StringRef IDVal = Parser.getTok().getIdentifier();
2562  if (IDVal == "lower16") {
2563    RefKind = ARMMCExpr::VK_ARM_LO16;
2564  } else if (IDVal == "upper16") {
2565    RefKind = ARMMCExpr::VK_ARM_HI16;
2566  } else {
2567    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2568    return true;
2569  }
2570  Parser.Lex();
2571
2572  if (getLexer().isNot(AsmToken::Colon)) {
2573    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2574    return true;
2575  }
2576  Parser.Lex(); // Eat the last ':'
2577  return false;
2578}
2579
2580const MCExpr *
2581ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2582                                MCSymbolRefExpr::VariantKind Variant) {
2583  // Recurse over the given expression, rebuilding it to apply the given variant
2584  // to the leftmost symbol.
2585  if (Variant == MCSymbolRefExpr::VK_None)
2586    return E;
2587
2588  switch (E->getKind()) {
2589  case MCExpr::Target:
2590    llvm_unreachable("Can't handle target expr yet");
2591  case MCExpr::Constant:
2592    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2593
2594  case MCExpr::SymbolRef: {
2595    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2596
2597    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2598      return 0;
2599
2600    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2601  }
2602
2603  case MCExpr::Unary:
2604    llvm_unreachable("Can't handle unary expressions yet");
2605
2606  case MCExpr::Binary: {
2607    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2608    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2609    const MCExpr *RHS = BE->getRHS();
2610    if (!LHS)
2611      return 0;
2612
2613    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2614  }
2615  }
2616
2617  assert(0 && "Invalid expression kind!");
2618  return 0;
2619}
2620
2621/// \brief Given a mnemonic, split out possible predication code and carry
2622/// setting letters to form a canonical mnemonic and flags.
2623//
2624// FIXME: Would be nice to autogen this.
2625StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2626                                      unsigned &PredicationCode,
2627                                      bool &CarrySetting,
2628                                      unsigned &ProcessorIMod) {
2629  PredicationCode = ARMCC::AL;
2630  CarrySetting = false;
2631  ProcessorIMod = 0;
2632
2633  // Ignore some mnemonics we know aren't predicated forms.
2634  //
2635  // FIXME: Would be nice to autogen this.
2636  if ((Mnemonic == "movs" && isThumb()) ||
2637      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2638      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2639      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2640      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2641      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2642      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2643      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2644    return Mnemonic;
2645
2646  // First, split out any predication code. Ignore mnemonics we know aren't
2647  // predicated but do have a carry-set and so weren't caught above.
2648  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2649      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2650      Mnemonic != "umlals" && Mnemonic != "umulls") {
2651    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2652      .Case("eq", ARMCC::EQ)
2653      .Case("ne", ARMCC::NE)
2654      .Case("hs", ARMCC::HS)
2655      .Case("cs", ARMCC::HS)
2656      .Case("lo", ARMCC::LO)
2657      .Case("cc", ARMCC::LO)
2658      .Case("mi", ARMCC::MI)
2659      .Case("pl", ARMCC::PL)
2660      .Case("vs", ARMCC::VS)
2661      .Case("vc", ARMCC::VC)
2662      .Case("hi", ARMCC::HI)
2663      .Case("ls", ARMCC::LS)
2664      .Case("ge", ARMCC::GE)
2665      .Case("lt", ARMCC::LT)
2666      .Case("gt", ARMCC::GT)
2667      .Case("le", ARMCC::LE)
2668      .Case("al", ARMCC::AL)
2669      .Default(~0U);
2670    if (CC != ~0U) {
2671      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2672      PredicationCode = CC;
2673    }
2674  }
2675
2676  // Next, determine if we have a carry setting bit. We explicitly ignore all
2677  // the instructions we know end in 's'.
2678  if (Mnemonic.endswith("s") &&
2679      !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2680        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2681        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2682        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2683        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2684        (Mnemonic == "movs" && isThumb()))) {
2685    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2686    CarrySetting = true;
2687  }
2688
2689  // The "cps" instruction can have a interrupt mode operand which is glued into
2690  // the mnemonic. Check if this is the case, split it and parse the imod op
2691  if (Mnemonic.startswith("cps")) {
2692    // Split out any imod code.
2693    unsigned IMod =
2694      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2695      .Case("ie", ARM_PROC::IE)
2696      .Case("id", ARM_PROC::ID)
2697      .Default(~0U);
2698    if (IMod != ~0U) {
2699      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2700      ProcessorIMod = IMod;
2701    }
2702  }
2703
2704  return Mnemonic;
2705}
2706
2707/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2708/// inclusion of carry set or predication code operands.
2709//
2710// FIXME: It would be nice to autogen this.
2711void ARMAsmParser::
2712getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2713                      bool &CanAcceptPredicationCode) {
2714  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2715      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2716      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2717      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2718      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2719      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2720      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2721      Mnemonic == "eor" || Mnemonic == "smlal" ||
2722      // FIXME: We need a better way. This really confused Thumb2
2723      // parsing for 'mov'.
2724      (Mnemonic == "mov" && !isThumbOne())) {
2725    CanAcceptCarrySet = true;
2726  } else {
2727    CanAcceptCarrySet = false;
2728  }
2729
2730  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2731      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2732      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2733      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2734      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2735      Mnemonic == "setend" ||
2736      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2737      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2738        && !isThumb()) ||
2739      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2740    CanAcceptPredicationCode = false;
2741  } else {
2742    CanAcceptPredicationCode = true;
2743  }
2744
2745  if (isThumb())
2746    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2747        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2748      CanAcceptPredicationCode = false;
2749}
2750
2751bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2752                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2753
2754  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2755  // another does not. Specifically, the MOVW instruction does not. So we
2756  // special case it here and remove the defaulted (non-setting) cc_out
2757  // operand if that's the instruction we're trying to match.
2758  //
2759  // We do this as post-processing of the explicit operands rather than just
2760  // conditionally adding the cc_out in the first place because we need
2761  // to check the type of the parsed immediate operand.
2762  if (Mnemonic == "mov" && Operands.size() > 4 &&
2763      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2764      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2765      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2766    return true;
2767
2768  // Register-register 'add' for thumb does not have a cc_out operand
2769  // when there are only two register operands.
2770  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2771      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2772      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2773      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2774    return true;
2775
2776  return false;
2777}
2778
2779/// Parse an arm instruction mnemonic followed by its operands.
2780bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2781                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2782  // Create the leading tokens for the mnemonic, split by '.' characters.
2783  size_t Start = 0, Next = Name.find('.');
2784  StringRef Mnemonic = Name.slice(Start, Next);
2785
2786  // Split out the predication code and carry setting flag from the mnemonic.
2787  unsigned PredicationCode;
2788  unsigned ProcessorIMod;
2789  bool CarrySetting;
2790  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2791                           ProcessorIMod);
2792
2793  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2794
2795  // FIXME: This is all a pretty gross hack. We should automatically handle
2796  // optional operands like this via tblgen.
2797
2798  // Next, add the CCOut and ConditionCode operands, if needed.
2799  //
2800  // For mnemonics which can ever incorporate a carry setting bit or predication
2801  // code, our matching model involves us always generating CCOut and
2802  // ConditionCode operands to match the mnemonic "as written" and then we let
2803  // the matcher deal with finding the right instruction or generating an
2804  // appropriate error.
2805  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2806  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2807
2808  // If we had a carry-set on an instruction that can't do that, issue an
2809  // error.
2810  if (!CanAcceptCarrySet && CarrySetting) {
2811    Parser.EatToEndOfStatement();
2812    return Error(NameLoc, "instruction '" + Mnemonic +
2813                 "' can not set flags, but 's' suffix specified");
2814  }
2815  // If we had a predication code on an instruction that can't do that, issue an
2816  // error.
2817  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2818    Parser.EatToEndOfStatement();
2819    return Error(NameLoc, "instruction '" + Mnemonic +
2820                 "' is not predicable, but condition code specified");
2821  }
2822
2823  // Add the carry setting operand, if necessary.
2824  //
2825  // FIXME: It would be awesome if we could somehow invent a location such that
2826  // match errors on this operand would print a nice diagnostic about how the
2827  // 's' character in the mnemonic resulted in a CCOut operand.
2828  if (CanAcceptCarrySet)
2829    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2830                                               NameLoc));
2831
2832  // Add the predication code operand, if necessary.
2833  if (CanAcceptPredicationCode) {
2834    Operands.push_back(ARMOperand::CreateCondCode(
2835                         ARMCC::CondCodes(PredicationCode), NameLoc));
2836  }
2837
2838  // Add the processor imod operand, if necessary.
2839  if (ProcessorIMod) {
2840    Operands.push_back(ARMOperand::CreateImm(
2841          MCConstantExpr::Create(ProcessorIMod, getContext()),
2842                                 NameLoc, NameLoc));
2843  } else {
2844    // This mnemonic can't ever accept a imod, but the user wrote
2845    // one (or misspelled another mnemonic).
2846
2847    // FIXME: Issue a nice error.
2848  }
2849
2850  // Add the remaining tokens in the mnemonic.
2851  while (Next != StringRef::npos) {
2852    Start = Next;
2853    Next = Name.find('.', Start + 1);
2854    StringRef ExtraToken = Name.slice(Start, Next);
2855
2856    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2857  }
2858
2859  // Read the remaining operands.
2860  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2861    // Read the first operand.
2862    if (parseOperand(Operands, Mnemonic)) {
2863      Parser.EatToEndOfStatement();
2864      return true;
2865    }
2866
2867    while (getLexer().is(AsmToken::Comma)) {
2868      Parser.Lex();  // Eat the comma.
2869
2870      // Parse and remember the operand.
2871      if (parseOperand(Operands, Mnemonic)) {
2872        Parser.EatToEndOfStatement();
2873        return true;
2874      }
2875    }
2876  }
2877
2878  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2879    Parser.EatToEndOfStatement();
2880    return TokError("unexpected token in argument list");
2881  }
2882
2883  Parser.Lex(); // Consume the EndOfStatement
2884
2885  // Some instructions, mostly Thumb, have forms for the same mnemonic that
2886  // do and don't have a cc_out optional-def operand. With some spot-checks
2887  // of the operand list, we can figure out which variant we're trying to
2888  // parse and adjust accordingly before actually matching. Reason number
2889  // #317 the table driven matcher doesn't fit well with the ARM instruction
2890  // set.
2891  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
2892    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2893    Operands.erase(Operands.begin() + 1);
2894    delete Op;
2895  }
2896
2897  // ARM mode 'blx' need special handling, as the register operand version
2898  // is predicable, but the label operand version is not. So, we can't rely
2899  // on the Mnemonic based checking to correctly figure out when to put
2900  // a CondCode operand in the list. If we're trying to match the label
2901  // version, remove the CondCode operand here.
2902  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
2903      static_cast<ARMOperand*>(Operands[2])->isImm()) {
2904    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2905    Operands.erase(Operands.begin() + 1);
2906    delete Op;
2907  }
2908
2909  // The vector-compare-to-zero instructions have a literal token "#0" at
2910  // the end that comes to here as an immediate operand. Convert it to a
2911  // token to play nicely with the matcher.
2912  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
2913      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
2914      static_cast<ARMOperand*>(Operands[5])->isImm()) {
2915    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
2916    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
2917    if (CE && CE->getValue() == 0) {
2918      Operands.erase(Operands.begin() + 5);
2919      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
2920      delete Op;
2921    }
2922  }
2923  return false;
2924}
2925
2926// Validate context-sensitive operand constraints.
2927// FIXME: We would really like to be able to tablegen'erate this.
2928bool ARMAsmParser::
2929validateInstruction(MCInst &Inst,
2930                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2931  switch (Inst.getOpcode()) {
2932  case ARM::LDRD:
2933  case ARM::LDRD_PRE:
2934  case ARM::LDRD_POST:
2935  case ARM::LDREXD: {
2936    // Rt2 must be Rt + 1.
2937    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2938    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2939    if (Rt2 != Rt + 1)
2940      return Error(Operands[3]->getStartLoc(),
2941                   "destination operands must be sequential");
2942    return false;
2943  }
2944  case ARM::STRD: {
2945    // Rt2 must be Rt + 1.
2946    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2947    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2948    if (Rt2 != Rt + 1)
2949      return Error(Operands[3]->getStartLoc(),
2950                   "source operands must be sequential");
2951    return false;
2952  }
2953  case ARM::STRD_PRE:
2954  case ARM::STRD_POST:
2955  case ARM::STREXD: {
2956    // Rt2 must be Rt + 1.
2957    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2958    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
2959    if (Rt2 != Rt + 1)
2960      return Error(Operands[3]->getStartLoc(),
2961                   "source operands must be sequential");
2962    return false;
2963  }
2964  case ARM::SBFX:
2965  case ARM::UBFX: {
2966    // width must be in range [1, 32-lsb]
2967    unsigned lsb = Inst.getOperand(2).getImm();
2968    unsigned widthm1 = Inst.getOperand(3).getImm();
2969    if (widthm1 >= 32 - lsb)
2970      return Error(Operands[5]->getStartLoc(),
2971                   "bitfield width must be in range [1,32-lsb]");
2972    return false;
2973  }
2974  }
2975
2976  return false;
2977}
2978
2979void ARMAsmParser::
2980processInstruction(MCInst &Inst,
2981                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2982  switch (Inst.getOpcode()) {
2983  case ARM::LDMIA_UPD:
2984    // If this is a load of a single register via a 'pop', then we should use
2985    // a post-indexed LDR instruction instead, per the ARM ARM.
2986    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
2987        Inst.getNumOperands() == 5) {
2988      MCInst TmpInst;
2989      TmpInst.setOpcode(ARM::LDR_POST_IMM);
2990      TmpInst.addOperand(Inst.getOperand(4)); // Rt
2991      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
2992      TmpInst.addOperand(Inst.getOperand(1)); // Rn
2993      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
2994      TmpInst.addOperand(MCOperand::CreateImm(4));
2995      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
2996      TmpInst.addOperand(Inst.getOperand(3));
2997      Inst = TmpInst;
2998    }
2999    break;
3000  case ARM::STMDB_UPD:
3001    // If this is a store of a single register via a 'push', then we should use
3002    // a pre-indexed STR instruction instead, per the ARM ARM.
3003    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3004        Inst.getNumOperands() == 5) {
3005      MCInst TmpInst;
3006      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3007      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3008      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3009      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3010      TmpInst.addOperand(MCOperand::CreateImm(-4));
3011      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3012      TmpInst.addOperand(Inst.getOperand(3));
3013      Inst = TmpInst;
3014    }
3015    break;
3016  }
3017}
3018
3019// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3020// the ARMInsts array) instead. Getting that here requires awkward
3021// API changes, though. Better way?
3022namespace llvm {
3023extern MCInstrDesc ARMInsts[];
3024}
3025static MCInstrDesc &getInstDesc(unsigned Opcode) {
3026  return ARMInsts[Opcode];
3027}
3028
3029unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3030  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3031  // suffix depending on whether they're in an IT block or not.
3032  unsigned Opc = Inst.getOpcode();
3033  MCInstrDesc &MCID = getInstDesc(Opc);
3034  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3035    assert(MCID.hasOptionalDef() &&
3036           "optionally flag setting instruction missing optional def operand");
3037    assert(MCID.NumOperands == Inst.getNumOperands() &&
3038           "operand count mismatch!");
3039    // Find the optional-def operand (cc_out).
3040    unsigned OpNo;
3041    for (OpNo = 0;
3042         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3043         ++OpNo)
3044      ;
3045    // If we're parsing Thumb1, reject it completely.
3046    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3047      return Match_MnemonicFail;
3048    // If we're parsing Thumb2, which form is legal depends on whether we're
3049    // in an IT block.
3050    // FIXME: We don't yet do IT blocks, so just always consider it to be
3051    // that we aren't in one until we do.
3052    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3053      return Match_RequiresITBlock;
3054  }
3055  // Some high-register supporting Thumb1 encodings only allow both registers
3056  // to be from r0-r7 when in Thumb2.
3057  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3058           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3059           isARMLowRegister(Inst.getOperand(2).getReg()))
3060    return Match_RequiresThumb2;
3061  // Others only require ARMv6 or later.
3062  else if (Opc == ARM::tMOVr && isThumbOne() &&
3063           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3064           isARMLowRegister(Inst.getOperand(1).getReg()))
3065    return Match_RequiresV6;
3066  return Match_Success;
3067}
3068
3069bool ARMAsmParser::
3070MatchAndEmitInstruction(SMLoc IDLoc,
3071                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3072                        MCStreamer &Out) {
3073  MCInst Inst;
3074  unsigned ErrorInfo;
3075  unsigned MatchResult;
3076  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3077  switch (MatchResult) {
3078  default: break;
3079  case Match_Success:
3080    // Context sensitive operand constraints aren't handled by the matcher,
3081    // so check them here.
3082    if (validateInstruction(Inst, Operands))
3083      return true;
3084
3085    // Some instructions need post-processing to, for example, tweak which
3086    // encoding is selected.
3087    processInstruction(Inst, Operands);
3088
3089    Out.EmitInstruction(Inst);
3090    return false;
3091  case Match_MissingFeature:
3092    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3093    return true;
3094  case Match_InvalidOperand: {
3095    SMLoc ErrorLoc = IDLoc;
3096    if (ErrorInfo != ~0U) {
3097      if (ErrorInfo >= Operands.size())
3098        return Error(IDLoc, "too few operands for instruction");
3099
3100      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3101      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3102    }
3103
3104    return Error(ErrorLoc, "invalid operand for instruction");
3105  }
3106  case Match_MnemonicFail:
3107    return Error(IDLoc, "invalid instruction");
3108  case Match_ConversionFail:
3109    return Error(IDLoc, "unable to convert operands to instruction");
3110  case Match_RequiresITBlock:
3111    return Error(IDLoc, "instruction only valid inside IT block");
3112  case Match_RequiresV6:
3113    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3114  case Match_RequiresThumb2:
3115    return Error(IDLoc, "instruction variant requires Thumb2");
3116  }
3117
3118  llvm_unreachable("Implement any new match types added!");
3119  return true;
3120}
3121
3122/// parseDirective parses the arm specific directives
3123bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3124  StringRef IDVal = DirectiveID.getIdentifier();
3125  if (IDVal == ".word")
3126    return parseDirectiveWord(4, DirectiveID.getLoc());
3127  else if (IDVal == ".thumb")
3128    return parseDirectiveThumb(DirectiveID.getLoc());
3129  else if (IDVal == ".thumb_func")
3130    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3131  else if (IDVal == ".code")
3132    return parseDirectiveCode(DirectiveID.getLoc());
3133  else if (IDVal == ".syntax")
3134    return parseDirectiveSyntax(DirectiveID.getLoc());
3135  return true;
3136}
3137
3138/// parseDirectiveWord
3139///  ::= .word [ expression (, expression)* ]
3140bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3141  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3142    for (;;) {
3143      const MCExpr *Value;
3144      if (getParser().ParseExpression(Value))
3145        return true;
3146
3147      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3148
3149      if (getLexer().is(AsmToken::EndOfStatement))
3150        break;
3151
3152      // FIXME: Improve diagnostic.
3153      if (getLexer().isNot(AsmToken::Comma))
3154        return Error(L, "unexpected token in directive");
3155      Parser.Lex();
3156    }
3157  }
3158
3159  Parser.Lex();
3160  return false;
3161}
3162
3163/// parseDirectiveThumb
3164///  ::= .thumb
3165bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3166  if (getLexer().isNot(AsmToken::EndOfStatement))
3167    return Error(L, "unexpected token in directive");
3168  Parser.Lex();
3169
3170  // TODO: set thumb mode
3171  // TODO: tell the MC streamer the mode
3172  // getParser().getStreamer().Emit???();
3173  return false;
3174}
3175
3176/// parseDirectiveThumbFunc
3177///  ::= .thumbfunc symbol_name
3178bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3179  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3180  bool isMachO = MAI.hasSubsectionsViaSymbols();
3181  StringRef Name;
3182
3183  // Darwin asm has function name after .thumb_func direction
3184  // ELF doesn't
3185  if (isMachO) {
3186    const AsmToken &Tok = Parser.getTok();
3187    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3188      return Error(L, "unexpected token in .thumb_func directive");
3189    Name = Tok.getString();
3190    Parser.Lex(); // Consume the identifier token.
3191  }
3192
3193  if (getLexer().isNot(AsmToken::EndOfStatement))
3194    return Error(L, "unexpected token in directive");
3195  Parser.Lex();
3196
3197  // FIXME: assuming function name will be the line following .thumb_func
3198  if (!isMachO) {
3199    Name = Parser.getTok().getString();
3200  }
3201
3202  // Mark symbol as a thumb symbol.
3203  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3204  getParser().getStreamer().EmitThumbFunc(Func);
3205  return false;
3206}
3207
3208/// parseDirectiveSyntax
3209///  ::= .syntax unified | divided
3210bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3211  const AsmToken &Tok = Parser.getTok();
3212  if (Tok.isNot(AsmToken::Identifier))
3213    return Error(L, "unexpected token in .syntax directive");
3214  StringRef Mode = Tok.getString();
3215  if (Mode == "unified" || Mode == "UNIFIED")
3216    Parser.Lex();
3217  else if (Mode == "divided" || Mode == "DIVIDED")
3218    return Error(L, "'.syntax divided' arm asssembly not supported");
3219  else
3220    return Error(L, "unrecognized syntax mode in .syntax directive");
3221
3222  if (getLexer().isNot(AsmToken::EndOfStatement))
3223    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3224  Parser.Lex();
3225
3226  // TODO tell the MC streamer the mode
3227  // getParser().getStreamer().Emit???();
3228  return false;
3229}
3230
3231/// parseDirectiveCode
3232///  ::= .code 16 | 32
3233bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3234  const AsmToken &Tok = Parser.getTok();
3235  if (Tok.isNot(AsmToken::Integer))
3236    return Error(L, "unexpected token in .code directive");
3237  int64_t Val = Parser.getTok().getIntVal();
3238  if (Val == 16)
3239    Parser.Lex();
3240  else if (Val == 32)
3241    Parser.Lex();
3242  else
3243    return Error(L, "invalid operand to .code directive");
3244
3245  if (getLexer().isNot(AsmToken::EndOfStatement))
3246    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3247  Parser.Lex();
3248
3249  if (Val == 16) {
3250    if (!isThumb()) {
3251      SwitchMode();
3252      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3253    }
3254  } else {
3255    if (isThumb()) {
3256      SwitchMode();
3257      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3258    }
3259  }
3260
3261  return false;
3262}
3263
3264extern "C" void LLVMInitializeARMAsmLexer();
3265
3266/// Force static initialization.
3267extern "C" void LLVMInitializeARMAsmParser() {
3268  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3269  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3270  LLVMInitializeARMAsmLexer();
3271}
3272
3273#define GET_REGISTER_MATCHER
3274#define GET_MATCHER_IMPLEMENTATION
3275#include "ARMGenAsmMatcher.inc"
3276