ARMAsmParser.cpp revision 2d539691a1e4b9d61853aa99d1a5580dc88595db 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  struct {
48    ARMCC::CondCodes Cond;    // Condition for IT block.
49    unsigned Mask:4;          // Condition mask for instructions.
50                              // Starting at first 1 (from lsb).
51                              //   '1'  condition as indicated in IT.
52                              //   '0'  inverse of condition (else).
53                              // Count of instructions in IT block is
54                              // 4 - trailingzeroes(mask)
55
56    bool FirstCond;           // Explicit flag for when we're parsing the
57                              // First instruction in the IT block. It's
58                              // implied in the mask, so needs special
59                              // handling.
60
61    unsigned CurPosition;     // Current position in parsing of IT
62                              // block. In range [0,3]. Initialized
63                              // according to count of instructions in block.
64                              // ~0U if no active IT block.
65  } ITState;
66  bool inITBlock() { return ITState.CurPosition != ~0U;}
67  void forwardITPosition() {
68    if (!inITBlock()) return;
69    // Move to the next instruction in the IT block, if there is one. If not,
70    // mark the block as done.
71    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72    if (++ITState.CurPosition == 5 - TZ)
73      ITState.CurPosition = ~0U; // Done with the IT block after this.
74  }
75
76
77  MCAsmParser &getParser() const { return Parser; }
78  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
79
80  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
82
83  int tryParseRegister();
84  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90  const MCExpr *applyPrefixToExpr(const MCExpr *E,
91                                  MCSymbolRefExpr::VariantKind Variant);
92
93
94  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95                              unsigned &ShiftAmount);
96  bool parseDirectiveWord(unsigned Size, SMLoc L);
97  bool parseDirectiveThumb(SMLoc L);
98  bool parseDirectiveThumbFunc(SMLoc L);
99  bool parseDirectiveCode(SMLoc L);
100  bool parseDirectiveSyntax(SMLoc L);
101
102  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
103                          bool &CarrySetting, unsigned &ProcessorIMod,
104                          StringRef &ITMask);
105  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
106                             bool &CanAcceptPredicationCode);
107
108  bool isThumb() const {
109    // FIXME: Can tablegen auto-generate this?
110    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
111  }
112  bool isThumbOne() const {
113    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
114  }
115  bool isThumbTwo() const {
116    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
117  }
118  bool hasV6Ops() const {
119    return STI.getFeatureBits() & ARM::HasV6Ops;
120  }
121  void SwitchMode() {
122    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123    setAvailableFeatures(FB);
124  }
125
126  /// @name Auto-generated Match Functions
127  /// {
128
129#define GET_ASSEMBLER_HEADER
130#include "ARMGenAsmMatcher.inc"
131
132  /// }
133
134  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
135  OperandMatchResultTy parseCoprocNumOperand(
136    SmallVectorImpl<MCParsedAsmOperand*>&);
137  OperandMatchResultTy parseCoprocRegOperand(
138    SmallVectorImpl<MCParsedAsmOperand*>&);
139  OperandMatchResultTy parseMemBarrierOptOperand(
140    SmallVectorImpl<MCParsedAsmOperand*>&);
141  OperandMatchResultTy parseProcIFlagsOperand(
142    SmallVectorImpl<MCParsedAsmOperand*>&);
143  OperandMatchResultTy parseMSRMaskOperand(
144    SmallVectorImpl<MCParsedAsmOperand*>&);
145  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
146                                   StringRef Op, int Low, int High);
147  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
148    return parsePKHImm(O, "lsl", 0, 31);
149  }
150  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151    return parsePKHImm(O, "asr", 1, 32);
152  }
153  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
154  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
156  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
159
160  // Asm Match Converter Methods
161  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
162                    const SmallVectorImpl<MCParsedAsmOperand*> &);
163  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
164                    const SmallVectorImpl<MCParsedAsmOperand*> &);
165  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
166                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
167  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
168                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
169  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
170                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
171  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
172                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
173  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
174                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
175  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
176                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
177  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
178                             const SmallVectorImpl<MCParsedAsmOperand*> &);
179  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
180                             const SmallVectorImpl<MCParsedAsmOperand*> &);
181  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
182                             const SmallVectorImpl<MCParsedAsmOperand*> &);
183  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
184                             const SmallVectorImpl<MCParsedAsmOperand*> &);
185  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
186                  const SmallVectorImpl<MCParsedAsmOperand*> &);
187  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
188                  const SmallVectorImpl<MCParsedAsmOperand*> &);
189  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
190                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
191  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
192                        const SmallVectorImpl<MCParsedAsmOperand*> &);
193
194  bool validateInstruction(MCInst &Inst,
195                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
196  void processInstruction(MCInst &Inst,
197                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
198  bool shouldOmitCCOutOperand(StringRef Mnemonic,
199                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
200
201public:
202  enum ARMMatchResultTy {
203    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
204    Match_RequiresNotITBlock,
205    Match_RequiresV6,
206    Match_RequiresThumb2
207  };
208
209  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
210    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
211    MCAsmParserExtension::Initialize(_Parser);
212
213    // Initialize the set of available features.
214    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
215
216    // Not in an ITBlock to start with.
217    ITState.CurPosition = ~0U;
218  }
219
220  // Implementation of the MCTargetAsmParser interface:
221  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
222  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
223                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
224  bool ParseDirective(AsmToken DirectiveID);
225
226  unsigned checkTargetMatchPredicate(MCInst &Inst);
227
228  bool MatchAndEmitInstruction(SMLoc IDLoc,
229                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
230                               MCStreamer &Out);
231};
232} // end anonymous namespace
233
234namespace {
235
236/// ARMOperand - Instances of this class represent a parsed ARM machine
237/// instruction.
238class ARMOperand : public MCParsedAsmOperand {
239  enum KindTy {
240    CondCode,
241    CCOut,
242    ITCondMask,
243    CoprocNum,
244    CoprocReg,
245    Immediate,
246    MemBarrierOpt,
247    Memory,
248    PostIndexRegister,
249    MSRMask,
250    ProcIFlags,
251    Register,
252    RegisterList,
253    DPRRegisterList,
254    SPRRegisterList,
255    ShiftedRegister,
256    ShiftedImmediate,
257    ShifterImmediate,
258    RotateImmediate,
259    BitfieldDescriptor,
260    Token
261  } Kind;
262
263  SMLoc StartLoc, EndLoc;
264  SmallVector<unsigned, 8> Registers;
265
266  union {
267    struct {
268      ARMCC::CondCodes Val;
269    } CC;
270
271    struct {
272      unsigned Val;
273    } Cop;
274
275    struct {
276      unsigned Mask:4;
277    } ITMask;
278
279    struct {
280      ARM_MB::MemBOpt Val;
281    } MBOpt;
282
283    struct {
284      ARM_PROC::IFlags Val;
285    } IFlags;
286
287    struct {
288      unsigned Val;
289    } MMask;
290
291    struct {
292      const char *Data;
293      unsigned Length;
294    } Tok;
295
296    struct {
297      unsigned RegNum;
298    } Reg;
299
300    struct {
301      const MCExpr *Val;
302    } Imm;
303
304    /// Combined record for all forms of ARM address expressions.
305    struct {
306      unsigned BaseRegNum;
307      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
308      // was specified.
309      const MCConstantExpr *OffsetImm;  // Offset immediate value
310      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
311      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
312      unsigned ShiftImm;      // shift for OffsetReg.
313      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
314    } Mem;
315
316    struct {
317      unsigned RegNum;
318      bool isAdd;
319      ARM_AM::ShiftOpc ShiftTy;
320      unsigned ShiftImm;
321    } PostIdxReg;
322
323    struct {
324      bool isASR;
325      unsigned Imm;
326    } ShifterImm;
327    struct {
328      ARM_AM::ShiftOpc ShiftTy;
329      unsigned SrcReg;
330      unsigned ShiftReg;
331      unsigned ShiftImm;
332    } RegShiftedReg;
333    struct {
334      ARM_AM::ShiftOpc ShiftTy;
335      unsigned SrcReg;
336      unsigned ShiftImm;
337    } RegShiftedImm;
338    struct {
339      unsigned Imm;
340    } RotImm;
341    struct {
342      unsigned LSB;
343      unsigned Width;
344    } Bitfield;
345  };
346
347  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
348public:
349  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
350    Kind = o.Kind;
351    StartLoc = o.StartLoc;
352    EndLoc = o.EndLoc;
353    switch (Kind) {
354    case CondCode:
355      CC = o.CC;
356      break;
357    case ITCondMask:
358      ITMask = o.ITMask;
359      break;
360    case Token:
361      Tok = o.Tok;
362      break;
363    case CCOut:
364    case Register:
365      Reg = o.Reg;
366      break;
367    case RegisterList:
368    case DPRRegisterList:
369    case SPRRegisterList:
370      Registers = o.Registers;
371      break;
372    case CoprocNum:
373    case CoprocReg:
374      Cop = o.Cop;
375      break;
376    case Immediate:
377      Imm = o.Imm;
378      break;
379    case MemBarrierOpt:
380      MBOpt = o.MBOpt;
381      break;
382    case Memory:
383      Mem = o.Mem;
384      break;
385    case PostIndexRegister:
386      PostIdxReg = o.PostIdxReg;
387      break;
388    case MSRMask:
389      MMask = o.MMask;
390      break;
391    case ProcIFlags:
392      IFlags = o.IFlags;
393      break;
394    case ShifterImmediate:
395      ShifterImm = o.ShifterImm;
396      break;
397    case ShiftedRegister:
398      RegShiftedReg = o.RegShiftedReg;
399      break;
400    case ShiftedImmediate:
401      RegShiftedImm = o.RegShiftedImm;
402      break;
403    case RotateImmediate:
404      RotImm = o.RotImm;
405      break;
406    case BitfieldDescriptor:
407      Bitfield = o.Bitfield;
408      break;
409    }
410  }
411
412  /// getStartLoc - Get the location of the first token of this operand.
413  SMLoc getStartLoc() const { return StartLoc; }
414  /// getEndLoc - Get the location of the last token of this operand.
415  SMLoc getEndLoc() const { return EndLoc; }
416
417  ARMCC::CondCodes getCondCode() const {
418    assert(Kind == CondCode && "Invalid access!");
419    return CC.Val;
420  }
421
422  unsigned getCoproc() const {
423    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
424    return Cop.Val;
425  }
426
427  StringRef getToken() const {
428    assert(Kind == Token && "Invalid access!");
429    return StringRef(Tok.Data, Tok.Length);
430  }
431
432  unsigned getReg() const {
433    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
434    return Reg.RegNum;
435  }
436
437  const SmallVectorImpl<unsigned> &getRegList() const {
438    assert((Kind == RegisterList || Kind == DPRRegisterList ||
439            Kind == SPRRegisterList) && "Invalid access!");
440    return Registers;
441  }
442
443  const MCExpr *getImm() const {
444    assert(Kind == Immediate && "Invalid access!");
445    return Imm.Val;
446  }
447
448  ARM_MB::MemBOpt getMemBarrierOpt() const {
449    assert(Kind == MemBarrierOpt && "Invalid access!");
450    return MBOpt.Val;
451  }
452
453  ARM_PROC::IFlags getProcIFlags() const {
454    assert(Kind == ProcIFlags && "Invalid access!");
455    return IFlags.Val;
456  }
457
458  unsigned getMSRMask() const {
459    assert(Kind == MSRMask && "Invalid access!");
460    return MMask.Val;
461  }
462
463  bool isCoprocNum() const { return Kind == CoprocNum; }
464  bool isCoprocReg() const { return Kind == CoprocReg; }
465  bool isCondCode() const { return Kind == CondCode; }
466  bool isCCOut() const { return Kind == CCOut; }
467  bool isITMask() const { return Kind == ITCondMask; }
468  bool isITCondCode() const { return Kind == CondCode; }
469  bool isImm() const { return Kind == Immediate; }
470  bool isImm8s4() const {
471    if (Kind != Immediate)
472      return false;
473    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474    if (!CE) return false;
475    int64_t Value = CE->getValue();
476    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
477  }
478  bool isImm0_1020s4() const {
479    if (Kind != Immediate)
480      return false;
481    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
482    if (!CE) return false;
483    int64_t Value = CE->getValue();
484    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
485  }
486  bool isImm0_508s4() const {
487    if (Kind != Immediate)
488      return false;
489    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
490    if (!CE) return false;
491    int64_t Value = CE->getValue();
492    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
493  }
494  bool isImm0_255() const {
495    if (Kind != Immediate)
496      return false;
497    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
498    if (!CE) return false;
499    int64_t Value = CE->getValue();
500    return Value >= 0 && Value < 256;
501  }
502  bool isImm0_7() const {
503    if (Kind != Immediate)
504      return false;
505    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
506    if (!CE) return false;
507    int64_t Value = CE->getValue();
508    return Value >= 0 && Value < 8;
509  }
510  bool isImm0_15() const {
511    if (Kind != Immediate)
512      return false;
513    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
514    if (!CE) return false;
515    int64_t Value = CE->getValue();
516    return Value >= 0 && Value < 16;
517  }
518  bool isImm0_31() const {
519    if (Kind != Immediate)
520      return false;
521    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
522    if (!CE) return false;
523    int64_t Value = CE->getValue();
524    return Value >= 0 && Value < 32;
525  }
526  bool isImm1_16() const {
527    if (Kind != Immediate)
528      return false;
529    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
530    if (!CE) return false;
531    int64_t Value = CE->getValue();
532    return Value > 0 && Value < 17;
533  }
534  bool isImm1_32() const {
535    if (Kind != Immediate)
536      return false;
537    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
538    if (!CE) return false;
539    int64_t Value = CE->getValue();
540    return Value > 0 && Value < 33;
541  }
542  bool isImm0_65535() const {
543    if (Kind != Immediate)
544      return false;
545    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546    if (!CE) return false;
547    int64_t Value = CE->getValue();
548    return Value >= 0 && Value < 65536;
549  }
550  bool isImm0_65535Expr() const {
551    if (Kind != Immediate)
552      return false;
553    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554    // If it's not a constant expression, it'll generate a fixup and be
555    // handled later.
556    if (!CE) return true;
557    int64_t Value = CE->getValue();
558    return Value >= 0 && Value < 65536;
559  }
560  bool isImm24bit() const {
561    if (Kind != Immediate)
562      return false;
563    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564    if (!CE) return false;
565    int64_t Value = CE->getValue();
566    return Value >= 0 && Value <= 0xffffff;
567  }
568  bool isImmThumbSR() const {
569    if (Kind != Immediate)
570      return false;
571    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
572    if (!CE) return false;
573    int64_t Value = CE->getValue();
574    return Value > 0 && Value < 33;
575  }
576  bool isPKHLSLImm() const {
577    if (Kind != Immediate)
578      return false;
579    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
580    if (!CE) return false;
581    int64_t Value = CE->getValue();
582    return Value >= 0 && Value < 32;
583  }
584  bool isPKHASRImm() const {
585    if (Kind != Immediate)
586      return false;
587    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
588    if (!CE) return false;
589    int64_t Value = CE->getValue();
590    return Value > 0 && Value <= 32;
591  }
592  bool isARMSOImm() const {
593    if (Kind != Immediate)
594      return false;
595    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596    if (!CE) return false;
597    int64_t Value = CE->getValue();
598    return ARM_AM::getSOImmVal(Value) != -1;
599  }
600  bool isT2SOImm() const {
601    if (Kind != Immediate)
602      return false;
603    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604    if (!CE) return false;
605    int64_t Value = CE->getValue();
606    return ARM_AM::getT2SOImmVal(Value) != -1;
607  }
608  bool isSetEndImm() const {
609    if (Kind != Immediate)
610      return false;
611    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
612    if (!CE) return false;
613    int64_t Value = CE->getValue();
614    return Value == 1 || Value == 0;
615  }
616  bool isReg() const { return Kind == Register; }
617  bool isRegList() const { return Kind == RegisterList; }
618  bool isDPRRegList() const { return Kind == DPRRegisterList; }
619  bool isSPRRegList() const { return Kind == SPRRegisterList; }
620  bool isToken() const { return Kind == Token; }
621  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
622  bool isMemory() const { return Kind == Memory; }
623  bool isShifterImm() const { return Kind == ShifterImmediate; }
624  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
625  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
626  bool isRotImm() const { return Kind == RotateImmediate; }
627  bool isBitfield() const { return Kind == BitfieldDescriptor; }
628  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
629  bool isPostIdxReg() const {
630    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
631  }
632  bool isMemNoOffset() const {
633    if (Kind != Memory)
634      return false;
635    // No offset of any kind.
636    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
637  }
638  bool isAddrMode2() const {
639    if (Kind != Memory)
640      return false;
641    // Check for register offset.
642    if (Mem.OffsetRegNum) return true;
643    // Immediate offset in range [-4095, 4095].
644    if (!Mem.OffsetImm) return true;
645    int64_t Val = Mem.OffsetImm->getValue();
646    return Val > -4096 && Val < 4096;
647  }
648  bool isAM2OffsetImm() const {
649    if (Kind != Immediate)
650      return false;
651    // Immediate offset in range [-4095, 4095].
652    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653    if (!CE) return false;
654    int64_t Val = CE->getValue();
655    return Val > -4096 && Val < 4096;
656  }
657  bool isAddrMode3() const {
658    if (Kind != Memory)
659      return false;
660    // No shifts are legal for AM3.
661    if (Mem.ShiftType != ARM_AM::no_shift) return false;
662    // Check for register offset.
663    if (Mem.OffsetRegNum) return true;
664    // Immediate offset in range [-255, 255].
665    if (!Mem.OffsetImm) return true;
666    int64_t Val = Mem.OffsetImm->getValue();
667    return Val > -256 && Val < 256;
668  }
669  bool isAM3Offset() const {
670    if (Kind != Immediate && Kind != PostIndexRegister)
671      return false;
672    if (Kind == PostIndexRegister)
673      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
674    // Immediate offset in range [-255, 255].
675    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676    if (!CE) return false;
677    int64_t Val = CE->getValue();
678    // Special case, #-0 is INT32_MIN.
679    return (Val > -256 && Val < 256) || Val == INT32_MIN;
680  }
681  bool isAddrMode5() const {
682    if (Kind != Memory)
683      return false;
684    // Check for register offset.
685    if (Mem.OffsetRegNum) return false;
686    // Immediate offset in range [-1020, 1020] and a multiple of 4.
687    if (!Mem.OffsetImm) return true;
688    int64_t Val = Mem.OffsetImm->getValue();
689    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
690           Val == INT32_MIN;
691  }
692  bool isMemRegOffset() const {
693    if (Kind != Memory || !Mem.OffsetRegNum)
694      return false;
695    return true;
696  }
697  bool isT2MemRegOffset() const {
698    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
699      return false;
700    // Only lsl #{0, 1, 2, 3} allowed.
701    if (Mem.ShiftType == ARM_AM::no_shift)
702      return true;
703    if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
704      return false;
705    return true;
706  }
707  bool isMemThumbRR() const {
708    // Thumb reg+reg addressing is simple. Just two registers, a base and
709    // an offset. No shifts, negations or any other complicating factors.
710    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
711        Mem.ShiftType != ARM_AM::no_shift)
712      return false;
713    return isARMLowRegister(Mem.BaseRegNum) &&
714      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
715  }
716  bool isMemThumbRIs4() const {
717    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
718        !isARMLowRegister(Mem.BaseRegNum))
719      return false;
720    // Immediate offset, multiple of 4 in range [0, 124].
721    if (!Mem.OffsetImm) return true;
722    int64_t Val = Mem.OffsetImm->getValue();
723    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
724  }
725  bool isMemThumbRIs2() const {
726    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
727        !isARMLowRegister(Mem.BaseRegNum))
728      return false;
729    // Immediate offset, multiple of 4 in range [0, 62].
730    if (!Mem.OffsetImm) return true;
731    int64_t Val = Mem.OffsetImm->getValue();
732    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
733  }
734  bool isMemThumbRIs1() const {
735    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
736        !isARMLowRegister(Mem.BaseRegNum))
737      return false;
738    // Immediate offset in range [0, 31].
739    if (!Mem.OffsetImm) return true;
740    int64_t Val = Mem.OffsetImm->getValue();
741    return Val >= 0 && Val <= 31;
742  }
743  bool isMemThumbSPI() const {
744    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
745      return false;
746    // Immediate offset, multiple of 4 in range [0, 1020].
747    if (!Mem.OffsetImm) return true;
748    int64_t Val = Mem.OffsetImm->getValue();
749    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
750  }
751  bool isMemImm8s4Offset() const {
752    if (Kind != Memory || Mem.OffsetRegNum != 0)
753      return false;
754    // Immediate offset a multiple of 4 in range [-1020, 1020].
755    if (!Mem.OffsetImm) return true;
756    int64_t Val = Mem.OffsetImm->getValue();
757    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
758  }
759  bool isMemImm0_1020s4Offset() const {
760    if (Kind != Memory || Mem.OffsetRegNum != 0)
761      return false;
762    // Immediate offset a multiple of 4 in range [0, 1020].
763    if (!Mem.OffsetImm) return true;
764    int64_t Val = Mem.OffsetImm->getValue();
765    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
766  }
767  bool isMemImm8Offset() const {
768    if (Kind != Memory || Mem.OffsetRegNum != 0)
769      return false;
770    // Immediate offset in range [-255, 255].
771    if (!Mem.OffsetImm) return true;
772    int64_t Val = Mem.OffsetImm->getValue();
773    return Val > -256 && Val < 256;
774  }
775  bool isMemPosImm8Offset() const {
776    if (Kind != Memory || Mem.OffsetRegNum != 0)
777      return false;
778    // Immediate offset in range [0, 255].
779    if (!Mem.OffsetImm) return true;
780    int64_t Val = Mem.OffsetImm->getValue();
781    return Val >= 0 && Val < 256;
782  }
783  bool isMemNegImm8Offset() const {
784    if (Kind != Memory || Mem.OffsetRegNum != 0)
785      return false;
786    // Immediate offset in range [-255, -1].
787    if (!Mem.OffsetImm) return true;
788    int64_t Val = Mem.OffsetImm->getValue();
789    return Val > -256 && Val < 0;
790  }
791  bool isMemUImm12Offset() const {
792    // If we have an immediate that's not a constant, treat it as a label
793    // reference needing a fixup. If it is a constant, it's something else
794    // and we reject it.
795    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
796      return true;
797
798    if (Kind != Memory || Mem.OffsetRegNum != 0)
799      return false;
800    // Immediate offset in range [0, 4095].
801    if (!Mem.OffsetImm) return true;
802    int64_t Val = Mem.OffsetImm->getValue();
803    return (Val >= 0 && Val < 4096);
804  }
805  bool isMemImm12Offset() const {
806    // If we have an immediate that's not a constant, treat it as a label
807    // reference needing a fixup. If it is a constant, it's something else
808    // and we reject it.
809    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
810      return true;
811
812    if (Kind != Memory || Mem.OffsetRegNum != 0)
813      return false;
814    // Immediate offset in range [-4095, 4095].
815    if (!Mem.OffsetImm) return true;
816    int64_t Val = Mem.OffsetImm->getValue();
817    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
818  }
819  bool isPostIdxImm8() const {
820    if (Kind != Immediate)
821      return false;
822    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823    if (!CE) return false;
824    int64_t Val = CE->getValue();
825    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
826  }
827
828  bool isMSRMask() const { return Kind == MSRMask; }
829  bool isProcIFlags() const { return Kind == ProcIFlags; }
830
831  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
832    // Add as immediates when possible.  Null MCExpr = 0.
833    if (Expr == 0)
834      Inst.addOperand(MCOperand::CreateImm(0));
835    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
836      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
837    else
838      Inst.addOperand(MCOperand::CreateExpr(Expr));
839  }
840
841  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
842    assert(N == 2 && "Invalid number of operands!");
843    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
844    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
845    Inst.addOperand(MCOperand::CreateReg(RegNum));
846  }
847
848  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
849    assert(N == 1 && "Invalid number of operands!");
850    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
851  }
852
853  void addITMaskOperands(MCInst &Inst, unsigned N) const {
854    assert(N == 1 && "Invalid number of operands!");
855    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
856  }
857
858  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
859    assert(N == 1 && "Invalid number of operands!");
860    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
861  }
862
863  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
864    assert(N == 1 && "Invalid number of operands!");
865    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
866  }
867
868  void addCCOutOperands(MCInst &Inst, unsigned N) const {
869    assert(N == 1 && "Invalid number of operands!");
870    Inst.addOperand(MCOperand::CreateReg(getReg()));
871  }
872
873  void addRegOperands(MCInst &Inst, unsigned N) const {
874    assert(N == 1 && "Invalid number of operands!");
875    Inst.addOperand(MCOperand::CreateReg(getReg()));
876  }
877
878  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
879    assert(N == 3 && "Invalid number of operands!");
880    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
881    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
882    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
883    Inst.addOperand(MCOperand::CreateImm(
884      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
885  }
886
887  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
888    assert(N == 2 && "Invalid number of operands!");
889    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
890    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
891    Inst.addOperand(MCOperand::CreateImm(
892      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
893  }
894
895  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
896    assert(N == 1 && "Invalid number of operands!");
897    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
898                                         ShifterImm.Imm));
899  }
900
901  void addRegListOperands(MCInst &Inst, unsigned N) const {
902    assert(N == 1 && "Invalid number of operands!");
903    const SmallVectorImpl<unsigned> &RegList = getRegList();
904    for (SmallVectorImpl<unsigned>::const_iterator
905           I = RegList.begin(), E = RegList.end(); I != E; ++I)
906      Inst.addOperand(MCOperand::CreateReg(*I));
907  }
908
909  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
910    addRegListOperands(Inst, N);
911  }
912
913  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
914    addRegListOperands(Inst, N);
915  }
916
917  void addRotImmOperands(MCInst &Inst, unsigned N) const {
918    assert(N == 1 && "Invalid number of operands!");
919    // Encoded as val>>3. The printer handles display as 8, 16, 24.
920    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
921  }
922
923  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
924    assert(N == 1 && "Invalid number of operands!");
925    // Munge the lsb/width into a bitfield mask.
926    unsigned lsb = Bitfield.LSB;
927    unsigned width = Bitfield.Width;
928    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
929    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
930                      (32 - (lsb + width)));
931    Inst.addOperand(MCOperand::CreateImm(Mask));
932  }
933
934  void addImmOperands(MCInst &Inst, unsigned N) const {
935    assert(N == 1 && "Invalid number of operands!");
936    addExpr(Inst, getImm());
937  }
938
939  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
940    assert(N == 1 && "Invalid number of operands!");
941    // FIXME: We really want to scale the value here, but the LDRD/STRD
942    // instruction don't encode operands that way yet.
943    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
944    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
945  }
946
947  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
948    assert(N == 1 && "Invalid number of operands!");
949    // The immediate is scaled by four in the encoding and is stored
950    // in the MCInst as such. Lop off the low two bits here.
951    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
952    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
953  }
954
955  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
956    assert(N == 1 && "Invalid number of operands!");
957    // The immediate is scaled by four in the encoding and is stored
958    // in the MCInst as such. Lop off the low two bits here.
959    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
961  }
962
963  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
964    assert(N == 1 && "Invalid number of operands!");
965    addExpr(Inst, getImm());
966  }
967
968  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
969    assert(N == 1 && "Invalid number of operands!");
970    addExpr(Inst, getImm());
971  }
972
973  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
974    assert(N == 1 && "Invalid number of operands!");
975    addExpr(Inst, getImm());
976  }
977
978  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
979    assert(N == 1 && "Invalid number of operands!");
980    addExpr(Inst, getImm());
981  }
982
983  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
984    assert(N == 1 && "Invalid number of operands!");
985    // The constant encodes as the immediate-1, and we store in the instruction
986    // the bits as encoded, so subtract off one here.
987    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
989  }
990
991  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
992    assert(N == 1 && "Invalid number of operands!");
993    // The constant encodes as the immediate-1, and we store in the instruction
994    // the bits as encoded, so subtract off one here.
995    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
996    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
997  }
998
999  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1000    assert(N == 1 && "Invalid number of operands!");
1001    addExpr(Inst, getImm());
1002  }
1003
1004  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1005    assert(N == 1 && "Invalid number of operands!");
1006    addExpr(Inst, getImm());
1007  }
1008
1009  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1010    assert(N == 1 && "Invalid number of operands!");
1011    addExpr(Inst, getImm());
1012  }
1013
1014  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1015    assert(N == 1 && "Invalid number of operands!");
1016    // The constant encodes as the immediate, except for 32, which encodes as
1017    // zero.
1018    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1019    unsigned Imm = CE->getValue();
1020    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1021  }
1022
1023  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1024    assert(N == 1 && "Invalid number of operands!");
1025    addExpr(Inst, getImm());
1026  }
1027
1028  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1029    assert(N == 1 && "Invalid number of operands!");
1030    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1031    // the instruction as well.
1032    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1033    int Val = CE->getValue();
1034    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1035  }
1036
1037  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1038    assert(N == 1 && "Invalid number of operands!");
1039    addExpr(Inst, getImm());
1040  }
1041
1042  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1043    assert(N == 1 && "Invalid number of operands!");
1044    addExpr(Inst, getImm());
1045  }
1046
1047  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1048    assert(N == 1 && "Invalid number of operands!");
1049    addExpr(Inst, getImm());
1050  }
1051
1052  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1053    assert(N == 1 && "Invalid number of operands!");
1054    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1055  }
1056
1057  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1058    assert(N == 1 && "Invalid number of operands!");
1059    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1060  }
1061
1062  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1063    assert(N == 3 && "Invalid number of operands!");
1064    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1065    if (!Mem.OffsetRegNum) {
1066      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1067      // Special case for #-0
1068      if (Val == INT32_MIN) Val = 0;
1069      if (Val < 0) Val = -Val;
1070      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1071    } else {
1072      // For register offset, we encode the shift type and negation flag
1073      // here.
1074      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1075                              Mem.ShiftImm, Mem.ShiftType);
1076    }
1077    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1078    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1079    Inst.addOperand(MCOperand::CreateImm(Val));
1080  }
1081
1082  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1083    assert(N == 2 && "Invalid number of operands!");
1084    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1085    assert(CE && "non-constant AM2OffsetImm operand!");
1086    int32_t Val = CE->getValue();
1087    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1088    // Special case for #-0
1089    if (Val == INT32_MIN) Val = 0;
1090    if (Val < 0) Val = -Val;
1091    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1092    Inst.addOperand(MCOperand::CreateReg(0));
1093    Inst.addOperand(MCOperand::CreateImm(Val));
1094  }
1095
1096  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1097    assert(N == 3 && "Invalid number of operands!");
1098    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1099    if (!Mem.OffsetRegNum) {
1100      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1101      // Special case for #-0
1102      if (Val == INT32_MIN) Val = 0;
1103      if (Val < 0) Val = -Val;
1104      Val = ARM_AM::getAM3Opc(AddSub, Val);
1105    } else {
1106      // For register offset, we encode the shift type and negation flag
1107      // here.
1108      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1109    }
1110    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1111    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1112    Inst.addOperand(MCOperand::CreateImm(Val));
1113  }
1114
1115  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1116    assert(N == 2 && "Invalid number of operands!");
1117    if (Kind == PostIndexRegister) {
1118      int32_t Val =
1119        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1120      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1121      Inst.addOperand(MCOperand::CreateImm(Val));
1122      return;
1123    }
1124
1125    // Constant offset.
1126    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1127    int32_t Val = CE->getValue();
1128    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1129    // Special case for #-0
1130    if (Val == INT32_MIN) Val = 0;
1131    if (Val < 0) Val = -Val;
1132    Val = ARM_AM::getAM3Opc(AddSub, Val);
1133    Inst.addOperand(MCOperand::CreateReg(0));
1134    Inst.addOperand(MCOperand::CreateImm(Val));
1135  }
1136
1137  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1138    assert(N == 2 && "Invalid number of operands!");
1139    // The lower two bits are always zero and as such are not encoded.
1140    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1141    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1142    // Special case for #-0
1143    if (Val == INT32_MIN) Val = 0;
1144    if (Val < 0) Val = -Val;
1145    Val = ARM_AM::getAM5Opc(AddSub, Val);
1146    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1147    Inst.addOperand(MCOperand::CreateImm(Val));
1148  }
1149
1150  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1151    assert(N == 2 && "Invalid number of operands!");
1152    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1153    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1154    Inst.addOperand(MCOperand::CreateImm(Val));
1155  }
1156
1157  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1158    assert(N == 2 && "Invalid number of operands!");
1159    // The lower two bits are always zero and as such are not encoded.
1160    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1161    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1162    Inst.addOperand(MCOperand::CreateImm(Val));
1163  }
1164
1165  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1166    assert(N == 2 && "Invalid number of operands!");
1167    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1168    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1169    Inst.addOperand(MCOperand::CreateImm(Val));
1170  }
1171
1172  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1173    addMemImm8OffsetOperands(Inst, N);
1174  }
1175
1176  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1177    addMemImm8OffsetOperands(Inst, N);
1178  }
1179
1180  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1181    assert(N == 2 && "Invalid number of operands!");
1182    // If this is an immediate, it's a label reference.
1183    if (Kind == Immediate) {
1184      addExpr(Inst, getImm());
1185      Inst.addOperand(MCOperand::CreateImm(0));
1186      return;
1187    }
1188
1189    // Otherwise, it's a normal memory reg+offset.
1190    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1191    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1192    Inst.addOperand(MCOperand::CreateImm(Val));
1193  }
1194
1195  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1196    assert(N == 2 && "Invalid number of operands!");
1197    // If this is an immediate, it's a label reference.
1198    if (Kind == Immediate) {
1199      addExpr(Inst, getImm());
1200      Inst.addOperand(MCOperand::CreateImm(0));
1201      return;
1202    }
1203
1204    // Otherwise, it's a normal memory reg+offset.
1205    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1206    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1207    Inst.addOperand(MCOperand::CreateImm(Val));
1208  }
1209
1210  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1211    assert(N == 3 && "Invalid number of operands!");
1212    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1213                                     Mem.ShiftImm, Mem.ShiftType);
1214    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1215    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1216    Inst.addOperand(MCOperand::CreateImm(Val));
1217  }
1218
1219  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1220    assert(N == 3 && "Invalid number of operands!");
1221    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1222    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1223    Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1224  }
1225
1226  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1227    assert(N == 2 && "Invalid number of operands!");
1228    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1229    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1230  }
1231
1232  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1233    assert(N == 2 && "Invalid number of operands!");
1234    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1235    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1236    Inst.addOperand(MCOperand::CreateImm(Val));
1237  }
1238
1239  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1240    assert(N == 2 && "Invalid number of operands!");
1241    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1242    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1243    Inst.addOperand(MCOperand::CreateImm(Val));
1244  }
1245
1246  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1247    assert(N == 2 && "Invalid number of operands!");
1248    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1249    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1250    Inst.addOperand(MCOperand::CreateImm(Val));
1251  }
1252
1253  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1254    assert(N == 2 && "Invalid number of operands!");
1255    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1256    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1257    Inst.addOperand(MCOperand::CreateImm(Val));
1258  }
1259
1260  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1261    assert(N == 1 && "Invalid number of operands!");
1262    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1263    assert(CE && "non-constant post-idx-imm8 operand!");
1264    int Imm = CE->getValue();
1265    bool isAdd = Imm >= 0;
1266    if (Imm == INT32_MIN) Imm = 0;
1267    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1268    Inst.addOperand(MCOperand::CreateImm(Imm));
1269  }
1270
1271  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1272    assert(N == 2 && "Invalid number of operands!");
1273    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1274    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1275  }
1276
1277  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1278    assert(N == 2 && "Invalid number of operands!");
1279    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1280    // The sign, shift type, and shift amount are encoded in a single operand
1281    // using the AM2 encoding helpers.
1282    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1283    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1284                                     PostIdxReg.ShiftTy);
1285    Inst.addOperand(MCOperand::CreateImm(Imm));
1286  }
1287
1288  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1289    assert(N == 1 && "Invalid number of operands!");
1290    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1291  }
1292
1293  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1294    assert(N == 1 && "Invalid number of operands!");
1295    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1296  }
1297
1298  virtual void print(raw_ostream &OS) const;
1299
1300  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1301    ARMOperand *Op = new ARMOperand(ITCondMask);
1302    Op->ITMask.Mask = Mask;
1303    Op->StartLoc = S;
1304    Op->EndLoc = S;
1305    return Op;
1306  }
1307
1308  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1309    ARMOperand *Op = new ARMOperand(CondCode);
1310    Op->CC.Val = CC;
1311    Op->StartLoc = S;
1312    Op->EndLoc = S;
1313    return Op;
1314  }
1315
1316  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1317    ARMOperand *Op = new ARMOperand(CoprocNum);
1318    Op->Cop.Val = CopVal;
1319    Op->StartLoc = S;
1320    Op->EndLoc = S;
1321    return Op;
1322  }
1323
1324  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1325    ARMOperand *Op = new ARMOperand(CoprocReg);
1326    Op->Cop.Val = CopVal;
1327    Op->StartLoc = S;
1328    Op->EndLoc = S;
1329    return Op;
1330  }
1331
1332  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1333    ARMOperand *Op = new ARMOperand(CCOut);
1334    Op->Reg.RegNum = RegNum;
1335    Op->StartLoc = S;
1336    Op->EndLoc = S;
1337    return Op;
1338  }
1339
1340  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1341    ARMOperand *Op = new ARMOperand(Token);
1342    Op->Tok.Data = Str.data();
1343    Op->Tok.Length = Str.size();
1344    Op->StartLoc = S;
1345    Op->EndLoc = S;
1346    return Op;
1347  }
1348
1349  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1350    ARMOperand *Op = new ARMOperand(Register);
1351    Op->Reg.RegNum = RegNum;
1352    Op->StartLoc = S;
1353    Op->EndLoc = E;
1354    return Op;
1355  }
1356
1357  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1358                                           unsigned SrcReg,
1359                                           unsigned ShiftReg,
1360                                           unsigned ShiftImm,
1361                                           SMLoc S, SMLoc E) {
1362    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1363    Op->RegShiftedReg.ShiftTy = ShTy;
1364    Op->RegShiftedReg.SrcReg = SrcReg;
1365    Op->RegShiftedReg.ShiftReg = ShiftReg;
1366    Op->RegShiftedReg.ShiftImm = ShiftImm;
1367    Op->StartLoc = S;
1368    Op->EndLoc = E;
1369    return Op;
1370  }
1371
1372  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1373                                            unsigned SrcReg,
1374                                            unsigned ShiftImm,
1375                                            SMLoc S, SMLoc E) {
1376    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1377    Op->RegShiftedImm.ShiftTy = ShTy;
1378    Op->RegShiftedImm.SrcReg = SrcReg;
1379    Op->RegShiftedImm.ShiftImm = ShiftImm;
1380    Op->StartLoc = S;
1381    Op->EndLoc = E;
1382    return Op;
1383  }
1384
1385  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1386                                   SMLoc S, SMLoc E) {
1387    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1388    Op->ShifterImm.isASR = isASR;
1389    Op->ShifterImm.Imm = Imm;
1390    Op->StartLoc = S;
1391    Op->EndLoc = E;
1392    return Op;
1393  }
1394
1395  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1396    ARMOperand *Op = new ARMOperand(RotateImmediate);
1397    Op->RotImm.Imm = Imm;
1398    Op->StartLoc = S;
1399    Op->EndLoc = E;
1400    return Op;
1401  }
1402
1403  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1404                                    SMLoc S, SMLoc E) {
1405    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1406    Op->Bitfield.LSB = LSB;
1407    Op->Bitfield.Width = Width;
1408    Op->StartLoc = S;
1409    Op->EndLoc = E;
1410    return Op;
1411  }
1412
1413  static ARMOperand *
1414  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1415                SMLoc StartLoc, SMLoc EndLoc) {
1416    KindTy Kind = RegisterList;
1417
1418    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1419        contains(Regs.front().first))
1420      Kind = DPRRegisterList;
1421    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1422             contains(Regs.front().first))
1423      Kind = SPRRegisterList;
1424
1425    ARMOperand *Op = new ARMOperand(Kind);
1426    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1427           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1428      Op->Registers.push_back(I->first);
1429    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1430    Op->StartLoc = StartLoc;
1431    Op->EndLoc = EndLoc;
1432    return Op;
1433  }
1434
1435  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1436    ARMOperand *Op = new ARMOperand(Immediate);
1437    Op->Imm.Val = Val;
1438    Op->StartLoc = S;
1439    Op->EndLoc = E;
1440    return Op;
1441  }
1442
1443  static ARMOperand *CreateMem(unsigned BaseRegNum,
1444                               const MCConstantExpr *OffsetImm,
1445                               unsigned OffsetRegNum,
1446                               ARM_AM::ShiftOpc ShiftType,
1447                               unsigned ShiftImm,
1448                               bool isNegative,
1449                               SMLoc S, SMLoc E) {
1450    ARMOperand *Op = new ARMOperand(Memory);
1451    Op->Mem.BaseRegNum = BaseRegNum;
1452    Op->Mem.OffsetImm = OffsetImm;
1453    Op->Mem.OffsetRegNum = OffsetRegNum;
1454    Op->Mem.ShiftType = ShiftType;
1455    Op->Mem.ShiftImm = ShiftImm;
1456    Op->Mem.isNegative = isNegative;
1457    Op->StartLoc = S;
1458    Op->EndLoc = E;
1459    return Op;
1460  }
1461
1462  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1463                                      ARM_AM::ShiftOpc ShiftTy,
1464                                      unsigned ShiftImm,
1465                                      SMLoc S, SMLoc E) {
1466    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1467    Op->PostIdxReg.RegNum = RegNum;
1468    Op->PostIdxReg.isAdd = isAdd;
1469    Op->PostIdxReg.ShiftTy = ShiftTy;
1470    Op->PostIdxReg.ShiftImm = ShiftImm;
1471    Op->StartLoc = S;
1472    Op->EndLoc = E;
1473    return Op;
1474  }
1475
1476  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1477    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1478    Op->MBOpt.Val = Opt;
1479    Op->StartLoc = S;
1480    Op->EndLoc = S;
1481    return Op;
1482  }
1483
1484  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1485    ARMOperand *Op = new ARMOperand(ProcIFlags);
1486    Op->IFlags.Val = IFlags;
1487    Op->StartLoc = S;
1488    Op->EndLoc = S;
1489    return Op;
1490  }
1491
1492  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1493    ARMOperand *Op = new ARMOperand(MSRMask);
1494    Op->MMask.Val = MMask;
1495    Op->StartLoc = S;
1496    Op->EndLoc = S;
1497    return Op;
1498  }
1499};
1500
1501} // end anonymous namespace.
1502
1503void ARMOperand::print(raw_ostream &OS) const {
1504  switch (Kind) {
1505  case CondCode:
1506    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1507    break;
1508  case CCOut:
1509    OS << "<ccout " << getReg() << ">";
1510    break;
1511  case ITCondMask: {
1512    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1513      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1514      "(tee)", "(eee)" };
1515    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1516    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1517    break;
1518  }
1519  case CoprocNum:
1520    OS << "<coprocessor number: " << getCoproc() << ">";
1521    break;
1522  case CoprocReg:
1523    OS << "<coprocessor register: " << getCoproc() << ">";
1524    break;
1525  case MSRMask:
1526    OS << "<mask: " << getMSRMask() << ">";
1527    break;
1528  case Immediate:
1529    getImm()->print(OS);
1530    break;
1531  case MemBarrierOpt:
1532    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1533    break;
1534  case Memory:
1535    OS << "<memory "
1536       << " base:" << Mem.BaseRegNum;
1537    OS << ">";
1538    break;
1539  case PostIndexRegister:
1540    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1541       << PostIdxReg.RegNum;
1542    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1543      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1544         << PostIdxReg.ShiftImm;
1545    OS << ">";
1546    break;
1547  case ProcIFlags: {
1548    OS << "<ARM_PROC::";
1549    unsigned IFlags = getProcIFlags();
1550    for (int i=2; i >= 0; --i)
1551      if (IFlags & (1 << i))
1552        OS << ARM_PROC::IFlagsToString(1 << i);
1553    OS << ">";
1554    break;
1555  }
1556  case Register:
1557    OS << "<register " << getReg() << ">";
1558    break;
1559  case ShifterImmediate:
1560    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1561       << " #" << ShifterImm.Imm << ">";
1562    break;
1563  case ShiftedRegister:
1564    OS << "<so_reg_reg "
1565       << RegShiftedReg.SrcReg
1566       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1567       << ", " << RegShiftedReg.ShiftReg << ", "
1568       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1569       << ">";
1570    break;
1571  case ShiftedImmediate:
1572    OS << "<so_reg_imm "
1573       << RegShiftedImm.SrcReg
1574       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1575       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1576       << ">";
1577    break;
1578  case RotateImmediate:
1579    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1580    break;
1581  case BitfieldDescriptor:
1582    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1583       << ", width: " << Bitfield.Width << ">";
1584    break;
1585  case RegisterList:
1586  case DPRRegisterList:
1587  case SPRRegisterList: {
1588    OS << "<register_list ";
1589
1590    const SmallVectorImpl<unsigned> &RegList = getRegList();
1591    for (SmallVectorImpl<unsigned>::const_iterator
1592           I = RegList.begin(), E = RegList.end(); I != E; ) {
1593      OS << *I;
1594      if (++I < E) OS << ", ";
1595    }
1596
1597    OS << ">";
1598    break;
1599  }
1600  case Token:
1601    OS << "'" << getToken() << "'";
1602    break;
1603  }
1604}
1605
1606/// @name Auto-generated Match Functions
1607/// {
1608
1609static unsigned MatchRegisterName(StringRef Name);
1610
1611/// }
1612
1613bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1614                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1615  RegNo = tryParseRegister();
1616
1617  return (RegNo == (unsigned)-1);
1618}
1619
1620/// Try to parse a register name.  The token must be an Identifier when called,
1621/// and if it is a register name the token is eaten and the register number is
1622/// returned.  Otherwise return -1.
1623///
1624int ARMAsmParser::tryParseRegister() {
1625  const AsmToken &Tok = Parser.getTok();
1626  if (Tok.isNot(AsmToken::Identifier)) return -1;
1627
1628  // FIXME: Validate register for the current architecture; we have to do
1629  // validation later, so maybe there is no need for this here.
1630  std::string upperCase = Tok.getString().str();
1631  std::string lowerCase = LowercaseString(upperCase);
1632  unsigned RegNum = MatchRegisterName(lowerCase);
1633  if (!RegNum) {
1634    RegNum = StringSwitch<unsigned>(lowerCase)
1635      .Case("r13", ARM::SP)
1636      .Case("r14", ARM::LR)
1637      .Case("r15", ARM::PC)
1638      .Case("ip", ARM::R12)
1639      .Default(0);
1640  }
1641  if (!RegNum) return -1;
1642
1643  Parser.Lex(); // Eat identifier token.
1644  return RegNum;
1645}
1646
1647// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1648// If a recoverable error occurs, return 1. If an irrecoverable error
1649// occurs, return -1. An irrecoverable error is one where tokens have been
1650// consumed in the process of trying to parse the shifter (i.e., when it is
1651// indeed a shifter operand, but malformed).
1652int ARMAsmParser::tryParseShiftRegister(
1653                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1654  SMLoc S = Parser.getTok().getLoc();
1655  const AsmToken &Tok = Parser.getTok();
1656  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1657
1658  std::string upperCase = Tok.getString().str();
1659  std::string lowerCase = LowercaseString(upperCase);
1660  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1661      .Case("lsl", ARM_AM::lsl)
1662      .Case("lsr", ARM_AM::lsr)
1663      .Case("asr", ARM_AM::asr)
1664      .Case("ror", ARM_AM::ror)
1665      .Case("rrx", ARM_AM::rrx)
1666      .Default(ARM_AM::no_shift);
1667
1668  if (ShiftTy == ARM_AM::no_shift)
1669    return 1;
1670
1671  Parser.Lex(); // Eat the operator.
1672
1673  // The source register for the shift has already been added to the
1674  // operand list, so we need to pop it off and combine it into the shifted
1675  // register operand instead.
1676  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1677  if (!PrevOp->isReg())
1678    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1679  int SrcReg = PrevOp->getReg();
1680  int64_t Imm = 0;
1681  int ShiftReg = 0;
1682  if (ShiftTy == ARM_AM::rrx) {
1683    // RRX Doesn't have an explicit shift amount. The encoder expects
1684    // the shift register to be the same as the source register. Seems odd,
1685    // but OK.
1686    ShiftReg = SrcReg;
1687  } else {
1688    // Figure out if this is shifted by a constant or a register (for non-RRX).
1689    if (Parser.getTok().is(AsmToken::Hash)) {
1690      Parser.Lex(); // Eat hash.
1691      SMLoc ImmLoc = Parser.getTok().getLoc();
1692      const MCExpr *ShiftExpr = 0;
1693      if (getParser().ParseExpression(ShiftExpr)) {
1694        Error(ImmLoc, "invalid immediate shift value");
1695        return -1;
1696      }
1697      // The expression must be evaluatable as an immediate.
1698      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1699      if (!CE) {
1700        Error(ImmLoc, "invalid immediate shift value");
1701        return -1;
1702      }
1703      // Range check the immediate.
1704      // lsl, ror: 0 <= imm <= 31
1705      // lsr, asr: 0 <= imm <= 32
1706      Imm = CE->getValue();
1707      if (Imm < 0 ||
1708          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1709          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1710        Error(ImmLoc, "immediate shift value out of range");
1711        return -1;
1712      }
1713    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1714      ShiftReg = tryParseRegister();
1715      SMLoc L = Parser.getTok().getLoc();
1716      if (ShiftReg == -1) {
1717        Error (L, "expected immediate or register in shift operand");
1718        return -1;
1719      }
1720    } else {
1721      Error (Parser.getTok().getLoc(),
1722                    "expected immediate or register in shift operand");
1723      return -1;
1724    }
1725  }
1726
1727  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1728    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1729                                                         ShiftReg, Imm,
1730                                               S, Parser.getTok().getLoc()));
1731  else
1732    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1733                                               S, Parser.getTok().getLoc()));
1734
1735  return 0;
1736}
1737
1738
1739/// Try to parse a register name.  The token must be an Identifier when called.
1740/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1741/// if there is a "writeback". 'true' if it's not a register.
1742///
1743/// TODO this is likely to change to allow different register types and or to
1744/// parse for a specific register type.
1745bool ARMAsmParser::
1746tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1747  SMLoc S = Parser.getTok().getLoc();
1748  int RegNo = tryParseRegister();
1749  if (RegNo == -1)
1750    return true;
1751
1752  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1753
1754  const AsmToken &ExclaimTok = Parser.getTok();
1755  if (ExclaimTok.is(AsmToken::Exclaim)) {
1756    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1757                                               ExclaimTok.getLoc()));
1758    Parser.Lex(); // Eat exclaim token
1759  }
1760
1761  return false;
1762}
1763
1764/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1765/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1766/// "c5", ...
1767static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1768  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1769  // but efficient.
1770  switch (Name.size()) {
1771  default: break;
1772  case 2:
1773    if (Name[0] != CoprocOp)
1774      return -1;
1775    switch (Name[1]) {
1776    default:  return -1;
1777    case '0': return 0;
1778    case '1': return 1;
1779    case '2': return 2;
1780    case '3': return 3;
1781    case '4': return 4;
1782    case '5': return 5;
1783    case '6': return 6;
1784    case '7': return 7;
1785    case '8': return 8;
1786    case '9': return 9;
1787    }
1788    break;
1789  case 3:
1790    if (Name[0] != CoprocOp || Name[1] != '1')
1791      return -1;
1792    switch (Name[2]) {
1793    default:  return -1;
1794    case '0': return 10;
1795    case '1': return 11;
1796    case '2': return 12;
1797    case '3': return 13;
1798    case '4': return 14;
1799    case '5': return 15;
1800    }
1801    break;
1802  }
1803
1804  return -1;
1805}
1806
1807/// parseITCondCode - Try to parse a condition code for an IT instruction.
1808ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1809parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1810  SMLoc S = Parser.getTok().getLoc();
1811  const AsmToken &Tok = Parser.getTok();
1812  if (!Tok.is(AsmToken::Identifier))
1813    return MatchOperand_NoMatch;
1814  unsigned CC = StringSwitch<unsigned>(Tok.getString())
1815    .Case("eq", ARMCC::EQ)
1816    .Case("ne", ARMCC::NE)
1817    .Case("hs", ARMCC::HS)
1818    .Case("cs", ARMCC::HS)
1819    .Case("lo", ARMCC::LO)
1820    .Case("cc", ARMCC::LO)
1821    .Case("mi", ARMCC::MI)
1822    .Case("pl", ARMCC::PL)
1823    .Case("vs", ARMCC::VS)
1824    .Case("vc", ARMCC::VC)
1825    .Case("hi", ARMCC::HI)
1826    .Case("ls", ARMCC::LS)
1827    .Case("ge", ARMCC::GE)
1828    .Case("lt", ARMCC::LT)
1829    .Case("gt", ARMCC::GT)
1830    .Case("le", ARMCC::LE)
1831    .Case("al", ARMCC::AL)
1832    .Default(~0U);
1833  if (CC == ~0U)
1834    return MatchOperand_NoMatch;
1835  Parser.Lex(); // Eat the token.
1836
1837  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1838
1839  return MatchOperand_Success;
1840}
1841
1842/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1843/// token must be an Identifier when called, and if it is a coprocessor
1844/// number, the token is eaten and the operand is added to the operand list.
1845ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1846parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1847  SMLoc S = Parser.getTok().getLoc();
1848  const AsmToken &Tok = Parser.getTok();
1849  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1850
1851  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1852  if (Num == -1)
1853    return MatchOperand_NoMatch;
1854
1855  Parser.Lex(); // Eat identifier token.
1856  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1857  return MatchOperand_Success;
1858}
1859
1860/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1861/// token must be an Identifier when called, and if it is a coprocessor
1862/// number, the token is eaten and the operand is added to the operand list.
1863ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1864parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1865  SMLoc S = Parser.getTok().getLoc();
1866  const AsmToken &Tok = Parser.getTok();
1867  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1868
1869  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1870  if (Reg == -1)
1871    return MatchOperand_NoMatch;
1872
1873  Parser.Lex(); // Eat identifier token.
1874  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1875  return MatchOperand_Success;
1876}
1877
1878/// Parse a register list, return it if successful else return null.  The first
1879/// token must be a '{' when called.
1880bool ARMAsmParser::
1881parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1882  assert(Parser.getTok().is(AsmToken::LCurly) &&
1883         "Token is not a Left Curly Brace");
1884  SMLoc S = Parser.getTok().getLoc();
1885
1886  // Read the rest of the registers in the list.
1887  unsigned PrevRegNum = 0;
1888  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1889
1890  do {
1891    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1892    Parser.Lex(); // Eat non-identifier token.
1893
1894    const AsmToken &RegTok = Parser.getTok();
1895    SMLoc RegLoc = RegTok.getLoc();
1896    if (RegTok.isNot(AsmToken::Identifier))
1897      return Error(RegLoc, "register expected");
1898
1899    int RegNum = tryParseRegister();
1900    if (RegNum == -1)
1901      return Error(RegLoc, "register expected");
1902
1903    if (IsRange) {
1904      int Reg = PrevRegNum;
1905      do {
1906        ++Reg;
1907        Registers.push_back(std::make_pair(Reg, RegLoc));
1908      } while (Reg != RegNum);
1909    } else
1910      Registers.push_back(std::make_pair(RegNum, RegLoc));
1911
1912    PrevRegNum = RegNum;
1913  } while (Parser.getTok().is(AsmToken::Comma) ||
1914           Parser.getTok().is(AsmToken::Minus));
1915
1916  // Process the right curly brace of the list.
1917  const AsmToken &RCurlyTok = Parser.getTok();
1918  if (RCurlyTok.isNot(AsmToken::RCurly))
1919    return Error(RCurlyTok.getLoc(), "'}' expected");
1920
1921  SMLoc E = RCurlyTok.getLoc();
1922  Parser.Lex(); // Eat right curly brace token.
1923
1924  // Verify the register list.
1925  bool EmittedWarning = false;
1926  unsigned HighRegNum = 0;
1927  BitVector RegMap(32);
1928  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1929    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1930    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1931
1932    if (RegMap[Reg])
1933      return Error(RegInfo.second, "register duplicated in register list");
1934
1935    if (!EmittedWarning && Reg < HighRegNum)
1936      Warning(RegInfo.second,
1937              "register not in ascending order in register list");
1938
1939    RegMap.set(Reg);
1940    HighRegNum = std::max(Reg, HighRegNum);
1941  }
1942
1943  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1944  return false;
1945}
1946
1947/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1948ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1949parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1950  SMLoc S = Parser.getTok().getLoc();
1951  const AsmToken &Tok = Parser.getTok();
1952  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1953  StringRef OptStr = Tok.getString();
1954
1955  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1956    .Case("sy",    ARM_MB::SY)
1957    .Case("st",    ARM_MB::ST)
1958    .Case("sh",    ARM_MB::ISH)
1959    .Case("ish",   ARM_MB::ISH)
1960    .Case("shst",  ARM_MB::ISHST)
1961    .Case("ishst", ARM_MB::ISHST)
1962    .Case("nsh",   ARM_MB::NSH)
1963    .Case("un",    ARM_MB::NSH)
1964    .Case("nshst", ARM_MB::NSHST)
1965    .Case("unst",  ARM_MB::NSHST)
1966    .Case("osh",   ARM_MB::OSH)
1967    .Case("oshst", ARM_MB::OSHST)
1968    .Default(~0U);
1969
1970  if (Opt == ~0U)
1971    return MatchOperand_NoMatch;
1972
1973  Parser.Lex(); // Eat identifier token.
1974  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1975  return MatchOperand_Success;
1976}
1977
1978/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1979ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1980parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1981  SMLoc S = Parser.getTok().getLoc();
1982  const AsmToken &Tok = Parser.getTok();
1983  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1984  StringRef IFlagsStr = Tok.getString();
1985
1986  unsigned IFlags = 0;
1987  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1988    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1989    .Case("a", ARM_PROC::A)
1990    .Case("i", ARM_PROC::I)
1991    .Case("f", ARM_PROC::F)
1992    .Default(~0U);
1993
1994    // If some specific iflag is already set, it means that some letter is
1995    // present more than once, this is not acceptable.
1996    if (Flag == ~0U || (IFlags & Flag))
1997      return MatchOperand_NoMatch;
1998
1999    IFlags |= Flag;
2000  }
2001
2002  Parser.Lex(); // Eat identifier token.
2003  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2004  return MatchOperand_Success;
2005}
2006
2007/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2008ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2009parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2010  SMLoc S = Parser.getTok().getLoc();
2011  const AsmToken &Tok = Parser.getTok();
2012  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2013  StringRef Mask = Tok.getString();
2014
2015  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2016  size_t Start = 0, Next = Mask.find('_');
2017  StringRef Flags = "";
2018  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2019  if (Next != StringRef::npos)
2020    Flags = Mask.slice(Next+1, Mask.size());
2021
2022  // FlagsVal contains the complete mask:
2023  // 3-0: Mask
2024  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2025  unsigned FlagsVal = 0;
2026
2027  if (SpecReg == "apsr") {
2028    FlagsVal = StringSwitch<unsigned>(Flags)
2029    .Case("nzcvq",  0x8) // same as CPSR_f
2030    .Case("g",      0x4) // same as CPSR_s
2031    .Case("nzcvqg", 0xc) // same as CPSR_fs
2032    .Default(~0U);
2033
2034    if (FlagsVal == ~0U) {
2035      if (!Flags.empty())
2036        return MatchOperand_NoMatch;
2037      else
2038        FlagsVal = 0; // No flag
2039    }
2040  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2041    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2042      Flags = "fc";
2043    for (int i = 0, e = Flags.size(); i != e; ++i) {
2044      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2045      .Case("c", 1)
2046      .Case("x", 2)
2047      .Case("s", 4)
2048      .Case("f", 8)
2049      .Default(~0U);
2050
2051      // If some specific flag is already set, it means that some letter is
2052      // present more than once, this is not acceptable.
2053      if (FlagsVal == ~0U || (FlagsVal & Flag))
2054        return MatchOperand_NoMatch;
2055      FlagsVal |= Flag;
2056    }
2057  } else // No match for special register.
2058    return MatchOperand_NoMatch;
2059
2060  // Special register without flags are equivalent to "fc" flags.
2061  if (!FlagsVal)
2062    FlagsVal = 0x9;
2063
2064  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2065  if (SpecReg == "spsr")
2066    FlagsVal |= 16;
2067
2068  Parser.Lex(); // Eat identifier token.
2069  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2070  return MatchOperand_Success;
2071}
2072
2073ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2074parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2075            int Low, int High) {
2076  const AsmToken &Tok = Parser.getTok();
2077  if (Tok.isNot(AsmToken::Identifier)) {
2078    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2079    return MatchOperand_ParseFail;
2080  }
2081  StringRef ShiftName = Tok.getString();
2082  std::string LowerOp = LowercaseString(Op);
2083  std::string UpperOp = UppercaseString(Op);
2084  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2085    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2086    return MatchOperand_ParseFail;
2087  }
2088  Parser.Lex(); // Eat shift type token.
2089
2090  // There must be a '#' and a shift amount.
2091  if (Parser.getTok().isNot(AsmToken::Hash)) {
2092    Error(Parser.getTok().getLoc(), "'#' expected");
2093    return MatchOperand_ParseFail;
2094  }
2095  Parser.Lex(); // Eat hash token.
2096
2097  const MCExpr *ShiftAmount;
2098  SMLoc Loc = Parser.getTok().getLoc();
2099  if (getParser().ParseExpression(ShiftAmount)) {
2100    Error(Loc, "illegal expression");
2101    return MatchOperand_ParseFail;
2102  }
2103  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2104  if (!CE) {
2105    Error(Loc, "constant expression expected");
2106    return MatchOperand_ParseFail;
2107  }
2108  int Val = CE->getValue();
2109  if (Val < Low || Val > High) {
2110    Error(Loc, "immediate value out of range");
2111    return MatchOperand_ParseFail;
2112  }
2113
2114  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2115
2116  return MatchOperand_Success;
2117}
2118
2119ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2120parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2121  const AsmToken &Tok = Parser.getTok();
2122  SMLoc S = Tok.getLoc();
2123  if (Tok.isNot(AsmToken::Identifier)) {
2124    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2125    return MatchOperand_ParseFail;
2126  }
2127  int Val = StringSwitch<int>(Tok.getString())
2128    .Case("be", 1)
2129    .Case("le", 0)
2130    .Default(-1);
2131  Parser.Lex(); // Eat the token.
2132
2133  if (Val == -1) {
2134    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2135    return MatchOperand_ParseFail;
2136  }
2137  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2138                                                                  getContext()),
2139                                           S, Parser.getTok().getLoc()));
2140  return MatchOperand_Success;
2141}
2142
2143/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2144/// instructions. Legal values are:
2145///     lsl #n  'n' in [0,31]
2146///     asr #n  'n' in [1,32]
2147///             n == 32 encoded as n == 0.
2148ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2149parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2150  const AsmToken &Tok = Parser.getTok();
2151  SMLoc S = Tok.getLoc();
2152  if (Tok.isNot(AsmToken::Identifier)) {
2153    Error(S, "shift operator 'asr' or 'lsl' expected");
2154    return MatchOperand_ParseFail;
2155  }
2156  StringRef ShiftName = Tok.getString();
2157  bool isASR;
2158  if (ShiftName == "lsl" || ShiftName == "LSL")
2159    isASR = false;
2160  else if (ShiftName == "asr" || ShiftName == "ASR")
2161    isASR = true;
2162  else {
2163    Error(S, "shift operator 'asr' or 'lsl' expected");
2164    return MatchOperand_ParseFail;
2165  }
2166  Parser.Lex(); // Eat the operator.
2167
2168  // A '#' and a shift amount.
2169  if (Parser.getTok().isNot(AsmToken::Hash)) {
2170    Error(Parser.getTok().getLoc(), "'#' expected");
2171    return MatchOperand_ParseFail;
2172  }
2173  Parser.Lex(); // Eat hash token.
2174
2175  const MCExpr *ShiftAmount;
2176  SMLoc E = Parser.getTok().getLoc();
2177  if (getParser().ParseExpression(ShiftAmount)) {
2178    Error(E, "malformed shift expression");
2179    return MatchOperand_ParseFail;
2180  }
2181  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2182  if (!CE) {
2183    Error(E, "shift amount must be an immediate");
2184    return MatchOperand_ParseFail;
2185  }
2186
2187  int64_t Val = CE->getValue();
2188  if (isASR) {
2189    // Shift amount must be in [1,32]
2190    if (Val < 1 || Val > 32) {
2191      Error(E, "'asr' shift amount must be in range [1,32]");
2192      return MatchOperand_ParseFail;
2193    }
2194    // asr #32 encoded as asr #0.
2195    if (Val == 32) Val = 0;
2196  } else {
2197    // Shift amount must be in [1,32]
2198    if (Val < 0 || Val > 31) {
2199      Error(E, "'lsr' shift amount must be in range [0,31]");
2200      return MatchOperand_ParseFail;
2201    }
2202  }
2203
2204  E = Parser.getTok().getLoc();
2205  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2206
2207  return MatchOperand_Success;
2208}
2209
2210/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2211/// of instructions. Legal values are:
2212///     ror #n  'n' in {0, 8, 16, 24}
2213ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2214parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2215  const AsmToken &Tok = Parser.getTok();
2216  SMLoc S = Tok.getLoc();
2217  if (Tok.isNot(AsmToken::Identifier)) {
2218    Error(S, "rotate operator 'ror' expected");
2219    return MatchOperand_ParseFail;
2220  }
2221  StringRef ShiftName = Tok.getString();
2222  if (ShiftName != "ror" && ShiftName != "ROR") {
2223    Error(S, "rotate operator 'ror' expected");
2224    return MatchOperand_ParseFail;
2225  }
2226  Parser.Lex(); // Eat the operator.
2227
2228  // A '#' and a rotate amount.
2229  if (Parser.getTok().isNot(AsmToken::Hash)) {
2230    Error(Parser.getTok().getLoc(), "'#' expected");
2231    return MatchOperand_ParseFail;
2232  }
2233  Parser.Lex(); // Eat hash token.
2234
2235  const MCExpr *ShiftAmount;
2236  SMLoc E = Parser.getTok().getLoc();
2237  if (getParser().ParseExpression(ShiftAmount)) {
2238    Error(E, "malformed rotate expression");
2239    return MatchOperand_ParseFail;
2240  }
2241  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2242  if (!CE) {
2243    Error(E, "rotate amount must be an immediate");
2244    return MatchOperand_ParseFail;
2245  }
2246
2247  int64_t Val = CE->getValue();
2248  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2249  // normally, zero is represented in asm by omitting the rotate operand
2250  // entirely.
2251  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2252    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2253    return MatchOperand_ParseFail;
2254  }
2255
2256  E = Parser.getTok().getLoc();
2257  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2258
2259  return MatchOperand_Success;
2260}
2261
2262ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2263parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2264  SMLoc S = Parser.getTok().getLoc();
2265  // The bitfield descriptor is really two operands, the LSB and the width.
2266  if (Parser.getTok().isNot(AsmToken::Hash)) {
2267    Error(Parser.getTok().getLoc(), "'#' expected");
2268    return MatchOperand_ParseFail;
2269  }
2270  Parser.Lex(); // Eat hash token.
2271
2272  const MCExpr *LSBExpr;
2273  SMLoc E = Parser.getTok().getLoc();
2274  if (getParser().ParseExpression(LSBExpr)) {
2275    Error(E, "malformed immediate expression");
2276    return MatchOperand_ParseFail;
2277  }
2278  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2279  if (!CE) {
2280    Error(E, "'lsb' operand must be an immediate");
2281    return MatchOperand_ParseFail;
2282  }
2283
2284  int64_t LSB = CE->getValue();
2285  // The LSB must be in the range [0,31]
2286  if (LSB < 0 || LSB > 31) {
2287    Error(E, "'lsb' operand must be in the range [0,31]");
2288    return MatchOperand_ParseFail;
2289  }
2290  E = Parser.getTok().getLoc();
2291
2292  // Expect another immediate operand.
2293  if (Parser.getTok().isNot(AsmToken::Comma)) {
2294    Error(Parser.getTok().getLoc(), "too few operands");
2295    return MatchOperand_ParseFail;
2296  }
2297  Parser.Lex(); // Eat hash token.
2298  if (Parser.getTok().isNot(AsmToken::Hash)) {
2299    Error(Parser.getTok().getLoc(), "'#' expected");
2300    return MatchOperand_ParseFail;
2301  }
2302  Parser.Lex(); // Eat hash token.
2303
2304  const MCExpr *WidthExpr;
2305  if (getParser().ParseExpression(WidthExpr)) {
2306    Error(E, "malformed immediate expression");
2307    return MatchOperand_ParseFail;
2308  }
2309  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2310  if (!CE) {
2311    Error(E, "'width' operand must be an immediate");
2312    return MatchOperand_ParseFail;
2313  }
2314
2315  int64_t Width = CE->getValue();
2316  // The LSB must be in the range [1,32-lsb]
2317  if (Width < 1 || Width > 32 - LSB) {
2318    Error(E, "'width' operand must be in the range [1,32-lsb]");
2319    return MatchOperand_ParseFail;
2320  }
2321  E = Parser.getTok().getLoc();
2322
2323  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2324
2325  return MatchOperand_Success;
2326}
2327
2328ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2329parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2330  // Check for a post-index addressing register operand. Specifically:
2331  // postidx_reg := '+' register {, shift}
2332  //              | '-' register {, shift}
2333  //              | register {, shift}
2334
2335  // This method must return MatchOperand_NoMatch without consuming any tokens
2336  // in the case where there is no match, as other alternatives take other
2337  // parse methods.
2338  AsmToken Tok = Parser.getTok();
2339  SMLoc S = Tok.getLoc();
2340  bool haveEaten = false;
2341  bool isAdd = true;
2342  int Reg = -1;
2343  if (Tok.is(AsmToken::Plus)) {
2344    Parser.Lex(); // Eat the '+' token.
2345    haveEaten = true;
2346  } else if (Tok.is(AsmToken::Minus)) {
2347    Parser.Lex(); // Eat the '-' token.
2348    isAdd = false;
2349    haveEaten = true;
2350  }
2351  if (Parser.getTok().is(AsmToken::Identifier))
2352    Reg = tryParseRegister();
2353  if (Reg == -1) {
2354    if (!haveEaten)
2355      return MatchOperand_NoMatch;
2356    Error(Parser.getTok().getLoc(), "register expected");
2357    return MatchOperand_ParseFail;
2358  }
2359  SMLoc E = Parser.getTok().getLoc();
2360
2361  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2362  unsigned ShiftImm = 0;
2363  if (Parser.getTok().is(AsmToken::Comma)) {
2364    Parser.Lex(); // Eat the ','.
2365    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2366      return MatchOperand_ParseFail;
2367  }
2368
2369  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2370                                                  ShiftImm, S, E));
2371
2372  return MatchOperand_Success;
2373}
2374
2375ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2376parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2377  // Check for a post-index addressing register operand. Specifically:
2378  // am3offset := '+' register
2379  //              | '-' register
2380  //              | register
2381  //              | # imm
2382  //              | # + imm
2383  //              | # - imm
2384
2385  // This method must return MatchOperand_NoMatch without consuming any tokens
2386  // in the case where there is no match, as other alternatives take other
2387  // parse methods.
2388  AsmToken Tok = Parser.getTok();
2389  SMLoc S = Tok.getLoc();
2390
2391  // Do immediates first, as we always parse those if we have a '#'.
2392  if (Parser.getTok().is(AsmToken::Hash)) {
2393    Parser.Lex(); // Eat the '#'.
2394    // Explicitly look for a '-', as we need to encode negative zero
2395    // differently.
2396    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2397    const MCExpr *Offset;
2398    if (getParser().ParseExpression(Offset))
2399      return MatchOperand_ParseFail;
2400    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2401    if (!CE) {
2402      Error(S, "constant expression expected");
2403      return MatchOperand_ParseFail;
2404    }
2405    SMLoc E = Tok.getLoc();
2406    // Negative zero is encoded as the flag value INT32_MIN.
2407    int32_t Val = CE->getValue();
2408    if (isNegative && Val == 0)
2409      Val = INT32_MIN;
2410
2411    Operands.push_back(
2412      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2413
2414    return MatchOperand_Success;
2415  }
2416
2417
2418  bool haveEaten = false;
2419  bool isAdd = true;
2420  int Reg = -1;
2421  if (Tok.is(AsmToken::Plus)) {
2422    Parser.Lex(); // Eat the '+' token.
2423    haveEaten = true;
2424  } else if (Tok.is(AsmToken::Minus)) {
2425    Parser.Lex(); // Eat the '-' token.
2426    isAdd = false;
2427    haveEaten = true;
2428  }
2429  if (Parser.getTok().is(AsmToken::Identifier))
2430    Reg = tryParseRegister();
2431  if (Reg == -1) {
2432    if (!haveEaten)
2433      return MatchOperand_NoMatch;
2434    Error(Parser.getTok().getLoc(), "register expected");
2435    return MatchOperand_ParseFail;
2436  }
2437  SMLoc E = Parser.getTok().getLoc();
2438
2439  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2440                                                  0, S, E));
2441
2442  return MatchOperand_Success;
2443}
2444
2445/// cvtT2LdrdPre - Convert parsed operands to MCInst.
2446/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2447/// when they refer multiple MIOperands inside a single one.
2448bool ARMAsmParser::
2449cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2450             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2451  // Rt, Rt2
2452  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2453  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2454  // Create a writeback register dummy placeholder.
2455  Inst.addOperand(MCOperand::CreateReg(0));
2456  // addr
2457  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2458  // pred
2459  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2460  return true;
2461}
2462
2463/// cvtT2StrdPre - Convert parsed operands to MCInst.
2464/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2465/// when they refer multiple MIOperands inside a single one.
2466bool ARMAsmParser::
2467cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
2468             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2469  // Create a writeback register dummy placeholder.
2470  Inst.addOperand(MCOperand::CreateReg(0));
2471  // Rt, Rt2
2472  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2473  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2474  // addr
2475  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2476  // pred
2477  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2478  return true;
2479}
2480
2481/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2482/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2483/// when they refer multiple MIOperands inside a single one.
2484bool ARMAsmParser::
2485cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2486                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2487  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2488
2489  // Create a writeback register dummy placeholder.
2490  Inst.addOperand(MCOperand::CreateImm(0));
2491
2492  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2493  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2494  return true;
2495}
2496
2497/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2498/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2499/// when they refer multiple MIOperands inside a single one.
2500bool ARMAsmParser::
2501cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2502                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2503  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2504
2505  // Create a writeback register dummy placeholder.
2506  Inst.addOperand(MCOperand::CreateImm(0));
2507
2508  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2509  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2510  return true;
2511}
2512
2513/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2514/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2515/// when they refer multiple MIOperands inside a single one.
2516bool ARMAsmParser::
2517cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2518                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2519  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2520
2521  // Create a writeback register dummy placeholder.
2522  Inst.addOperand(MCOperand::CreateImm(0));
2523
2524  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2525  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2526  return true;
2527}
2528
2529
2530/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2531/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2532/// when they refer multiple MIOperands inside a single one.
2533bool ARMAsmParser::
2534cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2535                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2536  // Create a writeback register dummy placeholder.
2537  Inst.addOperand(MCOperand::CreateImm(0));
2538  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2539  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2540  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2541  return true;
2542}
2543
2544/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2545/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2546/// when they refer multiple MIOperands inside a single one.
2547bool ARMAsmParser::
2548cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2549                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2550  // Create a writeback register dummy placeholder.
2551  Inst.addOperand(MCOperand::CreateImm(0));
2552  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2553  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2554  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2555  return true;
2556}
2557
2558/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2559/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2560/// when they refer multiple MIOperands inside a single one.
2561bool ARMAsmParser::
2562cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2563                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2564  // Create a writeback register dummy placeholder.
2565  Inst.addOperand(MCOperand::CreateImm(0));
2566  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2567  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2568  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2569  return true;
2570}
2571
2572/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2573/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2574/// when they refer multiple MIOperands inside a single one.
2575bool ARMAsmParser::
2576cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2577                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2578  // Rt
2579  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2580  // Create a writeback register dummy placeholder.
2581  Inst.addOperand(MCOperand::CreateImm(0));
2582  // addr
2583  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2584  // offset
2585  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2586  // pred
2587  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2588  return true;
2589}
2590
2591/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2592/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2593/// when they refer multiple MIOperands inside a single one.
2594bool ARMAsmParser::
2595cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2596                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2597  // Rt
2598  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2599  // Create a writeback register dummy placeholder.
2600  Inst.addOperand(MCOperand::CreateImm(0));
2601  // addr
2602  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2603  // offset
2604  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2605  // pred
2606  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2607  return true;
2608}
2609
2610/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2611/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2612/// when they refer multiple MIOperands inside a single one.
2613bool ARMAsmParser::
2614cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2615                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2616  // Create a writeback register dummy placeholder.
2617  Inst.addOperand(MCOperand::CreateImm(0));
2618  // Rt
2619  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2620  // addr
2621  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2622  // offset
2623  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2624  // pred
2625  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2626  return true;
2627}
2628
2629/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2630/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2631/// when they refer multiple MIOperands inside a single one.
2632bool ARMAsmParser::
2633cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2634                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2635  // Create a writeback register dummy placeholder.
2636  Inst.addOperand(MCOperand::CreateImm(0));
2637  // Rt
2638  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2639  // addr
2640  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2641  // offset
2642  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2643  // pred
2644  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2645  return true;
2646}
2647
2648/// cvtLdrdPre - Convert parsed operands to MCInst.
2649/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2650/// when they refer multiple MIOperands inside a single one.
2651bool ARMAsmParser::
2652cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2653           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2654  // Rt, Rt2
2655  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2656  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2657  // Create a writeback register dummy placeholder.
2658  Inst.addOperand(MCOperand::CreateImm(0));
2659  // addr
2660  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2661  // pred
2662  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2663  return true;
2664}
2665
2666/// cvtStrdPre - Convert parsed operands to MCInst.
2667/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2668/// when they refer multiple MIOperands inside a single one.
2669bool ARMAsmParser::
2670cvtStrdPre(MCInst &Inst, unsigned Opcode,
2671           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2672  // Create a writeback register dummy placeholder.
2673  Inst.addOperand(MCOperand::CreateImm(0));
2674  // Rt, Rt2
2675  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2676  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2677  // addr
2678  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2679  // pred
2680  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2681  return true;
2682}
2683
2684/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2685/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2686/// when they refer multiple MIOperands inside a single one.
2687bool ARMAsmParser::
2688cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2689                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2690  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2691  // Create a writeback register dummy placeholder.
2692  Inst.addOperand(MCOperand::CreateImm(0));
2693  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2694  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2695  return true;
2696}
2697
2698/// cvtThumbMultiple- Convert parsed operands to MCInst.
2699/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2700/// when they refer multiple MIOperands inside a single one.
2701bool ARMAsmParser::
2702cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2703           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2704  // The second source operand must be the same register as the destination
2705  // operand.
2706  if (Operands.size() == 6 &&
2707      (((ARMOperand*)Operands[3])->getReg() !=
2708       ((ARMOperand*)Operands[5])->getReg()) &&
2709      (((ARMOperand*)Operands[3])->getReg() !=
2710       ((ARMOperand*)Operands[4])->getReg())) {
2711    Error(Operands[3]->getStartLoc(),
2712          "destination register must match source register");
2713    return false;
2714  }
2715  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2716  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2717  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2718  // If we have a three-operand form, use that, else the second source operand
2719  // is just the destination operand again.
2720  if (Operands.size() == 6)
2721    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2722  else
2723    Inst.addOperand(Inst.getOperand(0));
2724  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2725
2726  return true;
2727}
2728
2729/// Parse an ARM memory expression, return false if successful else return true
2730/// or an error.  The first token must be a '[' when called.
2731bool ARMAsmParser::
2732parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2733  SMLoc S, E;
2734  assert(Parser.getTok().is(AsmToken::LBrac) &&
2735         "Token is not a Left Bracket");
2736  S = Parser.getTok().getLoc();
2737  Parser.Lex(); // Eat left bracket token.
2738
2739  const AsmToken &BaseRegTok = Parser.getTok();
2740  int BaseRegNum = tryParseRegister();
2741  if (BaseRegNum == -1)
2742    return Error(BaseRegTok.getLoc(), "register expected");
2743
2744  // The next token must either be a comma or a closing bracket.
2745  const AsmToken &Tok = Parser.getTok();
2746  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2747    return Error(Tok.getLoc(), "malformed memory operand");
2748
2749  if (Tok.is(AsmToken::RBrac)) {
2750    E = Tok.getLoc();
2751    Parser.Lex(); // Eat right bracket token.
2752
2753    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2754                                             0, false, S, E));
2755
2756    return false;
2757  }
2758
2759  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2760  Parser.Lex(); // Eat the comma.
2761
2762  // If we have a '#' it's an immediate offset, else assume it's a register
2763  // offset.
2764  if (Parser.getTok().is(AsmToken::Hash)) {
2765    Parser.Lex(); // Eat the '#'.
2766    E = Parser.getTok().getLoc();
2767
2768    bool isNegative = getParser().getTok().is(AsmToken::Minus);
2769    const MCExpr *Offset;
2770    if (getParser().ParseExpression(Offset))
2771     return true;
2772
2773    // The expression has to be a constant. Memory references with relocations
2774    // don't come through here, as they use the <label> forms of the relevant
2775    // instructions.
2776    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2777    if (!CE)
2778      return Error (E, "constant expression expected");
2779
2780    // If the constant was #-0, represent it as INT32_MIN.
2781    int32_t Val = CE->getValue();
2782    if (isNegative && Val == 0)
2783      CE = MCConstantExpr::Create(INT32_MIN, getContext());
2784
2785    // Now we should have the closing ']'
2786    E = Parser.getTok().getLoc();
2787    if (Parser.getTok().isNot(AsmToken::RBrac))
2788      return Error(E, "']' expected");
2789    Parser.Lex(); // Eat right bracket token.
2790
2791    // Don't worry about range checking the value here. That's handled by
2792    // the is*() predicates.
2793    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2794                                             ARM_AM::no_shift, 0, false, S,E));
2795
2796    // If there's a pre-indexing writeback marker, '!', just add it as a token
2797    // operand.
2798    if (Parser.getTok().is(AsmToken::Exclaim)) {
2799      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2800      Parser.Lex(); // Eat the '!'.
2801    }
2802
2803    return false;
2804  }
2805
2806  // The register offset is optionally preceded by a '+' or '-'
2807  bool isNegative = false;
2808  if (Parser.getTok().is(AsmToken::Minus)) {
2809    isNegative = true;
2810    Parser.Lex(); // Eat the '-'.
2811  } else if (Parser.getTok().is(AsmToken::Plus)) {
2812    // Nothing to do.
2813    Parser.Lex(); // Eat the '+'.
2814  }
2815
2816  E = Parser.getTok().getLoc();
2817  int OffsetRegNum = tryParseRegister();
2818  if (OffsetRegNum == -1)
2819    return Error(E, "register expected");
2820
2821  // If there's a shift operator, handle it.
2822  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2823  unsigned ShiftImm = 0;
2824  if (Parser.getTok().is(AsmToken::Comma)) {
2825    Parser.Lex(); // Eat the ','.
2826    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2827      return true;
2828  }
2829
2830  // Now we should have the closing ']'
2831  E = Parser.getTok().getLoc();
2832  if (Parser.getTok().isNot(AsmToken::RBrac))
2833    return Error(E, "']' expected");
2834  Parser.Lex(); // Eat right bracket token.
2835
2836  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2837                                           ShiftType, ShiftImm, isNegative,
2838                                           S, E));
2839
2840  // If there's a pre-indexing writeback marker, '!', just add it as a token
2841  // operand.
2842  if (Parser.getTok().is(AsmToken::Exclaim)) {
2843    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2844    Parser.Lex(); // Eat the '!'.
2845  }
2846
2847  return false;
2848}
2849
2850/// parseMemRegOffsetShift - one of these two:
2851///   ( lsl | lsr | asr | ror ) , # shift_amount
2852///   rrx
2853/// return true if it parses a shift otherwise it returns false.
2854bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2855                                          unsigned &Amount) {
2856  SMLoc Loc = Parser.getTok().getLoc();
2857  const AsmToken &Tok = Parser.getTok();
2858  if (Tok.isNot(AsmToken::Identifier))
2859    return true;
2860  StringRef ShiftName = Tok.getString();
2861  if (ShiftName == "lsl" || ShiftName == "LSL")
2862    St = ARM_AM::lsl;
2863  else if (ShiftName == "lsr" || ShiftName == "LSR")
2864    St = ARM_AM::lsr;
2865  else if (ShiftName == "asr" || ShiftName == "ASR")
2866    St = ARM_AM::asr;
2867  else if (ShiftName == "ror" || ShiftName == "ROR")
2868    St = ARM_AM::ror;
2869  else if (ShiftName == "rrx" || ShiftName == "RRX")
2870    St = ARM_AM::rrx;
2871  else
2872    return Error(Loc, "illegal shift operator");
2873  Parser.Lex(); // Eat shift type token.
2874
2875  // rrx stands alone.
2876  Amount = 0;
2877  if (St != ARM_AM::rrx) {
2878    Loc = Parser.getTok().getLoc();
2879    // A '#' and a shift amount.
2880    const AsmToken &HashTok = Parser.getTok();
2881    if (HashTok.isNot(AsmToken::Hash))
2882      return Error(HashTok.getLoc(), "'#' expected");
2883    Parser.Lex(); // Eat hash token.
2884
2885    const MCExpr *Expr;
2886    if (getParser().ParseExpression(Expr))
2887      return true;
2888    // Range check the immediate.
2889    // lsl, ror: 0 <= imm <= 31
2890    // lsr, asr: 0 <= imm <= 32
2891    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2892    if (!CE)
2893      return Error(Loc, "shift amount must be an immediate");
2894    int64_t Imm = CE->getValue();
2895    if (Imm < 0 ||
2896        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2897        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2898      return Error(Loc, "immediate shift value out of range");
2899    Amount = Imm;
2900  }
2901
2902  return false;
2903}
2904
2905/// Parse a arm instruction operand.  For now this parses the operand regardless
2906/// of the mnemonic.
2907bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2908                                StringRef Mnemonic) {
2909  SMLoc S, E;
2910
2911  // Check if the current operand has a custom associated parser, if so, try to
2912  // custom parse the operand, or fallback to the general approach.
2913  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2914  if (ResTy == MatchOperand_Success)
2915    return false;
2916  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2917  // there was a match, but an error occurred, in which case, just return that
2918  // the operand parsing failed.
2919  if (ResTy == MatchOperand_ParseFail)
2920    return true;
2921
2922  switch (getLexer().getKind()) {
2923  default:
2924    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2925    return true;
2926  case AsmToken::Identifier: {
2927    if (!tryParseRegisterWithWriteBack(Operands))
2928      return false;
2929    int Res = tryParseShiftRegister(Operands);
2930    if (Res == 0) // success
2931      return false;
2932    else if (Res == -1) // irrecoverable error
2933      return true;
2934
2935    // Fall though for the Identifier case that is not a register or a
2936    // special name.
2937  }
2938  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2939  case AsmToken::Dot: {   // . as a branch target
2940    // This was not a register so parse other operands that start with an
2941    // identifier (like labels) as expressions and create them as immediates.
2942    const MCExpr *IdVal;
2943    S = Parser.getTok().getLoc();
2944    if (getParser().ParseExpression(IdVal))
2945      return true;
2946    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2947    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2948    return false;
2949  }
2950  case AsmToken::LBrac:
2951    return parseMemory(Operands);
2952  case AsmToken::LCurly:
2953    return parseRegisterList(Operands);
2954  case AsmToken::Hash: {
2955    // #42 -> immediate.
2956    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2957    S = Parser.getTok().getLoc();
2958    Parser.Lex();
2959    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2960    const MCExpr *ImmVal;
2961    if (getParser().ParseExpression(ImmVal))
2962      return true;
2963    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
2964    if (!CE) {
2965      Error(S, "constant expression expected");
2966      return MatchOperand_ParseFail;
2967    }
2968    int32_t Val = CE->getValue();
2969    if (isNegative && Val == 0)
2970      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
2971    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2972    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2973    return false;
2974  }
2975  case AsmToken::Colon: {
2976    // ":lower16:" and ":upper16:" expression prefixes
2977    // FIXME: Check it's an expression prefix,
2978    // e.g. (FOO - :lower16:BAR) isn't legal.
2979    ARMMCExpr::VariantKind RefKind;
2980    if (parsePrefix(RefKind))
2981      return true;
2982
2983    const MCExpr *SubExprVal;
2984    if (getParser().ParseExpression(SubExprVal))
2985      return true;
2986
2987    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2988                                                   getContext());
2989    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2990    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2991    return false;
2992  }
2993  }
2994}
2995
2996// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2997//  :lower16: and :upper16:.
2998bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2999  RefKind = ARMMCExpr::VK_ARM_None;
3000
3001  // :lower16: and :upper16: modifiers
3002  assert(getLexer().is(AsmToken::Colon) && "expected a :");
3003  Parser.Lex(); // Eat ':'
3004
3005  if (getLexer().isNot(AsmToken::Identifier)) {
3006    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3007    return true;
3008  }
3009
3010  StringRef IDVal = Parser.getTok().getIdentifier();
3011  if (IDVal == "lower16") {
3012    RefKind = ARMMCExpr::VK_ARM_LO16;
3013  } else if (IDVal == "upper16") {
3014    RefKind = ARMMCExpr::VK_ARM_HI16;
3015  } else {
3016    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3017    return true;
3018  }
3019  Parser.Lex();
3020
3021  if (getLexer().isNot(AsmToken::Colon)) {
3022    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3023    return true;
3024  }
3025  Parser.Lex(); // Eat the last ':'
3026  return false;
3027}
3028
3029const MCExpr *
3030ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
3031                                MCSymbolRefExpr::VariantKind Variant) {
3032  // Recurse over the given expression, rebuilding it to apply the given variant
3033  // to the leftmost symbol.
3034  if (Variant == MCSymbolRefExpr::VK_None)
3035    return E;
3036
3037  switch (E->getKind()) {
3038  case MCExpr::Target:
3039    llvm_unreachable("Can't handle target expr yet");
3040  case MCExpr::Constant:
3041    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
3042
3043  case MCExpr::SymbolRef: {
3044    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
3045
3046    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
3047      return 0;
3048
3049    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
3050  }
3051
3052  case MCExpr::Unary:
3053    llvm_unreachable("Can't handle unary expressions yet");
3054
3055  case MCExpr::Binary: {
3056    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
3057    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
3058    const MCExpr *RHS = BE->getRHS();
3059    if (!LHS)
3060      return 0;
3061
3062    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
3063  }
3064  }
3065
3066  assert(0 && "Invalid expression kind!");
3067  return 0;
3068}
3069
3070/// \brief Given a mnemonic, split out possible predication code and carry
3071/// setting letters to form a canonical mnemonic and flags.
3072//
3073// FIXME: Would be nice to autogen this.
3074// FIXME: This is a bit of a maze of special cases.
3075StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3076                                      unsigned &PredicationCode,
3077                                      bool &CarrySetting,
3078                                      unsigned &ProcessorIMod,
3079                                      StringRef &ITMask) {
3080  PredicationCode = ARMCC::AL;
3081  CarrySetting = false;
3082  ProcessorIMod = 0;
3083
3084  // Ignore some mnemonics we know aren't predicated forms.
3085  //
3086  // FIXME: Would be nice to autogen this.
3087  if ((Mnemonic == "movs" && isThumb()) ||
3088      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
3089      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
3090      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
3091      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
3092      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
3093      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
3094      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3095    return Mnemonic;
3096
3097  // First, split out any predication code. Ignore mnemonics we know aren't
3098  // predicated but do have a carry-set and so weren't caught above.
3099  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3100      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3101      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3102      Mnemonic != "sbcs" && Mnemonic != "rscs") {
3103    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3104      .Case("eq", ARMCC::EQ)
3105      .Case("ne", ARMCC::NE)
3106      .Case("hs", ARMCC::HS)
3107      .Case("cs", ARMCC::HS)
3108      .Case("lo", ARMCC::LO)
3109      .Case("cc", ARMCC::LO)
3110      .Case("mi", ARMCC::MI)
3111      .Case("pl", ARMCC::PL)
3112      .Case("vs", ARMCC::VS)
3113      .Case("vc", ARMCC::VC)
3114      .Case("hi", ARMCC::HI)
3115      .Case("ls", ARMCC::LS)
3116      .Case("ge", ARMCC::GE)
3117      .Case("lt", ARMCC::LT)
3118      .Case("gt", ARMCC::GT)
3119      .Case("le", ARMCC::LE)
3120      .Case("al", ARMCC::AL)
3121      .Default(~0U);
3122    if (CC != ~0U) {
3123      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3124      PredicationCode = CC;
3125    }
3126  }
3127
3128  // Next, determine if we have a carry setting bit. We explicitly ignore all
3129  // the instructions we know end in 's'.
3130  if (Mnemonic.endswith("s") &&
3131      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3132        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3133        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3134        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3135        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3136        (Mnemonic == "movs" && isThumb()))) {
3137    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3138    CarrySetting = true;
3139  }
3140
3141  // The "cps" instruction can have a interrupt mode operand which is glued into
3142  // the mnemonic. Check if this is the case, split it and parse the imod op
3143  if (Mnemonic.startswith("cps")) {
3144    // Split out any imod code.
3145    unsigned IMod =
3146      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3147      .Case("ie", ARM_PROC::IE)
3148      .Case("id", ARM_PROC::ID)
3149      .Default(~0U);
3150    if (IMod != ~0U) {
3151      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3152      ProcessorIMod = IMod;
3153    }
3154  }
3155
3156  // The "it" instruction has the condition mask on the end of the mnemonic.
3157  if (Mnemonic.startswith("it")) {
3158    ITMask = Mnemonic.slice(2, Mnemonic.size());
3159    Mnemonic = Mnemonic.slice(0, 2);
3160  }
3161
3162  return Mnemonic;
3163}
3164
3165/// \brief Given a canonical mnemonic, determine if the instruction ever allows
3166/// inclusion of carry set or predication code operands.
3167//
3168// FIXME: It would be nice to autogen this.
3169void ARMAsmParser::
3170getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3171                      bool &CanAcceptPredicationCode) {
3172  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3173      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3174      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
3175      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3176      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3177      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3178      Mnemonic == "sbc" || Mnemonic == "umull" ||
3179      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
3180      ((Mnemonic == "mov" || Mnemonic == "mla") && !isThumb())) {
3181    CanAcceptCarrySet = true;
3182  } else {
3183    CanAcceptCarrySet = false;
3184  }
3185
3186  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3187      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3188      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3189      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3190      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3191      (Mnemonic == "clrex" && !isThumb()) ||
3192      (Mnemonic == "nop" && isThumbOne()) ||
3193      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3194       !isThumb()) ||
3195      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3196       !isThumb()) ||
3197      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3198    CanAcceptPredicationCode = false;
3199  } else {
3200    CanAcceptPredicationCode = true;
3201  }
3202
3203  if (isThumb())
3204    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3205        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3206      CanAcceptPredicationCode = false;
3207}
3208
3209bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3210                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3211  // FIXME: This is all horribly hacky. We really need a better way to deal
3212  // with optional operands like this in the matcher table.
3213
3214  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3215  // another does not. Specifically, the MOVW instruction does not. So we
3216  // special case it here and remove the defaulted (non-setting) cc_out
3217  // operand if that's the instruction we're trying to match.
3218  //
3219  // We do this as post-processing of the explicit operands rather than just
3220  // conditionally adding the cc_out in the first place because we need
3221  // to check the type of the parsed immediate operand.
3222  if (Mnemonic == "mov" && Operands.size() > 4 &&
3223      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3224      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3225      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3226    return true;
3227
3228  // Register-register 'add' for thumb does not have a cc_out operand
3229  // when there are only two register operands.
3230  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3231      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3232      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3233      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3234    return true;
3235  // Register-register 'add' for thumb does not have a cc_out operand
3236  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3237  // have to check the immediate range here since Thumb2 has a variant
3238  // that can handle a different range and has a cc_out operand.
3239  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3240      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3241      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3242      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3243      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3244      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3245       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3246    return true;
3247  // For Thumb2, add immediate does not have a cc_out operand for the
3248  // imm0_4096 variant. That's the least-preferred variant when
3249  // selecting via the generic "add" mnemonic, so to know that we
3250  // should remove the cc_out operand, we have to explicitly check that
3251  // it's not one of the other variants. Ugh.
3252  if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
3253      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3254      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3255      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3256    // Nest conditions rather than one big 'if' statement for readability.
3257    //
3258    // If either register is a high reg, it's either one of the SP
3259    // variants (handled above) or a 32-bit encoding, so we just
3260    // check against T3.
3261    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3262         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3263        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3264      return false;
3265    // If both registers are low, we're in an IT block, and the immediate is
3266    // in range, we should use encoding T1 instead, which has a cc_out.
3267    if (inITBlock() &&
3268        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3269        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3270        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3271      return false;
3272
3273    // Otherwise, we use encoding T4, which does not have a cc_out
3274    // operand.
3275    return true;
3276  }
3277
3278
3279  // Register-register 'add/sub' for thumb does not have a cc_out operand
3280  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3281  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3282  // right, this will result in better diagnostics (which operand is off)
3283  // anyway.
3284  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3285      (Operands.size() == 5 || Operands.size() == 6) &&
3286      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3287      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3288      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3289    return true;
3290
3291  return false;
3292}
3293
3294/// Parse an arm instruction mnemonic followed by its operands.
3295bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3296                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3297  // Create the leading tokens for the mnemonic, split by '.' characters.
3298  size_t Start = 0, Next = Name.find('.');
3299  StringRef Mnemonic = Name.slice(Start, Next);
3300
3301  // Split out the predication code and carry setting flag from the mnemonic.
3302  unsigned PredicationCode;
3303  unsigned ProcessorIMod;
3304  bool CarrySetting;
3305  StringRef ITMask;
3306  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3307                           ProcessorIMod, ITMask);
3308
3309  // In Thumb1, only the branch (B) instruction can be predicated.
3310  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3311    Parser.EatToEndOfStatement();
3312    return Error(NameLoc, "conditional execution not supported in Thumb1");
3313  }
3314
3315  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3316
3317  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3318  // is the mask as it will be for the IT encoding if the conditional
3319  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3320  // where the conditional bit0 is zero, the instruction post-processing
3321  // will adjust the mask accordingly.
3322  if (Mnemonic == "it") {
3323    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3324    if (ITMask.size() > 3) {
3325      Parser.EatToEndOfStatement();
3326      return Error(Loc, "too many conditions on IT instruction");
3327    }
3328    unsigned Mask = 8;
3329    for (unsigned i = ITMask.size(); i != 0; --i) {
3330      char pos = ITMask[i - 1];
3331      if (pos != 't' && pos != 'e') {
3332        Parser.EatToEndOfStatement();
3333        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3334      }
3335      Mask >>= 1;
3336      if (ITMask[i - 1] == 't')
3337        Mask |= 8;
3338    }
3339    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3340  }
3341
3342  // FIXME: This is all a pretty gross hack. We should automatically handle
3343  // optional operands like this via tblgen.
3344
3345  // Next, add the CCOut and ConditionCode operands, if needed.
3346  //
3347  // For mnemonics which can ever incorporate a carry setting bit or predication
3348  // code, our matching model involves us always generating CCOut and
3349  // ConditionCode operands to match the mnemonic "as written" and then we let
3350  // the matcher deal with finding the right instruction or generating an
3351  // appropriate error.
3352  bool CanAcceptCarrySet, CanAcceptPredicationCode;
3353  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3354
3355  // If we had a carry-set on an instruction that can't do that, issue an
3356  // error.
3357  if (!CanAcceptCarrySet && CarrySetting) {
3358    Parser.EatToEndOfStatement();
3359    return Error(NameLoc, "instruction '" + Mnemonic +
3360                 "' can not set flags, but 's' suffix specified");
3361  }
3362  // If we had a predication code on an instruction that can't do that, issue an
3363  // error.
3364  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3365    Parser.EatToEndOfStatement();
3366    return Error(NameLoc, "instruction '" + Mnemonic +
3367                 "' is not predicable, but condition code specified");
3368  }
3369
3370  // Add the carry setting operand, if necessary.
3371  if (CanAcceptCarrySet) {
3372    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3373    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3374                                               Loc));
3375  }
3376
3377  // Add the predication code operand, if necessary.
3378  if (CanAcceptPredicationCode) {
3379    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3380                                      CarrySetting);
3381    Operands.push_back(ARMOperand::CreateCondCode(
3382                         ARMCC::CondCodes(PredicationCode), Loc));
3383  }
3384
3385  // Add the processor imod operand, if necessary.
3386  if (ProcessorIMod) {
3387    Operands.push_back(ARMOperand::CreateImm(
3388          MCConstantExpr::Create(ProcessorIMod, getContext()),
3389                                 NameLoc, NameLoc));
3390  }
3391
3392  // Add the remaining tokens in the mnemonic.
3393  while (Next != StringRef::npos) {
3394    Start = Next;
3395    Next = Name.find('.', Start + 1);
3396    StringRef ExtraToken = Name.slice(Start, Next);
3397
3398    // For now, we're only parsing Thumb1 (for the most part), so
3399    // just ignore ".n" qualifiers. We'll use them to restrict
3400    // matching when we do Thumb2.
3401    if (ExtraToken != ".n") {
3402      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3403      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3404    }
3405  }
3406
3407  // Read the remaining operands.
3408  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3409    // Read the first operand.
3410    if (parseOperand(Operands, Mnemonic)) {
3411      Parser.EatToEndOfStatement();
3412      return true;
3413    }
3414
3415    while (getLexer().is(AsmToken::Comma)) {
3416      Parser.Lex();  // Eat the comma.
3417
3418      // Parse and remember the operand.
3419      if (parseOperand(Operands, Mnemonic)) {
3420        Parser.EatToEndOfStatement();
3421        return true;
3422      }
3423    }
3424  }
3425
3426  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3427    Parser.EatToEndOfStatement();
3428    return TokError("unexpected token in argument list");
3429  }
3430
3431  Parser.Lex(); // Consume the EndOfStatement
3432
3433  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3434  // do and don't have a cc_out optional-def operand. With some spot-checks
3435  // of the operand list, we can figure out which variant we're trying to
3436  // parse and adjust accordingly before actually matching. We shouldn't ever
3437  // try to remove a cc_out operand that was explicitly set on the the
3438  // mnemonic, of course (CarrySetting == true). Reason number #317 the
3439  // table driven matcher doesn't fit well with the ARM instruction set.
3440  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3441    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3442    Operands.erase(Operands.begin() + 1);
3443    delete Op;
3444  }
3445
3446  // ARM mode 'blx' need special handling, as the register operand version
3447  // is predicable, but the label operand version is not. So, we can't rely
3448  // on the Mnemonic based checking to correctly figure out when to put
3449  // a CondCode operand in the list. If we're trying to match the label
3450  // version, remove the CondCode operand here.
3451  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3452      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3453    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3454    Operands.erase(Operands.begin() + 1);
3455    delete Op;
3456  }
3457
3458  // The vector-compare-to-zero instructions have a literal token "#0" at
3459  // the end that comes to here as an immediate operand. Convert it to a
3460  // token to play nicely with the matcher.
3461  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3462      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3463      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3464    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3465    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3466    if (CE && CE->getValue() == 0) {
3467      Operands.erase(Operands.begin() + 5);
3468      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3469      delete Op;
3470    }
3471  }
3472  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3473  // end. Convert it to a token here.
3474  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3475      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3476    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3477    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3478    if (CE && CE->getValue() == 0) {
3479      Operands.erase(Operands.begin() + 5);
3480      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3481      delete Op;
3482    }
3483  }
3484
3485  return false;
3486}
3487
3488// Validate context-sensitive operand constraints.
3489
3490// return 'true' if register list contains non-low GPR registers,
3491// 'false' otherwise. If Reg is in the register list or is HiReg, set
3492// 'containsReg' to true.
3493static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3494                                 unsigned HiReg, bool &containsReg) {
3495  containsReg = false;
3496  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3497    unsigned OpReg = Inst.getOperand(i).getReg();
3498    if (OpReg == Reg)
3499      containsReg = true;
3500    // Anything other than a low register isn't legal here.
3501    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3502      return true;
3503  }
3504  return false;
3505}
3506
3507// Check if the specified regisgter is in the register list of the inst,
3508// starting at the indicated operand number.
3509static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3510  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3511    unsigned OpReg = Inst.getOperand(i).getReg();
3512    if (OpReg == Reg)
3513      return true;
3514  }
3515  return false;
3516}
3517
3518// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3519// the ARMInsts array) instead. Getting that here requires awkward
3520// API changes, though. Better way?
3521namespace llvm {
3522extern MCInstrDesc ARMInsts[];
3523}
3524static MCInstrDesc &getInstDesc(unsigned Opcode) {
3525  return ARMInsts[Opcode];
3526}
3527
3528// FIXME: We would really like to be able to tablegen'erate this.
3529bool ARMAsmParser::
3530validateInstruction(MCInst &Inst,
3531                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3532  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3533  SMLoc Loc = Operands[0]->getStartLoc();
3534  // Check the IT block state first.
3535  if (inITBlock()) {
3536    unsigned bit = 1;
3537    if (ITState.FirstCond)
3538      ITState.FirstCond = false;
3539    else
3540      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3541    // The instruction must be predicable.
3542    if (!MCID.isPredicable())
3543      return Error(Loc, "instructions in IT block must be predicable");
3544    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3545    unsigned ITCond = bit ? ITState.Cond :
3546      ARMCC::getOppositeCondition(ITState.Cond);
3547    if (Cond != ITCond) {
3548      // Find the condition code Operand to get its SMLoc information.
3549      SMLoc CondLoc;
3550      for (unsigned i = 1; i < Operands.size(); ++i)
3551        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3552          CondLoc = Operands[i]->getStartLoc();
3553      return Error(CondLoc, "incorrect condition in IT block; got '" +
3554                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3555                   "', but expected '" +
3556                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3557    }
3558  // Check for non-'al' condition codes outside of the IT block.
3559  } else if (isThumbTwo() && MCID.isPredicable() &&
3560             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3561             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
3562             Inst.getOpcode() != ARM::t2B)
3563    return Error(Loc, "predicated instructions must be in IT block");
3564
3565  switch (Inst.getOpcode()) {
3566  case ARM::LDRD:
3567  case ARM::LDRD_PRE:
3568  case ARM::LDRD_POST:
3569  case ARM::LDREXD: {
3570    // Rt2 must be Rt + 1.
3571    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3572    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3573    if (Rt2 != Rt + 1)
3574      return Error(Operands[3]->getStartLoc(),
3575                   "destination operands must be sequential");
3576    return false;
3577  }
3578  case ARM::STRD: {
3579    // Rt2 must be Rt + 1.
3580    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3581    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3582    if (Rt2 != Rt + 1)
3583      return Error(Operands[3]->getStartLoc(),
3584                   "source operands must be sequential");
3585    return false;
3586  }
3587  case ARM::STRD_PRE:
3588  case ARM::STRD_POST:
3589  case ARM::STREXD: {
3590    // Rt2 must be Rt + 1.
3591    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3592    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3593    if (Rt2 != Rt + 1)
3594      return Error(Operands[3]->getStartLoc(),
3595                   "source operands must be sequential");
3596    return false;
3597  }
3598  case ARM::SBFX:
3599  case ARM::UBFX: {
3600    // width must be in range [1, 32-lsb]
3601    unsigned lsb = Inst.getOperand(2).getImm();
3602    unsigned widthm1 = Inst.getOperand(3).getImm();
3603    if (widthm1 >= 32 - lsb)
3604      return Error(Operands[5]->getStartLoc(),
3605                   "bitfield width must be in range [1,32-lsb]");
3606    return false;
3607  }
3608  case ARM::tLDMIA: {
3609    // If we're parsing Thumb2, the .w variant is available and handles
3610    // most cases that are normally illegal for a Thumb1 LDM
3611    // instruction. We'll make the transformation in processInstruction()
3612    // if necessary.
3613    //
3614    // Thumb LDM instructions are writeback iff the base register is not
3615    // in the register list.
3616    unsigned Rn = Inst.getOperand(0).getReg();
3617    bool hasWritebackToken =
3618      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3619       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3620    bool listContainsBase;
3621    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3622      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3623                   "registers must be in range r0-r7");
3624    // If we should have writeback, then there should be a '!' token.
3625    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3626      return Error(Operands[2]->getStartLoc(),
3627                   "writeback operator '!' expected");
3628    // If we should not have writeback, there must not be a '!'. This is
3629    // true even for the 32-bit wide encodings.
3630    if (listContainsBase && hasWritebackToken)
3631      return Error(Operands[3]->getStartLoc(),
3632                   "writeback operator '!' not allowed when base register "
3633                   "in register list");
3634
3635    break;
3636  }
3637  case ARM::t2LDMIA_UPD: {
3638    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3639      return Error(Operands[4]->getStartLoc(),
3640                   "writeback operator '!' not allowed when base register "
3641                   "in register list");
3642    break;
3643  }
3644  case ARM::tPOP: {
3645    bool listContainsBase;
3646    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3647      return Error(Operands[2]->getStartLoc(),
3648                   "registers must be in range r0-r7 or pc");
3649    break;
3650  }
3651  case ARM::tPUSH: {
3652    bool listContainsBase;
3653    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3654      return Error(Operands[2]->getStartLoc(),
3655                   "registers must be in range r0-r7 or lr");
3656    break;
3657  }
3658  case ARM::tSTMIA_UPD: {
3659    bool listContainsBase;
3660    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3661      return Error(Operands[4]->getStartLoc(),
3662                   "registers must be in range r0-r7");
3663    break;
3664  }
3665  }
3666
3667  return false;
3668}
3669
3670void ARMAsmParser::
3671processInstruction(MCInst &Inst,
3672                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3673  switch (Inst.getOpcode()) {
3674  case ARM::LDMIA_UPD:
3675    // If this is a load of a single register via a 'pop', then we should use
3676    // a post-indexed LDR instruction instead, per the ARM ARM.
3677    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3678        Inst.getNumOperands() == 5) {
3679      MCInst TmpInst;
3680      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3681      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3682      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3683      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3684      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3685      TmpInst.addOperand(MCOperand::CreateImm(4));
3686      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3687      TmpInst.addOperand(Inst.getOperand(3));
3688      Inst = TmpInst;
3689    }
3690    break;
3691  case ARM::STMDB_UPD:
3692    // If this is a store of a single register via a 'push', then we should use
3693    // a pre-indexed STR instruction instead, per the ARM ARM.
3694    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3695        Inst.getNumOperands() == 5) {
3696      MCInst TmpInst;
3697      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3698      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3699      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3700      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3701      TmpInst.addOperand(MCOperand::CreateImm(-4));
3702      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3703      TmpInst.addOperand(Inst.getOperand(3));
3704      Inst = TmpInst;
3705    }
3706    break;
3707  case ARM::tADDi8:
3708    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3709    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3710    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3711    // to encoding T1 if <Rd> is omitted."
3712    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3713      Inst.setOpcode(ARM::tADDi3);
3714    break;
3715  case ARM::tB:
3716    // A Thumb conditional branch outside of an IT block is a tBcc.
3717    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3718      Inst.setOpcode(ARM::tBcc);
3719    break;
3720  case ARM::t2B:
3721    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
3722    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3723      Inst.setOpcode(ARM::t2Bcc);
3724    break;
3725  case ARM::t2Bcc:
3726    // If the conditional is AL or we're in an IT block, we really want t2B.
3727    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3728      Inst.setOpcode(ARM::t2B);
3729    break;
3730  case ARM::tBcc:
3731    // If the conditional is AL, we really want tB.
3732    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3733      Inst.setOpcode(ARM::tB);
3734    break;
3735  case ARM::tLDMIA: {
3736    // If the register list contains any high registers, or if the writeback
3737    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3738    // instead if we're in Thumb2. Otherwise, this should have generated
3739    // an error in validateInstruction().
3740    unsigned Rn = Inst.getOperand(0).getReg();
3741    bool hasWritebackToken =
3742      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3743       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3744    bool listContainsBase;
3745    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3746        (!listContainsBase && !hasWritebackToken) ||
3747        (listContainsBase && hasWritebackToken)) {
3748      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3749      assert (isThumbTwo());
3750      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3751      // If we're switching to the updating version, we need to insert
3752      // the writeback tied operand.
3753      if (hasWritebackToken)
3754        Inst.insert(Inst.begin(),
3755                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3756    }
3757    break;
3758  }
3759  case ARM::t2MOVi: {
3760    // If we can use the 16-bit encoding and the user didn't explicitly
3761    // request the 32-bit variant, transform it here.
3762    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3763        Inst.getOperand(1).getImm() <= 255 &&
3764        Inst.getOperand(2).getImm() == ARMCC::AL &&
3765        Inst.getOperand(4).getReg() == ARM::CPSR &&
3766        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3767         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3768      // The operands aren't in the same order for tMOVi8...
3769      MCInst TmpInst;
3770      TmpInst.setOpcode(ARM::tMOVi8);
3771      TmpInst.addOperand(Inst.getOperand(0));
3772      TmpInst.addOperand(Inst.getOperand(4));
3773      TmpInst.addOperand(Inst.getOperand(1));
3774      TmpInst.addOperand(Inst.getOperand(2));
3775      TmpInst.addOperand(Inst.getOperand(3));
3776      Inst = TmpInst;
3777    }
3778    break;
3779  }
3780  case ARM::t2MOVr: {
3781    // If we can use the 16-bit encoding and the user didn't explicitly
3782    // request the 32-bit variant, transform it here.
3783    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3784        isARMLowRegister(Inst.getOperand(1).getReg()) &&
3785        Inst.getOperand(2).getImm() == ARMCC::AL &&
3786        Inst.getOperand(4).getReg() == ARM::CPSR &&
3787        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3788         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3789      // The operands aren't the same for tMOV[S]r... (no cc_out)
3790      MCInst TmpInst;
3791      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
3792      TmpInst.addOperand(Inst.getOperand(0));
3793      TmpInst.addOperand(Inst.getOperand(1));
3794      TmpInst.addOperand(Inst.getOperand(2));
3795      TmpInst.addOperand(Inst.getOperand(3));
3796      Inst = TmpInst;
3797    }
3798    break;
3799  }
3800  case ARM::t2IT: {
3801    // The mask bits for all but the first condition are represented as
3802    // the low bit of the condition code value implies 't'. We currently
3803    // always have 1 implies 't', so XOR toggle the bits if the low bit
3804    // of the condition code is zero. The encoding also expects the low
3805    // bit of the condition to be encoded as bit 4 of the mask operand,
3806    // so mask that in if needed
3807    MCOperand &MO = Inst.getOperand(1);
3808    unsigned Mask = MO.getImm();
3809    unsigned OrigMask = Mask;
3810    unsigned TZ = CountTrailingZeros_32(Mask);
3811    if ((Inst.getOperand(0).getImm() & 1) == 0) {
3812      assert(Mask && TZ <= 3 && "illegal IT mask value!");
3813      for (unsigned i = 3; i != TZ; --i)
3814        Mask ^= 1 << i;
3815    } else
3816      Mask |= 0x10;
3817    MO.setImm(Mask);
3818
3819    // Set up the IT block state according to the IT instruction we just
3820    // matched.
3821    assert(!inITBlock() && "nested IT blocks?!");
3822    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3823    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3824    ITState.CurPosition = 0;
3825    ITState.FirstCond = true;
3826    break;
3827  }
3828  }
3829}
3830
3831unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3832  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3833  // suffix depending on whether they're in an IT block or not.
3834  unsigned Opc = Inst.getOpcode();
3835  MCInstrDesc &MCID = getInstDesc(Opc);
3836  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3837    assert(MCID.hasOptionalDef() &&
3838           "optionally flag setting instruction missing optional def operand");
3839    assert(MCID.NumOperands == Inst.getNumOperands() &&
3840           "operand count mismatch!");
3841    // Find the optional-def operand (cc_out).
3842    unsigned OpNo;
3843    for (OpNo = 0;
3844         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3845         ++OpNo)
3846      ;
3847    // If we're parsing Thumb1, reject it completely.
3848    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3849      return Match_MnemonicFail;
3850    // If we're parsing Thumb2, which form is legal depends on whether we're
3851    // in an IT block.
3852    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3853        !inITBlock())
3854      return Match_RequiresITBlock;
3855    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3856        inITBlock())
3857      return Match_RequiresNotITBlock;
3858  }
3859  // Some high-register supporting Thumb1 encodings only allow both registers
3860  // to be from r0-r7 when in Thumb2.
3861  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3862           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3863           isARMLowRegister(Inst.getOperand(2).getReg()))
3864    return Match_RequiresThumb2;
3865  // Others only require ARMv6 or later.
3866  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3867           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3868           isARMLowRegister(Inst.getOperand(1).getReg()))
3869    return Match_RequiresV6;
3870  return Match_Success;
3871}
3872
3873bool ARMAsmParser::
3874MatchAndEmitInstruction(SMLoc IDLoc,
3875                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3876                        MCStreamer &Out) {
3877  MCInst Inst;
3878  unsigned ErrorInfo;
3879  unsigned MatchResult;
3880  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3881  switch (MatchResult) {
3882  default: break;
3883  case Match_Success:
3884    // Context sensitive operand constraints aren't handled by the matcher,
3885    // so check them here.
3886    if (validateInstruction(Inst, Operands)) {
3887      // Still progress the IT block, otherwise one wrong condition causes
3888      // nasty cascading errors.
3889      forwardITPosition();
3890      return true;
3891    }
3892
3893    // Some instructions need post-processing to, for example, tweak which
3894    // encoding is selected.
3895    processInstruction(Inst, Operands);
3896
3897    // Only move forward at the very end so that everything in validate
3898    // and process gets a consistent answer about whether we're in an IT
3899    // block.
3900    forwardITPosition();
3901
3902    Out.EmitInstruction(Inst);
3903    return false;
3904  case Match_MissingFeature:
3905    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3906    return true;
3907  case Match_InvalidOperand: {
3908    SMLoc ErrorLoc = IDLoc;
3909    if (ErrorInfo != ~0U) {
3910      if (ErrorInfo >= Operands.size())
3911        return Error(IDLoc, "too few operands for instruction");
3912
3913      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3914      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3915    }
3916
3917    return Error(ErrorLoc, "invalid operand for instruction");
3918  }
3919  case Match_MnemonicFail:
3920    return Error(IDLoc, "invalid instruction");
3921  case Match_ConversionFail:
3922    // The converter function will have already emited a diagnostic.
3923    return true;
3924  case Match_RequiresNotITBlock:
3925    return Error(IDLoc, "flag setting instruction only valid outside IT block");
3926  case Match_RequiresITBlock:
3927    return Error(IDLoc, "instruction only valid inside IT block");
3928  case Match_RequiresV6:
3929    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3930  case Match_RequiresThumb2:
3931    return Error(IDLoc, "instruction variant requires Thumb2");
3932  }
3933
3934  llvm_unreachable("Implement any new match types added!");
3935  return true;
3936}
3937
3938/// parseDirective parses the arm specific directives
3939bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3940  StringRef IDVal = DirectiveID.getIdentifier();
3941  if (IDVal == ".word")
3942    return parseDirectiveWord(4, DirectiveID.getLoc());
3943  else if (IDVal == ".thumb")
3944    return parseDirectiveThumb(DirectiveID.getLoc());
3945  else if (IDVal == ".thumb_func")
3946    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3947  else if (IDVal == ".code")
3948    return parseDirectiveCode(DirectiveID.getLoc());
3949  else if (IDVal == ".syntax")
3950    return parseDirectiveSyntax(DirectiveID.getLoc());
3951  return true;
3952}
3953
3954/// parseDirectiveWord
3955///  ::= .word [ expression (, expression)* ]
3956bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3957  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3958    for (;;) {
3959      const MCExpr *Value;
3960      if (getParser().ParseExpression(Value))
3961        return true;
3962
3963      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3964
3965      if (getLexer().is(AsmToken::EndOfStatement))
3966        break;
3967
3968      // FIXME: Improve diagnostic.
3969      if (getLexer().isNot(AsmToken::Comma))
3970        return Error(L, "unexpected token in directive");
3971      Parser.Lex();
3972    }
3973  }
3974
3975  Parser.Lex();
3976  return false;
3977}
3978
3979/// parseDirectiveThumb
3980///  ::= .thumb
3981bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3982  if (getLexer().isNot(AsmToken::EndOfStatement))
3983    return Error(L, "unexpected token in directive");
3984  Parser.Lex();
3985
3986  // TODO: set thumb mode
3987  // TODO: tell the MC streamer the mode
3988  // getParser().getStreamer().Emit???();
3989  return false;
3990}
3991
3992/// parseDirectiveThumbFunc
3993///  ::= .thumbfunc symbol_name
3994bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3995  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3996  bool isMachO = MAI.hasSubsectionsViaSymbols();
3997  StringRef Name;
3998
3999  // Darwin asm has function name after .thumb_func direction
4000  // ELF doesn't
4001  if (isMachO) {
4002    const AsmToken &Tok = Parser.getTok();
4003    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4004      return Error(L, "unexpected token in .thumb_func directive");
4005    Name = Tok.getString();
4006    Parser.Lex(); // Consume the identifier token.
4007  }
4008
4009  if (getLexer().isNot(AsmToken::EndOfStatement))
4010    return Error(L, "unexpected token in directive");
4011  Parser.Lex();
4012
4013  // FIXME: assuming function name will be the line following .thumb_func
4014  if (!isMachO) {
4015    Name = Parser.getTok().getString();
4016  }
4017
4018  // Mark symbol as a thumb symbol.
4019  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4020  getParser().getStreamer().EmitThumbFunc(Func);
4021  return false;
4022}
4023
4024/// parseDirectiveSyntax
4025///  ::= .syntax unified | divided
4026bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4027  const AsmToken &Tok = Parser.getTok();
4028  if (Tok.isNot(AsmToken::Identifier))
4029    return Error(L, "unexpected token in .syntax directive");
4030  StringRef Mode = Tok.getString();
4031  if (Mode == "unified" || Mode == "UNIFIED")
4032    Parser.Lex();
4033  else if (Mode == "divided" || Mode == "DIVIDED")
4034    return Error(L, "'.syntax divided' arm asssembly not supported");
4035  else
4036    return Error(L, "unrecognized syntax mode in .syntax directive");
4037
4038  if (getLexer().isNot(AsmToken::EndOfStatement))
4039    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4040  Parser.Lex();
4041
4042  // TODO tell the MC streamer the mode
4043  // getParser().getStreamer().Emit???();
4044  return false;
4045}
4046
4047/// parseDirectiveCode
4048///  ::= .code 16 | 32
4049bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4050  const AsmToken &Tok = Parser.getTok();
4051  if (Tok.isNot(AsmToken::Integer))
4052    return Error(L, "unexpected token in .code directive");
4053  int64_t Val = Parser.getTok().getIntVal();
4054  if (Val == 16)
4055    Parser.Lex();
4056  else if (Val == 32)
4057    Parser.Lex();
4058  else
4059    return Error(L, "invalid operand to .code directive");
4060
4061  if (getLexer().isNot(AsmToken::EndOfStatement))
4062    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4063  Parser.Lex();
4064
4065  if (Val == 16) {
4066    if (!isThumb())
4067      SwitchMode();
4068    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4069  } else {
4070    if (isThumb())
4071      SwitchMode();
4072    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4073  }
4074
4075  return false;
4076}
4077
4078extern "C" void LLVMInitializeARMAsmLexer();
4079
4080/// Force static initialization.
4081extern "C" void LLVMInitializeARMAsmParser() {
4082  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4083  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4084  LLVMInitializeARMAsmLexer();
4085}
4086
4087#define GET_REGISTER_MATCHER
4088#define GET_MATCHER_IMPLEMENTATION
4089#include "ARMGenAsmMatcher.inc"
4090