ARMAsmParser.cpp revision 3912b73c74dc9c928228504e9a23c577b57c4e12 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MCTargetAsmParser.h"
24#include "llvm/Target/TargetRegistry.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/ADT/OwningPtr.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringExtras.h"
31#include "llvm/ADT/StringSwitch.h"
32#include "llvm/ADT/Twine.h"
33
34using namespace llvm;
35
36namespace {
37
38class ARMOperand;
39
40class ARMAsmParser : public MCTargetAsmParser {
41  MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43
44  MCAsmParser &getParser() const { return Parser; }
45  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
46
47  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
49
50  int tryParseRegister();
51  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57  const MCExpr *applyPrefixToExpr(const MCExpr *E,
58                                  MCSymbolRefExpr::VariantKind Variant);
59
60
61  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62                              unsigned &ShiftAmount);
63  bool parseDirectiveWord(unsigned Size, SMLoc L);
64  bool parseDirectiveThumb(SMLoc L);
65  bool parseDirectiveThumbFunc(SMLoc L);
66  bool parseDirectiveCode(SMLoc L);
67  bool parseDirectiveSyntax(SMLoc L);
68
69  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70                          bool &CarrySetting, unsigned &ProcessorIMod);
71  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72                             bool &CanAcceptPredicationCode);
73
74  bool isThumb() const {
75    // FIXME: Can tablegen auto-generate this?
76    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
77  }
78  bool isThumbOne() const {
79    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
80  }
81  bool isThumbTwo() const {
82    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
83  }
84  void SwitchMode() {
85    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
86    setAvailableFeatures(FB);
87  }
88
89  /// @name Auto-generated Match Functions
90  /// {
91
92#define GET_ASSEMBLER_HEADER
93#include "ARMGenAsmMatcher.inc"
94
95  /// }
96
97  OperandMatchResultTy parseCoprocNumOperand(
98    SmallVectorImpl<MCParsedAsmOperand*>&);
99  OperandMatchResultTy parseCoprocRegOperand(
100    SmallVectorImpl<MCParsedAsmOperand*>&);
101  OperandMatchResultTy parseMemBarrierOptOperand(
102    SmallVectorImpl<MCParsedAsmOperand*>&);
103  OperandMatchResultTy parseProcIFlagsOperand(
104    SmallVectorImpl<MCParsedAsmOperand*>&);
105  OperandMatchResultTy parseMSRMaskOperand(
106    SmallVectorImpl<MCParsedAsmOperand*>&);
107  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
108                                   StringRef Op, int Low, int High);
109  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
110    return parsePKHImm(O, "lsl", 0, 31);
111  }
112  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
113    return parsePKHImm(O, "asr", 1, 32);
114  }
115  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
116  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
117  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
118  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
119  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
120  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
121
122  // Asm Match Converter Methods
123  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
124                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
125  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
126                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
127  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
128                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
129  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
130                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
131  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
132                             const SmallVectorImpl<MCParsedAsmOperand*> &);
133  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
134                             const SmallVectorImpl<MCParsedAsmOperand*> &);
135  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
136                             const SmallVectorImpl<MCParsedAsmOperand*> &);
137  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
138                             const SmallVectorImpl<MCParsedAsmOperand*> &);
139  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
140                  const SmallVectorImpl<MCParsedAsmOperand*> &);
141  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
142                  const SmallVectorImpl<MCParsedAsmOperand*> &);
143  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
144                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
145
146  bool validateInstruction(MCInst &Inst,
147                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
148  void processInstruction(MCInst &Inst,
149                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
150  bool shouldOmitCCOutOperand(StringRef Mnemonic,
151                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
152
153public:
154  enum ARMMatchResultTy {
155    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY
156  };
157
158  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
159    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
160    MCAsmParserExtension::Initialize(_Parser);
161
162    // Initialize the set of available features.
163    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
164  }
165
166  // Implementation of the MCTargetAsmParser interface:
167  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
168  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
169                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
170  bool ParseDirective(AsmToken DirectiveID);
171
172  unsigned checkTargetMatchPredicate(MCInst &Inst);
173
174  bool MatchAndEmitInstruction(SMLoc IDLoc,
175                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
176                               MCStreamer &Out);
177};
178} // end anonymous namespace
179
180namespace {
181
182/// ARMOperand - Instances of this class represent a parsed ARM machine
183/// instruction.
184class ARMOperand : public MCParsedAsmOperand {
185  enum KindTy {
186    CondCode,
187    CCOut,
188    CoprocNum,
189    CoprocReg,
190    Immediate,
191    MemBarrierOpt,
192    Memory,
193    PostIndexRegister,
194    MSRMask,
195    ProcIFlags,
196    Register,
197    RegisterList,
198    DPRRegisterList,
199    SPRRegisterList,
200    ShiftedRegister,
201    ShiftedImmediate,
202    ShifterImmediate,
203    RotateImmediate,
204    BitfieldDescriptor,
205    Token
206  } Kind;
207
208  SMLoc StartLoc, EndLoc;
209  SmallVector<unsigned, 8> Registers;
210
211  union {
212    struct {
213      ARMCC::CondCodes Val;
214    } CC;
215
216    struct {
217      ARM_MB::MemBOpt Val;
218    } MBOpt;
219
220    struct {
221      unsigned Val;
222    } Cop;
223
224    struct {
225      ARM_PROC::IFlags Val;
226    } IFlags;
227
228    struct {
229      unsigned Val;
230    } MMask;
231
232    struct {
233      const char *Data;
234      unsigned Length;
235    } Tok;
236
237    struct {
238      unsigned RegNum;
239    } Reg;
240
241    struct {
242      const MCExpr *Val;
243    } Imm;
244
245    /// Combined record for all forms of ARM address expressions.
246    struct {
247      unsigned BaseRegNum;
248      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
249      // was specified.
250      const MCConstantExpr *OffsetImm;  // Offset immediate value
251      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
252      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
253      unsigned ShiftImm;      // shift for OffsetReg.
254      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
255    } Mem;
256
257    struct {
258      unsigned RegNum;
259      bool isAdd;
260      ARM_AM::ShiftOpc ShiftTy;
261      unsigned ShiftImm;
262    } PostIdxReg;
263
264    struct {
265      bool isASR;
266      unsigned Imm;
267    } ShifterImm;
268    struct {
269      ARM_AM::ShiftOpc ShiftTy;
270      unsigned SrcReg;
271      unsigned ShiftReg;
272      unsigned ShiftImm;
273    } RegShiftedReg;
274    struct {
275      ARM_AM::ShiftOpc ShiftTy;
276      unsigned SrcReg;
277      unsigned ShiftImm;
278    } RegShiftedImm;
279    struct {
280      unsigned Imm;
281    } RotImm;
282    struct {
283      unsigned LSB;
284      unsigned Width;
285    } Bitfield;
286  };
287
288  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
289public:
290  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
291    Kind = o.Kind;
292    StartLoc = o.StartLoc;
293    EndLoc = o.EndLoc;
294    switch (Kind) {
295    case CondCode:
296      CC = o.CC;
297      break;
298    case Token:
299      Tok = o.Tok;
300      break;
301    case CCOut:
302    case Register:
303      Reg = o.Reg;
304      break;
305    case RegisterList:
306    case DPRRegisterList:
307    case SPRRegisterList:
308      Registers = o.Registers;
309      break;
310    case CoprocNum:
311    case CoprocReg:
312      Cop = o.Cop;
313      break;
314    case Immediate:
315      Imm = o.Imm;
316      break;
317    case MemBarrierOpt:
318      MBOpt = o.MBOpt;
319      break;
320    case Memory:
321      Mem = o.Mem;
322      break;
323    case PostIndexRegister:
324      PostIdxReg = o.PostIdxReg;
325      break;
326    case MSRMask:
327      MMask = o.MMask;
328      break;
329    case ProcIFlags:
330      IFlags = o.IFlags;
331      break;
332    case ShifterImmediate:
333      ShifterImm = o.ShifterImm;
334      break;
335    case ShiftedRegister:
336      RegShiftedReg = o.RegShiftedReg;
337      break;
338    case ShiftedImmediate:
339      RegShiftedImm = o.RegShiftedImm;
340      break;
341    case RotateImmediate:
342      RotImm = o.RotImm;
343      break;
344    case BitfieldDescriptor:
345      Bitfield = o.Bitfield;
346      break;
347    }
348  }
349
350  /// getStartLoc - Get the location of the first token of this operand.
351  SMLoc getStartLoc() const { return StartLoc; }
352  /// getEndLoc - Get the location of the last token of this operand.
353  SMLoc getEndLoc() const { return EndLoc; }
354
355  ARMCC::CondCodes getCondCode() const {
356    assert(Kind == CondCode && "Invalid access!");
357    return CC.Val;
358  }
359
360  unsigned getCoproc() const {
361    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
362    return Cop.Val;
363  }
364
365  StringRef getToken() const {
366    assert(Kind == Token && "Invalid access!");
367    return StringRef(Tok.Data, Tok.Length);
368  }
369
370  unsigned getReg() const {
371    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
372    return Reg.RegNum;
373  }
374
375  const SmallVectorImpl<unsigned> &getRegList() const {
376    assert((Kind == RegisterList || Kind == DPRRegisterList ||
377            Kind == SPRRegisterList) && "Invalid access!");
378    return Registers;
379  }
380
381  const MCExpr *getImm() const {
382    assert(Kind == Immediate && "Invalid access!");
383    return Imm.Val;
384  }
385
386  ARM_MB::MemBOpt getMemBarrierOpt() const {
387    assert(Kind == MemBarrierOpt && "Invalid access!");
388    return MBOpt.Val;
389  }
390
391  ARM_PROC::IFlags getProcIFlags() const {
392    assert(Kind == ProcIFlags && "Invalid access!");
393    return IFlags.Val;
394  }
395
396  unsigned getMSRMask() const {
397    assert(Kind == MSRMask && "Invalid access!");
398    return MMask.Val;
399  }
400
401  bool isCoprocNum() const { return Kind == CoprocNum; }
402  bool isCoprocReg() const { return Kind == CoprocReg; }
403  bool isCondCode() const { return Kind == CondCode; }
404  bool isCCOut() const { return Kind == CCOut; }
405  bool isImm() const { return Kind == Immediate; }
406  bool isImm0_255() const {
407    if (Kind != Immediate)
408      return false;
409    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
410    if (!CE) return false;
411    int64_t Value = CE->getValue();
412    return Value >= 0 && Value < 256;
413  }
414  bool isImm0_7() const {
415    if (Kind != Immediate)
416      return false;
417    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
418    if (!CE) return false;
419    int64_t Value = CE->getValue();
420    return Value >= 0 && Value < 8;
421  }
422  bool isImm0_15() const {
423    if (Kind != Immediate)
424      return false;
425    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
426    if (!CE) return false;
427    int64_t Value = CE->getValue();
428    return Value >= 0 && Value < 16;
429  }
430  bool isImm0_31() const {
431    if (Kind != Immediate)
432      return false;
433    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
434    if (!CE) return false;
435    int64_t Value = CE->getValue();
436    return Value >= 0 && Value < 32;
437  }
438  bool isImm1_16() const {
439    if (Kind != Immediate)
440      return false;
441    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
442    if (!CE) return false;
443    int64_t Value = CE->getValue();
444    return Value > 0 && Value < 17;
445  }
446  bool isImm1_32() const {
447    if (Kind != Immediate)
448      return false;
449    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
450    if (!CE) return false;
451    int64_t Value = CE->getValue();
452    return Value > 0 && Value < 33;
453  }
454  bool isImm0_65535() const {
455    if (Kind != Immediate)
456      return false;
457    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
458    if (!CE) return false;
459    int64_t Value = CE->getValue();
460    return Value >= 0 && Value < 65536;
461  }
462  bool isImm0_65535Expr() const {
463    if (Kind != Immediate)
464      return false;
465    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
466    // If it's not a constant expression, it'll generate a fixup and be
467    // handled later.
468    if (!CE) return true;
469    int64_t Value = CE->getValue();
470    return Value >= 0 && Value < 65536;
471  }
472  bool isImm24bit() const {
473    if (Kind != Immediate)
474      return false;
475    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
476    if (!CE) return false;
477    int64_t Value = CE->getValue();
478    return Value >= 0 && Value <= 0xffffff;
479  }
480  bool isPKHLSLImm() const {
481    if (Kind != Immediate)
482      return false;
483    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
484    if (!CE) return false;
485    int64_t Value = CE->getValue();
486    return Value >= 0 && Value < 32;
487  }
488  bool isPKHASRImm() const {
489    if (Kind != Immediate)
490      return false;
491    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
492    if (!CE) return false;
493    int64_t Value = CE->getValue();
494    return Value > 0 && Value <= 32;
495  }
496  bool isARMSOImm() const {
497    if (Kind != Immediate)
498      return false;
499    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
500    if (!CE) return false;
501    int64_t Value = CE->getValue();
502    return ARM_AM::getSOImmVal(Value) != -1;
503  }
504  bool isT2SOImm() const {
505    if (Kind != Immediate)
506      return false;
507    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
508    if (!CE) return false;
509    int64_t Value = CE->getValue();
510    return ARM_AM::getT2SOImmVal(Value) != -1;
511  }
512  bool isSetEndImm() const {
513    if (Kind != Immediate)
514      return false;
515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516    if (!CE) return false;
517    int64_t Value = CE->getValue();
518    return Value == 1 || Value == 0;
519  }
520  bool isReg() const { return Kind == Register; }
521  bool isRegList() const { return Kind == RegisterList; }
522  bool isDPRRegList() const { return Kind == DPRRegisterList; }
523  bool isSPRRegList() const { return Kind == SPRRegisterList; }
524  bool isToken() const { return Kind == Token; }
525  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
526  bool isMemory() const { return Kind == Memory; }
527  bool isShifterImm() const { return Kind == ShifterImmediate; }
528  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
529  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
530  bool isRotImm() const { return Kind == RotateImmediate; }
531  bool isBitfield() const { return Kind == BitfieldDescriptor; }
532  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
533  bool isPostIdxReg() const {
534    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
535  }
536  bool isMemNoOffset() const {
537    if (Kind != Memory)
538      return false;
539    // No offset of any kind.
540    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
541  }
542  bool isAddrMode2() const {
543    if (Kind != Memory)
544      return false;
545    // Check for register offset.
546    if (Mem.OffsetRegNum) return true;
547    // Immediate offset in range [-4095, 4095].
548    if (!Mem.OffsetImm) return true;
549    int64_t Val = Mem.OffsetImm->getValue();
550    return Val > -4096 && Val < 4096;
551  }
552  bool isAM2OffsetImm() const {
553    if (Kind != Immediate)
554      return false;
555    // Immediate offset in range [-4095, 4095].
556    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
557    if (!CE) return false;
558    int64_t Val = CE->getValue();
559    return Val > -4096 && Val < 4096;
560  }
561  bool isAddrMode3() const {
562    if (Kind != Memory)
563      return false;
564    // No shifts are legal for AM3.
565    if (Mem.ShiftType != ARM_AM::no_shift) return false;
566    // Check for register offset.
567    if (Mem.OffsetRegNum) return true;
568    // Immediate offset in range [-255, 255].
569    if (!Mem.OffsetImm) return true;
570    int64_t Val = Mem.OffsetImm->getValue();
571    return Val > -256 && Val < 256;
572  }
573  bool isAM3Offset() const {
574    if (Kind != Immediate && Kind != PostIndexRegister)
575      return false;
576    if (Kind == PostIndexRegister)
577      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
578    // Immediate offset in range [-255, 255].
579    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
580    if (!CE) return false;
581    int64_t Val = CE->getValue();
582    // Special case, #-0 is INT32_MIN.
583    return (Val > -256 && Val < 256) || Val == INT32_MIN;
584  }
585  bool isAddrMode5() const {
586    if (Kind != Memory)
587      return false;
588    // Check for register offset.
589    if (Mem.OffsetRegNum) return false;
590    // Immediate offset in range [-1020, 1020] and a multiple of 4.
591    if (!Mem.OffsetImm) return true;
592    int64_t Val = Mem.OffsetImm->getValue();
593    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
594  }
595  bool isMemRegOffset() const {
596    if (Kind != Memory || !Mem.OffsetRegNum)
597      return false;
598    return true;
599  }
600  bool isMemThumbRR() const {
601    // Thumb reg+reg addressing is simple. Just two registers, a base and
602    // an offset. No shifts, negations or any other complicating factors.
603    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
604        Mem.ShiftType != ARM_AM::no_shift)
605      return false;
606    return true;
607  }
608  bool isMemImm8Offset() const {
609    if (Kind != Memory || Mem.OffsetRegNum != 0)
610      return false;
611    // Immediate offset in range [-255, 255].
612    if (!Mem.OffsetImm) return true;
613    int64_t Val = Mem.OffsetImm->getValue();
614    return Val > -256 && Val < 256;
615  }
616  bool isMemImm12Offset() const {
617    // If we have an immediate that's not a constant, treat it as a label
618    // reference needing a fixup. If it is a constant, it's something else
619    // and we reject it.
620    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
621      return true;
622
623    if (Kind != Memory || Mem.OffsetRegNum != 0)
624      return false;
625    // Immediate offset in range [-4095, 4095].
626    if (!Mem.OffsetImm) return true;
627    int64_t Val = Mem.OffsetImm->getValue();
628    return Val > -4096 && Val < 4096;
629  }
630  bool isPostIdxImm8() const {
631    if (Kind != Immediate)
632      return false;
633    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
634    if (!CE) return false;
635    int64_t Val = CE->getValue();
636    return Val > -256 && Val < 256;
637  }
638
639  bool isMSRMask() const { return Kind == MSRMask; }
640  bool isProcIFlags() const { return Kind == ProcIFlags; }
641
642  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
643    // Add as immediates when possible.  Null MCExpr = 0.
644    if (Expr == 0)
645      Inst.addOperand(MCOperand::CreateImm(0));
646    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
647      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
648    else
649      Inst.addOperand(MCOperand::CreateExpr(Expr));
650  }
651
652  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
653    assert(N == 2 && "Invalid number of operands!");
654    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
655    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
656    Inst.addOperand(MCOperand::CreateReg(RegNum));
657  }
658
659  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
660    assert(N == 1 && "Invalid number of operands!");
661    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
662  }
663
664  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
665    assert(N == 1 && "Invalid number of operands!");
666    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
667  }
668
669  void addCCOutOperands(MCInst &Inst, unsigned N) const {
670    assert(N == 1 && "Invalid number of operands!");
671    Inst.addOperand(MCOperand::CreateReg(getReg()));
672  }
673
674  void addRegOperands(MCInst &Inst, unsigned N) const {
675    assert(N == 1 && "Invalid number of operands!");
676    Inst.addOperand(MCOperand::CreateReg(getReg()));
677  }
678
679  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
680    assert(N == 3 && "Invalid number of operands!");
681    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
682    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
683    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
684    Inst.addOperand(MCOperand::CreateImm(
685      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
686  }
687
688  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
689    assert(N == 2 && "Invalid number of operands!");
690    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
691    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
692    Inst.addOperand(MCOperand::CreateImm(
693      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
694  }
695
696
697  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
698    assert(N == 1 && "Invalid number of operands!");
699    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
700                                         ShifterImm.Imm));
701  }
702
703  void addRegListOperands(MCInst &Inst, unsigned N) const {
704    assert(N == 1 && "Invalid number of operands!");
705    const SmallVectorImpl<unsigned> &RegList = getRegList();
706    for (SmallVectorImpl<unsigned>::const_iterator
707           I = RegList.begin(), E = RegList.end(); I != E; ++I)
708      Inst.addOperand(MCOperand::CreateReg(*I));
709  }
710
711  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
712    addRegListOperands(Inst, N);
713  }
714
715  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
716    addRegListOperands(Inst, N);
717  }
718
719  void addRotImmOperands(MCInst &Inst, unsigned N) const {
720    assert(N == 1 && "Invalid number of operands!");
721    // Encoded as val>>3. The printer handles display as 8, 16, 24.
722    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
723  }
724
725  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
726    assert(N == 1 && "Invalid number of operands!");
727    // Munge the lsb/width into a bitfield mask.
728    unsigned lsb = Bitfield.LSB;
729    unsigned width = Bitfield.Width;
730    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
731    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
732                      (32 - (lsb + width)));
733    Inst.addOperand(MCOperand::CreateImm(Mask));
734  }
735
736  void addImmOperands(MCInst &Inst, unsigned N) const {
737    assert(N == 1 && "Invalid number of operands!");
738    addExpr(Inst, getImm());
739  }
740
741  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
742    assert(N == 1 && "Invalid number of operands!");
743    addExpr(Inst, getImm());
744  }
745
746  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
747    assert(N == 1 && "Invalid number of operands!");
748    addExpr(Inst, getImm());
749  }
750
751  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
752    assert(N == 1 && "Invalid number of operands!");
753    addExpr(Inst, getImm());
754  }
755
756  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
757    assert(N == 1 && "Invalid number of operands!");
758    addExpr(Inst, getImm());
759  }
760
761  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
762    assert(N == 1 && "Invalid number of operands!");
763    // The constant encodes as the immediate-1, and we store in the instruction
764    // the bits as encoded, so subtract off one here.
765    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
766    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
767  }
768
769  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
770    assert(N == 1 && "Invalid number of operands!");
771    // The constant encodes as the immediate-1, and we store in the instruction
772    // the bits as encoded, so subtract off one here.
773    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
775  }
776
777  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
778    assert(N == 1 && "Invalid number of operands!");
779    addExpr(Inst, getImm());
780  }
781
782  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
783    assert(N == 1 && "Invalid number of operands!");
784    addExpr(Inst, getImm());
785  }
786
787  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
788    assert(N == 1 && "Invalid number of operands!");
789    addExpr(Inst, getImm());
790  }
791
792  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
793    assert(N == 1 && "Invalid number of operands!");
794    addExpr(Inst, getImm());
795  }
796
797  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
798    assert(N == 1 && "Invalid number of operands!");
799    // An ASR value of 32 encodes as 0, so that's how we want to add it to
800    // the instruction as well.
801    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
802    int Val = CE->getValue();
803    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
804  }
805
806  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
807    assert(N == 1 && "Invalid number of operands!");
808    addExpr(Inst, getImm());
809  }
810
811  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
812    assert(N == 1 && "Invalid number of operands!");
813    addExpr(Inst, getImm());
814  }
815
816  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
817    assert(N == 1 && "Invalid number of operands!");
818    addExpr(Inst, getImm());
819  }
820
821  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
822    assert(N == 1 && "Invalid number of operands!");
823    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
824  }
825
826  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
827    assert(N == 1 && "Invalid number of operands!");
828    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
829  }
830
831  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
832    assert(N == 3 && "Invalid number of operands!");
833    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
834    if (!Mem.OffsetRegNum) {
835      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
836      // Special case for #-0
837      if (Val == INT32_MIN) Val = 0;
838      if (Val < 0) Val = -Val;
839      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
840    } else {
841      // For register offset, we encode the shift type and negation flag
842      // here.
843      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
844                              Mem.ShiftImm, Mem.ShiftType);
845    }
846    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
847    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
848    Inst.addOperand(MCOperand::CreateImm(Val));
849  }
850
851  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
852    assert(N == 2 && "Invalid number of operands!");
853    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
854    assert(CE && "non-constant AM2OffsetImm operand!");
855    int32_t Val = CE->getValue();
856    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
857    // Special case for #-0
858    if (Val == INT32_MIN) Val = 0;
859    if (Val < 0) Val = -Val;
860    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
861    Inst.addOperand(MCOperand::CreateReg(0));
862    Inst.addOperand(MCOperand::CreateImm(Val));
863  }
864
865  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
866    assert(N == 3 && "Invalid number of operands!");
867    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
868    if (!Mem.OffsetRegNum) {
869      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
870      // Special case for #-0
871      if (Val == INT32_MIN) Val = 0;
872      if (Val < 0) Val = -Val;
873      Val = ARM_AM::getAM3Opc(AddSub, Val);
874    } else {
875      // For register offset, we encode the shift type and negation flag
876      // here.
877      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
878    }
879    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
880    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
881    Inst.addOperand(MCOperand::CreateImm(Val));
882  }
883
884  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
885    assert(N == 2 && "Invalid number of operands!");
886    if (Kind == PostIndexRegister) {
887      int32_t Val =
888        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
889      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
890      Inst.addOperand(MCOperand::CreateImm(Val));
891      return;
892    }
893
894    // Constant offset.
895    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
896    int32_t Val = CE->getValue();
897    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
898    // Special case for #-0
899    if (Val == INT32_MIN) Val = 0;
900    if (Val < 0) Val = -Val;
901    Val = ARM_AM::getAM3Opc(AddSub, Val);
902    Inst.addOperand(MCOperand::CreateReg(0));
903    Inst.addOperand(MCOperand::CreateImm(Val));
904  }
905
906  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
907    assert(N == 2 && "Invalid number of operands!");
908    // The lower two bits are always zero and as such are not encoded.
909    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
910    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
911    // Special case for #-0
912    if (Val == INT32_MIN) Val = 0;
913    if (Val < 0) Val = -Val;
914    Val = ARM_AM::getAM5Opc(AddSub, Val);
915    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
916    Inst.addOperand(MCOperand::CreateImm(Val));
917  }
918
919  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
920    assert(N == 2 && "Invalid number of operands!");
921    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
922    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
923    Inst.addOperand(MCOperand::CreateImm(Val));
924  }
925
926  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
927    assert(N == 2 && "Invalid number of operands!");
928    // If this is an immediate, it's a label reference.
929    if (Kind == Immediate) {
930      addExpr(Inst, getImm());
931      Inst.addOperand(MCOperand::CreateImm(0));
932      return;
933    }
934
935    // Otherwise, it's a normal memory reg+offset.
936    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
937    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
938    Inst.addOperand(MCOperand::CreateImm(Val));
939  }
940
941  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
942    assert(N == 3 && "Invalid number of operands!");
943    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
944                                     Mem.ShiftImm, Mem.ShiftType);
945    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
946    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
947    Inst.addOperand(MCOperand::CreateImm(Val));
948  }
949
950  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
951    assert(N == 2 && "Invalid number of operands!");
952    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
953    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
954  }
955
956  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
957    assert(N == 1 && "Invalid number of operands!");
958    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
959    assert(CE && "non-constant post-idx-imm8 operand!");
960    int Imm = CE->getValue();
961    bool isAdd = Imm >= 0;
962    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
963    Inst.addOperand(MCOperand::CreateImm(Imm));
964  }
965
966  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
967    assert(N == 2 && "Invalid number of operands!");
968    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
969    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
970  }
971
972  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
973    assert(N == 2 && "Invalid number of operands!");
974    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
975    // The sign, shift type, and shift amount are encoded in a single operand
976    // using the AM2 encoding helpers.
977    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
978    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
979                                     PostIdxReg.ShiftTy);
980    Inst.addOperand(MCOperand::CreateImm(Imm));
981  }
982
983  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
984    assert(N == 1 && "Invalid number of operands!");
985    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
986  }
987
988  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
989    assert(N == 1 && "Invalid number of operands!");
990    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
991  }
992
993  virtual void print(raw_ostream &OS) const;
994
995  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
996    ARMOperand *Op = new ARMOperand(CondCode);
997    Op->CC.Val = CC;
998    Op->StartLoc = S;
999    Op->EndLoc = S;
1000    return Op;
1001  }
1002
1003  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1004    ARMOperand *Op = new ARMOperand(CoprocNum);
1005    Op->Cop.Val = CopVal;
1006    Op->StartLoc = S;
1007    Op->EndLoc = S;
1008    return Op;
1009  }
1010
1011  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1012    ARMOperand *Op = new ARMOperand(CoprocReg);
1013    Op->Cop.Val = CopVal;
1014    Op->StartLoc = S;
1015    Op->EndLoc = S;
1016    return Op;
1017  }
1018
1019  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1020    ARMOperand *Op = new ARMOperand(CCOut);
1021    Op->Reg.RegNum = RegNum;
1022    Op->StartLoc = S;
1023    Op->EndLoc = S;
1024    return Op;
1025  }
1026
1027  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1028    ARMOperand *Op = new ARMOperand(Token);
1029    Op->Tok.Data = Str.data();
1030    Op->Tok.Length = Str.size();
1031    Op->StartLoc = S;
1032    Op->EndLoc = S;
1033    return Op;
1034  }
1035
1036  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1037    ARMOperand *Op = new ARMOperand(Register);
1038    Op->Reg.RegNum = RegNum;
1039    Op->StartLoc = S;
1040    Op->EndLoc = E;
1041    return Op;
1042  }
1043
1044  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1045                                           unsigned SrcReg,
1046                                           unsigned ShiftReg,
1047                                           unsigned ShiftImm,
1048                                           SMLoc S, SMLoc E) {
1049    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1050    Op->RegShiftedReg.ShiftTy = ShTy;
1051    Op->RegShiftedReg.SrcReg = SrcReg;
1052    Op->RegShiftedReg.ShiftReg = ShiftReg;
1053    Op->RegShiftedReg.ShiftImm = ShiftImm;
1054    Op->StartLoc = S;
1055    Op->EndLoc = E;
1056    return Op;
1057  }
1058
1059  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1060                                            unsigned SrcReg,
1061                                            unsigned ShiftImm,
1062                                            SMLoc S, SMLoc E) {
1063    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1064    Op->RegShiftedImm.ShiftTy = ShTy;
1065    Op->RegShiftedImm.SrcReg = SrcReg;
1066    Op->RegShiftedImm.ShiftImm = ShiftImm;
1067    Op->StartLoc = S;
1068    Op->EndLoc = E;
1069    return Op;
1070  }
1071
1072  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1073                                   SMLoc S, SMLoc E) {
1074    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1075    Op->ShifterImm.isASR = isASR;
1076    Op->ShifterImm.Imm = Imm;
1077    Op->StartLoc = S;
1078    Op->EndLoc = E;
1079    return Op;
1080  }
1081
1082  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1083    ARMOperand *Op = new ARMOperand(RotateImmediate);
1084    Op->RotImm.Imm = Imm;
1085    Op->StartLoc = S;
1086    Op->EndLoc = E;
1087    return Op;
1088  }
1089
1090  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1091                                    SMLoc S, SMLoc E) {
1092    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1093    Op->Bitfield.LSB = LSB;
1094    Op->Bitfield.Width = Width;
1095    Op->StartLoc = S;
1096    Op->EndLoc = E;
1097    return Op;
1098  }
1099
1100  static ARMOperand *
1101  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1102                SMLoc StartLoc, SMLoc EndLoc) {
1103    KindTy Kind = RegisterList;
1104
1105    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1106        contains(Regs.front().first))
1107      Kind = DPRRegisterList;
1108    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1109             contains(Regs.front().first))
1110      Kind = SPRRegisterList;
1111
1112    ARMOperand *Op = new ARMOperand(Kind);
1113    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1114           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1115      Op->Registers.push_back(I->first);
1116    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1117    Op->StartLoc = StartLoc;
1118    Op->EndLoc = EndLoc;
1119    return Op;
1120  }
1121
1122  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1123    ARMOperand *Op = new ARMOperand(Immediate);
1124    Op->Imm.Val = Val;
1125    Op->StartLoc = S;
1126    Op->EndLoc = E;
1127    return Op;
1128  }
1129
1130  static ARMOperand *CreateMem(unsigned BaseRegNum,
1131                               const MCConstantExpr *OffsetImm,
1132                               unsigned OffsetRegNum,
1133                               ARM_AM::ShiftOpc ShiftType,
1134                               unsigned ShiftImm,
1135                               bool isNegative,
1136                               SMLoc S, SMLoc E) {
1137    ARMOperand *Op = new ARMOperand(Memory);
1138    Op->Mem.BaseRegNum = BaseRegNum;
1139    Op->Mem.OffsetImm = OffsetImm;
1140    Op->Mem.OffsetRegNum = OffsetRegNum;
1141    Op->Mem.ShiftType = ShiftType;
1142    Op->Mem.ShiftImm = ShiftImm;
1143    Op->Mem.isNegative = isNegative;
1144    Op->StartLoc = S;
1145    Op->EndLoc = E;
1146    return Op;
1147  }
1148
1149  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1150                                      ARM_AM::ShiftOpc ShiftTy,
1151                                      unsigned ShiftImm,
1152                                      SMLoc S, SMLoc E) {
1153    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1154    Op->PostIdxReg.RegNum = RegNum;
1155    Op->PostIdxReg.isAdd = isAdd;
1156    Op->PostIdxReg.ShiftTy = ShiftTy;
1157    Op->PostIdxReg.ShiftImm = ShiftImm;
1158    Op->StartLoc = S;
1159    Op->EndLoc = E;
1160    return Op;
1161  }
1162
1163  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1164    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1165    Op->MBOpt.Val = Opt;
1166    Op->StartLoc = S;
1167    Op->EndLoc = S;
1168    return Op;
1169  }
1170
1171  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1172    ARMOperand *Op = new ARMOperand(ProcIFlags);
1173    Op->IFlags.Val = IFlags;
1174    Op->StartLoc = S;
1175    Op->EndLoc = S;
1176    return Op;
1177  }
1178
1179  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1180    ARMOperand *Op = new ARMOperand(MSRMask);
1181    Op->MMask.Val = MMask;
1182    Op->StartLoc = S;
1183    Op->EndLoc = S;
1184    return Op;
1185  }
1186};
1187
1188} // end anonymous namespace.
1189
1190void ARMOperand::print(raw_ostream &OS) const {
1191  switch (Kind) {
1192  case CondCode:
1193    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1194    break;
1195  case CCOut:
1196    OS << "<ccout " << getReg() << ">";
1197    break;
1198  case CoprocNum:
1199    OS << "<coprocessor number: " << getCoproc() << ">";
1200    break;
1201  case CoprocReg:
1202    OS << "<coprocessor register: " << getCoproc() << ">";
1203    break;
1204  case MSRMask:
1205    OS << "<mask: " << getMSRMask() << ">";
1206    break;
1207  case Immediate:
1208    getImm()->print(OS);
1209    break;
1210  case MemBarrierOpt:
1211    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1212    break;
1213  case Memory:
1214    OS << "<memory "
1215       << " base:" << Mem.BaseRegNum;
1216    OS << ">";
1217    break;
1218  case PostIndexRegister:
1219    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1220       << PostIdxReg.RegNum;
1221    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1222      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1223         << PostIdxReg.ShiftImm;
1224    OS << ">";
1225    break;
1226  case ProcIFlags: {
1227    OS << "<ARM_PROC::";
1228    unsigned IFlags = getProcIFlags();
1229    for (int i=2; i >= 0; --i)
1230      if (IFlags & (1 << i))
1231        OS << ARM_PROC::IFlagsToString(1 << i);
1232    OS << ">";
1233    break;
1234  }
1235  case Register:
1236    OS << "<register " << getReg() << ">";
1237    break;
1238  case ShifterImmediate:
1239    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1240       << " #" << ShifterImm.Imm << ">";
1241    break;
1242  case ShiftedRegister:
1243    OS << "<so_reg_reg "
1244       << RegShiftedReg.SrcReg
1245       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1246       << ", " << RegShiftedReg.ShiftReg << ", "
1247       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1248       << ">";
1249    break;
1250  case ShiftedImmediate:
1251    OS << "<so_reg_imm "
1252       << RegShiftedImm.SrcReg
1253       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1254       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1255       << ">";
1256    break;
1257  case RotateImmediate:
1258    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1259    break;
1260  case BitfieldDescriptor:
1261    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1262       << ", width: " << Bitfield.Width << ">";
1263    break;
1264  case RegisterList:
1265  case DPRRegisterList:
1266  case SPRRegisterList: {
1267    OS << "<register_list ";
1268
1269    const SmallVectorImpl<unsigned> &RegList = getRegList();
1270    for (SmallVectorImpl<unsigned>::const_iterator
1271           I = RegList.begin(), E = RegList.end(); I != E; ) {
1272      OS << *I;
1273      if (++I < E) OS << ", ";
1274    }
1275
1276    OS << ">";
1277    break;
1278  }
1279  case Token:
1280    OS << "'" << getToken() << "'";
1281    break;
1282  }
1283}
1284
1285/// @name Auto-generated Match Functions
1286/// {
1287
1288static unsigned MatchRegisterName(StringRef Name);
1289
1290/// }
1291
1292bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1293                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1294  RegNo = tryParseRegister();
1295
1296  return (RegNo == (unsigned)-1);
1297}
1298
1299/// Try to parse a register name.  The token must be an Identifier when called,
1300/// and if it is a register name the token is eaten and the register number is
1301/// returned.  Otherwise return -1.
1302///
1303int ARMAsmParser::tryParseRegister() {
1304  const AsmToken &Tok = Parser.getTok();
1305  if (Tok.isNot(AsmToken::Identifier)) return -1;
1306
1307  // FIXME: Validate register for the current architecture; we have to do
1308  // validation later, so maybe there is no need for this here.
1309  std::string upperCase = Tok.getString().str();
1310  std::string lowerCase = LowercaseString(upperCase);
1311  unsigned RegNum = MatchRegisterName(lowerCase);
1312  if (!RegNum) {
1313    RegNum = StringSwitch<unsigned>(lowerCase)
1314      .Case("r13", ARM::SP)
1315      .Case("r14", ARM::LR)
1316      .Case("r15", ARM::PC)
1317      .Case("ip", ARM::R12)
1318      .Default(0);
1319  }
1320  if (!RegNum) return -1;
1321
1322  Parser.Lex(); // Eat identifier token.
1323  return RegNum;
1324}
1325
1326// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1327// If a recoverable error occurs, return 1. If an irrecoverable error
1328// occurs, return -1. An irrecoverable error is one where tokens have been
1329// consumed in the process of trying to parse the shifter (i.e., when it is
1330// indeed a shifter operand, but malformed).
1331int ARMAsmParser::tryParseShiftRegister(
1332                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1333  SMLoc S = Parser.getTok().getLoc();
1334  const AsmToken &Tok = Parser.getTok();
1335  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1336
1337  std::string upperCase = Tok.getString().str();
1338  std::string lowerCase = LowercaseString(upperCase);
1339  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1340      .Case("lsl", ARM_AM::lsl)
1341      .Case("lsr", ARM_AM::lsr)
1342      .Case("asr", ARM_AM::asr)
1343      .Case("ror", ARM_AM::ror)
1344      .Case("rrx", ARM_AM::rrx)
1345      .Default(ARM_AM::no_shift);
1346
1347  if (ShiftTy == ARM_AM::no_shift)
1348    return 1;
1349
1350  Parser.Lex(); // Eat the operator.
1351
1352  // The source register for the shift has already been added to the
1353  // operand list, so we need to pop it off and combine it into the shifted
1354  // register operand instead.
1355  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1356  if (!PrevOp->isReg())
1357    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1358  int SrcReg = PrevOp->getReg();
1359  int64_t Imm = 0;
1360  int ShiftReg = 0;
1361  if (ShiftTy == ARM_AM::rrx) {
1362    // RRX Doesn't have an explicit shift amount. The encoder expects
1363    // the shift register to be the same as the source register. Seems odd,
1364    // but OK.
1365    ShiftReg = SrcReg;
1366  } else {
1367    // Figure out if this is shifted by a constant or a register (for non-RRX).
1368    if (Parser.getTok().is(AsmToken::Hash)) {
1369      Parser.Lex(); // Eat hash.
1370      SMLoc ImmLoc = Parser.getTok().getLoc();
1371      const MCExpr *ShiftExpr = 0;
1372      if (getParser().ParseExpression(ShiftExpr)) {
1373        Error(ImmLoc, "invalid immediate shift value");
1374        return -1;
1375      }
1376      // The expression must be evaluatable as an immediate.
1377      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1378      if (!CE) {
1379        Error(ImmLoc, "invalid immediate shift value");
1380        return -1;
1381      }
1382      // Range check the immediate.
1383      // lsl, ror: 0 <= imm <= 31
1384      // lsr, asr: 0 <= imm <= 32
1385      Imm = CE->getValue();
1386      if (Imm < 0 ||
1387          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1388          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1389        Error(ImmLoc, "immediate shift value out of range");
1390        return -1;
1391      }
1392    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1393      ShiftReg = tryParseRegister();
1394      SMLoc L = Parser.getTok().getLoc();
1395      if (ShiftReg == -1) {
1396        Error (L, "expected immediate or register in shift operand");
1397        return -1;
1398      }
1399    } else {
1400      Error (Parser.getTok().getLoc(),
1401                    "expected immediate or register in shift operand");
1402      return -1;
1403    }
1404  }
1405
1406  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1407    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1408                                                         ShiftReg, Imm,
1409                                               S, Parser.getTok().getLoc()));
1410  else
1411    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1412                                               S, Parser.getTok().getLoc()));
1413
1414  return 0;
1415}
1416
1417
1418/// Try to parse a register name.  The token must be an Identifier when called.
1419/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1420/// if there is a "writeback". 'true' if it's not a register.
1421///
1422/// TODO this is likely to change to allow different register types and or to
1423/// parse for a specific register type.
1424bool ARMAsmParser::
1425tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1426  SMLoc S = Parser.getTok().getLoc();
1427  int RegNo = tryParseRegister();
1428  if (RegNo == -1)
1429    return true;
1430
1431  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1432
1433  const AsmToken &ExclaimTok = Parser.getTok();
1434  if (ExclaimTok.is(AsmToken::Exclaim)) {
1435    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1436                                               ExclaimTok.getLoc()));
1437    Parser.Lex(); // Eat exclaim token
1438  }
1439
1440  return false;
1441}
1442
1443/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1444/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1445/// "c5", ...
1446static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1447  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1448  // but efficient.
1449  switch (Name.size()) {
1450  default: break;
1451  case 2:
1452    if (Name[0] != CoprocOp)
1453      return -1;
1454    switch (Name[1]) {
1455    default:  return -1;
1456    case '0': return 0;
1457    case '1': return 1;
1458    case '2': return 2;
1459    case '3': return 3;
1460    case '4': return 4;
1461    case '5': return 5;
1462    case '6': return 6;
1463    case '7': return 7;
1464    case '8': return 8;
1465    case '9': return 9;
1466    }
1467    break;
1468  case 3:
1469    if (Name[0] != CoprocOp || Name[1] != '1')
1470      return -1;
1471    switch (Name[2]) {
1472    default:  return -1;
1473    case '0': return 10;
1474    case '1': return 11;
1475    case '2': return 12;
1476    case '3': return 13;
1477    case '4': return 14;
1478    case '5': return 15;
1479    }
1480    break;
1481  }
1482
1483  return -1;
1484}
1485
1486/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1487/// token must be an Identifier when called, and if it is a coprocessor
1488/// number, the token is eaten and the operand is added to the operand list.
1489ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1490parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1491  SMLoc S = Parser.getTok().getLoc();
1492  const AsmToken &Tok = Parser.getTok();
1493  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1494
1495  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1496  if (Num == -1)
1497    return MatchOperand_NoMatch;
1498
1499  Parser.Lex(); // Eat identifier token.
1500  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1501  return MatchOperand_Success;
1502}
1503
1504/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1505/// token must be an Identifier when called, and if it is a coprocessor
1506/// number, the token is eaten and the operand is added to the operand list.
1507ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1508parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1509  SMLoc S = Parser.getTok().getLoc();
1510  const AsmToken &Tok = Parser.getTok();
1511  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1512
1513  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1514  if (Reg == -1)
1515    return MatchOperand_NoMatch;
1516
1517  Parser.Lex(); // Eat identifier token.
1518  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1519  return MatchOperand_Success;
1520}
1521
1522/// Parse a register list, return it if successful else return null.  The first
1523/// token must be a '{' when called.
1524bool ARMAsmParser::
1525parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1526  assert(Parser.getTok().is(AsmToken::LCurly) &&
1527         "Token is not a Left Curly Brace");
1528  SMLoc S = Parser.getTok().getLoc();
1529
1530  // Read the rest of the registers in the list.
1531  unsigned PrevRegNum = 0;
1532  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1533
1534  do {
1535    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1536    Parser.Lex(); // Eat non-identifier token.
1537
1538    const AsmToken &RegTok = Parser.getTok();
1539    SMLoc RegLoc = RegTok.getLoc();
1540    if (RegTok.isNot(AsmToken::Identifier)) {
1541      Error(RegLoc, "register expected");
1542      return true;
1543    }
1544
1545    int RegNum = tryParseRegister();
1546    if (RegNum == -1) {
1547      Error(RegLoc, "register expected");
1548      return true;
1549    }
1550
1551    if (IsRange) {
1552      int Reg = PrevRegNum;
1553      do {
1554        ++Reg;
1555        Registers.push_back(std::make_pair(Reg, RegLoc));
1556      } while (Reg != RegNum);
1557    } else {
1558      Registers.push_back(std::make_pair(RegNum, RegLoc));
1559    }
1560
1561    PrevRegNum = RegNum;
1562  } while (Parser.getTok().is(AsmToken::Comma) ||
1563           Parser.getTok().is(AsmToken::Minus));
1564
1565  // Process the right curly brace of the list.
1566  const AsmToken &RCurlyTok = Parser.getTok();
1567  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1568    Error(RCurlyTok.getLoc(), "'}' expected");
1569    return true;
1570  }
1571
1572  SMLoc E = RCurlyTok.getLoc();
1573  Parser.Lex(); // Eat right curly brace token.
1574
1575  // Verify the register list.
1576  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1577    RI = Registers.begin(), RE = Registers.end();
1578
1579  unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1580  bool EmittedWarning = false;
1581
1582  DenseMap<unsigned, bool> RegMap;
1583  RegMap[HighRegNum] = true;
1584
1585  for (++RI; RI != RE; ++RI) {
1586    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1587    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1588
1589    if (RegMap[Reg]) {
1590      Error(RegInfo.second, "register duplicated in register list");
1591      return true;
1592    }
1593
1594    if (!EmittedWarning && Reg < HighRegNum)
1595      Warning(RegInfo.second,
1596              "register not in ascending order in register list");
1597
1598    RegMap[Reg] = true;
1599    HighRegNum = std::max(Reg, HighRegNum);
1600  }
1601
1602  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1603  return false;
1604}
1605
1606/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1607ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1608parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1609  SMLoc S = Parser.getTok().getLoc();
1610  const AsmToken &Tok = Parser.getTok();
1611  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1612  StringRef OptStr = Tok.getString();
1613
1614  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1615    .Case("sy",    ARM_MB::SY)
1616    .Case("st",    ARM_MB::ST)
1617    .Case("sh",    ARM_MB::ISH)
1618    .Case("ish",   ARM_MB::ISH)
1619    .Case("shst",  ARM_MB::ISHST)
1620    .Case("ishst", ARM_MB::ISHST)
1621    .Case("nsh",   ARM_MB::NSH)
1622    .Case("un",    ARM_MB::NSH)
1623    .Case("nshst", ARM_MB::NSHST)
1624    .Case("unst",  ARM_MB::NSHST)
1625    .Case("osh",   ARM_MB::OSH)
1626    .Case("oshst", ARM_MB::OSHST)
1627    .Default(~0U);
1628
1629  if (Opt == ~0U)
1630    return MatchOperand_NoMatch;
1631
1632  Parser.Lex(); // Eat identifier token.
1633  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1634  return MatchOperand_Success;
1635}
1636
1637/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1638ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1639parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1640  SMLoc S = Parser.getTok().getLoc();
1641  const AsmToken &Tok = Parser.getTok();
1642  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1643  StringRef IFlagsStr = Tok.getString();
1644
1645  unsigned IFlags = 0;
1646  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1647    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1648    .Case("a", ARM_PROC::A)
1649    .Case("i", ARM_PROC::I)
1650    .Case("f", ARM_PROC::F)
1651    .Default(~0U);
1652
1653    // If some specific iflag is already set, it means that some letter is
1654    // present more than once, this is not acceptable.
1655    if (Flag == ~0U || (IFlags & Flag))
1656      return MatchOperand_NoMatch;
1657
1658    IFlags |= Flag;
1659  }
1660
1661  Parser.Lex(); // Eat identifier token.
1662  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1663  return MatchOperand_Success;
1664}
1665
1666/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1667ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1668parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1669  SMLoc S = Parser.getTok().getLoc();
1670  const AsmToken &Tok = Parser.getTok();
1671  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1672  StringRef Mask = Tok.getString();
1673
1674  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1675  size_t Start = 0, Next = Mask.find('_');
1676  StringRef Flags = "";
1677  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1678  if (Next != StringRef::npos)
1679    Flags = Mask.slice(Next+1, Mask.size());
1680
1681  // FlagsVal contains the complete mask:
1682  // 3-0: Mask
1683  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1684  unsigned FlagsVal = 0;
1685
1686  if (SpecReg == "apsr") {
1687    FlagsVal = StringSwitch<unsigned>(Flags)
1688    .Case("nzcvq",  0x8) // same as CPSR_f
1689    .Case("g",      0x4) // same as CPSR_s
1690    .Case("nzcvqg", 0xc) // same as CPSR_fs
1691    .Default(~0U);
1692
1693    if (FlagsVal == ~0U) {
1694      if (!Flags.empty())
1695        return MatchOperand_NoMatch;
1696      else
1697        FlagsVal = 0; // No flag
1698    }
1699  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1700    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1701      Flags = "fc";
1702    for (int i = 0, e = Flags.size(); i != e; ++i) {
1703      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1704      .Case("c", 1)
1705      .Case("x", 2)
1706      .Case("s", 4)
1707      .Case("f", 8)
1708      .Default(~0U);
1709
1710      // If some specific flag is already set, it means that some letter is
1711      // present more than once, this is not acceptable.
1712      if (FlagsVal == ~0U || (FlagsVal & Flag))
1713        return MatchOperand_NoMatch;
1714      FlagsVal |= Flag;
1715    }
1716  } else // No match for special register.
1717    return MatchOperand_NoMatch;
1718
1719  // Special register without flags are equivalent to "fc" flags.
1720  if (!FlagsVal)
1721    FlagsVal = 0x9;
1722
1723  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1724  if (SpecReg == "spsr")
1725    FlagsVal |= 16;
1726
1727  Parser.Lex(); // Eat identifier token.
1728  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1729  return MatchOperand_Success;
1730}
1731
1732ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1733parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1734            int Low, int High) {
1735  const AsmToken &Tok = Parser.getTok();
1736  if (Tok.isNot(AsmToken::Identifier)) {
1737    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1738    return MatchOperand_ParseFail;
1739  }
1740  StringRef ShiftName = Tok.getString();
1741  std::string LowerOp = LowercaseString(Op);
1742  std::string UpperOp = UppercaseString(Op);
1743  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1744    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1745    return MatchOperand_ParseFail;
1746  }
1747  Parser.Lex(); // Eat shift type token.
1748
1749  // There must be a '#' and a shift amount.
1750  if (Parser.getTok().isNot(AsmToken::Hash)) {
1751    Error(Parser.getTok().getLoc(), "'#' expected");
1752    return MatchOperand_ParseFail;
1753  }
1754  Parser.Lex(); // Eat hash token.
1755
1756  const MCExpr *ShiftAmount;
1757  SMLoc Loc = Parser.getTok().getLoc();
1758  if (getParser().ParseExpression(ShiftAmount)) {
1759    Error(Loc, "illegal expression");
1760    return MatchOperand_ParseFail;
1761  }
1762  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1763  if (!CE) {
1764    Error(Loc, "constant expression expected");
1765    return MatchOperand_ParseFail;
1766  }
1767  int Val = CE->getValue();
1768  if (Val < Low || Val > High) {
1769    Error(Loc, "immediate value out of range");
1770    return MatchOperand_ParseFail;
1771  }
1772
1773  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1774
1775  return MatchOperand_Success;
1776}
1777
1778ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1779parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1780  const AsmToken &Tok = Parser.getTok();
1781  SMLoc S = Tok.getLoc();
1782  if (Tok.isNot(AsmToken::Identifier)) {
1783    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1784    return MatchOperand_ParseFail;
1785  }
1786  int Val = StringSwitch<int>(Tok.getString())
1787    .Case("be", 1)
1788    .Case("le", 0)
1789    .Default(-1);
1790  Parser.Lex(); // Eat the token.
1791
1792  if (Val == -1) {
1793    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1794    return MatchOperand_ParseFail;
1795  }
1796  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1797                                                                  getContext()),
1798                                           S, Parser.getTok().getLoc()));
1799  return MatchOperand_Success;
1800}
1801
1802/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1803/// instructions. Legal values are:
1804///     lsl #n  'n' in [0,31]
1805///     asr #n  'n' in [1,32]
1806///             n == 32 encoded as n == 0.
1807ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1808parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1809  const AsmToken &Tok = Parser.getTok();
1810  SMLoc S = Tok.getLoc();
1811  if (Tok.isNot(AsmToken::Identifier)) {
1812    Error(S, "shift operator 'asr' or 'lsl' expected");
1813    return MatchOperand_ParseFail;
1814  }
1815  StringRef ShiftName = Tok.getString();
1816  bool isASR;
1817  if (ShiftName == "lsl" || ShiftName == "LSL")
1818    isASR = false;
1819  else if (ShiftName == "asr" || ShiftName == "ASR")
1820    isASR = true;
1821  else {
1822    Error(S, "shift operator 'asr' or 'lsl' expected");
1823    return MatchOperand_ParseFail;
1824  }
1825  Parser.Lex(); // Eat the operator.
1826
1827  // A '#' and a shift amount.
1828  if (Parser.getTok().isNot(AsmToken::Hash)) {
1829    Error(Parser.getTok().getLoc(), "'#' expected");
1830    return MatchOperand_ParseFail;
1831  }
1832  Parser.Lex(); // Eat hash token.
1833
1834  const MCExpr *ShiftAmount;
1835  SMLoc E = Parser.getTok().getLoc();
1836  if (getParser().ParseExpression(ShiftAmount)) {
1837    Error(E, "malformed shift expression");
1838    return MatchOperand_ParseFail;
1839  }
1840  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1841  if (!CE) {
1842    Error(E, "shift amount must be an immediate");
1843    return MatchOperand_ParseFail;
1844  }
1845
1846  int64_t Val = CE->getValue();
1847  if (isASR) {
1848    // Shift amount must be in [1,32]
1849    if (Val < 1 || Val > 32) {
1850      Error(E, "'asr' shift amount must be in range [1,32]");
1851      return MatchOperand_ParseFail;
1852    }
1853    // asr #32 encoded as asr #0.
1854    if (Val == 32) Val = 0;
1855  } else {
1856    // Shift amount must be in [1,32]
1857    if (Val < 0 || Val > 31) {
1858      Error(E, "'lsr' shift amount must be in range [0,31]");
1859      return MatchOperand_ParseFail;
1860    }
1861  }
1862
1863  E = Parser.getTok().getLoc();
1864  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1865
1866  return MatchOperand_Success;
1867}
1868
1869/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1870/// of instructions. Legal values are:
1871///     ror #n  'n' in {0, 8, 16, 24}
1872ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1873parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1874  const AsmToken &Tok = Parser.getTok();
1875  SMLoc S = Tok.getLoc();
1876  if (Tok.isNot(AsmToken::Identifier)) {
1877    Error(S, "rotate operator 'ror' expected");
1878    return MatchOperand_ParseFail;
1879  }
1880  StringRef ShiftName = Tok.getString();
1881  if (ShiftName != "ror" && ShiftName != "ROR") {
1882    Error(S, "rotate operator 'ror' expected");
1883    return MatchOperand_ParseFail;
1884  }
1885  Parser.Lex(); // Eat the operator.
1886
1887  // A '#' and a rotate amount.
1888  if (Parser.getTok().isNot(AsmToken::Hash)) {
1889    Error(Parser.getTok().getLoc(), "'#' expected");
1890    return MatchOperand_ParseFail;
1891  }
1892  Parser.Lex(); // Eat hash token.
1893
1894  const MCExpr *ShiftAmount;
1895  SMLoc E = Parser.getTok().getLoc();
1896  if (getParser().ParseExpression(ShiftAmount)) {
1897    Error(E, "malformed rotate expression");
1898    return MatchOperand_ParseFail;
1899  }
1900  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1901  if (!CE) {
1902    Error(E, "rotate amount must be an immediate");
1903    return MatchOperand_ParseFail;
1904  }
1905
1906  int64_t Val = CE->getValue();
1907  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1908  // normally, zero is represented in asm by omitting the rotate operand
1909  // entirely.
1910  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1911    Error(E, "'ror' rotate amount must be 8, 16, or 24");
1912    return MatchOperand_ParseFail;
1913  }
1914
1915  E = Parser.getTok().getLoc();
1916  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
1917
1918  return MatchOperand_Success;
1919}
1920
1921ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1922parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1923  SMLoc S = Parser.getTok().getLoc();
1924  // The bitfield descriptor is really two operands, the LSB and the width.
1925  if (Parser.getTok().isNot(AsmToken::Hash)) {
1926    Error(Parser.getTok().getLoc(), "'#' expected");
1927    return MatchOperand_ParseFail;
1928  }
1929  Parser.Lex(); // Eat hash token.
1930
1931  const MCExpr *LSBExpr;
1932  SMLoc E = Parser.getTok().getLoc();
1933  if (getParser().ParseExpression(LSBExpr)) {
1934    Error(E, "malformed immediate expression");
1935    return MatchOperand_ParseFail;
1936  }
1937  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
1938  if (!CE) {
1939    Error(E, "'lsb' operand must be an immediate");
1940    return MatchOperand_ParseFail;
1941  }
1942
1943  int64_t LSB = CE->getValue();
1944  // The LSB must be in the range [0,31]
1945  if (LSB < 0 || LSB > 31) {
1946    Error(E, "'lsb' operand must be in the range [0,31]");
1947    return MatchOperand_ParseFail;
1948  }
1949  E = Parser.getTok().getLoc();
1950
1951  // Expect another immediate operand.
1952  if (Parser.getTok().isNot(AsmToken::Comma)) {
1953    Error(Parser.getTok().getLoc(), "too few operands");
1954    return MatchOperand_ParseFail;
1955  }
1956  Parser.Lex(); // Eat hash token.
1957  if (Parser.getTok().isNot(AsmToken::Hash)) {
1958    Error(Parser.getTok().getLoc(), "'#' expected");
1959    return MatchOperand_ParseFail;
1960  }
1961  Parser.Lex(); // Eat hash token.
1962
1963  const MCExpr *WidthExpr;
1964  if (getParser().ParseExpression(WidthExpr)) {
1965    Error(E, "malformed immediate expression");
1966    return MatchOperand_ParseFail;
1967  }
1968  CE = dyn_cast<MCConstantExpr>(WidthExpr);
1969  if (!CE) {
1970    Error(E, "'width' operand must be an immediate");
1971    return MatchOperand_ParseFail;
1972  }
1973
1974  int64_t Width = CE->getValue();
1975  // The LSB must be in the range [1,32-lsb]
1976  if (Width < 1 || Width > 32 - LSB) {
1977    Error(E, "'width' operand must be in the range [1,32-lsb]");
1978    return MatchOperand_ParseFail;
1979  }
1980  E = Parser.getTok().getLoc();
1981
1982  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
1983
1984  return MatchOperand_Success;
1985}
1986
1987ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1988parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1989  // Check for a post-index addressing register operand. Specifically:
1990  // postidx_reg := '+' register {, shift}
1991  //              | '-' register {, shift}
1992  //              | register {, shift}
1993
1994  // This method must return MatchOperand_NoMatch without consuming any tokens
1995  // in the case where there is no match, as other alternatives take other
1996  // parse methods.
1997  AsmToken Tok = Parser.getTok();
1998  SMLoc S = Tok.getLoc();
1999  bool haveEaten = false;
2000  bool isAdd = true;
2001  int Reg = -1;
2002  if (Tok.is(AsmToken::Plus)) {
2003    Parser.Lex(); // Eat the '+' token.
2004    haveEaten = true;
2005  } else if (Tok.is(AsmToken::Minus)) {
2006    Parser.Lex(); // Eat the '-' token.
2007    isAdd = false;
2008    haveEaten = true;
2009  }
2010  if (Parser.getTok().is(AsmToken::Identifier))
2011    Reg = tryParseRegister();
2012  if (Reg == -1) {
2013    if (!haveEaten)
2014      return MatchOperand_NoMatch;
2015    Error(Parser.getTok().getLoc(), "register expected");
2016    return MatchOperand_ParseFail;
2017  }
2018  SMLoc E = Parser.getTok().getLoc();
2019
2020  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2021  unsigned ShiftImm = 0;
2022  if (Parser.getTok().is(AsmToken::Comma)) {
2023    Parser.Lex(); // Eat the ','.
2024    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2025      return MatchOperand_ParseFail;
2026  }
2027
2028  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2029                                                  ShiftImm, S, E));
2030
2031  return MatchOperand_Success;
2032}
2033
2034ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2035parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2036  // Check for a post-index addressing register operand. Specifically:
2037  // am3offset := '+' register
2038  //              | '-' register
2039  //              | register
2040  //              | # imm
2041  //              | # + imm
2042  //              | # - imm
2043
2044  // This method must return MatchOperand_NoMatch without consuming any tokens
2045  // in the case where there is no match, as other alternatives take other
2046  // parse methods.
2047  AsmToken Tok = Parser.getTok();
2048  SMLoc S = Tok.getLoc();
2049
2050  // Do immediates first, as we always parse those if we have a '#'.
2051  if (Parser.getTok().is(AsmToken::Hash)) {
2052    Parser.Lex(); // Eat the '#'.
2053    // Explicitly look for a '-', as we need to encode negative zero
2054    // differently.
2055    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2056    const MCExpr *Offset;
2057    if (getParser().ParseExpression(Offset))
2058      return MatchOperand_ParseFail;
2059    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2060    if (!CE) {
2061      Error(S, "constant expression expected");
2062      return MatchOperand_ParseFail;
2063    }
2064    SMLoc E = Tok.getLoc();
2065    // Negative zero is encoded as the flag value INT32_MIN.
2066    int32_t Val = CE->getValue();
2067    if (isNegative && Val == 0)
2068      Val = INT32_MIN;
2069
2070    Operands.push_back(
2071      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2072
2073    return MatchOperand_Success;
2074  }
2075
2076
2077  bool haveEaten = false;
2078  bool isAdd = true;
2079  int Reg = -1;
2080  if (Tok.is(AsmToken::Plus)) {
2081    Parser.Lex(); // Eat the '+' token.
2082    haveEaten = true;
2083  } else if (Tok.is(AsmToken::Minus)) {
2084    Parser.Lex(); // Eat the '-' token.
2085    isAdd = false;
2086    haveEaten = true;
2087  }
2088  if (Parser.getTok().is(AsmToken::Identifier))
2089    Reg = tryParseRegister();
2090  if (Reg == -1) {
2091    if (!haveEaten)
2092      return MatchOperand_NoMatch;
2093    Error(Parser.getTok().getLoc(), "register expected");
2094    return MatchOperand_ParseFail;
2095  }
2096  SMLoc E = Parser.getTok().getLoc();
2097
2098  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2099                                                  0, S, E));
2100
2101  return MatchOperand_Success;
2102}
2103
2104/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2105/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2106/// when they refer multiple MIOperands inside a single one.
2107bool ARMAsmParser::
2108cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2109                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2110  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2111
2112  // Create a writeback register dummy placeholder.
2113  Inst.addOperand(MCOperand::CreateImm(0));
2114
2115  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2116  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2117  return true;
2118}
2119
2120/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2121/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2122/// when they refer multiple MIOperands inside a single one.
2123bool ARMAsmParser::
2124cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2125                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2126  // Create a writeback register dummy placeholder.
2127  Inst.addOperand(MCOperand::CreateImm(0));
2128  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2129  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2130  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2131  return true;
2132}
2133
2134/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2135/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2136/// when they refer multiple MIOperands inside a single one.
2137bool ARMAsmParser::
2138cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2139                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2140  // Create a writeback register dummy placeholder.
2141  Inst.addOperand(MCOperand::CreateImm(0));
2142  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2143  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2144  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2145  return true;
2146}
2147
2148/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2149/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2150/// when they refer multiple MIOperands inside a single one.
2151bool ARMAsmParser::
2152cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2153                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2154  // Create a writeback register dummy placeholder.
2155  Inst.addOperand(MCOperand::CreateImm(0));
2156  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2157  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2158  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2159  return true;
2160}
2161
2162/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2163/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2164/// when they refer multiple MIOperands inside a single one.
2165bool ARMAsmParser::
2166cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2167                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2168  // Rt
2169  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2170  // Create a writeback register dummy placeholder.
2171  Inst.addOperand(MCOperand::CreateImm(0));
2172  // addr
2173  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2174  // offset
2175  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2176  // pred
2177  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2178  return true;
2179}
2180
2181/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2182/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2183/// when they refer multiple MIOperands inside a single one.
2184bool ARMAsmParser::
2185cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2186                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2187  // Rt
2188  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2189  // Create a writeback register dummy placeholder.
2190  Inst.addOperand(MCOperand::CreateImm(0));
2191  // addr
2192  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2193  // offset
2194  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2195  // pred
2196  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2197  return true;
2198}
2199
2200/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2201/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2202/// when they refer multiple MIOperands inside a single one.
2203bool ARMAsmParser::
2204cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2205                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2206  // Create a writeback register dummy placeholder.
2207  Inst.addOperand(MCOperand::CreateImm(0));
2208  // Rt
2209  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2210  // addr
2211  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2212  // offset
2213  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2214  // pred
2215  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2216  return true;
2217}
2218
2219/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2220/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2221/// when they refer multiple MIOperands inside a single one.
2222bool ARMAsmParser::
2223cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2224                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2225  // Create a writeback register dummy placeholder.
2226  Inst.addOperand(MCOperand::CreateImm(0));
2227  // Rt
2228  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2229  // addr
2230  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2231  // offset
2232  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2233  // pred
2234  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2235  return true;
2236}
2237
2238/// cvtLdrdPre - Convert parsed operands to MCInst.
2239/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2240/// when they refer multiple MIOperands inside a single one.
2241bool ARMAsmParser::
2242cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2243           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2244  // Rt, Rt2
2245  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2246  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2247  // Create a writeback register dummy placeholder.
2248  Inst.addOperand(MCOperand::CreateImm(0));
2249  // addr
2250  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2251  // pred
2252  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2253  return true;
2254}
2255
2256/// cvtStrdPre - Convert parsed operands to MCInst.
2257/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2258/// when they refer multiple MIOperands inside a single one.
2259bool ARMAsmParser::
2260cvtStrdPre(MCInst &Inst, unsigned Opcode,
2261           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2262  // Create a writeback register dummy placeholder.
2263  Inst.addOperand(MCOperand::CreateImm(0));
2264  // Rt, Rt2
2265  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2266  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2267  // addr
2268  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2269  // pred
2270  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2271  return true;
2272}
2273
2274/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2275/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2276/// when they refer multiple MIOperands inside a single one.
2277bool ARMAsmParser::
2278cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2279                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2280  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2281  // Create a writeback register dummy placeholder.
2282  Inst.addOperand(MCOperand::CreateImm(0));
2283  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2284  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2285  return true;
2286}
2287
2288
2289/// Parse an ARM memory expression, return false if successful else return true
2290/// or an error.  The first token must be a '[' when called.
2291bool ARMAsmParser::
2292parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2293  SMLoc S, E;
2294  assert(Parser.getTok().is(AsmToken::LBrac) &&
2295         "Token is not a Left Bracket");
2296  S = Parser.getTok().getLoc();
2297  Parser.Lex(); // Eat left bracket token.
2298
2299  const AsmToken &BaseRegTok = Parser.getTok();
2300  int BaseRegNum = tryParseRegister();
2301  if (BaseRegNum == -1)
2302    return Error(BaseRegTok.getLoc(), "register expected");
2303
2304  // The next token must either be a comma or a closing bracket.
2305  const AsmToken &Tok = Parser.getTok();
2306  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2307    return Error(Tok.getLoc(), "malformed memory operand");
2308
2309  if (Tok.is(AsmToken::RBrac)) {
2310    E = Tok.getLoc();
2311    Parser.Lex(); // Eat right bracket token.
2312
2313    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2314                                             0, false, S, E));
2315
2316    return false;
2317  }
2318
2319  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2320  Parser.Lex(); // Eat the comma.
2321
2322  // If we have a '#' it's an immediate offset, else assume it's a register
2323  // offset.
2324  if (Parser.getTok().is(AsmToken::Hash)) {
2325    Parser.Lex(); // Eat the '#'.
2326    E = Parser.getTok().getLoc();
2327
2328    // FIXME: Special case #-0 so we can correctly set the U bit.
2329
2330    const MCExpr *Offset;
2331    if (getParser().ParseExpression(Offset))
2332     return true;
2333
2334    // The expression has to be a constant. Memory references with relocations
2335    // don't come through here, as they use the <label> forms of the relevant
2336    // instructions.
2337    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2338    if (!CE)
2339      return Error (E, "constant expression expected");
2340
2341    // Now we should have the closing ']'
2342    E = Parser.getTok().getLoc();
2343    if (Parser.getTok().isNot(AsmToken::RBrac))
2344      return Error(E, "']' expected");
2345    Parser.Lex(); // Eat right bracket token.
2346
2347    // Don't worry about range checking the value here. That's handled by
2348    // the is*() predicates.
2349    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2350                                             ARM_AM::no_shift, 0, false, S,E));
2351
2352    // If there's a pre-indexing writeback marker, '!', just add it as a token
2353    // operand.
2354    if (Parser.getTok().is(AsmToken::Exclaim)) {
2355      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2356      Parser.Lex(); // Eat the '!'.
2357    }
2358
2359    return false;
2360  }
2361
2362  // The register offset is optionally preceded by a '+' or '-'
2363  bool isNegative = false;
2364  if (Parser.getTok().is(AsmToken::Minus)) {
2365    isNegative = true;
2366    Parser.Lex(); // Eat the '-'.
2367  } else if (Parser.getTok().is(AsmToken::Plus)) {
2368    // Nothing to do.
2369    Parser.Lex(); // Eat the '+'.
2370  }
2371
2372  E = Parser.getTok().getLoc();
2373  int OffsetRegNum = tryParseRegister();
2374  if (OffsetRegNum == -1)
2375    return Error(E, "register expected");
2376
2377  // If there's a shift operator, handle it.
2378  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2379  unsigned ShiftImm = 0;
2380  if (Parser.getTok().is(AsmToken::Comma)) {
2381    Parser.Lex(); // Eat the ','.
2382    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2383      return true;
2384  }
2385
2386  // Now we should have the closing ']'
2387  E = Parser.getTok().getLoc();
2388  if (Parser.getTok().isNot(AsmToken::RBrac))
2389    return Error(E, "']' expected");
2390  Parser.Lex(); // Eat right bracket token.
2391
2392  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2393                                           ShiftType, ShiftImm, isNegative,
2394                                           S, E));
2395
2396  // If there's a pre-indexing writeback marker, '!', just add it as a token
2397  // operand.
2398  if (Parser.getTok().is(AsmToken::Exclaim)) {
2399    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2400    Parser.Lex(); // Eat the '!'.
2401  }
2402
2403  return false;
2404}
2405
2406/// parseMemRegOffsetShift - one of these two:
2407///   ( lsl | lsr | asr | ror ) , # shift_amount
2408///   rrx
2409/// return true if it parses a shift otherwise it returns false.
2410bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2411                                          unsigned &Amount) {
2412  SMLoc Loc = Parser.getTok().getLoc();
2413  const AsmToken &Tok = Parser.getTok();
2414  if (Tok.isNot(AsmToken::Identifier))
2415    return true;
2416  StringRef ShiftName = Tok.getString();
2417  if (ShiftName == "lsl" || ShiftName == "LSL")
2418    St = ARM_AM::lsl;
2419  else if (ShiftName == "lsr" || ShiftName == "LSR")
2420    St = ARM_AM::lsr;
2421  else if (ShiftName == "asr" || ShiftName == "ASR")
2422    St = ARM_AM::asr;
2423  else if (ShiftName == "ror" || ShiftName == "ROR")
2424    St = ARM_AM::ror;
2425  else if (ShiftName == "rrx" || ShiftName == "RRX")
2426    St = ARM_AM::rrx;
2427  else
2428    return Error(Loc, "illegal shift operator");
2429  Parser.Lex(); // Eat shift type token.
2430
2431  // rrx stands alone.
2432  Amount = 0;
2433  if (St != ARM_AM::rrx) {
2434    Loc = Parser.getTok().getLoc();
2435    // A '#' and a shift amount.
2436    const AsmToken &HashTok = Parser.getTok();
2437    if (HashTok.isNot(AsmToken::Hash))
2438      return Error(HashTok.getLoc(), "'#' expected");
2439    Parser.Lex(); // Eat hash token.
2440
2441    const MCExpr *Expr;
2442    if (getParser().ParseExpression(Expr))
2443      return true;
2444    // Range check the immediate.
2445    // lsl, ror: 0 <= imm <= 31
2446    // lsr, asr: 0 <= imm <= 32
2447    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2448    if (!CE)
2449      return Error(Loc, "shift amount must be an immediate");
2450    int64_t Imm = CE->getValue();
2451    if (Imm < 0 ||
2452        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2453        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2454      return Error(Loc, "immediate shift value out of range");
2455    Amount = Imm;
2456  }
2457
2458  return false;
2459}
2460
2461/// Parse a arm instruction operand.  For now this parses the operand regardless
2462/// of the mnemonic.
2463bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2464                                StringRef Mnemonic) {
2465  SMLoc S, E;
2466
2467  // Check if the current operand has a custom associated parser, if so, try to
2468  // custom parse the operand, or fallback to the general approach.
2469  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2470  if (ResTy == MatchOperand_Success)
2471    return false;
2472  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2473  // there was a match, but an error occurred, in which case, just return that
2474  // the operand parsing failed.
2475  if (ResTy == MatchOperand_ParseFail)
2476    return true;
2477
2478  switch (getLexer().getKind()) {
2479  default:
2480    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2481    return true;
2482  case AsmToken::Identifier: {
2483    if (!tryParseRegisterWithWriteBack(Operands))
2484      return false;
2485    int Res = tryParseShiftRegister(Operands);
2486    if (Res == 0) // success
2487      return false;
2488    else if (Res == -1) // irrecoverable error
2489      return true;
2490
2491    // Fall though for the Identifier case that is not a register or a
2492    // special name.
2493  }
2494  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2495  case AsmToken::Dot: {   // . as a branch target
2496    // This was not a register so parse other operands that start with an
2497    // identifier (like labels) as expressions and create them as immediates.
2498    const MCExpr *IdVal;
2499    S = Parser.getTok().getLoc();
2500    if (getParser().ParseExpression(IdVal))
2501      return true;
2502    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2503    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2504    return false;
2505  }
2506  case AsmToken::LBrac:
2507    return parseMemory(Operands);
2508  case AsmToken::LCurly:
2509    return parseRegisterList(Operands);
2510  case AsmToken::Hash:
2511    // #42 -> immediate.
2512    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2513    S = Parser.getTok().getLoc();
2514    Parser.Lex();
2515    const MCExpr *ImmVal;
2516    if (getParser().ParseExpression(ImmVal))
2517      return true;
2518    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2519    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2520    return false;
2521  case AsmToken::Colon: {
2522    // ":lower16:" and ":upper16:" expression prefixes
2523    // FIXME: Check it's an expression prefix,
2524    // e.g. (FOO - :lower16:BAR) isn't legal.
2525    ARMMCExpr::VariantKind RefKind;
2526    if (parsePrefix(RefKind))
2527      return true;
2528
2529    const MCExpr *SubExprVal;
2530    if (getParser().ParseExpression(SubExprVal))
2531      return true;
2532
2533    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2534                                                   getContext());
2535    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2536    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2537    return false;
2538  }
2539  }
2540}
2541
2542// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2543//  :lower16: and :upper16:.
2544bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2545  RefKind = ARMMCExpr::VK_ARM_None;
2546
2547  // :lower16: and :upper16: modifiers
2548  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2549  Parser.Lex(); // Eat ':'
2550
2551  if (getLexer().isNot(AsmToken::Identifier)) {
2552    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2553    return true;
2554  }
2555
2556  StringRef IDVal = Parser.getTok().getIdentifier();
2557  if (IDVal == "lower16") {
2558    RefKind = ARMMCExpr::VK_ARM_LO16;
2559  } else if (IDVal == "upper16") {
2560    RefKind = ARMMCExpr::VK_ARM_HI16;
2561  } else {
2562    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2563    return true;
2564  }
2565  Parser.Lex();
2566
2567  if (getLexer().isNot(AsmToken::Colon)) {
2568    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2569    return true;
2570  }
2571  Parser.Lex(); // Eat the last ':'
2572  return false;
2573}
2574
2575const MCExpr *
2576ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2577                                MCSymbolRefExpr::VariantKind Variant) {
2578  // Recurse over the given expression, rebuilding it to apply the given variant
2579  // to the leftmost symbol.
2580  if (Variant == MCSymbolRefExpr::VK_None)
2581    return E;
2582
2583  switch (E->getKind()) {
2584  case MCExpr::Target:
2585    llvm_unreachable("Can't handle target expr yet");
2586  case MCExpr::Constant:
2587    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2588
2589  case MCExpr::SymbolRef: {
2590    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2591
2592    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2593      return 0;
2594
2595    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2596  }
2597
2598  case MCExpr::Unary:
2599    llvm_unreachable("Can't handle unary expressions yet");
2600
2601  case MCExpr::Binary: {
2602    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2603    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2604    const MCExpr *RHS = BE->getRHS();
2605    if (!LHS)
2606      return 0;
2607
2608    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2609  }
2610  }
2611
2612  assert(0 && "Invalid expression kind!");
2613  return 0;
2614}
2615
2616/// \brief Given a mnemonic, split out possible predication code and carry
2617/// setting letters to form a canonical mnemonic and flags.
2618//
2619// FIXME: Would be nice to autogen this.
2620StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2621                                      unsigned &PredicationCode,
2622                                      bool &CarrySetting,
2623                                      unsigned &ProcessorIMod) {
2624  PredicationCode = ARMCC::AL;
2625  CarrySetting = false;
2626  ProcessorIMod = 0;
2627
2628  // Ignore some mnemonics we know aren't predicated forms.
2629  //
2630  // FIXME: Would be nice to autogen this.
2631  if ((Mnemonic == "movs" && isThumb()) ||
2632      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2633      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2634      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2635      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2636      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2637      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2638      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2639    return Mnemonic;
2640
2641  // First, split out any predication code. Ignore mnemonics we know aren't
2642  // predicated but do have a carry-set and so weren't caught above.
2643  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2644      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2645      Mnemonic != "umlals" && Mnemonic != "umulls") {
2646    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2647      .Case("eq", ARMCC::EQ)
2648      .Case("ne", ARMCC::NE)
2649      .Case("hs", ARMCC::HS)
2650      .Case("cs", ARMCC::HS)
2651      .Case("lo", ARMCC::LO)
2652      .Case("cc", ARMCC::LO)
2653      .Case("mi", ARMCC::MI)
2654      .Case("pl", ARMCC::PL)
2655      .Case("vs", ARMCC::VS)
2656      .Case("vc", ARMCC::VC)
2657      .Case("hi", ARMCC::HI)
2658      .Case("ls", ARMCC::LS)
2659      .Case("ge", ARMCC::GE)
2660      .Case("lt", ARMCC::LT)
2661      .Case("gt", ARMCC::GT)
2662      .Case("le", ARMCC::LE)
2663      .Case("al", ARMCC::AL)
2664      .Default(~0U);
2665    if (CC != ~0U) {
2666      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2667      PredicationCode = CC;
2668    }
2669  }
2670
2671  // Next, determine if we have a carry setting bit. We explicitly ignore all
2672  // the instructions we know end in 's'.
2673  if (Mnemonic.endswith("s") &&
2674      !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2675        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2676        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2677        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2678        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2679        (Mnemonic == "movs" && isThumb()))) {
2680    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2681    CarrySetting = true;
2682  }
2683
2684  // The "cps" instruction can have a interrupt mode operand which is glued into
2685  // the mnemonic. Check if this is the case, split it and parse the imod op
2686  if (Mnemonic.startswith("cps")) {
2687    // Split out any imod code.
2688    unsigned IMod =
2689      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2690      .Case("ie", ARM_PROC::IE)
2691      .Case("id", ARM_PROC::ID)
2692      .Default(~0U);
2693    if (IMod != ~0U) {
2694      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2695      ProcessorIMod = IMod;
2696    }
2697  }
2698
2699  return Mnemonic;
2700}
2701
2702/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2703/// inclusion of carry set or predication code operands.
2704//
2705// FIXME: It would be nice to autogen this.
2706void ARMAsmParser::
2707getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2708                      bool &CanAcceptPredicationCode) {
2709  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2710      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2711      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2712      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2713      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2714      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2715      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2716      Mnemonic == "eor" || Mnemonic == "smlal" ||
2717      (Mnemonic == "mov" && !isThumbOne())) {
2718    CanAcceptCarrySet = true;
2719  } else {
2720    CanAcceptCarrySet = false;
2721  }
2722
2723  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2724      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2725      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2726      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2727      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2728      Mnemonic == "setend" ||
2729      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2730      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2731        && !isThumb()) ||
2732      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2733    CanAcceptPredicationCode = false;
2734  } else {
2735    CanAcceptPredicationCode = true;
2736  }
2737
2738  if (isThumb())
2739    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2740        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2741      CanAcceptPredicationCode = false;
2742}
2743
2744bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2745                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2746
2747  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2748  // another does not. Specifically, the MOVW instruction does not. So we
2749  // special case it here and remove the defaulted (non-setting) cc_out
2750  // operand if that's the instruction we're trying to match.
2751  //
2752  // We do this as post-processing of the explicit operands rather than just
2753  // conditionally adding the cc_out in the first place because we need
2754  // to check the type of the parsed immediate operand.
2755  if (Mnemonic == "mov" && Operands.size() > 4 &&
2756      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2757      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2758      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2759    return true;
2760
2761  // Register-register 'add' for thumb does not have a cc_out operand
2762  // when there are only two register operands.
2763  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2764      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2765      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2766      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2767    return true;
2768
2769  return false;
2770}
2771
2772/// Parse an arm instruction mnemonic followed by its operands.
2773bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2774                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2775  // Create the leading tokens for the mnemonic, split by '.' characters.
2776  size_t Start = 0, Next = Name.find('.');
2777  StringRef Mnemonic = Name.slice(Start, Next);
2778
2779  // Split out the predication code and carry setting flag from the mnemonic.
2780  unsigned PredicationCode;
2781  unsigned ProcessorIMod;
2782  bool CarrySetting;
2783  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2784                           ProcessorIMod);
2785
2786  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2787
2788  // FIXME: This is all a pretty gross hack. We should automatically handle
2789  // optional operands like this via tblgen.
2790
2791  // Next, add the CCOut and ConditionCode operands, if needed.
2792  //
2793  // For mnemonics which can ever incorporate a carry setting bit or predication
2794  // code, our matching model involves us always generating CCOut and
2795  // ConditionCode operands to match the mnemonic "as written" and then we let
2796  // the matcher deal with finding the right instruction or generating an
2797  // appropriate error.
2798  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2799  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2800
2801  // If we had a carry-set on an instruction that can't do that, issue an
2802  // error.
2803  if (!CanAcceptCarrySet && CarrySetting) {
2804    Parser.EatToEndOfStatement();
2805    return Error(NameLoc, "instruction '" + Mnemonic +
2806                 "' can not set flags, but 's' suffix specified");
2807  }
2808  // If we had a predication code on an instruction that can't do that, issue an
2809  // error.
2810  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2811    Parser.EatToEndOfStatement();
2812    return Error(NameLoc, "instruction '" + Mnemonic +
2813                 "' is not predicable, but condition code specified");
2814  }
2815
2816  // Add the carry setting operand, if necessary.
2817  //
2818  // FIXME: It would be awesome if we could somehow invent a location such that
2819  // match errors on this operand would print a nice diagnostic about how the
2820  // 's' character in the mnemonic resulted in a CCOut operand.
2821  if (CanAcceptCarrySet)
2822    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2823                                               NameLoc));
2824
2825  // Add the predication code operand, if necessary.
2826  if (CanAcceptPredicationCode) {
2827    Operands.push_back(ARMOperand::CreateCondCode(
2828                         ARMCC::CondCodes(PredicationCode), NameLoc));
2829  }
2830
2831  // Add the processor imod operand, if necessary.
2832  if (ProcessorIMod) {
2833    Operands.push_back(ARMOperand::CreateImm(
2834          MCConstantExpr::Create(ProcessorIMod, getContext()),
2835                                 NameLoc, NameLoc));
2836  } else {
2837    // This mnemonic can't ever accept a imod, but the user wrote
2838    // one (or misspelled another mnemonic).
2839
2840    // FIXME: Issue a nice error.
2841  }
2842
2843  // Add the remaining tokens in the mnemonic.
2844  while (Next != StringRef::npos) {
2845    Start = Next;
2846    Next = Name.find('.', Start + 1);
2847    StringRef ExtraToken = Name.slice(Start, Next);
2848
2849    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2850  }
2851
2852  // Read the remaining operands.
2853  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2854    // Read the first operand.
2855    if (parseOperand(Operands, Mnemonic)) {
2856      Parser.EatToEndOfStatement();
2857      return true;
2858    }
2859
2860    while (getLexer().is(AsmToken::Comma)) {
2861      Parser.Lex();  // Eat the comma.
2862
2863      // Parse and remember the operand.
2864      if (parseOperand(Operands, Mnemonic)) {
2865        Parser.EatToEndOfStatement();
2866        return true;
2867      }
2868    }
2869  }
2870
2871  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2872    Parser.EatToEndOfStatement();
2873    return TokError("unexpected token in argument list");
2874  }
2875
2876  Parser.Lex(); // Consume the EndOfStatement
2877
2878  // Some instructions, mostly Thumb, have forms for the same mnemonic that
2879  // do and don't have a cc_out optional-def operand. With some spot-checks
2880  // of the operand list, we can figure out which variant we're trying to
2881  // parse and adjust accordingly before actually matching. Reason number
2882  // #317 the table driven matcher doesn't fit well with the ARM instruction
2883  // set.
2884  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
2885    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2886    Operands.erase(Operands.begin() + 1);
2887    delete Op;
2888  }
2889
2890  // ARM mode 'blx' need special handling, as the register operand version
2891  // is predicable, but the label operand version is not. So, we can't rely
2892  // on the Mnemonic based checking to correctly figure out when to put
2893  // a CondCode operand in the list. If we're trying to match the label
2894  // version, remove the CondCode operand here.
2895  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
2896      static_cast<ARMOperand*>(Operands[2])->isImm()) {
2897    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2898    Operands.erase(Operands.begin() + 1);
2899    delete Op;
2900  }
2901
2902  // The vector-compare-to-zero instructions have a literal token "#0" at
2903  // the end that comes to here as an immediate operand. Convert it to a
2904  // token to play nicely with the matcher.
2905  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
2906      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
2907      static_cast<ARMOperand*>(Operands[5])->isImm()) {
2908    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
2909    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
2910    if (CE && CE->getValue() == 0) {
2911      Operands.erase(Operands.begin() + 5);
2912      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
2913      delete Op;
2914    }
2915  }
2916  return false;
2917}
2918
2919// Validate context-sensitive operand constraints.
2920// FIXME: We would really like to be able to tablegen'erate this.
2921bool ARMAsmParser::
2922validateInstruction(MCInst &Inst,
2923                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2924  switch (Inst.getOpcode()) {
2925  case ARM::LDRD:
2926  case ARM::LDRD_PRE:
2927  case ARM::LDRD_POST:
2928  case ARM::LDREXD: {
2929    // Rt2 must be Rt + 1.
2930    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2931    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2932    if (Rt2 != Rt + 1)
2933      return Error(Operands[3]->getStartLoc(),
2934                   "destination operands must be sequential");
2935    return false;
2936  }
2937  case ARM::STRD: {
2938    // Rt2 must be Rt + 1.
2939    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2940    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2941    if (Rt2 != Rt + 1)
2942      return Error(Operands[3]->getStartLoc(),
2943                   "source operands must be sequential");
2944    return false;
2945  }
2946  case ARM::STRD_PRE:
2947  case ARM::STRD_POST:
2948  case ARM::STREXD: {
2949    // Rt2 must be Rt + 1.
2950    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2951    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
2952    if (Rt2 != Rt + 1)
2953      return Error(Operands[3]->getStartLoc(),
2954                   "source operands must be sequential");
2955    return false;
2956  }
2957  case ARM::SBFX:
2958  case ARM::UBFX: {
2959    // width must be in range [1, 32-lsb]
2960    unsigned lsb = Inst.getOperand(2).getImm();
2961    unsigned widthm1 = Inst.getOperand(3).getImm();
2962    if (widthm1 >= 32 - lsb)
2963      return Error(Operands[5]->getStartLoc(),
2964                   "bitfield width must be in range [1,32-lsb]");
2965  }
2966  }
2967
2968  return false;
2969}
2970
2971void ARMAsmParser::
2972processInstruction(MCInst &Inst,
2973                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2974  switch (Inst.getOpcode()) {
2975  case ARM::LDMIA_UPD:
2976    // If this is a load of a single register via a 'pop', then we should use
2977    // a post-indexed LDR instruction instead, per the ARM ARM.
2978    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
2979        Inst.getNumOperands() == 5) {
2980      MCInst TmpInst;
2981      TmpInst.setOpcode(ARM::LDR_POST_IMM);
2982      TmpInst.addOperand(Inst.getOperand(4)); // Rt
2983      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
2984      TmpInst.addOperand(Inst.getOperand(1)); // Rn
2985      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
2986      TmpInst.addOperand(MCOperand::CreateImm(4));
2987      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
2988      TmpInst.addOperand(Inst.getOperand(3));
2989      Inst = TmpInst;
2990    }
2991    break;
2992  case ARM::STMDB_UPD:
2993    // If this is a store of a single register via a 'push', then we should use
2994    // a pre-indexed STR instruction instead, per the ARM ARM.
2995    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
2996        Inst.getNumOperands() == 5) {
2997      MCInst TmpInst;
2998      TmpInst.setOpcode(ARM::STR_PRE_IMM);
2999      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3000      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3001      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3002      TmpInst.addOperand(MCOperand::CreateImm(-4));
3003      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3004      TmpInst.addOperand(Inst.getOperand(3));
3005      Inst = TmpInst;
3006    }
3007    break;
3008  }
3009}
3010
3011// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3012// the ARMInsts array) instead. Getting that here requires awkward
3013// API changes, though. Better way?
3014namespace llvm {
3015extern MCInstrDesc ARMInsts[];
3016}
3017static MCInstrDesc &getInstDesc(unsigned Opcode) {
3018  return ARMInsts[Opcode];
3019}
3020
3021unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3022  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3023  // suffix depending on whether they're in an IT block or not.
3024  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3025  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3026    assert(MCID.hasOptionalDef() &&
3027           "optionally flag setting instruction missing optional def operand");
3028    assert(MCID.NumOperands == Inst.getNumOperands() &&
3029           "operand count mismatch!");
3030    // Find the optional-def operand (cc_out).
3031    unsigned OpNo;
3032    for (OpNo = 0;
3033         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3034         ++OpNo)
3035      ;
3036    // If we're parsing Thumb1, reject it completely.
3037    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3038      return Match_MnemonicFail;
3039    // If we're parsing Thumb2, which form is legal depends on whether we're
3040    // in an IT block.
3041    // FIXME: We don't yet do IT blocks, so just always consider it to be
3042    // that we aren't in one until we do.
3043    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3044      return Match_RequiresITBlock;
3045  }
3046  return Match_Success;
3047}
3048
3049bool ARMAsmParser::
3050MatchAndEmitInstruction(SMLoc IDLoc,
3051                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3052                        MCStreamer &Out) {
3053  MCInst Inst;
3054  unsigned ErrorInfo;
3055  unsigned MatchResult;
3056  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3057  switch (MatchResult) {
3058  default: break;
3059  case Match_Success:
3060    // Context sensitive operand constraints aren't handled by the matcher,
3061    // so check them here.
3062    if (validateInstruction(Inst, Operands))
3063      return true;
3064
3065    // Some instructions need post-processing to, for example, tweak which
3066    // encoding is selected.
3067    processInstruction(Inst, Operands);
3068
3069    Out.EmitInstruction(Inst);
3070    return false;
3071  case Match_MissingFeature:
3072    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3073    return true;
3074  case Match_InvalidOperand: {
3075    SMLoc ErrorLoc = IDLoc;
3076    if (ErrorInfo != ~0U) {
3077      if (ErrorInfo >= Operands.size())
3078        return Error(IDLoc, "too few operands for instruction");
3079
3080      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3081      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3082    }
3083
3084    return Error(ErrorLoc, "invalid operand for instruction");
3085  }
3086  case Match_MnemonicFail:
3087    return Error(IDLoc, "invalid instruction");
3088  case Match_ConversionFail:
3089    return Error(IDLoc, "unable to convert operands to instruction");
3090  case Match_RequiresITBlock:
3091    return Error(IDLoc, "instruction only valid inside IT block");
3092  }
3093
3094  llvm_unreachable("Implement any new match types added!");
3095  return true;
3096}
3097
3098/// parseDirective parses the arm specific directives
3099bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3100  StringRef IDVal = DirectiveID.getIdentifier();
3101  if (IDVal == ".word")
3102    return parseDirectiveWord(4, DirectiveID.getLoc());
3103  else if (IDVal == ".thumb")
3104    return parseDirectiveThumb(DirectiveID.getLoc());
3105  else if (IDVal == ".thumb_func")
3106    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3107  else if (IDVal == ".code")
3108    return parseDirectiveCode(DirectiveID.getLoc());
3109  else if (IDVal == ".syntax")
3110    return parseDirectiveSyntax(DirectiveID.getLoc());
3111  return true;
3112}
3113
3114/// parseDirectiveWord
3115///  ::= .word [ expression (, expression)* ]
3116bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3117  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3118    for (;;) {
3119      const MCExpr *Value;
3120      if (getParser().ParseExpression(Value))
3121        return true;
3122
3123      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3124
3125      if (getLexer().is(AsmToken::EndOfStatement))
3126        break;
3127
3128      // FIXME: Improve diagnostic.
3129      if (getLexer().isNot(AsmToken::Comma))
3130        return Error(L, "unexpected token in directive");
3131      Parser.Lex();
3132    }
3133  }
3134
3135  Parser.Lex();
3136  return false;
3137}
3138
3139/// parseDirectiveThumb
3140///  ::= .thumb
3141bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3142  if (getLexer().isNot(AsmToken::EndOfStatement))
3143    return Error(L, "unexpected token in directive");
3144  Parser.Lex();
3145
3146  // TODO: set thumb mode
3147  // TODO: tell the MC streamer the mode
3148  // getParser().getStreamer().Emit???();
3149  return false;
3150}
3151
3152/// parseDirectiveThumbFunc
3153///  ::= .thumbfunc symbol_name
3154bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3155  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3156  bool isMachO = MAI.hasSubsectionsViaSymbols();
3157  StringRef Name;
3158
3159  // Darwin asm has function name after .thumb_func direction
3160  // ELF doesn't
3161  if (isMachO) {
3162    const AsmToken &Tok = Parser.getTok();
3163    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3164      return Error(L, "unexpected token in .thumb_func directive");
3165    Name = Tok.getString();
3166    Parser.Lex(); // Consume the identifier token.
3167  }
3168
3169  if (getLexer().isNot(AsmToken::EndOfStatement))
3170    return Error(L, "unexpected token in directive");
3171  Parser.Lex();
3172
3173  // FIXME: assuming function name will be the line following .thumb_func
3174  if (!isMachO) {
3175    Name = Parser.getTok().getString();
3176  }
3177
3178  // Mark symbol as a thumb symbol.
3179  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3180  getParser().getStreamer().EmitThumbFunc(Func);
3181  return false;
3182}
3183
3184/// parseDirectiveSyntax
3185///  ::= .syntax unified | divided
3186bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3187  const AsmToken &Tok = Parser.getTok();
3188  if (Tok.isNot(AsmToken::Identifier))
3189    return Error(L, "unexpected token in .syntax directive");
3190  StringRef Mode = Tok.getString();
3191  if (Mode == "unified" || Mode == "UNIFIED")
3192    Parser.Lex();
3193  else if (Mode == "divided" || Mode == "DIVIDED")
3194    return Error(L, "'.syntax divided' arm asssembly not supported");
3195  else
3196    return Error(L, "unrecognized syntax mode in .syntax directive");
3197
3198  if (getLexer().isNot(AsmToken::EndOfStatement))
3199    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3200  Parser.Lex();
3201
3202  // TODO tell the MC streamer the mode
3203  // getParser().getStreamer().Emit???();
3204  return false;
3205}
3206
3207/// parseDirectiveCode
3208///  ::= .code 16 | 32
3209bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3210  const AsmToken &Tok = Parser.getTok();
3211  if (Tok.isNot(AsmToken::Integer))
3212    return Error(L, "unexpected token in .code directive");
3213  int64_t Val = Parser.getTok().getIntVal();
3214  if (Val == 16)
3215    Parser.Lex();
3216  else if (Val == 32)
3217    Parser.Lex();
3218  else
3219    return Error(L, "invalid operand to .code directive");
3220
3221  if (getLexer().isNot(AsmToken::EndOfStatement))
3222    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3223  Parser.Lex();
3224
3225  if (Val == 16) {
3226    if (!isThumb()) {
3227      SwitchMode();
3228      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3229    }
3230  } else {
3231    if (isThumb()) {
3232      SwitchMode();
3233      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3234    }
3235  }
3236
3237  return false;
3238}
3239
3240extern "C" void LLVMInitializeARMAsmLexer();
3241
3242/// Force static initialization.
3243extern "C" void LLVMInitializeARMAsmParser() {
3244  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3245  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3246  LLVMInitializeARMAsmLexer();
3247}
3248
3249#define GET_REGISTER_MATCHER
3250#define GET_MATCHER_IMPLEMENTATION
3251#include "ARMGenAsmMatcher.inc"
3252