ARMAsmParser.cpp revision 48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/MCTargetAsmParser.h"
24#include "llvm/Target/TargetRegistry.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/ADT/OwningPtr.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringExtras.h"
31#include "llvm/ADT/StringSwitch.h"
32#include "llvm/ADT/Twine.h"
33
34using namespace llvm;
35
36namespace {
37
38class ARMOperand;
39
40class ARMAsmParser : public MCTargetAsmParser {
41  MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43
44  MCAsmParser &getParser() const { return Parser; }
45  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
46
47  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
49
50  int tryParseRegister();
51  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57  const MCExpr *applyPrefixToExpr(const MCExpr *E,
58                                  MCSymbolRefExpr::VariantKind Variant);
59
60
61  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62                              unsigned &ShiftAmount);
63  bool parseDirectiveWord(unsigned Size, SMLoc L);
64  bool parseDirectiveThumb(SMLoc L);
65  bool parseDirectiveThumbFunc(SMLoc L);
66  bool parseDirectiveCode(SMLoc L);
67  bool parseDirectiveSyntax(SMLoc L);
68
69  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70                          bool &CarrySetting, unsigned &ProcessorIMod);
71  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72                             bool &CanAcceptPredicationCode);
73
74  bool isThumb() const {
75    // FIXME: Can tablegen auto-generate this?
76    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
77  }
78  bool isThumbOne() const {
79    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
80  }
81  bool isThumbTwo() const {
82    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
83  }
84  bool hasV6Ops() const {
85    return STI.getFeatureBits() & ARM::HasV6Ops;
86  }
87  void SwitchMode() {
88    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
89    setAvailableFeatures(FB);
90  }
91
92  /// @name Auto-generated Match Functions
93  /// {
94
95#define GET_ASSEMBLER_HEADER
96#include "ARMGenAsmMatcher.inc"
97
98  /// }
99
100  OperandMatchResultTy parseCoprocNumOperand(
101    SmallVectorImpl<MCParsedAsmOperand*>&);
102  OperandMatchResultTy parseCoprocRegOperand(
103    SmallVectorImpl<MCParsedAsmOperand*>&);
104  OperandMatchResultTy parseMemBarrierOptOperand(
105    SmallVectorImpl<MCParsedAsmOperand*>&);
106  OperandMatchResultTy parseProcIFlagsOperand(
107    SmallVectorImpl<MCParsedAsmOperand*>&);
108  OperandMatchResultTy parseMSRMaskOperand(
109    SmallVectorImpl<MCParsedAsmOperand*>&);
110  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
111                                   StringRef Op, int Low, int High);
112  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
113    return parsePKHImm(O, "lsl", 0, 31);
114  }
115  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
116    return parsePKHImm(O, "asr", 1, 32);
117  }
118  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
119  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
120  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
122  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
123  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
124
125  // Asm Match Converter Methods
126  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
127                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
128  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
129                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
130  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
131                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
132  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
133                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
134  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
135                             const SmallVectorImpl<MCParsedAsmOperand*> &);
136  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
137                             const SmallVectorImpl<MCParsedAsmOperand*> &);
138  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139                             const SmallVectorImpl<MCParsedAsmOperand*> &);
140  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141                             const SmallVectorImpl<MCParsedAsmOperand*> &);
142  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
143                  const SmallVectorImpl<MCParsedAsmOperand*> &);
144  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
145                  const SmallVectorImpl<MCParsedAsmOperand*> &);
146  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
147                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
148
149  bool validateInstruction(MCInst &Inst,
150                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
151  void processInstruction(MCInst &Inst,
152                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
153  bool shouldOmitCCOutOperand(StringRef Mnemonic,
154                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
155
156public:
157  enum ARMMatchResultTy {
158    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
159    Match_RequiresV6,
160    Match_RequiresThumb2
161  };
162
163  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
164    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
165    MCAsmParserExtension::Initialize(_Parser);
166
167    // Initialize the set of available features.
168    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
169  }
170
171  // Implementation of the MCTargetAsmParser interface:
172  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
173  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
174                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
175  bool ParseDirective(AsmToken DirectiveID);
176
177  unsigned checkTargetMatchPredicate(MCInst &Inst);
178
179  bool MatchAndEmitInstruction(SMLoc IDLoc,
180                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
181                               MCStreamer &Out);
182};
183} // end anonymous namespace
184
185namespace {
186
187/// ARMOperand - Instances of this class represent a parsed ARM machine
188/// instruction.
189class ARMOperand : public MCParsedAsmOperand {
190  enum KindTy {
191    CondCode,
192    CCOut,
193    CoprocNum,
194    CoprocReg,
195    Immediate,
196    MemBarrierOpt,
197    Memory,
198    PostIndexRegister,
199    MSRMask,
200    ProcIFlags,
201    Register,
202    RegisterList,
203    DPRRegisterList,
204    SPRRegisterList,
205    ShiftedRegister,
206    ShiftedImmediate,
207    ShifterImmediate,
208    RotateImmediate,
209    BitfieldDescriptor,
210    Token
211  } Kind;
212
213  SMLoc StartLoc, EndLoc;
214  SmallVector<unsigned, 8> Registers;
215
216  union {
217    struct {
218      ARMCC::CondCodes Val;
219    } CC;
220
221    struct {
222      ARM_MB::MemBOpt Val;
223    } MBOpt;
224
225    struct {
226      unsigned Val;
227    } Cop;
228
229    struct {
230      ARM_PROC::IFlags Val;
231    } IFlags;
232
233    struct {
234      unsigned Val;
235    } MMask;
236
237    struct {
238      const char *Data;
239      unsigned Length;
240    } Tok;
241
242    struct {
243      unsigned RegNum;
244    } Reg;
245
246    struct {
247      const MCExpr *Val;
248    } Imm;
249
250    /// Combined record for all forms of ARM address expressions.
251    struct {
252      unsigned BaseRegNum;
253      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
254      // was specified.
255      const MCConstantExpr *OffsetImm;  // Offset immediate value
256      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
257      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
258      unsigned ShiftImm;      // shift for OffsetReg.
259      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
260    } Mem;
261
262    struct {
263      unsigned RegNum;
264      bool isAdd;
265      ARM_AM::ShiftOpc ShiftTy;
266      unsigned ShiftImm;
267    } PostIdxReg;
268
269    struct {
270      bool isASR;
271      unsigned Imm;
272    } ShifterImm;
273    struct {
274      ARM_AM::ShiftOpc ShiftTy;
275      unsigned SrcReg;
276      unsigned ShiftReg;
277      unsigned ShiftImm;
278    } RegShiftedReg;
279    struct {
280      ARM_AM::ShiftOpc ShiftTy;
281      unsigned SrcReg;
282      unsigned ShiftImm;
283    } RegShiftedImm;
284    struct {
285      unsigned Imm;
286    } RotImm;
287    struct {
288      unsigned LSB;
289      unsigned Width;
290    } Bitfield;
291  };
292
293  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
294public:
295  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
296    Kind = o.Kind;
297    StartLoc = o.StartLoc;
298    EndLoc = o.EndLoc;
299    switch (Kind) {
300    case CondCode:
301      CC = o.CC;
302      break;
303    case Token:
304      Tok = o.Tok;
305      break;
306    case CCOut:
307    case Register:
308      Reg = o.Reg;
309      break;
310    case RegisterList:
311    case DPRRegisterList:
312    case SPRRegisterList:
313      Registers = o.Registers;
314      break;
315    case CoprocNum:
316    case CoprocReg:
317      Cop = o.Cop;
318      break;
319    case Immediate:
320      Imm = o.Imm;
321      break;
322    case MemBarrierOpt:
323      MBOpt = o.MBOpt;
324      break;
325    case Memory:
326      Mem = o.Mem;
327      break;
328    case PostIndexRegister:
329      PostIdxReg = o.PostIdxReg;
330      break;
331    case MSRMask:
332      MMask = o.MMask;
333      break;
334    case ProcIFlags:
335      IFlags = o.IFlags;
336      break;
337    case ShifterImmediate:
338      ShifterImm = o.ShifterImm;
339      break;
340    case ShiftedRegister:
341      RegShiftedReg = o.RegShiftedReg;
342      break;
343    case ShiftedImmediate:
344      RegShiftedImm = o.RegShiftedImm;
345      break;
346    case RotateImmediate:
347      RotImm = o.RotImm;
348      break;
349    case BitfieldDescriptor:
350      Bitfield = o.Bitfield;
351      break;
352    }
353  }
354
355  /// getStartLoc - Get the location of the first token of this operand.
356  SMLoc getStartLoc() const { return StartLoc; }
357  /// getEndLoc - Get the location of the last token of this operand.
358  SMLoc getEndLoc() const { return EndLoc; }
359
360  ARMCC::CondCodes getCondCode() const {
361    assert(Kind == CondCode && "Invalid access!");
362    return CC.Val;
363  }
364
365  unsigned getCoproc() const {
366    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
367    return Cop.Val;
368  }
369
370  StringRef getToken() const {
371    assert(Kind == Token && "Invalid access!");
372    return StringRef(Tok.Data, Tok.Length);
373  }
374
375  unsigned getReg() const {
376    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
377    return Reg.RegNum;
378  }
379
380  const SmallVectorImpl<unsigned> &getRegList() const {
381    assert((Kind == RegisterList || Kind == DPRRegisterList ||
382            Kind == SPRRegisterList) && "Invalid access!");
383    return Registers;
384  }
385
386  const MCExpr *getImm() const {
387    assert(Kind == Immediate && "Invalid access!");
388    return Imm.Val;
389  }
390
391  ARM_MB::MemBOpt getMemBarrierOpt() const {
392    assert(Kind == MemBarrierOpt && "Invalid access!");
393    return MBOpt.Val;
394  }
395
396  ARM_PROC::IFlags getProcIFlags() const {
397    assert(Kind == ProcIFlags && "Invalid access!");
398    return IFlags.Val;
399  }
400
401  unsigned getMSRMask() const {
402    assert(Kind == MSRMask && "Invalid access!");
403    return MMask.Val;
404  }
405
406  bool isCoprocNum() const { return Kind == CoprocNum; }
407  bool isCoprocReg() const { return Kind == CoprocReg; }
408  bool isCondCode() const { return Kind == CondCode; }
409  bool isCCOut() const { return Kind == CCOut; }
410  bool isImm() const { return Kind == Immediate; }
411  bool isImm0_255() const {
412    if (Kind != Immediate)
413      return false;
414    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
415    if (!CE) return false;
416    int64_t Value = CE->getValue();
417    return Value >= 0 && Value < 256;
418  }
419  bool isImm0_7() const {
420    if (Kind != Immediate)
421      return false;
422    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
423    if (!CE) return false;
424    int64_t Value = CE->getValue();
425    return Value >= 0 && Value < 8;
426  }
427  bool isImm0_15() const {
428    if (Kind != Immediate)
429      return false;
430    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
431    if (!CE) return false;
432    int64_t Value = CE->getValue();
433    return Value >= 0 && Value < 16;
434  }
435  bool isImm0_31() const {
436    if (Kind != Immediate)
437      return false;
438    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
439    if (!CE) return false;
440    int64_t Value = CE->getValue();
441    return Value >= 0 && Value < 32;
442  }
443  bool isImm1_16() const {
444    if (Kind != Immediate)
445      return false;
446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
447    if (!CE) return false;
448    int64_t Value = CE->getValue();
449    return Value > 0 && Value < 17;
450  }
451  bool isImm1_32() const {
452    if (Kind != Immediate)
453      return false;
454    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
455    if (!CE) return false;
456    int64_t Value = CE->getValue();
457    return Value > 0 && Value < 33;
458  }
459  bool isImm0_65535() const {
460    if (Kind != Immediate)
461      return false;
462    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
463    if (!CE) return false;
464    int64_t Value = CE->getValue();
465    return Value >= 0 && Value < 65536;
466  }
467  bool isImm0_65535Expr() const {
468    if (Kind != Immediate)
469      return false;
470    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
471    // If it's not a constant expression, it'll generate a fixup and be
472    // handled later.
473    if (!CE) return true;
474    int64_t Value = CE->getValue();
475    return Value >= 0 && Value < 65536;
476  }
477  bool isImm24bit() const {
478    if (Kind != Immediate)
479      return false;
480    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
481    if (!CE) return false;
482    int64_t Value = CE->getValue();
483    return Value >= 0 && Value <= 0xffffff;
484  }
485  bool isImmThumbSR() const {
486    if (Kind != Immediate)
487      return false;
488    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
489    if (!CE) return false;
490    int64_t Value = CE->getValue();
491    return Value > 0 && Value < 33;
492  }
493  bool isPKHLSLImm() const {
494    if (Kind != Immediate)
495      return false;
496    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
497    if (!CE) return false;
498    int64_t Value = CE->getValue();
499    return Value >= 0 && Value < 32;
500  }
501  bool isPKHASRImm() const {
502    if (Kind != Immediate)
503      return false;
504    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
505    if (!CE) return false;
506    int64_t Value = CE->getValue();
507    return Value > 0 && Value <= 32;
508  }
509  bool isARMSOImm() const {
510    if (Kind != Immediate)
511      return false;
512    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
513    if (!CE) return false;
514    int64_t Value = CE->getValue();
515    return ARM_AM::getSOImmVal(Value) != -1;
516  }
517  bool isT2SOImm() const {
518    if (Kind != Immediate)
519      return false;
520    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
521    if (!CE) return false;
522    int64_t Value = CE->getValue();
523    return ARM_AM::getT2SOImmVal(Value) != -1;
524  }
525  bool isSetEndImm() const {
526    if (Kind != Immediate)
527      return false;
528    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
529    if (!CE) return false;
530    int64_t Value = CE->getValue();
531    return Value == 1 || Value == 0;
532  }
533  bool isReg() const { return Kind == Register; }
534  bool isRegList() const { return Kind == RegisterList; }
535  bool isDPRRegList() const { return Kind == DPRRegisterList; }
536  bool isSPRRegList() const { return Kind == SPRRegisterList; }
537  bool isToken() const { return Kind == Token; }
538  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
539  bool isMemory() const { return Kind == Memory; }
540  bool isShifterImm() const { return Kind == ShifterImmediate; }
541  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
542  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
543  bool isRotImm() const { return Kind == RotateImmediate; }
544  bool isBitfield() const { return Kind == BitfieldDescriptor; }
545  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
546  bool isPostIdxReg() const {
547    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
548  }
549  bool isMemNoOffset() const {
550    if (Kind != Memory)
551      return false;
552    // No offset of any kind.
553    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
554  }
555  bool isAddrMode2() const {
556    if (Kind != Memory)
557      return false;
558    // Check for register offset.
559    if (Mem.OffsetRegNum) return true;
560    // Immediate offset in range [-4095, 4095].
561    if (!Mem.OffsetImm) return true;
562    int64_t Val = Mem.OffsetImm->getValue();
563    return Val > -4096 && Val < 4096;
564  }
565  bool isAM2OffsetImm() const {
566    if (Kind != Immediate)
567      return false;
568    // Immediate offset in range [-4095, 4095].
569    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570    if (!CE) return false;
571    int64_t Val = CE->getValue();
572    return Val > -4096 && Val < 4096;
573  }
574  bool isAddrMode3() const {
575    if (Kind != Memory)
576      return false;
577    // No shifts are legal for AM3.
578    if (Mem.ShiftType != ARM_AM::no_shift) return false;
579    // Check for register offset.
580    if (Mem.OffsetRegNum) return true;
581    // Immediate offset in range [-255, 255].
582    if (!Mem.OffsetImm) return true;
583    int64_t Val = Mem.OffsetImm->getValue();
584    return Val > -256 && Val < 256;
585  }
586  bool isAM3Offset() const {
587    if (Kind != Immediate && Kind != PostIndexRegister)
588      return false;
589    if (Kind == PostIndexRegister)
590      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
591    // Immediate offset in range [-255, 255].
592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593    if (!CE) return false;
594    int64_t Val = CE->getValue();
595    // Special case, #-0 is INT32_MIN.
596    return (Val > -256 && Val < 256) || Val == INT32_MIN;
597  }
598  bool isAddrMode5() const {
599    if (Kind != Memory)
600      return false;
601    // Check for register offset.
602    if (Mem.OffsetRegNum) return false;
603    // Immediate offset in range [-1020, 1020] and a multiple of 4.
604    if (!Mem.OffsetImm) return true;
605    int64_t Val = Mem.OffsetImm->getValue();
606    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
607  }
608  bool isMemRegOffset() const {
609    if (Kind != Memory || !Mem.OffsetRegNum)
610      return false;
611    return true;
612  }
613  bool isMemThumbRR() const {
614    // Thumb reg+reg addressing is simple. Just two registers, a base and
615    // an offset. No shifts, negations or any other complicating factors.
616    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
617        Mem.ShiftType != ARM_AM::no_shift)
618      return false;
619    return isARMLowRegister(Mem.BaseRegNum) &&
620      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
621  }
622  bool isMemThumbRIs4() const {
623    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
624        !isARMLowRegister(Mem.BaseRegNum))
625      return false;
626    // Immediate offset, multiple of 4 in range [0, 124].
627    if (!Mem.OffsetImm) return true;
628    int64_t Val = Mem.OffsetImm->getValue();
629    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
630  }
631  bool isMemThumbRIs1() const {
632    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
633        !isARMLowRegister(Mem.BaseRegNum))
634      return false;
635    // Immediate offset in range [0, 31].
636    if (!Mem.OffsetImm) return true;
637    int64_t Val = Mem.OffsetImm->getValue();
638    return Val >= 0 && Val <= 31;
639  }
640  bool isMemThumbSPI() const {
641    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
642      return false;
643    // Immediate offset, multiple of 4 in range [0, 1020].
644    if (!Mem.OffsetImm) return true;
645    int64_t Val = Mem.OffsetImm->getValue();
646    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
647  }
648  bool isMemImm8Offset() const {
649    if (Kind != Memory || Mem.OffsetRegNum != 0)
650      return false;
651    // Immediate offset in range [-255, 255].
652    if (!Mem.OffsetImm) return true;
653    int64_t Val = Mem.OffsetImm->getValue();
654    return Val > -256 && Val < 256;
655  }
656  bool isMemImm12Offset() const {
657    // If we have an immediate that's not a constant, treat it as a label
658    // reference needing a fixup. If it is a constant, it's something else
659    // and we reject it.
660    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
661      return true;
662
663    if (Kind != Memory || Mem.OffsetRegNum != 0)
664      return false;
665    // Immediate offset in range [-4095, 4095].
666    if (!Mem.OffsetImm) return true;
667    int64_t Val = Mem.OffsetImm->getValue();
668    return Val > -4096 && Val < 4096;
669  }
670  bool isPostIdxImm8() const {
671    if (Kind != Immediate)
672      return false;
673    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674    if (!CE) return false;
675    int64_t Val = CE->getValue();
676    return Val > -256 && Val < 256;
677  }
678
679  bool isMSRMask() const { return Kind == MSRMask; }
680  bool isProcIFlags() const { return Kind == ProcIFlags; }
681
682  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
683    // Add as immediates when possible.  Null MCExpr = 0.
684    if (Expr == 0)
685      Inst.addOperand(MCOperand::CreateImm(0));
686    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
687      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
688    else
689      Inst.addOperand(MCOperand::CreateExpr(Expr));
690  }
691
692  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
693    assert(N == 2 && "Invalid number of operands!");
694    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
695    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
696    Inst.addOperand(MCOperand::CreateReg(RegNum));
697  }
698
699  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
700    assert(N == 1 && "Invalid number of operands!");
701    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
702  }
703
704  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
705    assert(N == 1 && "Invalid number of operands!");
706    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
707  }
708
709  void addCCOutOperands(MCInst &Inst, unsigned N) const {
710    assert(N == 1 && "Invalid number of operands!");
711    Inst.addOperand(MCOperand::CreateReg(getReg()));
712  }
713
714  void addRegOperands(MCInst &Inst, unsigned N) const {
715    assert(N == 1 && "Invalid number of operands!");
716    Inst.addOperand(MCOperand::CreateReg(getReg()));
717  }
718
719  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
720    assert(N == 3 && "Invalid number of operands!");
721    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
722    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
723    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
724    Inst.addOperand(MCOperand::CreateImm(
725      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
726  }
727
728  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
729    assert(N == 2 && "Invalid number of operands!");
730    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
731    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
732    Inst.addOperand(MCOperand::CreateImm(
733      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
734  }
735
736
737  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
738    assert(N == 1 && "Invalid number of operands!");
739    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
740                                         ShifterImm.Imm));
741  }
742
743  void addRegListOperands(MCInst &Inst, unsigned N) const {
744    assert(N == 1 && "Invalid number of operands!");
745    const SmallVectorImpl<unsigned> &RegList = getRegList();
746    for (SmallVectorImpl<unsigned>::const_iterator
747           I = RegList.begin(), E = RegList.end(); I != E; ++I)
748      Inst.addOperand(MCOperand::CreateReg(*I));
749  }
750
751  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
752    addRegListOperands(Inst, N);
753  }
754
755  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
756    addRegListOperands(Inst, N);
757  }
758
759  void addRotImmOperands(MCInst &Inst, unsigned N) const {
760    assert(N == 1 && "Invalid number of operands!");
761    // Encoded as val>>3. The printer handles display as 8, 16, 24.
762    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
763  }
764
765  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
766    assert(N == 1 && "Invalid number of operands!");
767    // Munge the lsb/width into a bitfield mask.
768    unsigned lsb = Bitfield.LSB;
769    unsigned width = Bitfield.Width;
770    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
771    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
772                      (32 - (lsb + width)));
773    Inst.addOperand(MCOperand::CreateImm(Mask));
774  }
775
776  void addImmOperands(MCInst &Inst, unsigned N) const {
777    assert(N == 1 && "Invalid number of operands!");
778    addExpr(Inst, getImm());
779  }
780
781  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
782    assert(N == 1 && "Invalid number of operands!");
783    addExpr(Inst, getImm());
784  }
785
786  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
787    assert(N == 1 && "Invalid number of operands!");
788    addExpr(Inst, getImm());
789  }
790
791  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
792    assert(N == 1 && "Invalid number of operands!");
793    addExpr(Inst, getImm());
794  }
795
796  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
797    assert(N == 1 && "Invalid number of operands!");
798    addExpr(Inst, getImm());
799  }
800
801  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
802    assert(N == 1 && "Invalid number of operands!");
803    // The constant encodes as the immediate-1, and we store in the instruction
804    // the bits as encoded, so subtract off one here.
805    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
806    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
807  }
808
809  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
810    assert(N == 1 && "Invalid number of operands!");
811    // The constant encodes as the immediate-1, and we store in the instruction
812    // the bits as encoded, so subtract off one here.
813    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
815  }
816
817  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
818    assert(N == 1 && "Invalid number of operands!");
819    addExpr(Inst, getImm());
820  }
821
822  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
823    assert(N == 1 && "Invalid number of operands!");
824    addExpr(Inst, getImm());
825  }
826
827  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
828    assert(N == 1 && "Invalid number of operands!");
829    addExpr(Inst, getImm());
830  }
831
832  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
833    assert(N == 1 && "Invalid number of operands!");
834    // The constant encodes as the immediate, except for 32, which encodes as
835    // zero.
836    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
837    unsigned Imm = CE->getValue();
838    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
839  }
840
841  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
842    assert(N == 1 && "Invalid number of operands!");
843    addExpr(Inst, getImm());
844  }
845
846  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
847    assert(N == 1 && "Invalid number of operands!");
848    // An ASR value of 32 encodes as 0, so that's how we want to add it to
849    // the instruction as well.
850    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
851    int Val = CE->getValue();
852    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
853  }
854
855  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
856    assert(N == 1 && "Invalid number of operands!");
857    addExpr(Inst, getImm());
858  }
859
860  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
861    assert(N == 1 && "Invalid number of operands!");
862    addExpr(Inst, getImm());
863  }
864
865  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
866    assert(N == 1 && "Invalid number of operands!");
867    addExpr(Inst, getImm());
868  }
869
870  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
871    assert(N == 1 && "Invalid number of operands!");
872    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
873  }
874
875  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
876    assert(N == 1 && "Invalid number of operands!");
877    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
878  }
879
880  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
881    assert(N == 3 && "Invalid number of operands!");
882    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
883    if (!Mem.OffsetRegNum) {
884      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
885      // Special case for #-0
886      if (Val == INT32_MIN) Val = 0;
887      if (Val < 0) Val = -Val;
888      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
889    } else {
890      // For register offset, we encode the shift type and negation flag
891      // here.
892      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
893                              Mem.ShiftImm, Mem.ShiftType);
894    }
895    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
896    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
897    Inst.addOperand(MCOperand::CreateImm(Val));
898  }
899
900  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
901    assert(N == 2 && "Invalid number of operands!");
902    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
903    assert(CE && "non-constant AM2OffsetImm operand!");
904    int32_t Val = CE->getValue();
905    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
906    // Special case for #-0
907    if (Val == INT32_MIN) Val = 0;
908    if (Val < 0) Val = -Val;
909    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
910    Inst.addOperand(MCOperand::CreateReg(0));
911    Inst.addOperand(MCOperand::CreateImm(Val));
912  }
913
914  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
915    assert(N == 3 && "Invalid number of operands!");
916    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
917    if (!Mem.OffsetRegNum) {
918      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
919      // Special case for #-0
920      if (Val == INT32_MIN) Val = 0;
921      if (Val < 0) Val = -Val;
922      Val = ARM_AM::getAM3Opc(AddSub, Val);
923    } else {
924      // For register offset, we encode the shift type and negation flag
925      // here.
926      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
927    }
928    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
929    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
930    Inst.addOperand(MCOperand::CreateImm(Val));
931  }
932
933  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
934    assert(N == 2 && "Invalid number of operands!");
935    if (Kind == PostIndexRegister) {
936      int32_t Val =
937        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
938      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
939      Inst.addOperand(MCOperand::CreateImm(Val));
940      return;
941    }
942
943    // Constant offset.
944    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
945    int32_t Val = CE->getValue();
946    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
947    // Special case for #-0
948    if (Val == INT32_MIN) Val = 0;
949    if (Val < 0) Val = -Val;
950    Val = ARM_AM::getAM3Opc(AddSub, Val);
951    Inst.addOperand(MCOperand::CreateReg(0));
952    Inst.addOperand(MCOperand::CreateImm(Val));
953  }
954
955  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
956    assert(N == 2 && "Invalid number of operands!");
957    // The lower two bits are always zero and as such are not encoded.
958    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
959    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
960    // Special case for #-0
961    if (Val == INT32_MIN) Val = 0;
962    if (Val < 0) Val = -Val;
963    Val = ARM_AM::getAM5Opc(AddSub, Val);
964    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
965    Inst.addOperand(MCOperand::CreateImm(Val));
966  }
967
968  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
969    assert(N == 2 && "Invalid number of operands!");
970    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
971    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
972    Inst.addOperand(MCOperand::CreateImm(Val));
973  }
974
975  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
976    assert(N == 2 && "Invalid number of operands!");
977    // If this is an immediate, it's a label reference.
978    if (Kind == Immediate) {
979      addExpr(Inst, getImm());
980      Inst.addOperand(MCOperand::CreateImm(0));
981      return;
982    }
983
984    // Otherwise, it's a normal memory reg+offset.
985    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
986    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
987    Inst.addOperand(MCOperand::CreateImm(Val));
988  }
989
990  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
991    assert(N == 3 && "Invalid number of operands!");
992    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
993                                     Mem.ShiftImm, Mem.ShiftType);
994    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
995    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
996    Inst.addOperand(MCOperand::CreateImm(Val));
997  }
998
999  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1000    assert(N == 2 && "Invalid number of operands!");
1001    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1002    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1003  }
1004
1005  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1006    assert(N == 2 && "Invalid number of operands!");
1007    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1008    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1009    Inst.addOperand(MCOperand::CreateImm(Val));
1010  }
1011
1012  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1013    assert(N == 2 && "Invalid number of operands!");
1014    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1015    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1016    Inst.addOperand(MCOperand::CreateImm(Val));
1017  }
1018
1019  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1020    assert(N == 2 && "Invalid number of operands!");
1021    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1022    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1023    Inst.addOperand(MCOperand::CreateImm(Val));
1024  }
1025
1026  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1027    assert(N == 1 && "Invalid number of operands!");
1028    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029    assert(CE && "non-constant post-idx-imm8 operand!");
1030    int Imm = CE->getValue();
1031    bool isAdd = Imm >= 0;
1032    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1033    Inst.addOperand(MCOperand::CreateImm(Imm));
1034  }
1035
1036  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1037    assert(N == 2 && "Invalid number of operands!");
1038    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1039    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1040  }
1041
1042  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1043    assert(N == 2 && "Invalid number of operands!");
1044    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1045    // The sign, shift type, and shift amount are encoded in a single operand
1046    // using the AM2 encoding helpers.
1047    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1048    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1049                                     PostIdxReg.ShiftTy);
1050    Inst.addOperand(MCOperand::CreateImm(Imm));
1051  }
1052
1053  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1054    assert(N == 1 && "Invalid number of operands!");
1055    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1056  }
1057
1058  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1059    assert(N == 1 && "Invalid number of operands!");
1060    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1061  }
1062
1063  virtual void print(raw_ostream &OS) const;
1064
1065  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1066    ARMOperand *Op = new ARMOperand(CondCode);
1067    Op->CC.Val = CC;
1068    Op->StartLoc = S;
1069    Op->EndLoc = S;
1070    return Op;
1071  }
1072
1073  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1074    ARMOperand *Op = new ARMOperand(CoprocNum);
1075    Op->Cop.Val = CopVal;
1076    Op->StartLoc = S;
1077    Op->EndLoc = S;
1078    return Op;
1079  }
1080
1081  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1082    ARMOperand *Op = new ARMOperand(CoprocReg);
1083    Op->Cop.Val = CopVal;
1084    Op->StartLoc = S;
1085    Op->EndLoc = S;
1086    return Op;
1087  }
1088
1089  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1090    ARMOperand *Op = new ARMOperand(CCOut);
1091    Op->Reg.RegNum = RegNum;
1092    Op->StartLoc = S;
1093    Op->EndLoc = S;
1094    return Op;
1095  }
1096
1097  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1098    ARMOperand *Op = new ARMOperand(Token);
1099    Op->Tok.Data = Str.data();
1100    Op->Tok.Length = Str.size();
1101    Op->StartLoc = S;
1102    Op->EndLoc = S;
1103    return Op;
1104  }
1105
1106  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1107    ARMOperand *Op = new ARMOperand(Register);
1108    Op->Reg.RegNum = RegNum;
1109    Op->StartLoc = S;
1110    Op->EndLoc = E;
1111    return Op;
1112  }
1113
1114  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1115                                           unsigned SrcReg,
1116                                           unsigned ShiftReg,
1117                                           unsigned ShiftImm,
1118                                           SMLoc S, SMLoc E) {
1119    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1120    Op->RegShiftedReg.ShiftTy = ShTy;
1121    Op->RegShiftedReg.SrcReg = SrcReg;
1122    Op->RegShiftedReg.ShiftReg = ShiftReg;
1123    Op->RegShiftedReg.ShiftImm = ShiftImm;
1124    Op->StartLoc = S;
1125    Op->EndLoc = E;
1126    return Op;
1127  }
1128
1129  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1130                                            unsigned SrcReg,
1131                                            unsigned ShiftImm,
1132                                            SMLoc S, SMLoc E) {
1133    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1134    Op->RegShiftedImm.ShiftTy = ShTy;
1135    Op->RegShiftedImm.SrcReg = SrcReg;
1136    Op->RegShiftedImm.ShiftImm = ShiftImm;
1137    Op->StartLoc = S;
1138    Op->EndLoc = E;
1139    return Op;
1140  }
1141
1142  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1143                                   SMLoc S, SMLoc E) {
1144    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1145    Op->ShifterImm.isASR = isASR;
1146    Op->ShifterImm.Imm = Imm;
1147    Op->StartLoc = S;
1148    Op->EndLoc = E;
1149    return Op;
1150  }
1151
1152  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1153    ARMOperand *Op = new ARMOperand(RotateImmediate);
1154    Op->RotImm.Imm = Imm;
1155    Op->StartLoc = S;
1156    Op->EndLoc = E;
1157    return Op;
1158  }
1159
1160  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1161                                    SMLoc S, SMLoc E) {
1162    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1163    Op->Bitfield.LSB = LSB;
1164    Op->Bitfield.Width = Width;
1165    Op->StartLoc = S;
1166    Op->EndLoc = E;
1167    return Op;
1168  }
1169
1170  static ARMOperand *
1171  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1172                SMLoc StartLoc, SMLoc EndLoc) {
1173    KindTy Kind = RegisterList;
1174
1175    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1176        contains(Regs.front().first))
1177      Kind = DPRRegisterList;
1178    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1179             contains(Regs.front().first))
1180      Kind = SPRRegisterList;
1181
1182    ARMOperand *Op = new ARMOperand(Kind);
1183    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1184           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1185      Op->Registers.push_back(I->first);
1186    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1187    Op->StartLoc = StartLoc;
1188    Op->EndLoc = EndLoc;
1189    return Op;
1190  }
1191
1192  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1193    ARMOperand *Op = new ARMOperand(Immediate);
1194    Op->Imm.Val = Val;
1195    Op->StartLoc = S;
1196    Op->EndLoc = E;
1197    return Op;
1198  }
1199
1200  static ARMOperand *CreateMem(unsigned BaseRegNum,
1201                               const MCConstantExpr *OffsetImm,
1202                               unsigned OffsetRegNum,
1203                               ARM_AM::ShiftOpc ShiftType,
1204                               unsigned ShiftImm,
1205                               bool isNegative,
1206                               SMLoc S, SMLoc E) {
1207    ARMOperand *Op = new ARMOperand(Memory);
1208    Op->Mem.BaseRegNum = BaseRegNum;
1209    Op->Mem.OffsetImm = OffsetImm;
1210    Op->Mem.OffsetRegNum = OffsetRegNum;
1211    Op->Mem.ShiftType = ShiftType;
1212    Op->Mem.ShiftImm = ShiftImm;
1213    Op->Mem.isNegative = isNegative;
1214    Op->StartLoc = S;
1215    Op->EndLoc = E;
1216    return Op;
1217  }
1218
1219  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1220                                      ARM_AM::ShiftOpc ShiftTy,
1221                                      unsigned ShiftImm,
1222                                      SMLoc S, SMLoc E) {
1223    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1224    Op->PostIdxReg.RegNum = RegNum;
1225    Op->PostIdxReg.isAdd = isAdd;
1226    Op->PostIdxReg.ShiftTy = ShiftTy;
1227    Op->PostIdxReg.ShiftImm = ShiftImm;
1228    Op->StartLoc = S;
1229    Op->EndLoc = E;
1230    return Op;
1231  }
1232
1233  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1234    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1235    Op->MBOpt.Val = Opt;
1236    Op->StartLoc = S;
1237    Op->EndLoc = S;
1238    return Op;
1239  }
1240
1241  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1242    ARMOperand *Op = new ARMOperand(ProcIFlags);
1243    Op->IFlags.Val = IFlags;
1244    Op->StartLoc = S;
1245    Op->EndLoc = S;
1246    return Op;
1247  }
1248
1249  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1250    ARMOperand *Op = new ARMOperand(MSRMask);
1251    Op->MMask.Val = MMask;
1252    Op->StartLoc = S;
1253    Op->EndLoc = S;
1254    return Op;
1255  }
1256};
1257
1258} // end anonymous namespace.
1259
1260void ARMOperand::print(raw_ostream &OS) const {
1261  switch (Kind) {
1262  case CondCode:
1263    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1264    break;
1265  case CCOut:
1266    OS << "<ccout " << getReg() << ">";
1267    break;
1268  case CoprocNum:
1269    OS << "<coprocessor number: " << getCoproc() << ">";
1270    break;
1271  case CoprocReg:
1272    OS << "<coprocessor register: " << getCoproc() << ">";
1273    break;
1274  case MSRMask:
1275    OS << "<mask: " << getMSRMask() << ">";
1276    break;
1277  case Immediate:
1278    getImm()->print(OS);
1279    break;
1280  case MemBarrierOpt:
1281    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1282    break;
1283  case Memory:
1284    OS << "<memory "
1285       << " base:" << Mem.BaseRegNum;
1286    OS << ">";
1287    break;
1288  case PostIndexRegister:
1289    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1290       << PostIdxReg.RegNum;
1291    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1292      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1293         << PostIdxReg.ShiftImm;
1294    OS << ">";
1295    break;
1296  case ProcIFlags: {
1297    OS << "<ARM_PROC::";
1298    unsigned IFlags = getProcIFlags();
1299    for (int i=2; i >= 0; --i)
1300      if (IFlags & (1 << i))
1301        OS << ARM_PROC::IFlagsToString(1 << i);
1302    OS << ">";
1303    break;
1304  }
1305  case Register:
1306    OS << "<register " << getReg() << ">";
1307    break;
1308  case ShifterImmediate:
1309    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1310       << " #" << ShifterImm.Imm << ">";
1311    break;
1312  case ShiftedRegister:
1313    OS << "<so_reg_reg "
1314       << RegShiftedReg.SrcReg
1315       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1316       << ", " << RegShiftedReg.ShiftReg << ", "
1317       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1318       << ">";
1319    break;
1320  case ShiftedImmediate:
1321    OS << "<so_reg_imm "
1322       << RegShiftedImm.SrcReg
1323       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1324       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1325       << ">";
1326    break;
1327  case RotateImmediate:
1328    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1329    break;
1330  case BitfieldDescriptor:
1331    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1332       << ", width: " << Bitfield.Width << ">";
1333    break;
1334  case RegisterList:
1335  case DPRRegisterList:
1336  case SPRRegisterList: {
1337    OS << "<register_list ";
1338
1339    const SmallVectorImpl<unsigned> &RegList = getRegList();
1340    for (SmallVectorImpl<unsigned>::const_iterator
1341           I = RegList.begin(), E = RegList.end(); I != E; ) {
1342      OS << *I;
1343      if (++I < E) OS << ", ";
1344    }
1345
1346    OS << ">";
1347    break;
1348  }
1349  case Token:
1350    OS << "'" << getToken() << "'";
1351    break;
1352  }
1353}
1354
1355/// @name Auto-generated Match Functions
1356/// {
1357
1358static unsigned MatchRegisterName(StringRef Name);
1359
1360/// }
1361
1362bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1363                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1364  RegNo = tryParseRegister();
1365
1366  return (RegNo == (unsigned)-1);
1367}
1368
1369/// Try to parse a register name.  The token must be an Identifier when called,
1370/// and if it is a register name the token is eaten and the register number is
1371/// returned.  Otherwise return -1.
1372///
1373int ARMAsmParser::tryParseRegister() {
1374  const AsmToken &Tok = Parser.getTok();
1375  if (Tok.isNot(AsmToken::Identifier)) return -1;
1376
1377  // FIXME: Validate register for the current architecture; we have to do
1378  // validation later, so maybe there is no need for this here.
1379  std::string upperCase = Tok.getString().str();
1380  std::string lowerCase = LowercaseString(upperCase);
1381  unsigned RegNum = MatchRegisterName(lowerCase);
1382  if (!RegNum) {
1383    RegNum = StringSwitch<unsigned>(lowerCase)
1384      .Case("r13", ARM::SP)
1385      .Case("r14", ARM::LR)
1386      .Case("r15", ARM::PC)
1387      .Case("ip", ARM::R12)
1388      .Default(0);
1389  }
1390  if (!RegNum) return -1;
1391
1392  Parser.Lex(); // Eat identifier token.
1393  return RegNum;
1394}
1395
1396// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1397// If a recoverable error occurs, return 1. If an irrecoverable error
1398// occurs, return -1. An irrecoverable error is one where tokens have been
1399// consumed in the process of trying to parse the shifter (i.e., when it is
1400// indeed a shifter operand, but malformed).
1401int ARMAsmParser::tryParseShiftRegister(
1402                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1403  SMLoc S = Parser.getTok().getLoc();
1404  const AsmToken &Tok = Parser.getTok();
1405  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1406
1407  std::string upperCase = Tok.getString().str();
1408  std::string lowerCase = LowercaseString(upperCase);
1409  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1410      .Case("lsl", ARM_AM::lsl)
1411      .Case("lsr", ARM_AM::lsr)
1412      .Case("asr", ARM_AM::asr)
1413      .Case("ror", ARM_AM::ror)
1414      .Case("rrx", ARM_AM::rrx)
1415      .Default(ARM_AM::no_shift);
1416
1417  if (ShiftTy == ARM_AM::no_shift)
1418    return 1;
1419
1420  Parser.Lex(); // Eat the operator.
1421
1422  // The source register for the shift has already been added to the
1423  // operand list, so we need to pop it off and combine it into the shifted
1424  // register operand instead.
1425  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1426  if (!PrevOp->isReg())
1427    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1428  int SrcReg = PrevOp->getReg();
1429  int64_t Imm = 0;
1430  int ShiftReg = 0;
1431  if (ShiftTy == ARM_AM::rrx) {
1432    // RRX Doesn't have an explicit shift amount. The encoder expects
1433    // the shift register to be the same as the source register. Seems odd,
1434    // but OK.
1435    ShiftReg = SrcReg;
1436  } else {
1437    // Figure out if this is shifted by a constant or a register (for non-RRX).
1438    if (Parser.getTok().is(AsmToken::Hash)) {
1439      Parser.Lex(); // Eat hash.
1440      SMLoc ImmLoc = Parser.getTok().getLoc();
1441      const MCExpr *ShiftExpr = 0;
1442      if (getParser().ParseExpression(ShiftExpr)) {
1443        Error(ImmLoc, "invalid immediate shift value");
1444        return -1;
1445      }
1446      // The expression must be evaluatable as an immediate.
1447      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1448      if (!CE) {
1449        Error(ImmLoc, "invalid immediate shift value");
1450        return -1;
1451      }
1452      // Range check the immediate.
1453      // lsl, ror: 0 <= imm <= 31
1454      // lsr, asr: 0 <= imm <= 32
1455      Imm = CE->getValue();
1456      if (Imm < 0 ||
1457          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1458          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1459        Error(ImmLoc, "immediate shift value out of range");
1460        return -1;
1461      }
1462    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1463      ShiftReg = tryParseRegister();
1464      SMLoc L = Parser.getTok().getLoc();
1465      if (ShiftReg == -1) {
1466        Error (L, "expected immediate or register in shift operand");
1467        return -1;
1468      }
1469    } else {
1470      Error (Parser.getTok().getLoc(),
1471                    "expected immediate or register in shift operand");
1472      return -1;
1473    }
1474  }
1475
1476  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1477    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1478                                                         ShiftReg, Imm,
1479                                               S, Parser.getTok().getLoc()));
1480  else
1481    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1482                                               S, Parser.getTok().getLoc()));
1483
1484  return 0;
1485}
1486
1487
1488/// Try to parse a register name.  The token must be an Identifier when called.
1489/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1490/// if there is a "writeback". 'true' if it's not a register.
1491///
1492/// TODO this is likely to change to allow different register types and or to
1493/// parse for a specific register type.
1494bool ARMAsmParser::
1495tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1496  SMLoc S = Parser.getTok().getLoc();
1497  int RegNo = tryParseRegister();
1498  if (RegNo == -1)
1499    return true;
1500
1501  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1502
1503  const AsmToken &ExclaimTok = Parser.getTok();
1504  if (ExclaimTok.is(AsmToken::Exclaim)) {
1505    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1506                                               ExclaimTok.getLoc()));
1507    Parser.Lex(); // Eat exclaim token
1508  }
1509
1510  return false;
1511}
1512
1513/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1514/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1515/// "c5", ...
1516static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1517  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1518  // but efficient.
1519  switch (Name.size()) {
1520  default: break;
1521  case 2:
1522    if (Name[0] != CoprocOp)
1523      return -1;
1524    switch (Name[1]) {
1525    default:  return -1;
1526    case '0': return 0;
1527    case '1': return 1;
1528    case '2': return 2;
1529    case '3': return 3;
1530    case '4': return 4;
1531    case '5': return 5;
1532    case '6': return 6;
1533    case '7': return 7;
1534    case '8': return 8;
1535    case '9': return 9;
1536    }
1537    break;
1538  case 3:
1539    if (Name[0] != CoprocOp || Name[1] != '1')
1540      return -1;
1541    switch (Name[2]) {
1542    default:  return -1;
1543    case '0': return 10;
1544    case '1': return 11;
1545    case '2': return 12;
1546    case '3': return 13;
1547    case '4': return 14;
1548    case '5': return 15;
1549    }
1550    break;
1551  }
1552
1553  return -1;
1554}
1555
1556/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1557/// token must be an Identifier when called, and if it is a coprocessor
1558/// number, the token is eaten and the operand is added to the operand list.
1559ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1560parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1561  SMLoc S = Parser.getTok().getLoc();
1562  const AsmToken &Tok = Parser.getTok();
1563  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1564
1565  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1566  if (Num == -1)
1567    return MatchOperand_NoMatch;
1568
1569  Parser.Lex(); // Eat identifier token.
1570  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1571  return MatchOperand_Success;
1572}
1573
1574/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1575/// token must be an Identifier when called, and if it is a coprocessor
1576/// number, the token is eaten and the operand is added to the operand list.
1577ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1578parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1579  SMLoc S = Parser.getTok().getLoc();
1580  const AsmToken &Tok = Parser.getTok();
1581  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1582
1583  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1584  if (Reg == -1)
1585    return MatchOperand_NoMatch;
1586
1587  Parser.Lex(); // Eat identifier token.
1588  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1589  return MatchOperand_Success;
1590}
1591
1592/// Parse a register list, return it if successful else return null.  The first
1593/// token must be a '{' when called.
1594bool ARMAsmParser::
1595parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1596  assert(Parser.getTok().is(AsmToken::LCurly) &&
1597         "Token is not a Left Curly Brace");
1598  SMLoc S = Parser.getTok().getLoc();
1599
1600  // Read the rest of the registers in the list.
1601  unsigned PrevRegNum = 0;
1602  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1603
1604  do {
1605    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1606    Parser.Lex(); // Eat non-identifier token.
1607
1608    const AsmToken &RegTok = Parser.getTok();
1609    SMLoc RegLoc = RegTok.getLoc();
1610    if (RegTok.isNot(AsmToken::Identifier)) {
1611      Error(RegLoc, "register expected");
1612      return true;
1613    }
1614
1615    int RegNum = tryParseRegister();
1616    if (RegNum == -1) {
1617      Error(RegLoc, "register expected");
1618      return true;
1619    }
1620
1621    if (IsRange) {
1622      int Reg = PrevRegNum;
1623      do {
1624        ++Reg;
1625        Registers.push_back(std::make_pair(Reg, RegLoc));
1626      } while (Reg != RegNum);
1627    } else {
1628      Registers.push_back(std::make_pair(RegNum, RegLoc));
1629    }
1630
1631    PrevRegNum = RegNum;
1632  } while (Parser.getTok().is(AsmToken::Comma) ||
1633           Parser.getTok().is(AsmToken::Minus));
1634
1635  // Process the right curly brace of the list.
1636  const AsmToken &RCurlyTok = Parser.getTok();
1637  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1638    Error(RCurlyTok.getLoc(), "'}' expected");
1639    return true;
1640  }
1641
1642  SMLoc E = RCurlyTok.getLoc();
1643  Parser.Lex(); // Eat right curly brace token.
1644
1645  // Verify the register list.
1646  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1647    RI = Registers.begin(), RE = Registers.end();
1648
1649  unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1650  bool EmittedWarning = false;
1651
1652  DenseMap<unsigned, bool> RegMap;
1653  RegMap[HighRegNum] = true;
1654
1655  for (++RI; RI != RE; ++RI) {
1656    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1657    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1658
1659    if (RegMap[Reg]) {
1660      Error(RegInfo.second, "register duplicated in register list");
1661      return true;
1662    }
1663
1664    if (!EmittedWarning && Reg < HighRegNum)
1665      Warning(RegInfo.second,
1666              "register not in ascending order in register list");
1667
1668    RegMap[Reg] = true;
1669    HighRegNum = std::max(Reg, HighRegNum);
1670  }
1671
1672  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1673  return false;
1674}
1675
1676/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1677ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1678parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1679  SMLoc S = Parser.getTok().getLoc();
1680  const AsmToken &Tok = Parser.getTok();
1681  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1682  StringRef OptStr = Tok.getString();
1683
1684  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1685    .Case("sy",    ARM_MB::SY)
1686    .Case("st",    ARM_MB::ST)
1687    .Case("sh",    ARM_MB::ISH)
1688    .Case("ish",   ARM_MB::ISH)
1689    .Case("shst",  ARM_MB::ISHST)
1690    .Case("ishst", ARM_MB::ISHST)
1691    .Case("nsh",   ARM_MB::NSH)
1692    .Case("un",    ARM_MB::NSH)
1693    .Case("nshst", ARM_MB::NSHST)
1694    .Case("unst",  ARM_MB::NSHST)
1695    .Case("osh",   ARM_MB::OSH)
1696    .Case("oshst", ARM_MB::OSHST)
1697    .Default(~0U);
1698
1699  if (Opt == ~0U)
1700    return MatchOperand_NoMatch;
1701
1702  Parser.Lex(); // Eat identifier token.
1703  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1704  return MatchOperand_Success;
1705}
1706
1707/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1708ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1709parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1710  SMLoc S = Parser.getTok().getLoc();
1711  const AsmToken &Tok = Parser.getTok();
1712  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1713  StringRef IFlagsStr = Tok.getString();
1714
1715  unsigned IFlags = 0;
1716  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1717    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1718    .Case("a", ARM_PROC::A)
1719    .Case("i", ARM_PROC::I)
1720    .Case("f", ARM_PROC::F)
1721    .Default(~0U);
1722
1723    // If some specific iflag is already set, it means that some letter is
1724    // present more than once, this is not acceptable.
1725    if (Flag == ~0U || (IFlags & Flag))
1726      return MatchOperand_NoMatch;
1727
1728    IFlags |= Flag;
1729  }
1730
1731  Parser.Lex(); // Eat identifier token.
1732  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1733  return MatchOperand_Success;
1734}
1735
1736/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1737ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1738parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1739  SMLoc S = Parser.getTok().getLoc();
1740  const AsmToken &Tok = Parser.getTok();
1741  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1742  StringRef Mask = Tok.getString();
1743
1744  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1745  size_t Start = 0, Next = Mask.find('_');
1746  StringRef Flags = "";
1747  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1748  if (Next != StringRef::npos)
1749    Flags = Mask.slice(Next+1, Mask.size());
1750
1751  // FlagsVal contains the complete mask:
1752  // 3-0: Mask
1753  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1754  unsigned FlagsVal = 0;
1755
1756  if (SpecReg == "apsr") {
1757    FlagsVal = StringSwitch<unsigned>(Flags)
1758    .Case("nzcvq",  0x8) // same as CPSR_f
1759    .Case("g",      0x4) // same as CPSR_s
1760    .Case("nzcvqg", 0xc) // same as CPSR_fs
1761    .Default(~0U);
1762
1763    if (FlagsVal == ~0U) {
1764      if (!Flags.empty())
1765        return MatchOperand_NoMatch;
1766      else
1767        FlagsVal = 0; // No flag
1768    }
1769  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1770    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1771      Flags = "fc";
1772    for (int i = 0, e = Flags.size(); i != e; ++i) {
1773      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1774      .Case("c", 1)
1775      .Case("x", 2)
1776      .Case("s", 4)
1777      .Case("f", 8)
1778      .Default(~0U);
1779
1780      // If some specific flag is already set, it means that some letter is
1781      // present more than once, this is not acceptable.
1782      if (FlagsVal == ~0U || (FlagsVal & Flag))
1783        return MatchOperand_NoMatch;
1784      FlagsVal |= Flag;
1785    }
1786  } else // No match for special register.
1787    return MatchOperand_NoMatch;
1788
1789  // Special register without flags are equivalent to "fc" flags.
1790  if (!FlagsVal)
1791    FlagsVal = 0x9;
1792
1793  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1794  if (SpecReg == "spsr")
1795    FlagsVal |= 16;
1796
1797  Parser.Lex(); // Eat identifier token.
1798  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1799  return MatchOperand_Success;
1800}
1801
1802ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1803parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1804            int Low, int High) {
1805  const AsmToken &Tok = Parser.getTok();
1806  if (Tok.isNot(AsmToken::Identifier)) {
1807    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1808    return MatchOperand_ParseFail;
1809  }
1810  StringRef ShiftName = Tok.getString();
1811  std::string LowerOp = LowercaseString(Op);
1812  std::string UpperOp = UppercaseString(Op);
1813  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1814    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1815    return MatchOperand_ParseFail;
1816  }
1817  Parser.Lex(); // Eat shift type token.
1818
1819  // There must be a '#' and a shift amount.
1820  if (Parser.getTok().isNot(AsmToken::Hash)) {
1821    Error(Parser.getTok().getLoc(), "'#' expected");
1822    return MatchOperand_ParseFail;
1823  }
1824  Parser.Lex(); // Eat hash token.
1825
1826  const MCExpr *ShiftAmount;
1827  SMLoc Loc = Parser.getTok().getLoc();
1828  if (getParser().ParseExpression(ShiftAmount)) {
1829    Error(Loc, "illegal expression");
1830    return MatchOperand_ParseFail;
1831  }
1832  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1833  if (!CE) {
1834    Error(Loc, "constant expression expected");
1835    return MatchOperand_ParseFail;
1836  }
1837  int Val = CE->getValue();
1838  if (Val < Low || Val > High) {
1839    Error(Loc, "immediate value out of range");
1840    return MatchOperand_ParseFail;
1841  }
1842
1843  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1844
1845  return MatchOperand_Success;
1846}
1847
1848ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1849parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1850  const AsmToken &Tok = Parser.getTok();
1851  SMLoc S = Tok.getLoc();
1852  if (Tok.isNot(AsmToken::Identifier)) {
1853    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1854    return MatchOperand_ParseFail;
1855  }
1856  int Val = StringSwitch<int>(Tok.getString())
1857    .Case("be", 1)
1858    .Case("le", 0)
1859    .Default(-1);
1860  Parser.Lex(); // Eat the token.
1861
1862  if (Val == -1) {
1863    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1864    return MatchOperand_ParseFail;
1865  }
1866  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1867                                                                  getContext()),
1868                                           S, Parser.getTok().getLoc()));
1869  return MatchOperand_Success;
1870}
1871
1872/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1873/// instructions. Legal values are:
1874///     lsl #n  'n' in [0,31]
1875///     asr #n  'n' in [1,32]
1876///             n == 32 encoded as n == 0.
1877ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1878parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1879  const AsmToken &Tok = Parser.getTok();
1880  SMLoc S = Tok.getLoc();
1881  if (Tok.isNot(AsmToken::Identifier)) {
1882    Error(S, "shift operator 'asr' or 'lsl' expected");
1883    return MatchOperand_ParseFail;
1884  }
1885  StringRef ShiftName = Tok.getString();
1886  bool isASR;
1887  if (ShiftName == "lsl" || ShiftName == "LSL")
1888    isASR = false;
1889  else if (ShiftName == "asr" || ShiftName == "ASR")
1890    isASR = true;
1891  else {
1892    Error(S, "shift operator 'asr' or 'lsl' expected");
1893    return MatchOperand_ParseFail;
1894  }
1895  Parser.Lex(); // Eat the operator.
1896
1897  // A '#' and a shift amount.
1898  if (Parser.getTok().isNot(AsmToken::Hash)) {
1899    Error(Parser.getTok().getLoc(), "'#' expected");
1900    return MatchOperand_ParseFail;
1901  }
1902  Parser.Lex(); // Eat hash token.
1903
1904  const MCExpr *ShiftAmount;
1905  SMLoc E = Parser.getTok().getLoc();
1906  if (getParser().ParseExpression(ShiftAmount)) {
1907    Error(E, "malformed shift expression");
1908    return MatchOperand_ParseFail;
1909  }
1910  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1911  if (!CE) {
1912    Error(E, "shift amount must be an immediate");
1913    return MatchOperand_ParseFail;
1914  }
1915
1916  int64_t Val = CE->getValue();
1917  if (isASR) {
1918    // Shift amount must be in [1,32]
1919    if (Val < 1 || Val > 32) {
1920      Error(E, "'asr' shift amount must be in range [1,32]");
1921      return MatchOperand_ParseFail;
1922    }
1923    // asr #32 encoded as asr #0.
1924    if (Val == 32) Val = 0;
1925  } else {
1926    // Shift amount must be in [1,32]
1927    if (Val < 0 || Val > 31) {
1928      Error(E, "'lsr' shift amount must be in range [0,31]");
1929      return MatchOperand_ParseFail;
1930    }
1931  }
1932
1933  E = Parser.getTok().getLoc();
1934  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1935
1936  return MatchOperand_Success;
1937}
1938
1939/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1940/// of instructions. Legal values are:
1941///     ror #n  'n' in {0, 8, 16, 24}
1942ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1943parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1944  const AsmToken &Tok = Parser.getTok();
1945  SMLoc S = Tok.getLoc();
1946  if (Tok.isNot(AsmToken::Identifier)) {
1947    Error(S, "rotate operator 'ror' expected");
1948    return MatchOperand_ParseFail;
1949  }
1950  StringRef ShiftName = Tok.getString();
1951  if (ShiftName != "ror" && ShiftName != "ROR") {
1952    Error(S, "rotate operator 'ror' expected");
1953    return MatchOperand_ParseFail;
1954  }
1955  Parser.Lex(); // Eat the operator.
1956
1957  // A '#' and a rotate amount.
1958  if (Parser.getTok().isNot(AsmToken::Hash)) {
1959    Error(Parser.getTok().getLoc(), "'#' expected");
1960    return MatchOperand_ParseFail;
1961  }
1962  Parser.Lex(); // Eat hash token.
1963
1964  const MCExpr *ShiftAmount;
1965  SMLoc E = Parser.getTok().getLoc();
1966  if (getParser().ParseExpression(ShiftAmount)) {
1967    Error(E, "malformed rotate expression");
1968    return MatchOperand_ParseFail;
1969  }
1970  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1971  if (!CE) {
1972    Error(E, "rotate amount must be an immediate");
1973    return MatchOperand_ParseFail;
1974  }
1975
1976  int64_t Val = CE->getValue();
1977  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1978  // normally, zero is represented in asm by omitting the rotate operand
1979  // entirely.
1980  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1981    Error(E, "'ror' rotate amount must be 8, 16, or 24");
1982    return MatchOperand_ParseFail;
1983  }
1984
1985  E = Parser.getTok().getLoc();
1986  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
1987
1988  return MatchOperand_Success;
1989}
1990
1991ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1992parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1993  SMLoc S = Parser.getTok().getLoc();
1994  // The bitfield descriptor is really two operands, the LSB and the width.
1995  if (Parser.getTok().isNot(AsmToken::Hash)) {
1996    Error(Parser.getTok().getLoc(), "'#' expected");
1997    return MatchOperand_ParseFail;
1998  }
1999  Parser.Lex(); // Eat hash token.
2000
2001  const MCExpr *LSBExpr;
2002  SMLoc E = Parser.getTok().getLoc();
2003  if (getParser().ParseExpression(LSBExpr)) {
2004    Error(E, "malformed immediate expression");
2005    return MatchOperand_ParseFail;
2006  }
2007  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2008  if (!CE) {
2009    Error(E, "'lsb' operand must be an immediate");
2010    return MatchOperand_ParseFail;
2011  }
2012
2013  int64_t LSB = CE->getValue();
2014  // The LSB must be in the range [0,31]
2015  if (LSB < 0 || LSB > 31) {
2016    Error(E, "'lsb' operand must be in the range [0,31]");
2017    return MatchOperand_ParseFail;
2018  }
2019  E = Parser.getTok().getLoc();
2020
2021  // Expect another immediate operand.
2022  if (Parser.getTok().isNot(AsmToken::Comma)) {
2023    Error(Parser.getTok().getLoc(), "too few operands");
2024    return MatchOperand_ParseFail;
2025  }
2026  Parser.Lex(); // Eat hash token.
2027  if (Parser.getTok().isNot(AsmToken::Hash)) {
2028    Error(Parser.getTok().getLoc(), "'#' expected");
2029    return MatchOperand_ParseFail;
2030  }
2031  Parser.Lex(); // Eat hash token.
2032
2033  const MCExpr *WidthExpr;
2034  if (getParser().ParseExpression(WidthExpr)) {
2035    Error(E, "malformed immediate expression");
2036    return MatchOperand_ParseFail;
2037  }
2038  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2039  if (!CE) {
2040    Error(E, "'width' operand must be an immediate");
2041    return MatchOperand_ParseFail;
2042  }
2043
2044  int64_t Width = CE->getValue();
2045  // The LSB must be in the range [1,32-lsb]
2046  if (Width < 1 || Width > 32 - LSB) {
2047    Error(E, "'width' operand must be in the range [1,32-lsb]");
2048    return MatchOperand_ParseFail;
2049  }
2050  E = Parser.getTok().getLoc();
2051
2052  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2053
2054  return MatchOperand_Success;
2055}
2056
2057ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2058parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2059  // Check for a post-index addressing register operand. Specifically:
2060  // postidx_reg := '+' register {, shift}
2061  //              | '-' register {, shift}
2062  //              | register {, shift}
2063
2064  // This method must return MatchOperand_NoMatch without consuming any tokens
2065  // in the case where there is no match, as other alternatives take other
2066  // parse methods.
2067  AsmToken Tok = Parser.getTok();
2068  SMLoc S = Tok.getLoc();
2069  bool haveEaten = false;
2070  bool isAdd = true;
2071  int Reg = -1;
2072  if (Tok.is(AsmToken::Plus)) {
2073    Parser.Lex(); // Eat the '+' token.
2074    haveEaten = true;
2075  } else if (Tok.is(AsmToken::Minus)) {
2076    Parser.Lex(); // Eat the '-' token.
2077    isAdd = false;
2078    haveEaten = true;
2079  }
2080  if (Parser.getTok().is(AsmToken::Identifier))
2081    Reg = tryParseRegister();
2082  if (Reg == -1) {
2083    if (!haveEaten)
2084      return MatchOperand_NoMatch;
2085    Error(Parser.getTok().getLoc(), "register expected");
2086    return MatchOperand_ParseFail;
2087  }
2088  SMLoc E = Parser.getTok().getLoc();
2089
2090  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2091  unsigned ShiftImm = 0;
2092  if (Parser.getTok().is(AsmToken::Comma)) {
2093    Parser.Lex(); // Eat the ','.
2094    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2095      return MatchOperand_ParseFail;
2096  }
2097
2098  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2099                                                  ShiftImm, S, E));
2100
2101  return MatchOperand_Success;
2102}
2103
2104ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2105parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2106  // Check for a post-index addressing register operand. Specifically:
2107  // am3offset := '+' register
2108  //              | '-' register
2109  //              | register
2110  //              | # imm
2111  //              | # + imm
2112  //              | # - imm
2113
2114  // This method must return MatchOperand_NoMatch without consuming any tokens
2115  // in the case where there is no match, as other alternatives take other
2116  // parse methods.
2117  AsmToken Tok = Parser.getTok();
2118  SMLoc S = Tok.getLoc();
2119
2120  // Do immediates first, as we always parse those if we have a '#'.
2121  if (Parser.getTok().is(AsmToken::Hash)) {
2122    Parser.Lex(); // Eat the '#'.
2123    // Explicitly look for a '-', as we need to encode negative zero
2124    // differently.
2125    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2126    const MCExpr *Offset;
2127    if (getParser().ParseExpression(Offset))
2128      return MatchOperand_ParseFail;
2129    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2130    if (!CE) {
2131      Error(S, "constant expression expected");
2132      return MatchOperand_ParseFail;
2133    }
2134    SMLoc E = Tok.getLoc();
2135    // Negative zero is encoded as the flag value INT32_MIN.
2136    int32_t Val = CE->getValue();
2137    if (isNegative && Val == 0)
2138      Val = INT32_MIN;
2139
2140    Operands.push_back(
2141      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2142
2143    return MatchOperand_Success;
2144  }
2145
2146
2147  bool haveEaten = false;
2148  bool isAdd = true;
2149  int Reg = -1;
2150  if (Tok.is(AsmToken::Plus)) {
2151    Parser.Lex(); // Eat the '+' token.
2152    haveEaten = true;
2153  } else if (Tok.is(AsmToken::Minus)) {
2154    Parser.Lex(); // Eat the '-' token.
2155    isAdd = false;
2156    haveEaten = true;
2157  }
2158  if (Parser.getTok().is(AsmToken::Identifier))
2159    Reg = tryParseRegister();
2160  if (Reg == -1) {
2161    if (!haveEaten)
2162      return MatchOperand_NoMatch;
2163    Error(Parser.getTok().getLoc(), "register expected");
2164    return MatchOperand_ParseFail;
2165  }
2166  SMLoc E = Parser.getTok().getLoc();
2167
2168  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2169                                                  0, S, E));
2170
2171  return MatchOperand_Success;
2172}
2173
2174/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2175/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2176/// when they refer multiple MIOperands inside a single one.
2177bool ARMAsmParser::
2178cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2179                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2180  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2181
2182  // Create a writeback register dummy placeholder.
2183  Inst.addOperand(MCOperand::CreateImm(0));
2184
2185  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2186  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2187  return true;
2188}
2189
2190/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2191/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2192/// when they refer multiple MIOperands inside a single one.
2193bool ARMAsmParser::
2194cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2195                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2196  // Create a writeback register dummy placeholder.
2197  Inst.addOperand(MCOperand::CreateImm(0));
2198  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2199  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2200  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2201  return true;
2202}
2203
2204/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2205/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2206/// when they refer multiple MIOperands inside a single one.
2207bool ARMAsmParser::
2208cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2209                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2210  // Create a writeback register dummy placeholder.
2211  Inst.addOperand(MCOperand::CreateImm(0));
2212  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2213  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2214  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2215  return true;
2216}
2217
2218/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2219/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2220/// when they refer multiple MIOperands inside a single one.
2221bool ARMAsmParser::
2222cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2223                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2224  // Create a writeback register dummy placeholder.
2225  Inst.addOperand(MCOperand::CreateImm(0));
2226  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2227  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2228  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2229  return true;
2230}
2231
2232/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2233/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2234/// when they refer multiple MIOperands inside a single one.
2235bool ARMAsmParser::
2236cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2237                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2238  // Rt
2239  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2240  // Create a writeback register dummy placeholder.
2241  Inst.addOperand(MCOperand::CreateImm(0));
2242  // addr
2243  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2244  // offset
2245  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2246  // pred
2247  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2248  return true;
2249}
2250
2251/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2252/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2253/// when they refer multiple MIOperands inside a single one.
2254bool ARMAsmParser::
2255cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2256                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2257  // Rt
2258  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2259  // Create a writeback register dummy placeholder.
2260  Inst.addOperand(MCOperand::CreateImm(0));
2261  // addr
2262  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2263  // offset
2264  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2265  // pred
2266  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2267  return true;
2268}
2269
2270/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2271/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2272/// when they refer multiple MIOperands inside a single one.
2273bool ARMAsmParser::
2274cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2275                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2276  // Create a writeback register dummy placeholder.
2277  Inst.addOperand(MCOperand::CreateImm(0));
2278  // Rt
2279  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2280  // addr
2281  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2282  // offset
2283  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2284  // pred
2285  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2286  return true;
2287}
2288
2289/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2290/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2291/// when they refer multiple MIOperands inside a single one.
2292bool ARMAsmParser::
2293cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2294                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2295  // Create a writeback register dummy placeholder.
2296  Inst.addOperand(MCOperand::CreateImm(0));
2297  // Rt
2298  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2299  // addr
2300  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2301  // offset
2302  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2303  // pred
2304  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2305  return true;
2306}
2307
2308/// cvtLdrdPre - Convert parsed operands to MCInst.
2309/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2310/// when they refer multiple MIOperands inside a single one.
2311bool ARMAsmParser::
2312cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2313           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2314  // Rt, Rt2
2315  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2316  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2317  // Create a writeback register dummy placeholder.
2318  Inst.addOperand(MCOperand::CreateImm(0));
2319  // addr
2320  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2321  // pred
2322  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2323  return true;
2324}
2325
2326/// cvtStrdPre - Convert parsed operands to MCInst.
2327/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2328/// when they refer multiple MIOperands inside a single one.
2329bool ARMAsmParser::
2330cvtStrdPre(MCInst &Inst, unsigned Opcode,
2331           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2332  // Create a writeback register dummy placeholder.
2333  Inst.addOperand(MCOperand::CreateImm(0));
2334  // Rt, Rt2
2335  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2336  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2337  // addr
2338  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2339  // pred
2340  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2341  return true;
2342}
2343
2344/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2345/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2346/// when they refer multiple MIOperands inside a single one.
2347bool ARMAsmParser::
2348cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2349                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2350  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2351  // Create a writeback register dummy placeholder.
2352  Inst.addOperand(MCOperand::CreateImm(0));
2353  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2354  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2355  return true;
2356}
2357
2358
2359/// Parse an ARM memory expression, return false if successful else return true
2360/// or an error.  The first token must be a '[' when called.
2361bool ARMAsmParser::
2362parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2363  SMLoc S, E;
2364  assert(Parser.getTok().is(AsmToken::LBrac) &&
2365         "Token is not a Left Bracket");
2366  S = Parser.getTok().getLoc();
2367  Parser.Lex(); // Eat left bracket token.
2368
2369  const AsmToken &BaseRegTok = Parser.getTok();
2370  int BaseRegNum = tryParseRegister();
2371  if (BaseRegNum == -1)
2372    return Error(BaseRegTok.getLoc(), "register expected");
2373
2374  // The next token must either be a comma or a closing bracket.
2375  const AsmToken &Tok = Parser.getTok();
2376  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2377    return Error(Tok.getLoc(), "malformed memory operand");
2378
2379  if (Tok.is(AsmToken::RBrac)) {
2380    E = Tok.getLoc();
2381    Parser.Lex(); // Eat right bracket token.
2382
2383    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2384                                             0, false, S, E));
2385
2386    return false;
2387  }
2388
2389  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2390  Parser.Lex(); // Eat the comma.
2391
2392  // If we have a '#' it's an immediate offset, else assume it's a register
2393  // offset.
2394  if (Parser.getTok().is(AsmToken::Hash)) {
2395    Parser.Lex(); // Eat the '#'.
2396    E = Parser.getTok().getLoc();
2397
2398    // FIXME: Special case #-0 so we can correctly set the U bit.
2399
2400    const MCExpr *Offset;
2401    if (getParser().ParseExpression(Offset))
2402     return true;
2403
2404    // The expression has to be a constant. Memory references with relocations
2405    // don't come through here, as they use the <label> forms of the relevant
2406    // instructions.
2407    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2408    if (!CE)
2409      return Error (E, "constant expression expected");
2410
2411    // Now we should have the closing ']'
2412    E = Parser.getTok().getLoc();
2413    if (Parser.getTok().isNot(AsmToken::RBrac))
2414      return Error(E, "']' expected");
2415    Parser.Lex(); // Eat right bracket token.
2416
2417    // Don't worry about range checking the value here. That's handled by
2418    // the is*() predicates.
2419    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2420                                             ARM_AM::no_shift, 0, false, S,E));
2421
2422    // If there's a pre-indexing writeback marker, '!', just add it as a token
2423    // operand.
2424    if (Parser.getTok().is(AsmToken::Exclaim)) {
2425      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2426      Parser.Lex(); // Eat the '!'.
2427    }
2428
2429    return false;
2430  }
2431
2432  // The register offset is optionally preceded by a '+' or '-'
2433  bool isNegative = false;
2434  if (Parser.getTok().is(AsmToken::Minus)) {
2435    isNegative = true;
2436    Parser.Lex(); // Eat the '-'.
2437  } else if (Parser.getTok().is(AsmToken::Plus)) {
2438    // Nothing to do.
2439    Parser.Lex(); // Eat the '+'.
2440  }
2441
2442  E = Parser.getTok().getLoc();
2443  int OffsetRegNum = tryParseRegister();
2444  if (OffsetRegNum == -1)
2445    return Error(E, "register expected");
2446
2447  // If there's a shift operator, handle it.
2448  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2449  unsigned ShiftImm = 0;
2450  if (Parser.getTok().is(AsmToken::Comma)) {
2451    Parser.Lex(); // Eat the ','.
2452    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2453      return true;
2454  }
2455
2456  // Now we should have the closing ']'
2457  E = Parser.getTok().getLoc();
2458  if (Parser.getTok().isNot(AsmToken::RBrac))
2459    return Error(E, "']' expected");
2460  Parser.Lex(); // Eat right bracket token.
2461
2462  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2463                                           ShiftType, ShiftImm, isNegative,
2464                                           S, E));
2465
2466  // If there's a pre-indexing writeback marker, '!', just add it as a token
2467  // operand.
2468  if (Parser.getTok().is(AsmToken::Exclaim)) {
2469    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2470    Parser.Lex(); // Eat the '!'.
2471  }
2472
2473  return false;
2474}
2475
2476/// parseMemRegOffsetShift - one of these two:
2477///   ( lsl | lsr | asr | ror ) , # shift_amount
2478///   rrx
2479/// return true if it parses a shift otherwise it returns false.
2480bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2481                                          unsigned &Amount) {
2482  SMLoc Loc = Parser.getTok().getLoc();
2483  const AsmToken &Tok = Parser.getTok();
2484  if (Tok.isNot(AsmToken::Identifier))
2485    return true;
2486  StringRef ShiftName = Tok.getString();
2487  if (ShiftName == "lsl" || ShiftName == "LSL")
2488    St = ARM_AM::lsl;
2489  else if (ShiftName == "lsr" || ShiftName == "LSR")
2490    St = ARM_AM::lsr;
2491  else if (ShiftName == "asr" || ShiftName == "ASR")
2492    St = ARM_AM::asr;
2493  else if (ShiftName == "ror" || ShiftName == "ROR")
2494    St = ARM_AM::ror;
2495  else if (ShiftName == "rrx" || ShiftName == "RRX")
2496    St = ARM_AM::rrx;
2497  else
2498    return Error(Loc, "illegal shift operator");
2499  Parser.Lex(); // Eat shift type token.
2500
2501  // rrx stands alone.
2502  Amount = 0;
2503  if (St != ARM_AM::rrx) {
2504    Loc = Parser.getTok().getLoc();
2505    // A '#' and a shift amount.
2506    const AsmToken &HashTok = Parser.getTok();
2507    if (HashTok.isNot(AsmToken::Hash))
2508      return Error(HashTok.getLoc(), "'#' expected");
2509    Parser.Lex(); // Eat hash token.
2510
2511    const MCExpr *Expr;
2512    if (getParser().ParseExpression(Expr))
2513      return true;
2514    // Range check the immediate.
2515    // lsl, ror: 0 <= imm <= 31
2516    // lsr, asr: 0 <= imm <= 32
2517    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2518    if (!CE)
2519      return Error(Loc, "shift amount must be an immediate");
2520    int64_t Imm = CE->getValue();
2521    if (Imm < 0 ||
2522        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2523        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2524      return Error(Loc, "immediate shift value out of range");
2525    Amount = Imm;
2526  }
2527
2528  return false;
2529}
2530
2531/// Parse a arm instruction operand.  For now this parses the operand regardless
2532/// of the mnemonic.
2533bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2534                                StringRef Mnemonic) {
2535  SMLoc S, E;
2536
2537  // Check if the current operand has a custom associated parser, if so, try to
2538  // custom parse the operand, or fallback to the general approach.
2539  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2540  if (ResTy == MatchOperand_Success)
2541    return false;
2542  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2543  // there was a match, but an error occurred, in which case, just return that
2544  // the operand parsing failed.
2545  if (ResTy == MatchOperand_ParseFail)
2546    return true;
2547
2548  switch (getLexer().getKind()) {
2549  default:
2550    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2551    return true;
2552  case AsmToken::Identifier: {
2553    if (!tryParseRegisterWithWriteBack(Operands))
2554      return false;
2555    int Res = tryParseShiftRegister(Operands);
2556    if (Res == 0) // success
2557      return false;
2558    else if (Res == -1) // irrecoverable error
2559      return true;
2560
2561    // Fall though for the Identifier case that is not a register or a
2562    // special name.
2563  }
2564  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2565  case AsmToken::Dot: {   // . as a branch target
2566    // This was not a register so parse other operands that start with an
2567    // identifier (like labels) as expressions and create them as immediates.
2568    const MCExpr *IdVal;
2569    S = Parser.getTok().getLoc();
2570    if (getParser().ParseExpression(IdVal))
2571      return true;
2572    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2573    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2574    return false;
2575  }
2576  case AsmToken::LBrac:
2577    return parseMemory(Operands);
2578  case AsmToken::LCurly:
2579    return parseRegisterList(Operands);
2580  case AsmToken::Hash:
2581    // #42 -> immediate.
2582    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2583    S = Parser.getTok().getLoc();
2584    Parser.Lex();
2585    const MCExpr *ImmVal;
2586    if (getParser().ParseExpression(ImmVal))
2587      return true;
2588    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2589    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2590    return false;
2591  case AsmToken::Colon: {
2592    // ":lower16:" and ":upper16:" expression prefixes
2593    // FIXME: Check it's an expression prefix,
2594    // e.g. (FOO - :lower16:BAR) isn't legal.
2595    ARMMCExpr::VariantKind RefKind;
2596    if (parsePrefix(RefKind))
2597      return true;
2598
2599    const MCExpr *SubExprVal;
2600    if (getParser().ParseExpression(SubExprVal))
2601      return true;
2602
2603    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2604                                                   getContext());
2605    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2606    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2607    return false;
2608  }
2609  }
2610}
2611
2612// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2613//  :lower16: and :upper16:.
2614bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2615  RefKind = ARMMCExpr::VK_ARM_None;
2616
2617  // :lower16: and :upper16: modifiers
2618  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2619  Parser.Lex(); // Eat ':'
2620
2621  if (getLexer().isNot(AsmToken::Identifier)) {
2622    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2623    return true;
2624  }
2625
2626  StringRef IDVal = Parser.getTok().getIdentifier();
2627  if (IDVal == "lower16") {
2628    RefKind = ARMMCExpr::VK_ARM_LO16;
2629  } else if (IDVal == "upper16") {
2630    RefKind = ARMMCExpr::VK_ARM_HI16;
2631  } else {
2632    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2633    return true;
2634  }
2635  Parser.Lex();
2636
2637  if (getLexer().isNot(AsmToken::Colon)) {
2638    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2639    return true;
2640  }
2641  Parser.Lex(); // Eat the last ':'
2642  return false;
2643}
2644
2645const MCExpr *
2646ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2647                                MCSymbolRefExpr::VariantKind Variant) {
2648  // Recurse over the given expression, rebuilding it to apply the given variant
2649  // to the leftmost symbol.
2650  if (Variant == MCSymbolRefExpr::VK_None)
2651    return E;
2652
2653  switch (E->getKind()) {
2654  case MCExpr::Target:
2655    llvm_unreachable("Can't handle target expr yet");
2656  case MCExpr::Constant:
2657    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2658
2659  case MCExpr::SymbolRef: {
2660    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2661
2662    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2663      return 0;
2664
2665    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2666  }
2667
2668  case MCExpr::Unary:
2669    llvm_unreachable("Can't handle unary expressions yet");
2670
2671  case MCExpr::Binary: {
2672    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2673    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2674    const MCExpr *RHS = BE->getRHS();
2675    if (!LHS)
2676      return 0;
2677
2678    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2679  }
2680  }
2681
2682  assert(0 && "Invalid expression kind!");
2683  return 0;
2684}
2685
2686/// \brief Given a mnemonic, split out possible predication code and carry
2687/// setting letters to form a canonical mnemonic and flags.
2688//
2689// FIXME: Would be nice to autogen this.
2690StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2691                                      unsigned &PredicationCode,
2692                                      bool &CarrySetting,
2693                                      unsigned &ProcessorIMod) {
2694  PredicationCode = ARMCC::AL;
2695  CarrySetting = false;
2696  ProcessorIMod = 0;
2697
2698  // Ignore some mnemonics we know aren't predicated forms.
2699  //
2700  // FIXME: Would be nice to autogen this.
2701  if ((Mnemonic == "movs" && isThumb()) ||
2702      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2703      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2704      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2705      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2706      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2707      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2708      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2709    return Mnemonic;
2710
2711  // First, split out any predication code. Ignore mnemonics we know aren't
2712  // predicated but do have a carry-set and so weren't caught above.
2713  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2714      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2715      Mnemonic != "umlals" && Mnemonic != "umulls") {
2716    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2717      .Case("eq", ARMCC::EQ)
2718      .Case("ne", ARMCC::NE)
2719      .Case("hs", ARMCC::HS)
2720      .Case("cs", ARMCC::HS)
2721      .Case("lo", ARMCC::LO)
2722      .Case("cc", ARMCC::LO)
2723      .Case("mi", ARMCC::MI)
2724      .Case("pl", ARMCC::PL)
2725      .Case("vs", ARMCC::VS)
2726      .Case("vc", ARMCC::VC)
2727      .Case("hi", ARMCC::HI)
2728      .Case("ls", ARMCC::LS)
2729      .Case("ge", ARMCC::GE)
2730      .Case("lt", ARMCC::LT)
2731      .Case("gt", ARMCC::GT)
2732      .Case("le", ARMCC::LE)
2733      .Case("al", ARMCC::AL)
2734      .Default(~0U);
2735    if (CC != ~0U) {
2736      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2737      PredicationCode = CC;
2738    }
2739  }
2740
2741  // Next, determine if we have a carry setting bit. We explicitly ignore all
2742  // the instructions we know end in 's'.
2743  if (Mnemonic.endswith("s") &&
2744      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2745        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2746        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2747        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2748        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2749        (Mnemonic == "movs" && isThumb()))) {
2750    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2751    CarrySetting = true;
2752  }
2753
2754  // The "cps" instruction can have a interrupt mode operand which is glued into
2755  // the mnemonic. Check if this is the case, split it and parse the imod op
2756  if (Mnemonic.startswith("cps")) {
2757    // Split out any imod code.
2758    unsigned IMod =
2759      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2760      .Case("ie", ARM_PROC::IE)
2761      .Case("id", ARM_PROC::ID)
2762      .Default(~0U);
2763    if (IMod != ~0U) {
2764      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2765      ProcessorIMod = IMod;
2766    }
2767  }
2768
2769  return Mnemonic;
2770}
2771
2772/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2773/// inclusion of carry set or predication code operands.
2774//
2775// FIXME: It would be nice to autogen this.
2776void ARMAsmParser::
2777getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2778                      bool &CanAcceptPredicationCode) {
2779  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2780      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2781      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2782      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2783      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2784      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2785      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2786      Mnemonic == "eor" || Mnemonic == "smlal" ||
2787      // FIXME: We need a better way. This really confused Thumb2
2788      // parsing for 'mov'.
2789      (Mnemonic == "mov" && !isThumbOne())) {
2790    CanAcceptCarrySet = true;
2791  } else {
2792    CanAcceptCarrySet = false;
2793  }
2794
2795  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2796      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2797      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2798      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2799      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2800      Mnemonic == "setend" ||
2801      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2802      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2803        && !isThumb()) ||
2804      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2805    CanAcceptPredicationCode = false;
2806  } else {
2807    CanAcceptPredicationCode = true;
2808  }
2809
2810  if (isThumb())
2811    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2812        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2813      CanAcceptPredicationCode = false;
2814}
2815
2816bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2817                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2818
2819  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2820  // another does not. Specifically, the MOVW instruction does not. So we
2821  // special case it here and remove the defaulted (non-setting) cc_out
2822  // operand if that's the instruction we're trying to match.
2823  //
2824  // We do this as post-processing of the explicit operands rather than just
2825  // conditionally adding the cc_out in the first place because we need
2826  // to check the type of the parsed immediate operand.
2827  if (Mnemonic == "mov" && Operands.size() > 4 &&
2828      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2829      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2830      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2831    return true;
2832
2833  // Register-register 'add' for thumb does not have a cc_out operand
2834  // when there are only two register operands.
2835  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2836      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2837      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2838      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2839    return true;
2840
2841  return false;
2842}
2843
2844/// Parse an arm instruction mnemonic followed by its operands.
2845bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2846                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2847  // Create the leading tokens for the mnemonic, split by '.' characters.
2848  size_t Start = 0, Next = Name.find('.');
2849  StringRef Mnemonic = Name.slice(Start, Next);
2850
2851  // Split out the predication code and carry setting flag from the mnemonic.
2852  unsigned PredicationCode;
2853  unsigned ProcessorIMod;
2854  bool CarrySetting;
2855  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2856                           ProcessorIMod);
2857
2858  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2859
2860  // FIXME: This is all a pretty gross hack. We should automatically handle
2861  // optional operands like this via tblgen.
2862
2863  // Next, add the CCOut and ConditionCode operands, if needed.
2864  //
2865  // For mnemonics which can ever incorporate a carry setting bit or predication
2866  // code, our matching model involves us always generating CCOut and
2867  // ConditionCode operands to match the mnemonic "as written" and then we let
2868  // the matcher deal with finding the right instruction or generating an
2869  // appropriate error.
2870  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2871  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2872
2873  // If we had a carry-set on an instruction that can't do that, issue an
2874  // error.
2875  if (!CanAcceptCarrySet && CarrySetting) {
2876    Parser.EatToEndOfStatement();
2877    return Error(NameLoc, "instruction '" + Mnemonic +
2878                 "' can not set flags, but 's' suffix specified");
2879  }
2880  // If we had a predication code on an instruction that can't do that, issue an
2881  // error.
2882  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2883    Parser.EatToEndOfStatement();
2884    return Error(NameLoc, "instruction '" + Mnemonic +
2885                 "' is not predicable, but condition code specified");
2886  }
2887
2888  // Add the carry setting operand, if necessary.
2889  //
2890  // FIXME: It would be awesome if we could somehow invent a location such that
2891  // match errors on this operand would print a nice diagnostic about how the
2892  // 's' character in the mnemonic resulted in a CCOut operand.
2893  if (CanAcceptCarrySet)
2894    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2895                                               NameLoc));
2896
2897  // Add the predication code operand, if necessary.
2898  if (CanAcceptPredicationCode) {
2899    Operands.push_back(ARMOperand::CreateCondCode(
2900                         ARMCC::CondCodes(PredicationCode), NameLoc));
2901  }
2902
2903  // Add the processor imod operand, if necessary.
2904  if (ProcessorIMod) {
2905    Operands.push_back(ARMOperand::CreateImm(
2906          MCConstantExpr::Create(ProcessorIMod, getContext()),
2907                                 NameLoc, NameLoc));
2908  } else {
2909    // This mnemonic can't ever accept a imod, but the user wrote
2910    // one (or misspelled another mnemonic).
2911
2912    // FIXME: Issue a nice error.
2913  }
2914
2915  // Add the remaining tokens in the mnemonic.
2916  while (Next != StringRef::npos) {
2917    Start = Next;
2918    Next = Name.find('.', Start + 1);
2919    StringRef ExtraToken = Name.slice(Start, Next);
2920
2921    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2922  }
2923
2924  // Read the remaining operands.
2925  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2926    // Read the first operand.
2927    if (parseOperand(Operands, Mnemonic)) {
2928      Parser.EatToEndOfStatement();
2929      return true;
2930    }
2931
2932    while (getLexer().is(AsmToken::Comma)) {
2933      Parser.Lex();  // Eat the comma.
2934
2935      // Parse and remember the operand.
2936      if (parseOperand(Operands, Mnemonic)) {
2937        Parser.EatToEndOfStatement();
2938        return true;
2939      }
2940    }
2941  }
2942
2943  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2944    Parser.EatToEndOfStatement();
2945    return TokError("unexpected token in argument list");
2946  }
2947
2948  Parser.Lex(); // Consume the EndOfStatement
2949
2950  // Some instructions, mostly Thumb, have forms for the same mnemonic that
2951  // do and don't have a cc_out optional-def operand. With some spot-checks
2952  // of the operand list, we can figure out which variant we're trying to
2953  // parse and adjust accordingly before actually matching. Reason number
2954  // #317 the table driven matcher doesn't fit well with the ARM instruction
2955  // set.
2956  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
2957    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2958    Operands.erase(Operands.begin() + 1);
2959    delete Op;
2960  }
2961
2962  // ARM mode 'blx' need special handling, as the register operand version
2963  // is predicable, but the label operand version is not. So, we can't rely
2964  // on the Mnemonic based checking to correctly figure out when to put
2965  // a CondCode operand in the list. If we're trying to match the label
2966  // version, remove the CondCode operand here.
2967  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
2968      static_cast<ARMOperand*>(Operands[2])->isImm()) {
2969    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2970    Operands.erase(Operands.begin() + 1);
2971    delete Op;
2972  }
2973
2974  // The vector-compare-to-zero instructions have a literal token "#0" at
2975  // the end that comes to here as an immediate operand. Convert it to a
2976  // token to play nicely with the matcher.
2977  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
2978      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
2979      static_cast<ARMOperand*>(Operands[5])->isImm()) {
2980    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
2981    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
2982    if (CE && CE->getValue() == 0) {
2983      Operands.erase(Operands.begin() + 5);
2984      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
2985      delete Op;
2986    }
2987  }
2988  return false;
2989}
2990
2991// Validate context-sensitive operand constraints.
2992// FIXME: We would really like to be able to tablegen'erate this.
2993bool ARMAsmParser::
2994validateInstruction(MCInst &Inst,
2995                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2996  switch (Inst.getOpcode()) {
2997  case ARM::LDRD:
2998  case ARM::LDRD_PRE:
2999  case ARM::LDRD_POST:
3000  case ARM::LDREXD: {
3001    // Rt2 must be Rt + 1.
3002    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3003    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3004    if (Rt2 != Rt + 1)
3005      return Error(Operands[3]->getStartLoc(),
3006                   "destination operands must be sequential");
3007    return false;
3008  }
3009  case ARM::STRD: {
3010    // Rt2 must be Rt + 1.
3011    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3012    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3013    if (Rt2 != Rt + 1)
3014      return Error(Operands[3]->getStartLoc(),
3015                   "source operands must be sequential");
3016    return false;
3017  }
3018  case ARM::STRD_PRE:
3019  case ARM::STRD_POST:
3020  case ARM::STREXD: {
3021    // Rt2 must be Rt + 1.
3022    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3023    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3024    if (Rt2 != Rt + 1)
3025      return Error(Operands[3]->getStartLoc(),
3026                   "source operands must be sequential");
3027    return false;
3028  }
3029  case ARM::SBFX:
3030  case ARM::UBFX: {
3031    // width must be in range [1, 32-lsb]
3032    unsigned lsb = Inst.getOperand(2).getImm();
3033    unsigned widthm1 = Inst.getOperand(3).getImm();
3034    if (widthm1 >= 32 - lsb)
3035      return Error(Operands[5]->getStartLoc(),
3036                   "bitfield width must be in range [1,32-lsb]");
3037    return false;
3038  }
3039  case ARM::tLDMIA: {
3040    // Thumb LDM instructions are writeback iff the base register is not
3041    // in the register list.
3042    unsigned Rn = Inst.getOperand(0).getReg();
3043    bool doesWriteback = true;
3044    for (unsigned i = 3; i < Inst.getNumOperands(); ++i) {
3045      unsigned Reg = Inst.getOperand(i).getReg();
3046      if (Reg == Rn)
3047        doesWriteback = false;
3048      // Anything other than a low register isn't legal here.
3049      if (!isARMLowRegister(Reg))
3050        return Error(Operands[4]->getStartLoc(),
3051                     "registers must be in range r0-r7");
3052    }
3053    // If we should have writeback, then there should be a '!' token.
3054    if (doesWriteback &&
3055        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
3056         static_cast<ARMOperand*>(Operands[3])->getToken() != "!"))
3057      return Error(Operands[2]->getStartLoc(),
3058                   "writeback operator '!' expected");
3059
3060    break;
3061  }
3062  }
3063
3064  return false;
3065}
3066
3067void ARMAsmParser::
3068processInstruction(MCInst &Inst,
3069                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3070  switch (Inst.getOpcode()) {
3071  case ARM::LDMIA_UPD:
3072    // If this is a load of a single register via a 'pop', then we should use
3073    // a post-indexed LDR instruction instead, per the ARM ARM.
3074    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3075        Inst.getNumOperands() == 5) {
3076      MCInst TmpInst;
3077      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3078      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3079      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3080      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3081      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3082      TmpInst.addOperand(MCOperand::CreateImm(4));
3083      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3084      TmpInst.addOperand(Inst.getOperand(3));
3085      Inst = TmpInst;
3086    }
3087    break;
3088  case ARM::STMDB_UPD:
3089    // If this is a store of a single register via a 'push', then we should use
3090    // a pre-indexed STR instruction instead, per the ARM ARM.
3091    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3092        Inst.getNumOperands() == 5) {
3093      MCInst TmpInst;
3094      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3095      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3096      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3097      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3098      TmpInst.addOperand(MCOperand::CreateImm(-4));
3099      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3100      TmpInst.addOperand(Inst.getOperand(3));
3101      Inst = TmpInst;
3102    }
3103    break;
3104  case ARM::tADDi8:
3105    // If the immediate is in the range 0-7, we really wanted tADDi3.
3106    if (Inst.getOperand(3).getImm() < 8)
3107      Inst.setOpcode(ARM::tADDi3);
3108    break;
3109  case ARM::tBcc:
3110    // If the conditional is AL, we really want tB.
3111    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3112      Inst.setOpcode(ARM::tB);
3113    break;
3114  }
3115}
3116
3117// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3118// the ARMInsts array) instead. Getting that here requires awkward
3119// API changes, though. Better way?
3120namespace llvm {
3121extern MCInstrDesc ARMInsts[];
3122}
3123static MCInstrDesc &getInstDesc(unsigned Opcode) {
3124  return ARMInsts[Opcode];
3125}
3126
3127unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3128  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3129  // suffix depending on whether they're in an IT block or not.
3130  unsigned Opc = Inst.getOpcode();
3131  MCInstrDesc &MCID = getInstDesc(Opc);
3132  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3133    assert(MCID.hasOptionalDef() &&
3134           "optionally flag setting instruction missing optional def operand");
3135    assert(MCID.NumOperands == Inst.getNumOperands() &&
3136           "operand count mismatch!");
3137    // Find the optional-def operand (cc_out).
3138    unsigned OpNo;
3139    for (OpNo = 0;
3140         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3141         ++OpNo)
3142      ;
3143    // If we're parsing Thumb1, reject it completely.
3144    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3145      return Match_MnemonicFail;
3146    // If we're parsing Thumb2, which form is legal depends on whether we're
3147    // in an IT block.
3148    // FIXME: We don't yet do IT blocks, so just always consider it to be
3149    // that we aren't in one until we do.
3150    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3151      return Match_RequiresITBlock;
3152  }
3153  // Some high-register supporting Thumb1 encodings only allow both registers
3154  // to be from r0-r7 when in Thumb2.
3155  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3156           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3157           isARMLowRegister(Inst.getOperand(2).getReg()))
3158    return Match_RequiresThumb2;
3159  // Others only require ARMv6 or later.
3160  else if (Opc == ARM::tMOVr && isThumbOne() &&
3161           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3162           isARMLowRegister(Inst.getOperand(1).getReg()))
3163    return Match_RequiresV6;
3164  return Match_Success;
3165}
3166
3167bool ARMAsmParser::
3168MatchAndEmitInstruction(SMLoc IDLoc,
3169                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3170                        MCStreamer &Out) {
3171  MCInst Inst;
3172  unsigned ErrorInfo;
3173  unsigned MatchResult;
3174  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3175  switch (MatchResult) {
3176  default: break;
3177  case Match_Success:
3178    // Context sensitive operand constraints aren't handled by the matcher,
3179    // so check them here.
3180    if (validateInstruction(Inst, Operands))
3181      return true;
3182
3183    // Some instructions need post-processing to, for example, tweak which
3184    // encoding is selected.
3185    processInstruction(Inst, Operands);
3186
3187    Out.EmitInstruction(Inst);
3188    return false;
3189  case Match_MissingFeature:
3190    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3191    return true;
3192  case Match_InvalidOperand: {
3193    SMLoc ErrorLoc = IDLoc;
3194    if (ErrorInfo != ~0U) {
3195      if (ErrorInfo >= Operands.size())
3196        return Error(IDLoc, "too few operands for instruction");
3197
3198      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3199      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3200    }
3201
3202    return Error(ErrorLoc, "invalid operand for instruction");
3203  }
3204  case Match_MnemonicFail:
3205    return Error(IDLoc, "invalid instruction");
3206  case Match_ConversionFail:
3207    return Error(IDLoc, "unable to convert operands to instruction");
3208  case Match_RequiresITBlock:
3209    return Error(IDLoc, "instruction only valid inside IT block");
3210  case Match_RequiresV6:
3211    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3212  case Match_RequiresThumb2:
3213    return Error(IDLoc, "instruction variant requires Thumb2");
3214  }
3215
3216  llvm_unreachable("Implement any new match types added!");
3217  return true;
3218}
3219
3220/// parseDirective parses the arm specific directives
3221bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3222  StringRef IDVal = DirectiveID.getIdentifier();
3223  if (IDVal == ".word")
3224    return parseDirectiveWord(4, DirectiveID.getLoc());
3225  else if (IDVal == ".thumb")
3226    return parseDirectiveThumb(DirectiveID.getLoc());
3227  else if (IDVal == ".thumb_func")
3228    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3229  else if (IDVal == ".code")
3230    return parseDirectiveCode(DirectiveID.getLoc());
3231  else if (IDVal == ".syntax")
3232    return parseDirectiveSyntax(DirectiveID.getLoc());
3233  return true;
3234}
3235
3236/// parseDirectiveWord
3237///  ::= .word [ expression (, expression)* ]
3238bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3239  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3240    for (;;) {
3241      const MCExpr *Value;
3242      if (getParser().ParseExpression(Value))
3243        return true;
3244
3245      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3246
3247      if (getLexer().is(AsmToken::EndOfStatement))
3248        break;
3249
3250      // FIXME: Improve diagnostic.
3251      if (getLexer().isNot(AsmToken::Comma))
3252        return Error(L, "unexpected token in directive");
3253      Parser.Lex();
3254    }
3255  }
3256
3257  Parser.Lex();
3258  return false;
3259}
3260
3261/// parseDirectiveThumb
3262///  ::= .thumb
3263bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3264  if (getLexer().isNot(AsmToken::EndOfStatement))
3265    return Error(L, "unexpected token in directive");
3266  Parser.Lex();
3267
3268  // TODO: set thumb mode
3269  // TODO: tell the MC streamer the mode
3270  // getParser().getStreamer().Emit???();
3271  return false;
3272}
3273
3274/// parseDirectiveThumbFunc
3275///  ::= .thumbfunc symbol_name
3276bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3277  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3278  bool isMachO = MAI.hasSubsectionsViaSymbols();
3279  StringRef Name;
3280
3281  // Darwin asm has function name after .thumb_func direction
3282  // ELF doesn't
3283  if (isMachO) {
3284    const AsmToken &Tok = Parser.getTok();
3285    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3286      return Error(L, "unexpected token in .thumb_func directive");
3287    Name = Tok.getString();
3288    Parser.Lex(); // Consume the identifier token.
3289  }
3290
3291  if (getLexer().isNot(AsmToken::EndOfStatement))
3292    return Error(L, "unexpected token in directive");
3293  Parser.Lex();
3294
3295  // FIXME: assuming function name will be the line following .thumb_func
3296  if (!isMachO) {
3297    Name = Parser.getTok().getString();
3298  }
3299
3300  // Mark symbol as a thumb symbol.
3301  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3302  getParser().getStreamer().EmitThumbFunc(Func);
3303  return false;
3304}
3305
3306/// parseDirectiveSyntax
3307///  ::= .syntax unified | divided
3308bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3309  const AsmToken &Tok = Parser.getTok();
3310  if (Tok.isNot(AsmToken::Identifier))
3311    return Error(L, "unexpected token in .syntax directive");
3312  StringRef Mode = Tok.getString();
3313  if (Mode == "unified" || Mode == "UNIFIED")
3314    Parser.Lex();
3315  else if (Mode == "divided" || Mode == "DIVIDED")
3316    return Error(L, "'.syntax divided' arm asssembly not supported");
3317  else
3318    return Error(L, "unrecognized syntax mode in .syntax directive");
3319
3320  if (getLexer().isNot(AsmToken::EndOfStatement))
3321    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3322  Parser.Lex();
3323
3324  // TODO tell the MC streamer the mode
3325  // getParser().getStreamer().Emit???();
3326  return false;
3327}
3328
3329/// parseDirectiveCode
3330///  ::= .code 16 | 32
3331bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3332  const AsmToken &Tok = Parser.getTok();
3333  if (Tok.isNot(AsmToken::Integer))
3334    return Error(L, "unexpected token in .code directive");
3335  int64_t Val = Parser.getTok().getIntVal();
3336  if (Val == 16)
3337    Parser.Lex();
3338  else if (Val == 32)
3339    Parser.Lex();
3340  else
3341    return Error(L, "invalid operand to .code directive");
3342
3343  if (getLexer().isNot(AsmToken::EndOfStatement))
3344    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3345  Parser.Lex();
3346
3347  if (Val == 16) {
3348    if (!isThumb()) {
3349      SwitchMode();
3350      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3351    }
3352  } else {
3353    if (isThumb()) {
3354      SwitchMode();
3355      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3356    }
3357  }
3358
3359  return false;
3360}
3361
3362extern "C" void LLVMInitializeARMAsmLexer();
3363
3364/// Force static initialization.
3365extern "C" void LLVMInitializeARMAsmParser() {
3366  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3367  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3368  LLVMInitializeARMAsmLexer();
3369}
3370
3371#define GET_REGISTER_MATCHER
3372#define GET_MATCHER_IMPLEMENTATION
3373#include "ARMGenAsmMatcher.inc"
3374