ARMAsmParser.cpp revision 5fa22a19750c082ff161db1702ebe96dd2a787e7 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "ARM.h"
11#include "ARMAddressingModes.h"
12#include "ARMSubtarget.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/Target/TargetRegistry.h"
21#include "llvm/Target/TargetAsmParser.h"
22#include "llvm/Support/SourceMgr.h"
23#include "llvm/Support/raw_ostream.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/ADT/StringSwitch.h"
26#include "llvm/ADT/Twine.h"
27using namespace llvm;
28
29// The shift types for register controlled shifts in arm memory addressing
30enum ShiftType {
31  Lsl,
32  Lsr,
33  Asr,
34  Ror,
35  Rrx
36};
37
38namespace {
39
40class ARMOperand;
41
42class ARMAsmParser : public TargetAsmParser {
43  MCAsmParser &Parser;
44  TargetMachine &TM;
45
46  MCAsmParser &getParser() const { return Parser; }
47  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48
49  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
51
52  int TryParseRegister();
53  ARMOperand *TryParseRegisterWithWriteBack();
54  ARMOperand *ParseRegisterList();
55  ARMOperand *ParseMemory();
56  ARMOperand *ParseOperand();
57
58  bool ParseMemoryOffsetReg(bool &Negative,
59                            bool &OffsetRegShifted,
60                            enum ShiftType &ShiftType,
61                            const MCExpr *&ShiftAmount,
62                            const MCExpr *&Offset,
63                            bool &OffsetIsReg,
64                            int &OffsetRegNum,
65                            SMLoc &E);
66  bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67  bool ParseDirectiveWord(unsigned Size, SMLoc L);
68  bool ParseDirectiveThumb(SMLoc L);
69  bool ParseDirectiveThumbFunc(SMLoc L);
70  bool ParseDirectiveCode(SMLoc L);
71  bool ParseDirectiveSyntax(SMLoc L);
72
73  bool MatchAndEmitInstruction(SMLoc IDLoc,
74                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
75                               MCStreamer &Out);
76
77  /// @name Auto-generated Match Functions
78  /// {
79
80#define GET_ASSEMBLER_HEADER
81#include "ARMGenAsmMatcher.inc"
82
83  /// }
84
85public:
86  ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
87    : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
88      // Initialize the set of available features.
89      setAvailableFeatures(ComputeAvailableFeatures(
90          &TM.getSubtarget<ARMSubtarget>()));
91    }
92
93  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
94                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
95  virtual bool ParseDirective(AsmToken DirectiveID);
96};
97} // end anonymous namespace
98
99namespace {
100
101/// ARMOperand - Instances of this class represent a parsed ARM machine
102/// instruction.
103class ARMOperand : public MCParsedAsmOperand {
104  enum KindTy {
105    CondCode,
106    Immediate,
107    Memory,
108    Register,
109    RegisterList,
110    Token
111  } Kind;
112
113  SMLoc StartLoc, EndLoc;
114
115  union {
116    struct {
117      ARMCC::CondCodes Val;
118    } CC;
119
120    struct {
121      const char *Data;
122      unsigned Length;
123    } Tok;
124
125    struct {
126      unsigned RegNum;
127      bool Writeback;
128    } Reg;
129
130    struct {
131      SmallVector<unsigned, 32> *Registers;
132    } RegList;
133
134    struct {
135      const MCExpr *Val;
136    } Imm;
137
138    // This is for all forms of ARM address expressions
139    struct {
140      unsigned BaseRegNum;
141      unsigned OffsetRegNum;         // used when OffsetIsReg is true
142      const MCExpr *Offset;          // used when OffsetIsReg is false
143      const MCExpr *ShiftAmount;     // used when OffsetRegShifted is true
144      enum ShiftType ShiftType;      // used when OffsetRegShifted is true
145      unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
146      unsigned Preindexed : 1;
147      unsigned Postindexed : 1;
148      unsigned OffsetIsReg : 1;
149      unsigned Negative : 1;         // only used when OffsetIsReg is true
150      unsigned Writeback : 1;
151    } Mem;
152  };
153
154  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
155public:
156  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
157    Kind = o.Kind;
158    StartLoc = o.StartLoc;
159    EndLoc = o.EndLoc;
160    switch (Kind) {
161    case CondCode:
162      CC = o.CC;
163      break;
164    case Token:
165      Tok = o.Tok;
166      break;
167    case Register:
168      Reg = o.Reg;
169      break;
170    case RegisterList:
171      RegList = o.RegList;
172      break;
173    case Immediate:
174      Imm = o.Imm;
175      break;
176    case Memory:
177      Mem = o.Mem;
178      break;
179    }
180  }
181  ~ARMOperand() {
182    if (isRegList())
183      delete RegList.Registers;
184  }
185
186  /// getStartLoc - Get the location of the first token of this operand.
187  SMLoc getStartLoc() const { return StartLoc; }
188  /// getEndLoc - Get the location of the last token of this operand.
189  SMLoc getEndLoc() const { return EndLoc; }
190
191  ARMCC::CondCodes getCondCode() const {
192    assert(Kind == CondCode && "Invalid access!");
193    return CC.Val;
194  }
195
196  StringRef getToken() const {
197    assert(Kind == Token && "Invalid access!");
198    return StringRef(Tok.Data, Tok.Length);
199  }
200
201  unsigned getReg() const {
202    assert(Kind == Register && "Invalid access!");
203    return Reg.RegNum;
204  }
205
206  const SmallVectorImpl<unsigned> &getRegList() const {
207    assert(Kind == RegisterList && "Invalid access!");
208    return *RegList.Registers;
209  }
210
211  const MCExpr *getImm() const {
212    assert(Kind == Immediate && "Invalid access!");
213    return Imm.Val;
214  }
215
216  bool isCondCode() const { return Kind == CondCode; }
217  bool isImm() const { return Kind == Immediate; }
218  bool isReg() const { return Kind == Register; }
219  bool isRegList() const { return Kind == RegisterList; }
220  bool isToken() const { return Kind == Token; }
221  bool isMemory() const { return Kind == Memory; }
222  bool isMemMode5() const {
223    if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
224        Mem.Writeback || Mem.Negative)
225      return false;
226    // If there is an offset expression, make sure it's valid.
227    if (!Mem.Offset)
228      return true;
229    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
230    if (!CE)
231      return false;
232    // The offset must be a multiple of 4 in the range 0-1020.
233    int64_t Value = CE->getValue();
234    return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
235  }
236
237  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
238    // Add as immediates when possible.  Null MCExpr = 0.
239    if (Expr == 0)
240      Inst.addOperand(MCOperand::CreateImm(0));
241    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
242      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
243    else
244      Inst.addOperand(MCOperand::CreateExpr(Expr));
245  }
246
247  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
248    assert(N == 2 && "Invalid number of operands!");
249    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
250    // FIXME: What belongs here?
251    Inst.addOperand(MCOperand::CreateReg(0));
252  }
253
254  void addRegOperands(MCInst &Inst, unsigned N) const {
255    assert(N == 1 && "Invalid number of operands!");
256    Inst.addOperand(MCOperand::CreateReg(getReg()));
257  }
258
259  void addRegListOperands(MCInst &Inst, unsigned N) const {
260    assert(N == 1 && "Invalid number of operands!");
261    const SmallVectorImpl<unsigned> &RegList = getRegList();
262    for (SmallVectorImpl<unsigned>::const_iterator
263           I = RegList.begin(), E = RegList.end(); I != E; ++I)
264      Inst.addOperand(MCOperand::CreateReg(*I));
265  }
266
267  void addImmOperands(MCInst &Inst, unsigned N) const {
268    assert(N == 1 && "Invalid number of operands!");
269    addExpr(Inst, getImm());
270  }
271
272  void addMemMode5Operands(MCInst &Inst, unsigned N) const {
273    assert(N == 2 && isMemMode5() && "Invalid number of operands!");
274
275    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
276    assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
277
278    // FIXME: #-0 is encoded differently than #0. Does the parser preserve
279    // the difference?
280    if (Mem.Offset) {
281      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
282      assert(CE && "Non-constant mode 5 offset operand!");
283
284      // The MCInst offset operand doesn't include the low two bits (like
285      // the instruction encoding).
286      int64_t Offset = CE->getValue() / 4;
287      if (Offset >= 0)
288        Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
289                                                               Offset)));
290      else
291        Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
292                                                               -Offset)));
293    } else {
294      Inst.addOperand(MCOperand::CreateImm(0));
295    }
296  }
297
298  virtual void dump(raw_ostream &OS) const;
299
300  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
301    ARMOperand *Op = new ARMOperand(CondCode);
302    Op->CC.Val = CC;
303    Op->StartLoc = S;
304    Op->EndLoc = S;
305    return Op;
306  }
307
308  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
309    ARMOperand *Op = new ARMOperand(Token);
310    Op->Tok.Data = Str.data();
311    Op->Tok.Length = Str.size();
312    Op->StartLoc = S;
313    Op->EndLoc = S;
314    return Op;
315  }
316
317  static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
318                               SMLoc E) {
319    ARMOperand *Op = new ARMOperand(Register);
320    Op->Reg.RegNum = RegNum;
321    Op->Reg.Writeback = Writeback;
322    Op->StartLoc = S;
323    Op->EndLoc = E;
324    return Op;
325  }
326
327  static ARMOperand *
328  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
329                SMLoc S, SMLoc E) {
330    ARMOperand *Op = new ARMOperand(RegisterList);
331    Op->RegList.Registers = new SmallVector<unsigned, 32>();
332    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
333           I = Regs.begin(), E = Regs.end(); I != E; ++I)
334      Op->RegList.Registers->push_back(I->first);
335    std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end());
336    Op->StartLoc = S;
337    Op->EndLoc = E;
338    return Op;
339  }
340
341  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
342    ARMOperand *Op = new ARMOperand(Immediate);
343    Op->Imm.Val = Val;
344    Op->StartLoc = S;
345    Op->EndLoc = E;
346    return Op;
347  }
348
349  static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
350                               const MCExpr *Offset, unsigned OffsetRegNum,
351                               bool OffsetRegShifted, enum ShiftType ShiftType,
352                               const MCExpr *ShiftAmount, bool Preindexed,
353                               bool Postindexed, bool Negative, bool Writeback,
354                               SMLoc S, SMLoc E) {
355    ARMOperand *Op = new ARMOperand(Memory);
356    Op->Mem.BaseRegNum = BaseRegNum;
357    Op->Mem.OffsetIsReg = OffsetIsReg;
358    Op->Mem.Offset = Offset;
359    Op->Mem.OffsetRegNum = OffsetRegNum;
360    Op->Mem.OffsetRegShifted = OffsetRegShifted;
361    Op->Mem.ShiftType = ShiftType;
362    Op->Mem.ShiftAmount = ShiftAmount;
363    Op->Mem.Preindexed = Preindexed;
364    Op->Mem.Postindexed = Postindexed;
365    Op->Mem.Negative = Negative;
366    Op->Mem.Writeback = Writeback;
367
368    Op->StartLoc = S;
369    Op->EndLoc = E;
370    return Op;
371  }
372};
373
374} // end anonymous namespace.
375
376void ARMOperand::dump(raw_ostream &OS) const {
377  switch (Kind) {
378  case CondCode:
379    OS << ARMCondCodeToString(getCondCode());
380    break;
381  case Immediate:
382    getImm()->print(OS);
383    break;
384  case Memory:
385    OS << "<memory>";
386    break;
387  case Register:
388    OS << "<register " << getReg() << ">";
389    break;
390  case RegisterList: {
391    OS << "<register_list ";
392
393    const SmallVectorImpl<unsigned> &RegList = getRegList();
394    for (SmallVectorImpl<unsigned>::const_iterator
395           I = RegList.begin(), E = RegList.end(); I != E; ) {
396      OS << *I;
397      if (++I < E) OS << ", ";
398    }
399
400    OS << ">";
401    break;
402  }
403  case Token:
404    OS << "'" << getToken() << "'";
405    break;
406  }
407}
408
409/// @name Auto-generated Match Functions
410/// {
411
412static unsigned MatchRegisterName(StringRef Name);
413
414/// }
415
416/// Try to parse a register name.  The token must be an Identifier when called,
417/// and if it is a register name the token is eaten and the register number is
418/// returned.  Otherwise return -1.
419///
420int ARMAsmParser::TryParseRegister() {
421  const AsmToken &Tok = Parser.getTok();
422  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
423
424  // FIXME: Validate register for the current architecture; we have to do
425  // validation later, so maybe there is no need for this here.
426  unsigned RegNum = MatchRegisterName(Tok.getString());
427  if (RegNum == 0)
428    return -1;
429  Parser.Lex(); // Eat identifier token.
430  return RegNum;
431}
432
433
434/// Try to parse a register name.  The token must be an Identifier when called,
435/// and if it is a register name the token is eaten and the register number is
436/// returned.  Otherwise return -1.
437///
438/// TODO this is likely to change to allow different register types and or to
439/// parse for a specific register type.
440ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
441  SMLoc S = Parser.getTok().getLoc();
442  int RegNo = TryParseRegister();
443  if (RegNo == -1)
444    return 0;
445
446  SMLoc E = Parser.getTok().getLoc();
447
448  bool Writeback = false;
449  const AsmToken &ExclaimTok = Parser.getTok();
450  if (ExclaimTok.is(AsmToken::Exclaim)) {
451    E = ExclaimTok.getLoc();
452    Writeback = true;
453    Parser.Lex(); // Eat exclaim token
454  }
455
456  return ARMOperand::CreateReg(RegNo, Writeback, S, E);
457}
458
459/// Parse a register list, return it if successful else return null.  The first
460/// token must be a '{' when called.
461ARMOperand *ARMAsmParser::ParseRegisterList() {
462  assert(Parser.getTok().is(AsmToken::LCurly) &&
463         "Token is not a Left Curly Brace");
464  SMLoc S = Parser.getTok().getLoc();
465
466  // Read the rest of the registers in the list.
467  unsigned PrevRegNum = 0;
468  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
469
470  do {
471    bool IsRange = Parser.getTok().is(AsmToken::Minus);
472    Parser.Lex(); // Eat non-identifier token.
473
474    const AsmToken &RegTok = Parser.getTok();
475    SMLoc RegLoc = RegTok.getLoc();
476    if (RegTok.isNot(AsmToken::Identifier)) {
477      Error(RegLoc, "register expected");
478      return 0;
479    }
480
481    int RegNum = TryParseRegister();
482    if (RegNum == -1) {
483      Error(RegLoc, "register expected");
484      return 0;
485    }
486
487    if (IsRange) {
488      int Reg = PrevRegNum;
489      do {
490        ++Reg;
491        Registers.push_back(std::make_pair(Reg, RegLoc));
492      } while (Reg != RegNum);
493    } else {
494      Registers.push_back(std::make_pair(RegNum, RegLoc));
495    }
496
497    PrevRegNum = RegNum;
498  } while (Parser.getTok().is(AsmToken::Comma) ||
499           Parser.getTok().is(AsmToken::Minus));
500
501  // Process the right curly brace of the list.
502  const AsmToken &RCurlyTok = Parser.getTok();
503  if (RCurlyTok.isNot(AsmToken::RCurly)) {
504    Error(RCurlyTok.getLoc(), "'}' expected");
505    return 0;
506  }
507
508  SMLoc E = RCurlyTok.getLoc();
509  Parser.Lex(); // Eat right curly brace token.
510
511  // Verify the register list.
512  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
513    RI = Registers.begin(), RE = Registers.end();
514
515  unsigned HighRegNum = RI->first;
516  DenseMap<unsigned, bool> RegMap;
517  RegMap[RI->first] = true;
518
519  for (++RI; RI != RE; ++RI) {
520    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
521
522    if (RegMap[RegInfo.first]) {
523      Error(RegInfo.second, "register duplicated in register list");
524      return 0;
525    }
526
527    if (RegInfo.first < HighRegNum)
528      Warning(RegInfo.second,
529              "register not in ascending order in register list");
530
531    RegMap[RegInfo.first] = true;
532    HighRegNum = std::max(RegInfo.first, HighRegNum);
533  }
534
535  return ARMOperand::CreateRegList(Registers, S, E);
536}
537
538/// Parse an ARM memory expression, return false if successful else return true
539/// or an error.  The first token must be a '[' when called.
540/// TODO Only preindexing and postindexing addressing are started, unindexed
541/// with option, etc are still to do.
542ARMOperand *ARMAsmParser::ParseMemory() {
543  SMLoc S, E;
544  assert(Parser.getTok().is(AsmToken::LBrac) &&
545         "Token is not a Left Bracket");
546  S = Parser.getTok().getLoc();
547  Parser.Lex(); // Eat left bracket token.
548
549  const AsmToken &BaseRegTok = Parser.getTok();
550  if (BaseRegTok.isNot(AsmToken::Identifier)) {
551    Error(BaseRegTok.getLoc(), "register expected");
552    return 0;
553  }
554  int BaseRegNum = TryParseRegister();
555  if (BaseRegNum == -1) {
556    Error(BaseRegTok.getLoc(), "register expected");
557    return 0;
558  }
559
560  bool Preindexed = false;
561  bool Postindexed = false;
562  bool OffsetIsReg = false;
563  bool Negative = false;
564  bool Writeback = false;
565
566  // First look for preindexed address forms, that is after the "[Rn" we now
567  // have to see if the next token is a comma.
568  const AsmToken &Tok = Parser.getTok();
569  if (Tok.is(AsmToken::Comma)) {
570    Preindexed = true;
571    Parser.Lex(); // Eat comma token.
572    int OffsetRegNum;
573    bool OffsetRegShifted;
574    enum ShiftType ShiftType;
575    const MCExpr *ShiftAmount;
576    const MCExpr *Offset;
577    if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
578                             Offset, OffsetIsReg, OffsetRegNum, E))
579      return 0;
580    const AsmToken &RBracTok = Parser.getTok();
581    if (RBracTok.isNot(AsmToken::RBrac)) {
582      Error(RBracTok.getLoc(), "']' expected");
583      return 0;
584    }
585    E = RBracTok.getLoc();
586    Parser.Lex(); // Eat right bracket token.
587
588    const AsmToken &ExclaimTok = Parser.getTok();
589    if (ExclaimTok.is(AsmToken::Exclaim)) {
590      E = ExclaimTok.getLoc();
591      Writeback = true;
592      Parser.Lex(); // Eat exclaim token
593    }
594    return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
595                                 OffsetRegShifted, ShiftType, ShiftAmount,
596                                 Preindexed, Postindexed, Negative, Writeback,
597                                 S, E);
598  }
599  // The "[Rn" we have so far was not followed by a comma.
600  else if (Tok.is(AsmToken::RBrac)) {
601    // If there's anything other than the right brace, this is a post indexing
602    // addressing form.
603    E = Tok.getLoc();
604    Parser.Lex(); // Eat right bracket token.
605
606    int OffsetRegNum = 0;
607    bool OffsetRegShifted = false;
608    enum ShiftType ShiftType;
609    const MCExpr *ShiftAmount;
610    const MCExpr *Offset = 0;
611
612    const AsmToken &NextTok = Parser.getTok();
613    if (NextTok.isNot(AsmToken::EndOfStatement)) {
614      Postindexed = true;
615      Writeback = true;
616      if (NextTok.isNot(AsmToken::Comma)) {
617        Error(NextTok.getLoc(), "',' expected");
618        return 0;
619      }
620      Parser.Lex(); // Eat comma token.
621      if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
622                               ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
623                               E))
624        return 0;
625    }
626
627    return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
628                                 OffsetRegShifted, ShiftType, ShiftAmount,
629                                 Preindexed, Postindexed, Negative, Writeback,
630                                 S, E);
631  }
632
633  return 0;
634}
635
636/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
637/// we will parse the following (were +/- means that a plus or minus is
638/// optional):
639///   +/-Rm
640///   +/-Rm, shift
641///   #offset
642/// we return false on success or an error otherwise.
643bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
644                                        bool &OffsetRegShifted,
645                                        enum ShiftType &ShiftType,
646                                        const MCExpr *&ShiftAmount,
647                                        const MCExpr *&Offset,
648                                        bool &OffsetIsReg,
649                                        int &OffsetRegNum,
650                                        SMLoc &E) {
651  Negative = false;
652  OffsetRegShifted = false;
653  OffsetIsReg = false;
654  OffsetRegNum = -1;
655  const AsmToken &NextTok = Parser.getTok();
656  E = NextTok.getLoc();
657  if (NextTok.is(AsmToken::Plus))
658    Parser.Lex(); // Eat plus token.
659  else if (NextTok.is(AsmToken::Minus)) {
660    Negative = true;
661    Parser.Lex(); // Eat minus token
662  }
663  // See if there is a register following the "[Rn," or "[Rn]," we have so far.
664  const AsmToken &OffsetRegTok = Parser.getTok();
665  if (OffsetRegTok.is(AsmToken::Identifier)) {
666    SMLoc CurLoc = OffsetRegTok.getLoc();
667    OffsetRegNum = TryParseRegister();
668    if (OffsetRegNum != -1) {
669      OffsetIsReg = true;
670      E = CurLoc;
671    }
672  }
673
674  // If we parsed a register as the offset then there can be a shift after that.
675  if (OffsetRegNum != -1) {
676    // Look for a comma then a shift
677    const AsmToken &Tok = Parser.getTok();
678    if (Tok.is(AsmToken::Comma)) {
679      Parser.Lex(); // Eat comma token.
680
681      const AsmToken &Tok = Parser.getTok();
682      if (ParseShift(ShiftType, ShiftAmount, E))
683        return Error(Tok.getLoc(), "shift expected");
684      OffsetRegShifted = true;
685    }
686  }
687  else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
688    // Look for #offset following the "[Rn," or "[Rn],"
689    const AsmToken &HashTok = Parser.getTok();
690    if (HashTok.isNot(AsmToken::Hash))
691      return Error(HashTok.getLoc(), "'#' expected");
692
693    Parser.Lex(); // Eat hash token.
694
695    if (getParser().ParseExpression(Offset))
696     return true;
697    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
698  }
699  return false;
700}
701
702/// ParseShift as one of these two:
703///   ( lsl | lsr | asr | ror ) , # shift_amount
704///   rrx
705/// and returns true if it parses a shift otherwise it returns false.
706bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
707                              SMLoc &E) {
708  const AsmToken &Tok = Parser.getTok();
709  if (Tok.isNot(AsmToken::Identifier))
710    return true;
711  StringRef ShiftName = Tok.getString();
712  if (ShiftName == "lsl" || ShiftName == "LSL")
713    St = Lsl;
714  else if (ShiftName == "lsr" || ShiftName == "LSR")
715    St = Lsr;
716  else if (ShiftName == "asr" || ShiftName == "ASR")
717    St = Asr;
718  else if (ShiftName == "ror" || ShiftName == "ROR")
719    St = Ror;
720  else if (ShiftName == "rrx" || ShiftName == "RRX")
721    St = Rrx;
722  else
723    return true;
724  Parser.Lex(); // Eat shift type token.
725
726  // Rrx stands alone.
727  if (St == Rrx)
728    return false;
729
730  // Otherwise, there must be a '#' and a shift amount.
731  const AsmToken &HashTok = Parser.getTok();
732  if (HashTok.isNot(AsmToken::Hash))
733    return Error(HashTok.getLoc(), "'#' expected");
734  Parser.Lex(); // Eat hash token.
735
736  if (getParser().ParseExpression(ShiftAmount))
737    return true;
738
739  return false;
740}
741
742/// Parse a arm instruction operand.  For now this parses the operand regardless
743/// of the mnemonic.
744ARMOperand *ARMAsmParser::ParseOperand() {
745  SMLoc S, E;
746  switch (getLexer().getKind()) {
747  default:
748    Error(Parser.getTok().getLoc(), "unexpected token in operand");
749    return 0;
750  case AsmToken::Identifier:
751    if (ARMOperand *Op = TryParseRegisterWithWriteBack())
752      return Op;
753
754    // This was not a register so parse other operands that start with an
755    // identifier (like labels) as expressions and create them as immediates.
756    const MCExpr *IdVal;
757    S = Parser.getTok().getLoc();
758    if (getParser().ParseExpression(IdVal))
759      return 0;
760    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
761    return ARMOperand::CreateImm(IdVal, S, E);
762  case AsmToken::LBrac:
763    return ParseMemory();
764  case AsmToken::LCurly:
765    return ParseRegisterList();
766  case AsmToken::Hash:
767    // #42 -> immediate.
768    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
769    S = Parser.getTok().getLoc();
770    Parser.Lex();
771    const MCExpr *ImmVal;
772    if (getParser().ParseExpression(ImmVal))
773      return 0;
774    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
775    return ARMOperand::CreateImm(ImmVal, S, E);
776  }
777}
778
779/// Parse an arm instruction mnemonic followed by its operands.
780bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
781                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
782  // Create the leading tokens for the mnemonic, split by '.' characters.
783  size_t Start = 0, Next = Name.find('.');
784  StringRef Head = Name.slice(Start, Next);
785
786  // Determine the predicate, if any.
787  //
788  // FIXME: We need a way to check whether a prefix supports predication,
789  // otherwise we will end up with an ambiguity for instructions that happen to
790  // end with a predicate name.
791  // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
792  // indicates to update the condition codes. Those instructions have an
793  // additional immediate operand which encodes the prefix as reg0 or CPSR.
794  // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
795  // the SMMLS instruction.
796  unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
797    .Case("eq", ARMCC::EQ)
798    .Case("ne", ARMCC::NE)
799    .Case("hs", ARMCC::HS)
800    .Case("lo", ARMCC::LO)
801    .Case("mi", ARMCC::MI)
802    .Case("pl", ARMCC::PL)
803    .Case("vs", ARMCC::VS)
804    .Case("vc", ARMCC::VC)
805    .Case("hi", ARMCC::HI)
806    .Case("ls", ARMCC::LS)
807    .Case("ge", ARMCC::GE)
808    .Case("lt", ARMCC::LT)
809    .Case("gt", ARMCC::GT)
810    .Case("le", ARMCC::LE)
811    .Case("al", ARMCC::AL)
812    .Default(~0U);
813
814  if (CC == ~0U ||
815      (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
816    CC = ARMCC::AL;
817  } else {
818    Head = Head.slice(0, Head.size() - 2);
819  }
820
821  Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
822  // FIXME: Should only add this operand for predicated instructions
823  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
824
825  // Add the remaining tokens in the mnemonic.
826  while (Next != StringRef::npos) {
827    Start = Next;
828    Next = Name.find('.', Start + 1);
829    Head = Name.slice(Start, Next);
830
831    Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
832  }
833
834  // Read the remaining operands.
835  if (getLexer().isNot(AsmToken::EndOfStatement)) {
836    // Read the first operand.
837    if (ARMOperand *Op = ParseOperand())
838      Operands.push_back(Op);
839    else {
840      Parser.EatToEndOfStatement();
841      return true;
842    }
843
844    while (getLexer().is(AsmToken::Comma)) {
845      Parser.Lex();  // Eat the comma.
846
847      // Parse and remember the operand.
848      if (ARMOperand *Op = ParseOperand())
849        Operands.push_back(Op);
850      else {
851        Parser.EatToEndOfStatement();
852        return true;
853      }
854    }
855  }
856
857  if (getLexer().isNot(AsmToken::EndOfStatement)) {
858    Parser.EatToEndOfStatement();
859    return TokError("unexpected token in argument list");
860  }
861
862  Parser.Lex(); // Consume the EndOfStatement
863  return false;
864}
865
866bool ARMAsmParser::
867MatchAndEmitInstruction(SMLoc IDLoc,
868                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
869                        MCStreamer &Out) {
870  MCInst Inst;
871  unsigned ErrorInfo;
872  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
873  case Match_Success:
874    Out.EmitInstruction(Inst);
875    return false;
876  case Match_MissingFeature:
877    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
878    return true;
879  case Match_InvalidOperand: {
880    SMLoc ErrorLoc = IDLoc;
881    if (ErrorInfo != ~0U) {
882      if (ErrorInfo >= Operands.size())
883        return Error(IDLoc, "too few operands for instruction");
884
885      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
886      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
887    }
888
889    return Error(ErrorLoc, "invalid operand for instruction");
890  }
891  case Match_MnemonicFail:
892    return Error(IDLoc, "unrecognized instruction mnemonic");
893  }
894
895  llvm_unreachable("Implement any new match types added!");
896  return true;
897}
898
899/// ParseDirective parses the arm specific directives
900bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
901  StringRef IDVal = DirectiveID.getIdentifier();
902  if (IDVal == ".word")
903    return ParseDirectiveWord(4, DirectiveID.getLoc());
904  else if (IDVal == ".thumb")
905    return ParseDirectiveThumb(DirectiveID.getLoc());
906  else if (IDVal == ".thumb_func")
907    return ParseDirectiveThumbFunc(DirectiveID.getLoc());
908  else if (IDVal == ".code")
909    return ParseDirectiveCode(DirectiveID.getLoc());
910  else if (IDVal == ".syntax")
911    return ParseDirectiveSyntax(DirectiveID.getLoc());
912  return true;
913}
914
915/// ParseDirectiveWord
916///  ::= .word [ expression (, expression)* ]
917bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
918  if (getLexer().isNot(AsmToken::EndOfStatement)) {
919    for (;;) {
920      const MCExpr *Value;
921      if (getParser().ParseExpression(Value))
922        return true;
923
924      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
925
926      if (getLexer().is(AsmToken::EndOfStatement))
927        break;
928
929      // FIXME: Improve diagnostic.
930      if (getLexer().isNot(AsmToken::Comma))
931        return Error(L, "unexpected token in directive");
932      Parser.Lex();
933    }
934  }
935
936  Parser.Lex();
937  return false;
938}
939
940/// ParseDirectiveThumb
941///  ::= .thumb
942bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
943  if (getLexer().isNot(AsmToken::EndOfStatement))
944    return Error(L, "unexpected token in directive");
945  Parser.Lex();
946
947  // TODO: set thumb mode
948  // TODO: tell the MC streamer the mode
949  // getParser().getStreamer().Emit???();
950  return false;
951}
952
953/// ParseDirectiveThumbFunc
954///  ::= .thumbfunc symbol_name
955bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
956  const AsmToken &Tok = Parser.getTok();
957  if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
958    return Error(L, "unexpected token in .thumb_func directive");
959  StringRef Name = Tok.getString();
960  Parser.Lex(); // Consume the identifier token.
961  if (getLexer().isNot(AsmToken::EndOfStatement))
962    return Error(L, "unexpected token in directive");
963  Parser.Lex();
964
965  // Mark symbol as a thumb symbol.
966  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
967  getParser().getStreamer().EmitThumbFunc(Func);
968  return false;
969}
970
971/// ParseDirectiveSyntax
972///  ::= .syntax unified | divided
973bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
974  const AsmToken &Tok = Parser.getTok();
975  if (Tok.isNot(AsmToken::Identifier))
976    return Error(L, "unexpected token in .syntax directive");
977  StringRef Mode = Tok.getString();
978  if (Mode == "unified" || Mode == "UNIFIED")
979    Parser.Lex();
980  else if (Mode == "divided" || Mode == "DIVIDED")
981    Parser.Lex();
982  else
983    return Error(L, "unrecognized syntax mode in .syntax directive");
984
985  if (getLexer().isNot(AsmToken::EndOfStatement))
986    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
987  Parser.Lex();
988
989  // TODO tell the MC streamer the mode
990  // getParser().getStreamer().Emit???();
991  return false;
992}
993
994/// ParseDirectiveCode
995///  ::= .code 16 | 32
996bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
997  const AsmToken &Tok = Parser.getTok();
998  if (Tok.isNot(AsmToken::Integer))
999    return Error(L, "unexpected token in .code directive");
1000  int64_t Val = Parser.getTok().getIntVal();
1001  if (Val == 16)
1002    Parser.Lex();
1003  else if (Val == 32)
1004    Parser.Lex();
1005  else
1006    return Error(L, "invalid operand to .code directive");
1007
1008  if (getLexer().isNot(AsmToken::EndOfStatement))
1009    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1010  Parser.Lex();
1011
1012  if (Val == 16)
1013    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
1014  else
1015    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1016
1017  return false;
1018}
1019
1020extern "C" void LLVMInitializeARMAsmLexer();
1021
1022/// Force static initialization.
1023extern "C" void LLVMInitializeARMAsmParser() {
1024  RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1025  RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1026  LLVMInitializeARMAsmLexer();
1027}
1028
1029#define GET_REGISTER_MATCHER
1030#define GET_MATCHER_IMPLEMENTATION
1031#include "ARMGenAsmMatcher.inc"
1032