ARMAsmParser.cpp revision 63553c77cd1cf3b204d955fb65350db087aaff1d 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  MCAsmParser &getParser() const { return Parser; }
48  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49
50  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
51  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52
53  int tryParseRegister();
54  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
55  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
56  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
57  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
58  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
59  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
60  const MCExpr *applyPrefixToExpr(const MCExpr *E,
61                                  MCSymbolRefExpr::VariantKind Variant);
62
63
64  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
65                              unsigned &ShiftAmount);
66  bool parseDirectiveWord(unsigned Size, SMLoc L);
67  bool parseDirectiveThumb(SMLoc L);
68  bool parseDirectiveThumbFunc(SMLoc L);
69  bool parseDirectiveCode(SMLoc L);
70  bool parseDirectiveSyntax(SMLoc L);
71
72  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
73                          bool &CarrySetting, unsigned &ProcessorIMod,
74                          StringRef &ITMask);
75  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
76                             bool &CanAcceptPredicationCode);
77
78  bool isThumb() const {
79    // FIXME: Can tablegen auto-generate this?
80    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
81  }
82  bool isThumbOne() const {
83    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
84  }
85  bool isThumbTwo() const {
86    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
87  }
88  bool hasV6Ops() const {
89    return STI.getFeatureBits() & ARM::HasV6Ops;
90  }
91  void SwitchMode() {
92    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
93    setAvailableFeatures(FB);
94  }
95
96  /// @name Auto-generated Match Functions
97  /// {
98
99#define GET_ASSEMBLER_HEADER
100#include "ARMGenAsmMatcher.inc"
101
102  /// }
103
104  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
105  OperandMatchResultTy parseCoprocNumOperand(
106    SmallVectorImpl<MCParsedAsmOperand*>&);
107  OperandMatchResultTy parseCoprocRegOperand(
108    SmallVectorImpl<MCParsedAsmOperand*>&);
109  OperandMatchResultTy parseMemBarrierOptOperand(
110    SmallVectorImpl<MCParsedAsmOperand*>&);
111  OperandMatchResultTy parseProcIFlagsOperand(
112    SmallVectorImpl<MCParsedAsmOperand*>&);
113  OperandMatchResultTy parseMSRMaskOperand(
114    SmallVectorImpl<MCParsedAsmOperand*>&);
115  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
116                                   StringRef Op, int Low, int High);
117  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
118    return parsePKHImm(O, "lsl", 0, 31);
119  }
120  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
121    return parsePKHImm(O, "asr", 1, 32);
122  }
123  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
124  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
125  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
126  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
127  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
128  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
129
130  // Asm Match Converter Methods
131  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
132                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
133  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
134                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
135  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
136                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
137  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
138                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
139  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
140                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
141  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
142                             const SmallVectorImpl<MCParsedAsmOperand*> &);
143  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
144                             const SmallVectorImpl<MCParsedAsmOperand*> &);
145  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
146                             const SmallVectorImpl<MCParsedAsmOperand*> &);
147  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
148                             const SmallVectorImpl<MCParsedAsmOperand*> &);
149  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
150                  const SmallVectorImpl<MCParsedAsmOperand*> &);
151  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
152                  const SmallVectorImpl<MCParsedAsmOperand*> &);
153  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
154                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
155  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
156                        const SmallVectorImpl<MCParsedAsmOperand*> &);
157
158  bool validateInstruction(MCInst &Inst,
159                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
160  void processInstruction(MCInst &Inst,
161                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
162  bool shouldOmitCCOutOperand(StringRef Mnemonic,
163                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
164
165public:
166  enum ARMMatchResultTy {
167    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
168    Match_RequiresV6,
169    Match_RequiresThumb2
170  };
171
172  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
173    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
174    MCAsmParserExtension::Initialize(_Parser);
175
176    // Initialize the set of available features.
177    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
178  }
179
180  // Implementation of the MCTargetAsmParser interface:
181  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
182  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
183                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
184  bool ParseDirective(AsmToken DirectiveID);
185
186  unsigned checkTargetMatchPredicate(MCInst &Inst);
187
188  bool MatchAndEmitInstruction(SMLoc IDLoc,
189                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
190                               MCStreamer &Out);
191};
192} // end anonymous namespace
193
194namespace {
195
196/// ARMOperand - Instances of this class represent a parsed ARM machine
197/// instruction.
198class ARMOperand : public MCParsedAsmOperand {
199  enum KindTy {
200    CondCode,
201    CCOut,
202    ITCondMask,
203    CoprocNum,
204    CoprocReg,
205    Immediate,
206    MemBarrierOpt,
207    Memory,
208    PostIndexRegister,
209    MSRMask,
210    ProcIFlags,
211    Register,
212    RegisterList,
213    DPRRegisterList,
214    SPRRegisterList,
215    ShiftedRegister,
216    ShiftedImmediate,
217    ShifterImmediate,
218    RotateImmediate,
219    BitfieldDescriptor,
220    Token
221  } Kind;
222
223  SMLoc StartLoc, EndLoc;
224  SmallVector<unsigned, 8> Registers;
225
226  union {
227    struct {
228      ARMCC::CondCodes Val;
229    } CC;
230
231    struct {
232      unsigned Val;
233    } Cop;
234
235    struct {
236      unsigned Mask:4;
237    } ITMask;
238
239    struct {
240      ARM_MB::MemBOpt Val;
241    } MBOpt;
242
243    struct {
244      ARM_PROC::IFlags Val;
245    } IFlags;
246
247    struct {
248      unsigned Val;
249    } MMask;
250
251    struct {
252      const char *Data;
253      unsigned Length;
254    } Tok;
255
256    struct {
257      unsigned RegNum;
258    } Reg;
259
260    struct {
261      const MCExpr *Val;
262    } Imm;
263
264    /// Combined record for all forms of ARM address expressions.
265    struct {
266      unsigned BaseRegNum;
267      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
268      // was specified.
269      const MCConstantExpr *OffsetImm;  // Offset immediate value
270      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
271      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
272      unsigned ShiftImm;      // shift for OffsetReg.
273      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
274    } Mem;
275
276    struct {
277      unsigned RegNum;
278      bool isAdd;
279      ARM_AM::ShiftOpc ShiftTy;
280      unsigned ShiftImm;
281    } PostIdxReg;
282
283    struct {
284      bool isASR;
285      unsigned Imm;
286    } ShifterImm;
287    struct {
288      ARM_AM::ShiftOpc ShiftTy;
289      unsigned SrcReg;
290      unsigned ShiftReg;
291      unsigned ShiftImm;
292    } RegShiftedReg;
293    struct {
294      ARM_AM::ShiftOpc ShiftTy;
295      unsigned SrcReg;
296      unsigned ShiftImm;
297    } RegShiftedImm;
298    struct {
299      unsigned Imm;
300    } RotImm;
301    struct {
302      unsigned LSB;
303      unsigned Width;
304    } Bitfield;
305  };
306
307  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
308public:
309  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
310    Kind = o.Kind;
311    StartLoc = o.StartLoc;
312    EndLoc = o.EndLoc;
313    switch (Kind) {
314    case CondCode:
315      CC = o.CC;
316      break;
317    case ITCondMask:
318      ITMask = o.ITMask;
319      break;
320    case Token:
321      Tok = o.Tok;
322      break;
323    case CCOut:
324    case Register:
325      Reg = o.Reg;
326      break;
327    case RegisterList:
328    case DPRRegisterList:
329    case SPRRegisterList:
330      Registers = o.Registers;
331      break;
332    case CoprocNum:
333    case CoprocReg:
334      Cop = o.Cop;
335      break;
336    case Immediate:
337      Imm = o.Imm;
338      break;
339    case MemBarrierOpt:
340      MBOpt = o.MBOpt;
341      break;
342    case Memory:
343      Mem = o.Mem;
344      break;
345    case PostIndexRegister:
346      PostIdxReg = o.PostIdxReg;
347      break;
348    case MSRMask:
349      MMask = o.MMask;
350      break;
351    case ProcIFlags:
352      IFlags = o.IFlags;
353      break;
354    case ShifterImmediate:
355      ShifterImm = o.ShifterImm;
356      break;
357    case ShiftedRegister:
358      RegShiftedReg = o.RegShiftedReg;
359      break;
360    case ShiftedImmediate:
361      RegShiftedImm = o.RegShiftedImm;
362      break;
363    case RotateImmediate:
364      RotImm = o.RotImm;
365      break;
366    case BitfieldDescriptor:
367      Bitfield = o.Bitfield;
368      break;
369    }
370  }
371
372  /// getStartLoc - Get the location of the first token of this operand.
373  SMLoc getStartLoc() const { return StartLoc; }
374  /// getEndLoc - Get the location of the last token of this operand.
375  SMLoc getEndLoc() const { return EndLoc; }
376
377  ARMCC::CondCodes getCondCode() const {
378    assert(Kind == CondCode && "Invalid access!");
379    return CC.Val;
380  }
381
382  unsigned getCoproc() const {
383    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
384    return Cop.Val;
385  }
386
387  StringRef getToken() const {
388    assert(Kind == Token && "Invalid access!");
389    return StringRef(Tok.Data, Tok.Length);
390  }
391
392  unsigned getReg() const {
393    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
394    return Reg.RegNum;
395  }
396
397  const SmallVectorImpl<unsigned> &getRegList() const {
398    assert((Kind == RegisterList || Kind == DPRRegisterList ||
399            Kind == SPRRegisterList) && "Invalid access!");
400    return Registers;
401  }
402
403  const MCExpr *getImm() const {
404    assert(Kind == Immediate && "Invalid access!");
405    return Imm.Val;
406  }
407
408  ARM_MB::MemBOpt getMemBarrierOpt() const {
409    assert(Kind == MemBarrierOpt && "Invalid access!");
410    return MBOpt.Val;
411  }
412
413  ARM_PROC::IFlags getProcIFlags() const {
414    assert(Kind == ProcIFlags && "Invalid access!");
415    return IFlags.Val;
416  }
417
418  unsigned getMSRMask() const {
419    assert(Kind == MSRMask && "Invalid access!");
420    return MMask.Val;
421  }
422
423  bool isCoprocNum() const { return Kind == CoprocNum; }
424  bool isCoprocReg() const { return Kind == CoprocReg; }
425  bool isCondCode() const { return Kind == CondCode; }
426  bool isCCOut() const { return Kind == CCOut; }
427  bool isITMask() const { return Kind == ITCondMask; }
428  bool isITCondCode() const { return Kind == CondCode; }
429  bool isImm() const { return Kind == Immediate; }
430  bool isImm0_1020s4() const {
431    if (Kind != Immediate)
432      return false;
433    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
434    if (!CE) return false;
435    int64_t Value = CE->getValue();
436    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
437  }
438  bool isImm0_508s4() const {
439    if (Kind != Immediate)
440      return false;
441    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
442    if (!CE) return false;
443    int64_t Value = CE->getValue();
444    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
445  }
446  bool isImm0_255() const {
447    if (Kind != Immediate)
448      return false;
449    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
450    if (!CE) return false;
451    int64_t Value = CE->getValue();
452    return Value >= 0 && Value < 256;
453  }
454  bool isImm0_7() const {
455    if (Kind != Immediate)
456      return false;
457    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
458    if (!CE) return false;
459    int64_t Value = CE->getValue();
460    return Value >= 0 && Value < 8;
461  }
462  bool isImm0_15() const {
463    if (Kind != Immediate)
464      return false;
465    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
466    if (!CE) return false;
467    int64_t Value = CE->getValue();
468    return Value >= 0 && Value < 16;
469  }
470  bool isImm0_31() const {
471    if (Kind != Immediate)
472      return false;
473    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474    if (!CE) return false;
475    int64_t Value = CE->getValue();
476    return Value >= 0 && Value < 32;
477  }
478  bool isImm1_16() const {
479    if (Kind != Immediate)
480      return false;
481    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
482    if (!CE) return false;
483    int64_t Value = CE->getValue();
484    return Value > 0 && Value < 17;
485  }
486  bool isImm1_32() const {
487    if (Kind != Immediate)
488      return false;
489    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
490    if (!CE) return false;
491    int64_t Value = CE->getValue();
492    return Value > 0 && Value < 33;
493  }
494  bool isImm0_65535() const {
495    if (Kind != Immediate)
496      return false;
497    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
498    if (!CE) return false;
499    int64_t Value = CE->getValue();
500    return Value >= 0 && Value < 65536;
501  }
502  bool isImm0_65535Expr() const {
503    if (Kind != Immediate)
504      return false;
505    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
506    // If it's not a constant expression, it'll generate a fixup and be
507    // handled later.
508    if (!CE) return true;
509    int64_t Value = CE->getValue();
510    return Value >= 0 && Value < 65536;
511  }
512  bool isImm24bit() const {
513    if (Kind != Immediate)
514      return false;
515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516    if (!CE) return false;
517    int64_t Value = CE->getValue();
518    return Value >= 0 && Value <= 0xffffff;
519  }
520  bool isImmThumbSR() const {
521    if (Kind != Immediate)
522      return false;
523    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
524    if (!CE) return false;
525    int64_t Value = CE->getValue();
526    return Value > 0 && Value < 33;
527  }
528  bool isPKHLSLImm() const {
529    if (Kind != Immediate)
530      return false;
531    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
532    if (!CE) return false;
533    int64_t Value = CE->getValue();
534    return Value >= 0 && Value < 32;
535  }
536  bool isPKHASRImm() const {
537    if (Kind != Immediate)
538      return false;
539    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
540    if (!CE) return false;
541    int64_t Value = CE->getValue();
542    return Value > 0 && Value <= 32;
543  }
544  bool isARMSOImm() const {
545    if (Kind != Immediate)
546      return false;
547    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
548    if (!CE) return false;
549    int64_t Value = CE->getValue();
550    return ARM_AM::getSOImmVal(Value) != -1;
551  }
552  bool isT2SOImm() const {
553    if (Kind != Immediate)
554      return false;
555    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
556    if (!CE) return false;
557    int64_t Value = CE->getValue();
558    return ARM_AM::getT2SOImmVal(Value) != -1;
559  }
560  bool isSetEndImm() const {
561    if (Kind != Immediate)
562      return false;
563    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564    if (!CE) return false;
565    int64_t Value = CE->getValue();
566    return Value == 1 || Value == 0;
567  }
568  bool isReg() const { return Kind == Register; }
569  bool isRegList() const { return Kind == RegisterList; }
570  bool isDPRRegList() const { return Kind == DPRRegisterList; }
571  bool isSPRRegList() const { return Kind == SPRRegisterList; }
572  bool isToken() const { return Kind == Token; }
573  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
574  bool isMemory() const { return Kind == Memory; }
575  bool isShifterImm() const { return Kind == ShifterImmediate; }
576  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
577  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
578  bool isRotImm() const { return Kind == RotateImmediate; }
579  bool isBitfield() const { return Kind == BitfieldDescriptor; }
580  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
581  bool isPostIdxReg() const {
582    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
583  }
584  bool isMemNoOffset() const {
585    if (Kind != Memory)
586      return false;
587    // No offset of any kind.
588    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
589  }
590  bool isAddrMode2() const {
591    if (Kind != Memory)
592      return false;
593    // Check for register offset.
594    if (Mem.OffsetRegNum) return true;
595    // Immediate offset in range [-4095, 4095].
596    if (!Mem.OffsetImm) return true;
597    int64_t Val = Mem.OffsetImm->getValue();
598    return Val > -4096 && Val < 4096;
599  }
600  bool isAM2OffsetImm() const {
601    if (Kind != Immediate)
602      return false;
603    // Immediate offset in range [-4095, 4095].
604    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
605    if (!CE) return false;
606    int64_t Val = CE->getValue();
607    return Val > -4096 && Val < 4096;
608  }
609  bool isAddrMode3() const {
610    if (Kind != Memory)
611      return false;
612    // No shifts are legal for AM3.
613    if (Mem.ShiftType != ARM_AM::no_shift) return false;
614    // Check for register offset.
615    if (Mem.OffsetRegNum) return true;
616    // Immediate offset in range [-255, 255].
617    if (!Mem.OffsetImm) return true;
618    int64_t Val = Mem.OffsetImm->getValue();
619    return Val > -256 && Val < 256;
620  }
621  bool isAM3Offset() const {
622    if (Kind != Immediate && Kind != PostIndexRegister)
623      return false;
624    if (Kind == PostIndexRegister)
625      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
626    // Immediate offset in range [-255, 255].
627    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
628    if (!CE) return false;
629    int64_t Val = CE->getValue();
630    // Special case, #-0 is INT32_MIN.
631    return (Val > -256 && Val < 256) || Val == INT32_MIN;
632  }
633  bool isAddrMode5() const {
634    if (Kind != Memory)
635      return false;
636    // Check for register offset.
637    if (Mem.OffsetRegNum) return false;
638    // Immediate offset in range [-1020, 1020] and a multiple of 4.
639    if (!Mem.OffsetImm) return true;
640    int64_t Val = Mem.OffsetImm->getValue();
641    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
642  }
643  bool isMemRegOffset() const {
644    if (Kind != Memory || !Mem.OffsetRegNum)
645      return false;
646    return true;
647  }
648  bool isMemThumbRR() const {
649    // Thumb reg+reg addressing is simple. Just two registers, a base and
650    // an offset. No shifts, negations or any other complicating factors.
651    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
652        Mem.ShiftType != ARM_AM::no_shift)
653      return false;
654    return isARMLowRegister(Mem.BaseRegNum) &&
655      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
656  }
657  bool isMemThumbRIs4() const {
658    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
659        !isARMLowRegister(Mem.BaseRegNum))
660      return false;
661    // Immediate offset, multiple of 4 in range [0, 124].
662    if (!Mem.OffsetImm) return true;
663    int64_t Val = Mem.OffsetImm->getValue();
664    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
665  }
666  bool isMemThumbRIs2() const {
667    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
668        !isARMLowRegister(Mem.BaseRegNum))
669      return false;
670    // Immediate offset, multiple of 4 in range [0, 62].
671    if (!Mem.OffsetImm) return true;
672    int64_t Val = Mem.OffsetImm->getValue();
673    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
674  }
675  bool isMemThumbRIs1() const {
676    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
677        !isARMLowRegister(Mem.BaseRegNum))
678      return false;
679    // Immediate offset in range [0, 31].
680    if (!Mem.OffsetImm) return true;
681    int64_t Val = Mem.OffsetImm->getValue();
682    return Val >= 0 && Val <= 31;
683  }
684  bool isMemThumbSPI() const {
685    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
686      return false;
687    // Immediate offset, multiple of 4 in range [0, 1020].
688    if (!Mem.OffsetImm) return true;
689    int64_t Val = Mem.OffsetImm->getValue();
690    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
691  }
692  bool isMemImm8Offset() const {
693    if (Kind != Memory || Mem.OffsetRegNum != 0)
694      return false;
695    // Immediate offset in range [-255, 255].
696    if (!Mem.OffsetImm) return true;
697    int64_t Val = Mem.OffsetImm->getValue();
698    return Val > -256 && Val < 256;
699  }
700  bool isMemImm12Offset() const {
701    // If we have an immediate that's not a constant, treat it as a label
702    // reference needing a fixup. If it is a constant, it's something else
703    // and we reject it.
704    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
705      return true;
706
707    if (Kind != Memory || Mem.OffsetRegNum != 0)
708      return false;
709    // Immediate offset in range [-4095, 4095].
710    if (!Mem.OffsetImm) return true;
711    int64_t Val = Mem.OffsetImm->getValue();
712    return Val > -4096 && Val < 4096;
713  }
714  bool isPostIdxImm8() const {
715    if (Kind != Immediate)
716      return false;
717    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
718    if (!CE) return false;
719    int64_t Val = CE->getValue();
720    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
721  }
722
723  bool isMSRMask() const { return Kind == MSRMask; }
724  bool isProcIFlags() const { return Kind == ProcIFlags; }
725
726  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
727    // Add as immediates when possible.  Null MCExpr = 0.
728    if (Expr == 0)
729      Inst.addOperand(MCOperand::CreateImm(0));
730    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
731      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
732    else
733      Inst.addOperand(MCOperand::CreateExpr(Expr));
734  }
735
736  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
737    assert(N == 2 && "Invalid number of operands!");
738    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
739    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
740    Inst.addOperand(MCOperand::CreateReg(RegNum));
741  }
742
743  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
744    assert(N == 1 && "Invalid number of operands!");
745    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
746  }
747
748  void addITMaskOperands(MCInst &Inst, unsigned N) const {
749    assert(N == 1 && "Invalid number of operands!");
750    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
751  }
752
753  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
754    assert(N == 1 && "Invalid number of operands!");
755    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
756  }
757
758  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
759    assert(N == 1 && "Invalid number of operands!");
760    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
761  }
762
763  void addCCOutOperands(MCInst &Inst, unsigned N) const {
764    assert(N == 1 && "Invalid number of operands!");
765    Inst.addOperand(MCOperand::CreateReg(getReg()));
766  }
767
768  void addRegOperands(MCInst &Inst, unsigned N) const {
769    assert(N == 1 && "Invalid number of operands!");
770    Inst.addOperand(MCOperand::CreateReg(getReg()));
771  }
772
773  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
774    assert(N == 3 && "Invalid number of operands!");
775    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
776    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
777    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
778    Inst.addOperand(MCOperand::CreateImm(
779      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
780  }
781
782  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
783    assert(N == 2 && "Invalid number of operands!");
784    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
785    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
786    Inst.addOperand(MCOperand::CreateImm(
787      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
788  }
789
790
791  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
792    assert(N == 1 && "Invalid number of operands!");
793    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
794                                         ShifterImm.Imm));
795  }
796
797  void addRegListOperands(MCInst &Inst, unsigned N) const {
798    assert(N == 1 && "Invalid number of operands!");
799    const SmallVectorImpl<unsigned> &RegList = getRegList();
800    for (SmallVectorImpl<unsigned>::const_iterator
801           I = RegList.begin(), E = RegList.end(); I != E; ++I)
802      Inst.addOperand(MCOperand::CreateReg(*I));
803  }
804
805  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
806    addRegListOperands(Inst, N);
807  }
808
809  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
810    addRegListOperands(Inst, N);
811  }
812
813  void addRotImmOperands(MCInst &Inst, unsigned N) const {
814    assert(N == 1 && "Invalid number of operands!");
815    // Encoded as val>>3. The printer handles display as 8, 16, 24.
816    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
817  }
818
819  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
820    assert(N == 1 && "Invalid number of operands!");
821    // Munge the lsb/width into a bitfield mask.
822    unsigned lsb = Bitfield.LSB;
823    unsigned width = Bitfield.Width;
824    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
825    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
826                      (32 - (lsb + width)));
827    Inst.addOperand(MCOperand::CreateImm(Mask));
828  }
829
830  void addImmOperands(MCInst &Inst, unsigned N) const {
831    assert(N == 1 && "Invalid number of operands!");
832    addExpr(Inst, getImm());
833  }
834
835  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
836    assert(N == 1 && "Invalid number of operands!");
837    // The immediate is scaled by four in the encoding and is stored
838    // in the MCInst as such. Lop off the low two bits here.
839    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
840    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
841  }
842
843  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
844    assert(N == 1 && "Invalid number of operands!");
845    // The immediate is scaled by four in the encoding and is stored
846    // in the MCInst as such. Lop off the low two bits here.
847    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
849  }
850
851  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
852    assert(N == 1 && "Invalid number of operands!");
853    addExpr(Inst, getImm());
854  }
855
856  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
857    assert(N == 1 && "Invalid number of operands!");
858    addExpr(Inst, getImm());
859  }
860
861  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
862    assert(N == 1 && "Invalid number of operands!");
863    addExpr(Inst, getImm());
864  }
865
866  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
867    assert(N == 1 && "Invalid number of operands!");
868    addExpr(Inst, getImm());
869  }
870
871  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
872    assert(N == 1 && "Invalid number of operands!");
873    // The constant encodes as the immediate-1, and we store in the instruction
874    // the bits as encoded, so subtract off one here.
875    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
877  }
878
879  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
880    assert(N == 1 && "Invalid number of operands!");
881    // The constant encodes as the immediate-1, and we store in the instruction
882    // the bits as encoded, so subtract off one here.
883    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
885  }
886
887  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
888    assert(N == 1 && "Invalid number of operands!");
889    addExpr(Inst, getImm());
890  }
891
892  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
893    assert(N == 1 && "Invalid number of operands!");
894    addExpr(Inst, getImm());
895  }
896
897  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
898    assert(N == 1 && "Invalid number of operands!");
899    addExpr(Inst, getImm());
900  }
901
902  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
903    assert(N == 1 && "Invalid number of operands!");
904    // The constant encodes as the immediate, except for 32, which encodes as
905    // zero.
906    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
907    unsigned Imm = CE->getValue();
908    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
909  }
910
911  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
912    assert(N == 1 && "Invalid number of operands!");
913    addExpr(Inst, getImm());
914  }
915
916  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
917    assert(N == 1 && "Invalid number of operands!");
918    // An ASR value of 32 encodes as 0, so that's how we want to add it to
919    // the instruction as well.
920    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
921    int Val = CE->getValue();
922    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
923  }
924
925  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
926    assert(N == 1 && "Invalid number of operands!");
927    addExpr(Inst, getImm());
928  }
929
930  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
931    assert(N == 1 && "Invalid number of operands!");
932    addExpr(Inst, getImm());
933  }
934
935  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
936    assert(N == 1 && "Invalid number of operands!");
937    addExpr(Inst, getImm());
938  }
939
940  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
941    assert(N == 1 && "Invalid number of operands!");
942    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
943  }
944
945  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
946    assert(N == 1 && "Invalid number of operands!");
947    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
948  }
949
950  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
951    assert(N == 3 && "Invalid number of operands!");
952    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
953    if (!Mem.OffsetRegNum) {
954      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
955      // Special case for #-0
956      if (Val == INT32_MIN) Val = 0;
957      if (Val < 0) Val = -Val;
958      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
959    } else {
960      // For register offset, we encode the shift type and negation flag
961      // here.
962      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
963                              Mem.ShiftImm, Mem.ShiftType);
964    }
965    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
966    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
967    Inst.addOperand(MCOperand::CreateImm(Val));
968  }
969
970  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
971    assert(N == 2 && "Invalid number of operands!");
972    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973    assert(CE && "non-constant AM2OffsetImm operand!");
974    int32_t Val = CE->getValue();
975    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
976    // Special case for #-0
977    if (Val == INT32_MIN) Val = 0;
978    if (Val < 0) Val = -Val;
979    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
980    Inst.addOperand(MCOperand::CreateReg(0));
981    Inst.addOperand(MCOperand::CreateImm(Val));
982  }
983
984  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
985    assert(N == 3 && "Invalid number of operands!");
986    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
987    if (!Mem.OffsetRegNum) {
988      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
989      // Special case for #-0
990      if (Val == INT32_MIN) Val = 0;
991      if (Val < 0) Val = -Val;
992      Val = ARM_AM::getAM3Opc(AddSub, Val);
993    } else {
994      // For register offset, we encode the shift type and negation flag
995      // here.
996      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
997    }
998    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
999    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1000    Inst.addOperand(MCOperand::CreateImm(Val));
1001  }
1002
1003  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1004    assert(N == 2 && "Invalid number of operands!");
1005    if (Kind == PostIndexRegister) {
1006      int32_t Val =
1007        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1008      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1009      Inst.addOperand(MCOperand::CreateImm(Val));
1010      return;
1011    }
1012
1013    // Constant offset.
1014    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1015    int32_t Val = CE->getValue();
1016    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1017    // Special case for #-0
1018    if (Val == INT32_MIN) Val = 0;
1019    if (Val < 0) Val = -Val;
1020    Val = ARM_AM::getAM3Opc(AddSub, Val);
1021    Inst.addOperand(MCOperand::CreateReg(0));
1022    Inst.addOperand(MCOperand::CreateImm(Val));
1023  }
1024
1025  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1026    assert(N == 2 && "Invalid number of operands!");
1027    // The lower two bits are always zero and as such are not encoded.
1028    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1029    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1030    // Special case for #-0
1031    if (Val == INT32_MIN) Val = 0;
1032    if (Val < 0) Val = -Val;
1033    Val = ARM_AM::getAM5Opc(AddSub, Val);
1034    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1035    Inst.addOperand(MCOperand::CreateImm(Val));
1036  }
1037
1038  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1039    assert(N == 2 && "Invalid number of operands!");
1040    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1041    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1042    Inst.addOperand(MCOperand::CreateImm(Val));
1043  }
1044
1045  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1046    assert(N == 2 && "Invalid number of operands!");
1047    // If this is an immediate, it's a label reference.
1048    if (Kind == Immediate) {
1049      addExpr(Inst, getImm());
1050      Inst.addOperand(MCOperand::CreateImm(0));
1051      return;
1052    }
1053
1054    // Otherwise, it's a normal memory reg+offset.
1055    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1056    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1057    Inst.addOperand(MCOperand::CreateImm(Val));
1058  }
1059
1060  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1061    assert(N == 3 && "Invalid number of operands!");
1062    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1063                                     Mem.ShiftImm, Mem.ShiftType);
1064    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1065    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1066    Inst.addOperand(MCOperand::CreateImm(Val));
1067  }
1068
1069  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1070    assert(N == 2 && "Invalid number of operands!");
1071    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1072    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1073  }
1074
1075  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1076    assert(N == 2 && "Invalid number of operands!");
1077    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1078    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1079    Inst.addOperand(MCOperand::CreateImm(Val));
1080  }
1081
1082  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1083    assert(N == 2 && "Invalid number of operands!");
1084    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1085    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1086    Inst.addOperand(MCOperand::CreateImm(Val));
1087  }
1088
1089  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1090    assert(N == 2 && "Invalid number of operands!");
1091    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1092    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1093    Inst.addOperand(MCOperand::CreateImm(Val));
1094  }
1095
1096  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1097    assert(N == 2 && "Invalid number of operands!");
1098    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1099    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1100    Inst.addOperand(MCOperand::CreateImm(Val));
1101  }
1102
1103  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1104    assert(N == 1 && "Invalid number of operands!");
1105    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1106    assert(CE && "non-constant post-idx-imm8 operand!");
1107    int Imm = CE->getValue();
1108    bool isAdd = Imm >= 0;
1109    if (Imm == INT32_MIN) Imm = 0;
1110    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1111    Inst.addOperand(MCOperand::CreateImm(Imm));
1112  }
1113
1114  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1115    assert(N == 2 && "Invalid number of operands!");
1116    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1117    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1118  }
1119
1120  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1121    assert(N == 2 && "Invalid number of operands!");
1122    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1123    // The sign, shift type, and shift amount are encoded in a single operand
1124    // using the AM2 encoding helpers.
1125    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1126    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1127                                     PostIdxReg.ShiftTy);
1128    Inst.addOperand(MCOperand::CreateImm(Imm));
1129  }
1130
1131  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1132    assert(N == 1 && "Invalid number of operands!");
1133    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1134  }
1135
1136  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1137    assert(N == 1 && "Invalid number of operands!");
1138    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1139  }
1140
1141  virtual void print(raw_ostream &OS) const;
1142
1143  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1144    ARMOperand *Op = new ARMOperand(ITCondMask);
1145    Op->ITMask.Mask = Mask;
1146    Op->StartLoc = S;
1147    Op->EndLoc = S;
1148    return Op;
1149  }
1150
1151  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1152    ARMOperand *Op = new ARMOperand(CondCode);
1153    Op->CC.Val = CC;
1154    Op->StartLoc = S;
1155    Op->EndLoc = S;
1156    return Op;
1157  }
1158
1159  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1160    ARMOperand *Op = new ARMOperand(CoprocNum);
1161    Op->Cop.Val = CopVal;
1162    Op->StartLoc = S;
1163    Op->EndLoc = S;
1164    return Op;
1165  }
1166
1167  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1168    ARMOperand *Op = new ARMOperand(CoprocReg);
1169    Op->Cop.Val = CopVal;
1170    Op->StartLoc = S;
1171    Op->EndLoc = S;
1172    return Op;
1173  }
1174
1175  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1176    ARMOperand *Op = new ARMOperand(CCOut);
1177    Op->Reg.RegNum = RegNum;
1178    Op->StartLoc = S;
1179    Op->EndLoc = S;
1180    return Op;
1181  }
1182
1183  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1184    ARMOperand *Op = new ARMOperand(Token);
1185    Op->Tok.Data = Str.data();
1186    Op->Tok.Length = Str.size();
1187    Op->StartLoc = S;
1188    Op->EndLoc = S;
1189    return Op;
1190  }
1191
1192  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1193    ARMOperand *Op = new ARMOperand(Register);
1194    Op->Reg.RegNum = RegNum;
1195    Op->StartLoc = S;
1196    Op->EndLoc = E;
1197    return Op;
1198  }
1199
1200  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1201                                           unsigned SrcReg,
1202                                           unsigned ShiftReg,
1203                                           unsigned ShiftImm,
1204                                           SMLoc S, SMLoc E) {
1205    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1206    Op->RegShiftedReg.ShiftTy = ShTy;
1207    Op->RegShiftedReg.SrcReg = SrcReg;
1208    Op->RegShiftedReg.ShiftReg = ShiftReg;
1209    Op->RegShiftedReg.ShiftImm = ShiftImm;
1210    Op->StartLoc = S;
1211    Op->EndLoc = E;
1212    return Op;
1213  }
1214
1215  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1216                                            unsigned SrcReg,
1217                                            unsigned ShiftImm,
1218                                            SMLoc S, SMLoc E) {
1219    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1220    Op->RegShiftedImm.ShiftTy = ShTy;
1221    Op->RegShiftedImm.SrcReg = SrcReg;
1222    Op->RegShiftedImm.ShiftImm = ShiftImm;
1223    Op->StartLoc = S;
1224    Op->EndLoc = E;
1225    return Op;
1226  }
1227
1228  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1229                                   SMLoc S, SMLoc E) {
1230    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1231    Op->ShifterImm.isASR = isASR;
1232    Op->ShifterImm.Imm = Imm;
1233    Op->StartLoc = S;
1234    Op->EndLoc = E;
1235    return Op;
1236  }
1237
1238  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1239    ARMOperand *Op = new ARMOperand(RotateImmediate);
1240    Op->RotImm.Imm = Imm;
1241    Op->StartLoc = S;
1242    Op->EndLoc = E;
1243    return Op;
1244  }
1245
1246  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1247                                    SMLoc S, SMLoc E) {
1248    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1249    Op->Bitfield.LSB = LSB;
1250    Op->Bitfield.Width = Width;
1251    Op->StartLoc = S;
1252    Op->EndLoc = E;
1253    return Op;
1254  }
1255
1256  static ARMOperand *
1257  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1258                SMLoc StartLoc, SMLoc EndLoc) {
1259    KindTy Kind = RegisterList;
1260
1261    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1262        contains(Regs.front().first))
1263      Kind = DPRRegisterList;
1264    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1265             contains(Regs.front().first))
1266      Kind = SPRRegisterList;
1267
1268    ARMOperand *Op = new ARMOperand(Kind);
1269    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1270           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1271      Op->Registers.push_back(I->first);
1272    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1273    Op->StartLoc = StartLoc;
1274    Op->EndLoc = EndLoc;
1275    return Op;
1276  }
1277
1278  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1279    ARMOperand *Op = new ARMOperand(Immediate);
1280    Op->Imm.Val = Val;
1281    Op->StartLoc = S;
1282    Op->EndLoc = E;
1283    return Op;
1284  }
1285
1286  static ARMOperand *CreateMem(unsigned BaseRegNum,
1287                               const MCConstantExpr *OffsetImm,
1288                               unsigned OffsetRegNum,
1289                               ARM_AM::ShiftOpc ShiftType,
1290                               unsigned ShiftImm,
1291                               bool isNegative,
1292                               SMLoc S, SMLoc E) {
1293    ARMOperand *Op = new ARMOperand(Memory);
1294    Op->Mem.BaseRegNum = BaseRegNum;
1295    Op->Mem.OffsetImm = OffsetImm;
1296    Op->Mem.OffsetRegNum = OffsetRegNum;
1297    Op->Mem.ShiftType = ShiftType;
1298    Op->Mem.ShiftImm = ShiftImm;
1299    Op->Mem.isNegative = isNegative;
1300    Op->StartLoc = S;
1301    Op->EndLoc = E;
1302    return Op;
1303  }
1304
1305  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1306                                      ARM_AM::ShiftOpc ShiftTy,
1307                                      unsigned ShiftImm,
1308                                      SMLoc S, SMLoc E) {
1309    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1310    Op->PostIdxReg.RegNum = RegNum;
1311    Op->PostIdxReg.isAdd = isAdd;
1312    Op->PostIdxReg.ShiftTy = ShiftTy;
1313    Op->PostIdxReg.ShiftImm = ShiftImm;
1314    Op->StartLoc = S;
1315    Op->EndLoc = E;
1316    return Op;
1317  }
1318
1319  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1320    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1321    Op->MBOpt.Val = Opt;
1322    Op->StartLoc = S;
1323    Op->EndLoc = S;
1324    return Op;
1325  }
1326
1327  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1328    ARMOperand *Op = new ARMOperand(ProcIFlags);
1329    Op->IFlags.Val = IFlags;
1330    Op->StartLoc = S;
1331    Op->EndLoc = S;
1332    return Op;
1333  }
1334
1335  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1336    ARMOperand *Op = new ARMOperand(MSRMask);
1337    Op->MMask.Val = MMask;
1338    Op->StartLoc = S;
1339    Op->EndLoc = S;
1340    return Op;
1341  }
1342};
1343
1344} // end anonymous namespace.
1345
1346void ARMOperand::print(raw_ostream &OS) const {
1347  switch (Kind) {
1348  case CondCode:
1349    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1350    break;
1351  case CCOut:
1352    OS << "<ccout " << getReg() << ">";
1353    break;
1354  case ITCondMask: {
1355    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1356      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1357      "(tee)", "(eee)" };
1358    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1359    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1360    break;
1361  }
1362  case CoprocNum:
1363    OS << "<coprocessor number: " << getCoproc() << ">";
1364    break;
1365  case CoprocReg:
1366    OS << "<coprocessor register: " << getCoproc() << ">";
1367    break;
1368  case MSRMask:
1369    OS << "<mask: " << getMSRMask() << ">";
1370    break;
1371  case Immediate:
1372    getImm()->print(OS);
1373    break;
1374  case MemBarrierOpt:
1375    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1376    break;
1377  case Memory:
1378    OS << "<memory "
1379       << " base:" << Mem.BaseRegNum;
1380    OS << ">";
1381    break;
1382  case PostIndexRegister:
1383    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1384       << PostIdxReg.RegNum;
1385    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1386      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1387         << PostIdxReg.ShiftImm;
1388    OS << ">";
1389    break;
1390  case ProcIFlags: {
1391    OS << "<ARM_PROC::";
1392    unsigned IFlags = getProcIFlags();
1393    for (int i=2; i >= 0; --i)
1394      if (IFlags & (1 << i))
1395        OS << ARM_PROC::IFlagsToString(1 << i);
1396    OS << ">";
1397    break;
1398  }
1399  case Register:
1400    OS << "<register " << getReg() << ">";
1401    break;
1402  case ShifterImmediate:
1403    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1404       << " #" << ShifterImm.Imm << ">";
1405    break;
1406  case ShiftedRegister:
1407    OS << "<so_reg_reg "
1408       << RegShiftedReg.SrcReg
1409       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1410       << ", " << RegShiftedReg.ShiftReg << ", "
1411       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1412       << ">";
1413    break;
1414  case ShiftedImmediate:
1415    OS << "<so_reg_imm "
1416       << RegShiftedImm.SrcReg
1417       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1418       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1419       << ">";
1420    break;
1421  case RotateImmediate:
1422    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1423    break;
1424  case BitfieldDescriptor:
1425    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1426       << ", width: " << Bitfield.Width << ">";
1427    break;
1428  case RegisterList:
1429  case DPRRegisterList:
1430  case SPRRegisterList: {
1431    OS << "<register_list ";
1432
1433    const SmallVectorImpl<unsigned> &RegList = getRegList();
1434    for (SmallVectorImpl<unsigned>::const_iterator
1435           I = RegList.begin(), E = RegList.end(); I != E; ) {
1436      OS << *I;
1437      if (++I < E) OS << ", ";
1438    }
1439
1440    OS << ">";
1441    break;
1442  }
1443  case Token:
1444    OS << "'" << getToken() << "'";
1445    break;
1446  }
1447}
1448
1449/// @name Auto-generated Match Functions
1450/// {
1451
1452static unsigned MatchRegisterName(StringRef Name);
1453
1454/// }
1455
1456bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1457                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1458  RegNo = tryParseRegister();
1459
1460  return (RegNo == (unsigned)-1);
1461}
1462
1463/// Try to parse a register name.  The token must be an Identifier when called,
1464/// and if it is a register name the token is eaten and the register number is
1465/// returned.  Otherwise return -1.
1466///
1467int ARMAsmParser::tryParseRegister() {
1468  const AsmToken &Tok = Parser.getTok();
1469  if (Tok.isNot(AsmToken::Identifier)) return -1;
1470
1471  // FIXME: Validate register for the current architecture; we have to do
1472  // validation later, so maybe there is no need for this here.
1473  std::string upperCase = Tok.getString().str();
1474  std::string lowerCase = LowercaseString(upperCase);
1475  unsigned RegNum = MatchRegisterName(lowerCase);
1476  if (!RegNum) {
1477    RegNum = StringSwitch<unsigned>(lowerCase)
1478      .Case("r13", ARM::SP)
1479      .Case("r14", ARM::LR)
1480      .Case("r15", ARM::PC)
1481      .Case("ip", ARM::R12)
1482      .Default(0);
1483  }
1484  if (!RegNum) return -1;
1485
1486  Parser.Lex(); // Eat identifier token.
1487  return RegNum;
1488}
1489
1490// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1491// If a recoverable error occurs, return 1. If an irrecoverable error
1492// occurs, return -1. An irrecoverable error is one where tokens have been
1493// consumed in the process of trying to parse the shifter (i.e., when it is
1494// indeed a shifter operand, but malformed).
1495int ARMAsmParser::tryParseShiftRegister(
1496                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1497  SMLoc S = Parser.getTok().getLoc();
1498  const AsmToken &Tok = Parser.getTok();
1499  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1500
1501  std::string upperCase = Tok.getString().str();
1502  std::string lowerCase = LowercaseString(upperCase);
1503  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1504      .Case("lsl", ARM_AM::lsl)
1505      .Case("lsr", ARM_AM::lsr)
1506      .Case("asr", ARM_AM::asr)
1507      .Case("ror", ARM_AM::ror)
1508      .Case("rrx", ARM_AM::rrx)
1509      .Default(ARM_AM::no_shift);
1510
1511  if (ShiftTy == ARM_AM::no_shift)
1512    return 1;
1513
1514  Parser.Lex(); // Eat the operator.
1515
1516  // The source register for the shift has already been added to the
1517  // operand list, so we need to pop it off and combine it into the shifted
1518  // register operand instead.
1519  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1520  if (!PrevOp->isReg())
1521    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1522  int SrcReg = PrevOp->getReg();
1523  int64_t Imm = 0;
1524  int ShiftReg = 0;
1525  if (ShiftTy == ARM_AM::rrx) {
1526    // RRX Doesn't have an explicit shift amount. The encoder expects
1527    // the shift register to be the same as the source register. Seems odd,
1528    // but OK.
1529    ShiftReg = SrcReg;
1530  } else {
1531    // Figure out if this is shifted by a constant or a register (for non-RRX).
1532    if (Parser.getTok().is(AsmToken::Hash)) {
1533      Parser.Lex(); // Eat hash.
1534      SMLoc ImmLoc = Parser.getTok().getLoc();
1535      const MCExpr *ShiftExpr = 0;
1536      if (getParser().ParseExpression(ShiftExpr)) {
1537        Error(ImmLoc, "invalid immediate shift value");
1538        return -1;
1539      }
1540      // The expression must be evaluatable as an immediate.
1541      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1542      if (!CE) {
1543        Error(ImmLoc, "invalid immediate shift value");
1544        return -1;
1545      }
1546      // Range check the immediate.
1547      // lsl, ror: 0 <= imm <= 31
1548      // lsr, asr: 0 <= imm <= 32
1549      Imm = CE->getValue();
1550      if (Imm < 0 ||
1551          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1552          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1553        Error(ImmLoc, "immediate shift value out of range");
1554        return -1;
1555      }
1556    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1557      ShiftReg = tryParseRegister();
1558      SMLoc L = Parser.getTok().getLoc();
1559      if (ShiftReg == -1) {
1560        Error (L, "expected immediate or register in shift operand");
1561        return -1;
1562      }
1563    } else {
1564      Error (Parser.getTok().getLoc(),
1565                    "expected immediate or register in shift operand");
1566      return -1;
1567    }
1568  }
1569
1570  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1571    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1572                                                         ShiftReg, Imm,
1573                                               S, Parser.getTok().getLoc()));
1574  else
1575    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1576                                               S, Parser.getTok().getLoc()));
1577
1578  return 0;
1579}
1580
1581
1582/// Try to parse a register name.  The token must be an Identifier when called.
1583/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1584/// if there is a "writeback". 'true' if it's not a register.
1585///
1586/// TODO this is likely to change to allow different register types and or to
1587/// parse for a specific register type.
1588bool ARMAsmParser::
1589tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1590  SMLoc S = Parser.getTok().getLoc();
1591  int RegNo = tryParseRegister();
1592  if (RegNo == -1)
1593    return true;
1594
1595  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1596
1597  const AsmToken &ExclaimTok = Parser.getTok();
1598  if (ExclaimTok.is(AsmToken::Exclaim)) {
1599    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1600                                               ExclaimTok.getLoc()));
1601    Parser.Lex(); // Eat exclaim token
1602  }
1603
1604  return false;
1605}
1606
1607/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1608/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1609/// "c5", ...
1610static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1611  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1612  // but efficient.
1613  switch (Name.size()) {
1614  default: break;
1615  case 2:
1616    if (Name[0] != CoprocOp)
1617      return -1;
1618    switch (Name[1]) {
1619    default:  return -1;
1620    case '0': return 0;
1621    case '1': return 1;
1622    case '2': return 2;
1623    case '3': return 3;
1624    case '4': return 4;
1625    case '5': return 5;
1626    case '6': return 6;
1627    case '7': return 7;
1628    case '8': return 8;
1629    case '9': return 9;
1630    }
1631    break;
1632  case 3:
1633    if (Name[0] != CoprocOp || Name[1] != '1')
1634      return -1;
1635    switch (Name[2]) {
1636    default:  return -1;
1637    case '0': return 10;
1638    case '1': return 11;
1639    case '2': return 12;
1640    case '3': return 13;
1641    case '4': return 14;
1642    case '5': return 15;
1643    }
1644    break;
1645  }
1646
1647  return -1;
1648}
1649
1650/// parseITCondCode - Try to parse a condition code for an IT instruction.
1651ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1652parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1653  SMLoc S = Parser.getTok().getLoc();
1654  const AsmToken &Tok = Parser.getTok();
1655  if (!Tok.is(AsmToken::Identifier))
1656    return MatchOperand_NoMatch;
1657  unsigned CC = StringSwitch<unsigned>(Tok.getString())
1658    .Case("eq", ARMCC::EQ)
1659    .Case("ne", ARMCC::NE)
1660    .Case("hs", ARMCC::HS)
1661    .Case("cs", ARMCC::HS)
1662    .Case("lo", ARMCC::LO)
1663    .Case("cc", ARMCC::LO)
1664    .Case("mi", ARMCC::MI)
1665    .Case("pl", ARMCC::PL)
1666    .Case("vs", ARMCC::VS)
1667    .Case("vc", ARMCC::VC)
1668    .Case("hi", ARMCC::HI)
1669    .Case("ls", ARMCC::LS)
1670    .Case("ge", ARMCC::GE)
1671    .Case("lt", ARMCC::LT)
1672    .Case("gt", ARMCC::GT)
1673    .Case("le", ARMCC::LE)
1674    .Case("al", ARMCC::AL)
1675    .Default(~0U);
1676  if (CC == ~0U)
1677    return MatchOperand_NoMatch;
1678  Parser.Lex(); // Eat the token.
1679
1680  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1681
1682  return MatchOperand_Success;
1683}
1684
1685/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1686/// token must be an Identifier when called, and if it is a coprocessor
1687/// number, the token is eaten and the operand is added to the operand list.
1688ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1689parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1690  SMLoc S = Parser.getTok().getLoc();
1691  const AsmToken &Tok = Parser.getTok();
1692  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1693
1694  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1695  if (Num == -1)
1696    return MatchOperand_NoMatch;
1697
1698  Parser.Lex(); // Eat identifier token.
1699  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1700  return MatchOperand_Success;
1701}
1702
1703/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1704/// token must be an Identifier when called, and if it is a coprocessor
1705/// number, the token is eaten and the operand is added to the operand list.
1706ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1707parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1708  SMLoc S = Parser.getTok().getLoc();
1709  const AsmToken &Tok = Parser.getTok();
1710  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1711
1712  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1713  if (Reg == -1)
1714    return MatchOperand_NoMatch;
1715
1716  Parser.Lex(); // Eat identifier token.
1717  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1718  return MatchOperand_Success;
1719}
1720
1721/// Parse a register list, return it if successful else return null.  The first
1722/// token must be a '{' when called.
1723bool ARMAsmParser::
1724parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1725  assert(Parser.getTok().is(AsmToken::LCurly) &&
1726         "Token is not a Left Curly Brace");
1727  SMLoc S = Parser.getTok().getLoc();
1728
1729  // Read the rest of the registers in the list.
1730  unsigned PrevRegNum = 0;
1731  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1732
1733  do {
1734    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1735    Parser.Lex(); // Eat non-identifier token.
1736
1737    const AsmToken &RegTok = Parser.getTok();
1738    SMLoc RegLoc = RegTok.getLoc();
1739    if (RegTok.isNot(AsmToken::Identifier)) {
1740      Error(RegLoc, "register expected");
1741      return true;
1742    }
1743
1744    int RegNum = tryParseRegister();
1745    if (RegNum == -1) {
1746      Error(RegLoc, "register expected");
1747      return true;
1748    }
1749
1750    if (IsRange) {
1751      int Reg = PrevRegNum;
1752      do {
1753        ++Reg;
1754        Registers.push_back(std::make_pair(Reg, RegLoc));
1755      } while (Reg != RegNum);
1756    } else {
1757      Registers.push_back(std::make_pair(RegNum, RegLoc));
1758    }
1759
1760    PrevRegNum = RegNum;
1761  } while (Parser.getTok().is(AsmToken::Comma) ||
1762           Parser.getTok().is(AsmToken::Minus));
1763
1764  // Process the right curly brace of the list.
1765  const AsmToken &RCurlyTok = Parser.getTok();
1766  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1767    Error(RCurlyTok.getLoc(), "'}' expected");
1768    return true;
1769  }
1770
1771  SMLoc E = RCurlyTok.getLoc();
1772  Parser.Lex(); // Eat right curly brace token.
1773
1774  // Verify the register list.
1775  bool EmittedWarning = false;
1776  unsigned HighRegNum = 0;
1777  BitVector RegMap(32);
1778  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1779    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1780    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1781
1782    if (RegMap[Reg]) {
1783      Error(RegInfo.second, "register duplicated in register list");
1784      return true;
1785    }
1786
1787    if (!EmittedWarning && Reg < HighRegNum)
1788      Warning(RegInfo.second,
1789              "register not in ascending order in register list");
1790
1791    RegMap.set(Reg);
1792    HighRegNum = std::max(Reg, HighRegNum);
1793  }
1794
1795  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1796  return false;
1797}
1798
1799/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1800ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1801parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1802  SMLoc S = Parser.getTok().getLoc();
1803  const AsmToken &Tok = Parser.getTok();
1804  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1805  StringRef OptStr = Tok.getString();
1806
1807  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1808    .Case("sy",    ARM_MB::SY)
1809    .Case("st",    ARM_MB::ST)
1810    .Case("sh",    ARM_MB::ISH)
1811    .Case("ish",   ARM_MB::ISH)
1812    .Case("shst",  ARM_MB::ISHST)
1813    .Case("ishst", ARM_MB::ISHST)
1814    .Case("nsh",   ARM_MB::NSH)
1815    .Case("un",    ARM_MB::NSH)
1816    .Case("nshst", ARM_MB::NSHST)
1817    .Case("unst",  ARM_MB::NSHST)
1818    .Case("osh",   ARM_MB::OSH)
1819    .Case("oshst", ARM_MB::OSHST)
1820    .Default(~0U);
1821
1822  if (Opt == ~0U)
1823    return MatchOperand_NoMatch;
1824
1825  Parser.Lex(); // Eat identifier token.
1826  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1827  return MatchOperand_Success;
1828}
1829
1830/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1831ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1832parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1833  SMLoc S = Parser.getTok().getLoc();
1834  const AsmToken &Tok = Parser.getTok();
1835  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1836  StringRef IFlagsStr = Tok.getString();
1837
1838  unsigned IFlags = 0;
1839  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1840    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1841    .Case("a", ARM_PROC::A)
1842    .Case("i", ARM_PROC::I)
1843    .Case("f", ARM_PROC::F)
1844    .Default(~0U);
1845
1846    // If some specific iflag is already set, it means that some letter is
1847    // present more than once, this is not acceptable.
1848    if (Flag == ~0U || (IFlags & Flag))
1849      return MatchOperand_NoMatch;
1850
1851    IFlags |= Flag;
1852  }
1853
1854  Parser.Lex(); // Eat identifier token.
1855  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1856  return MatchOperand_Success;
1857}
1858
1859/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1860ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1861parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1862  SMLoc S = Parser.getTok().getLoc();
1863  const AsmToken &Tok = Parser.getTok();
1864  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1865  StringRef Mask = Tok.getString();
1866
1867  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1868  size_t Start = 0, Next = Mask.find('_');
1869  StringRef Flags = "";
1870  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1871  if (Next != StringRef::npos)
1872    Flags = Mask.slice(Next+1, Mask.size());
1873
1874  // FlagsVal contains the complete mask:
1875  // 3-0: Mask
1876  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1877  unsigned FlagsVal = 0;
1878
1879  if (SpecReg == "apsr") {
1880    FlagsVal = StringSwitch<unsigned>(Flags)
1881    .Case("nzcvq",  0x8) // same as CPSR_f
1882    .Case("g",      0x4) // same as CPSR_s
1883    .Case("nzcvqg", 0xc) // same as CPSR_fs
1884    .Default(~0U);
1885
1886    if (FlagsVal == ~0U) {
1887      if (!Flags.empty())
1888        return MatchOperand_NoMatch;
1889      else
1890        FlagsVal = 0; // No flag
1891    }
1892  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1893    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1894      Flags = "fc";
1895    for (int i = 0, e = Flags.size(); i != e; ++i) {
1896      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1897      .Case("c", 1)
1898      .Case("x", 2)
1899      .Case("s", 4)
1900      .Case("f", 8)
1901      .Default(~0U);
1902
1903      // If some specific flag is already set, it means that some letter is
1904      // present more than once, this is not acceptable.
1905      if (FlagsVal == ~0U || (FlagsVal & Flag))
1906        return MatchOperand_NoMatch;
1907      FlagsVal |= Flag;
1908    }
1909  } else // No match for special register.
1910    return MatchOperand_NoMatch;
1911
1912  // Special register without flags are equivalent to "fc" flags.
1913  if (!FlagsVal)
1914    FlagsVal = 0x9;
1915
1916  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1917  if (SpecReg == "spsr")
1918    FlagsVal |= 16;
1919
1920  Parser.Lex(); // Eat identifier token.
1921  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1922  return MatchOperand_Success;
1923}
1924
1925ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1926parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1927            int Low, int High) {
1928  const AsmToken &Tok = Parser.getTok();
1929  if (Tok.isNot(AsmToken::Identifier)) {
1930    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1931    return MatchOperand_ParseFail;
1932  }
1933  StringRef ShiftName = Tok.getString();
1934  std::string LowerOp = LowercaseString(Op);
1935  std::string UpperOp = UppercaseString(Op);
1936  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1937    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1938    return MatchOperand_ParseFail;
1939  }
1940  Parser.Lex(); // Eat shift type token.
1941
1942  // There must be a '#' and a shift amount.
1943  if (Parser.getTok().isNot(AsmToken::Hash)) {
1944    Error(Parser.getTok().getLoc(), "'#' expected");
1945    return MatchOperand_ParseFail;
1946  }
1947  Parser.Lex(); // Eat hash token.
1948
1949  const MCExpr *ShiftAmount;
1950  SMLoc Loc = Parser.getTok().getLoc();
1951  if (getParser().ParseExpression(ShiftAmount)) {
1952    Error(Loc, "illegal expression");
1953    return MatchOperand_ParseFail;
1954  }
1955  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1956  if (!CE) {
1957    Error(Loc, "constant expression expected");
1958    return MatchOperand_ParseFail;
1959  }
1960  int Val = CE->getValue();
1961  if (Val < Low || Val > High) {
1962    Error(Loc, "immediate value out of range");
1963    return MatchOperand_ParseFail;
1964  }
1965
1966  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1967
1968  return MatchOperand_Success;
1969}
1970
1971ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1972parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1973  const AsmToken &Tok = Parser.getTok();
1974  SMLoc S = Tok.getLoc();
1975  if (Tok.isNot(AsmToken::Identifier)) {
1976    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1977    return MatchOperand_ParseFail;
1978  }
1979  int Val = StringSwitch<int>(Tok.getString())
1980    .Case("be", 1)
1981    .Case("le", 0)
1982    .Default(-1);
1983  Parser.Lex(); // Eat the token.
1984
1985  if (Val == -1) {
1986    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1987    return MatchOperand_ParseFail;
1988  }
1989  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1990                                                                  getContext()),
1991                                           S, Parser.getTok().getLoc()));
1992  return MatchOperand_Success;
1993}
1994
1995/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1996/// instructions. Legal values are:
1997///     lsl #n  'n' in [0,31]
1998///     asr #n  'n' in [1,32]
1999///             n == 32 encoded as n == 0.
2000ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2001parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2002  const AsmToken &Tok = Parser.getTok();
2003  SMLoc S = Tok.getLoc();
2004  if (Tok.isNot(AsmToken::Identifier)) {
2005    Error(S, "shift operator 'asr' or 'lsl' expected");
2006    return MatchOperand_ParseFail;
2007  }
2008  StringRef ShiftName = Tok.getString();
2009  bool isASR;
2010  if (ShiftName == "lsl" || ShiftName == "LSL")
2011    isASR = false;
2012  else if (ShiftName == "asr" || ShiftName == "ASR")
2013    isASR = true;
2014  else {
2015    Error(S, "shift operator 'asr' or 'lsl' expected");
2016    return MatchOperand_ParseFail;
2017  }
2018  Parser.Lex(); // Eat the operator.
2019
2020  // A '#' and a shift amount.
2021  if (Parser.getTok().isNot(AsmToken::Hash)) {
2022    Error(Parser.getTok().getLoc(), "'#' expected");
2023    return MatchOperand_ParseFail;
2024  }
2025  Parser.Lex(); // Eat hash token.
2026
2027  const MCExpr *ShiftAmount;
2028  SMLoc E = Parser.getTok().getLoc();
2029  if (getParser().ParseExpression(ShiftAmount)) {
2030    Error(E, "malformed shift expression");
2031    return MatchOperand_ParseFail;
2032  }
2033  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2034  if (!CE) {
2035    Error(E, "shift amount must be an immediate");
2036    return MatchOperand_ParseFail;
2037  }
2038
2039  int64_t Val = CE->getValue();
2040  if (isASR) {
2041    // Shift amount must be in [1,32]
2042    if (Val < 1 || Val > 32) {
2043      Error(E, "'asr' shift amount must be in range [1,32]");
2044      return MatchOperand_ParseFail;
2045    }
2046    // asr #32 encoded as asr #0.
2047    if (Val == 32) Val = 0;
2048  } else {
2049    // Shift amount must be in [1,32]
2050    if (Val < 0 || Val > 31) {
2051      Error(E, "'lsr' shift amount must be in range [0,31]");
2052      return MatchOperand_ParseFail;
2053    }
2054  }
2055
2056  E = Parser.getTok().getLoc();
2057  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2058
2059  return MatchOperand_Success;
2060}
2061
2062/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2063/// of instructions. Legal values are:
2064///     ror #n  'n' in {0, 8, 16, 24}
2065ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2066parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2067  const AsmToken &Tok = Parser.getTok();
2068  SMLoc S = Tok.getLoc();
2069  if (Tok.isNot(AsmToken::Identifier)) {
2070    Error(S, "rotate operator 'ror' expected");
2071    return MatchOperand_ParseFail;
2072  }
2073  StringRef ShiftName = Tok.getString();
2074  if (ShiftName != "ror" && ShiftName != "ROR") {
2075    Error(S, "rotate operator 'ror' expected");
2076    return MatchOperand_ParseFail;
2077  }
2078  Parser.Lex(); // Eat the operator.
2079
2080  // A '#' and a rotate amount.
2081  if (Parser.getTok().isNot(AsmToken::Hash)) {
2082    Error(Parser.getTok().getLoc(), "'#' expected");
2083    return MatchOperand_ParseFail;
2084  }
2085  Parser.Lex(); // Eat hash token.
2086
2087  const MCExpr *ShiftAmount;
2088  SMLoc E = Parser.getTok().getLoc();
2089  if (getParser().ParseExpression(ShiftAmount)) {
2090    Error(E, "malformed rotate expression");
2091    return MatchOperand_ParseFail;
2092  }
2093  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2094  if (!CE) {
2095    Error(E, "rotate amount must be an immediate");
2096    return MatchOperand_ParseFail;
2097  }
2098
2099  int64_t Val = CE->getValue();
2100  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2101  // normally, zero is represented in asm by omitting the rotate operand
2102  // entirely.
2103  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2104    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2105    return MatchOperand_ParseFail;
2106  }
2107
2108  E = Parser.getTok().getLoc();
2109  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2110
2111  return MatchOperand_Success;
2112}
2113
2114ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2115parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2116  SMLoc S = Parser.getTok().getLoc();
2117  // The bitfield descriptor is really two operands, the LSB and the width.
2118  if (Parser.getTok().isNot(AsmToken::Hash)) {
2119    Error(Parser.getTok().getLoc(), "'#' expected");
2120    return MatchOperand_ParseFail;
2121  }
2122  Parser.Lex(); // Eat hash token.
2123
2124  const MCExpr *LSBExpr;
2125  SMLoc E = Parser.getTok().getLoc();
2126  if (getParser().ParseExpression(LSBExpr)) {
2127    Error(E, "malformed immediate expression");
2128    return MatchOperand_ParseFail;
2129  }
2130  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2131  if (!CE) {
2132    Error(E, "'lsb' operand must be an immediate");
2133    return MatchOperand_ParseFail;
2134  }
2135
2136  int64_t LSB = CE->getValue();
2137  // The LSB must be in the range [0,31]
2138  if (LSB < 0 || LSB > 31) {
2139    Error(E, "'lsb' operand must be in the range [0,31]");
2140    return MatchOperand_ParseFail;
2141  }
2142  E = Parser.getTok().getLoc();
2143
2144  // Expect another immediate operand.
2145  if (Parser.getTok().isNot(AsmToken::Comma)) {
2146    Error(Parser.getTok().getLoc(), "too few operands");
2147    return MatchOperand_ParseFail;
2148  }
2149  Parser.Lex(); // Eat hash token.
2150  if (Parser.getTok().isNot(AsmToken::Hash)) {
2151    Error(Parser.getTok().getLoc(), "'#' expected");
2152    return MatchOperand_ParseFail;
2153  }
2154  Parser.Lex(); // Eat hash token.
2155
2156  const MCExpr *WidthExpr;
2157  if (getParser().ParseExpression(WidthExpr)) {
2158    Error(E, "malformed immediate expression");
2159    return MatchOperand_ParseFail;
2160  }
2161  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2162  if (!CE) {
2163    Error(E, "'width' operand must be an immediate");
2164    return MatchOperand_ParseFail;
2165  }
2166
2167  int64_t Width = CE->getValue();
2168  // The LSB must be in the range [1,32-lsb]
2169  if (Width < 1 || Width > 32 - LSB) {
2170    Error(E, "'width' operand must be in the range [1,32-lsb]");
2171    return MatchOperand_ParseFail;
2172  }
2173  E = Parser.getTok().getLoc();
2174
2175  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2176
2177  return MatchOperand_Success;
2178}
2179
2180ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2181parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2182  // Check for a post-index addressing register operand. Specifically:
2183  // postidx_reg := '+' register {, shift}
2184  //              | '-' register {, shift}
2185  //              | register {, shift}
2186
2187  // This method must return MatchOperand_NoMatch without consuming any tokens
2188  // in the case where there is no match, as other alternatives take other
2189  // parse methods.
2190  AsmToken Tok = Parser.getTok();
2191  SMLoc S = Tok.getLoc();
2192  bool haveEaten = false;
2193  bool isAdd = true;
2194  int Reg = -1;
2195  if (Tok.is(AsmToken::Plus)) {
2196    Parser.Lex(); // Eat the '+' token.
2197    haveEaten = true;
2198  } else if (Tok.is(AsmToken::Minus)) {
2199    Parser.Lex(); // Eat the '-' token.
2200    isAdd = false;
2201    haveEaten = true;
2202  }
2203  if (Parser.getTok().is(AsmToken::Identifier))
2204    Reg = tryParseRegister();
2205  if (Reg == -1) {
2206    if (!haveEaten)
2207      return MatchOperand_NoMatch;
2208    Error(Parser.getTok().getLoc(), "register expected");
2209    return MatchOperand_ParseFail;
2210  }
2211  SMLoc E = Parser.getTok().getLoc();
2212
2213  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2214  unsigned ShiftImm = 0;
2215  if (Parser.getTok().is(AsmToken::Comma)) {
2216    Parser.Lex(); // Eat the ','.
2217    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2218      return MatchOperand_ParseFail;
2219  }
2220
2221  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2222                                                  ShiftImm, S, E));
2223
2224  return MatchOperand_Success;
2225}
2226
2227ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2228parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2229  // Check for a post-index addressing register operand. Specifically:
2230  // am3offset := '+' register
2231  //              | '-' register
2232  //              | register
2233  //              | # imm
2234  //              | # + imm
2235  //              | # - imm
2236
2237  // This method must return MatchOperand_NoMatch without consuming any tokens
2238  // in the case where there is no match, as other alternatives take other
2239  // parse methods.
2240  AsmToken Tok = Parser.getTok();
2241  SMLoc S = Tok.getLoc();
2242
2243  // Do immediates first, as we always parse those if we have a '#'.
2244  if (Parser.getTok().is(AsmToken::Hash)) {
2245    Parser.Lex(); // Eat the '#'.
2246    // Explicitly look for a '-', as we need to encode negative zero
2247    // differently.
2248    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2249    const MCExpr *Offset;
2250    if (getParser().ParseExpression(Offset))
2251      return MatchOperand_ParseFail;
2252    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2253    if (!CE) {
2254      Error(S, "constant expression expected");
2255      return MatchOperand_ParseFail;
2256    }
2257    SMLoc E = Tok.getLoc();
2258    // Negative zero is encoded as the flag value INT32_MIN.
2259    int32_t Val = CE->getValue();
2260    if (isNegative && Val == 0)
2261      Val = INT32_MIN;
2262
2263    Operands.push_back(
2264      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2265
2266    return MatchOperand_Success;
2267  }
2268
2269
2270  bool haveEaten = false;
2271  bool isAdd = true;
2272  int Reg = -1;
2273  if (Tok.is(AsmToken::Plus)) {
2274    Parser.Lex(); // Eat the '+' token.
2275    haveEaten = true;
2276  } else if (Tok.is(AsmToken::Minus)) {
2277    Parser.Lex(); // Eat the '-' token.
2278    isAdd = false;
2279    haveEaten = true;
2280  }
2281  if (Parser.getTok().is(AsmToken::Identifier))
2282    Reg = tryParseRegister();
2283  if (Reg == -1) {
2284    if (!haveEaten)
2285      return MatchOperand_NoMatch;
2286    Error(Parser.getTok().getLoc(), "register expected");
2287    return MatchOperand_ParseFail;
2288  }
2289  SMLoc E = Parser.getTok().getLoc();
2290
2291  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2292                                                  0, S, E));
2293
2294  return MatchOperand_Success;
2295}
2296
2297/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2298/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2299/// when they refer multiple MIOperands inside a single one.
2300bool ARMAsmParser::
2301cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2302                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2303  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2304
2305  // Create a writeback register dummy placeholder.
2306  Inst.addOperand(MCOperand::CreateImm(0));
2307
2308  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2309  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2310  return true;
2311}
2312
2313/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2314/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2315/// when they refer multiple MIOperands inside a single one.
2316bool ARMAsmParser::
2317cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2318                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2319  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2320
2321  // Create a writeback register dummy placeholder.
2322  Inst.addOperand(MCOperand::CreateImm(0));
2323
2324  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2325  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2326  return true;
2327}
2328
2329
2330/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2331/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2332/// when they refer multiple MIOperands inside a single one.
2333bool ARMAsmParser::
2334cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2335                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2336  // Create a writeback register dummy placeholder.
2337  Inst.addOperand(MCOperand::CreateImm(0));
2338  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2339  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2340  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2341  return true;
2342}
2343
2344/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2345/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2346/// when they refer multiple MIOperands inside a single one.
2347bool ARMAsmParser::
2348cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2349                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2350  // Create a writeback register dummy placeholder.
2351  Inst.addOperand(MCOperand::CreateImm(0));
2352  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2353  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2354  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2355  return true;
2356}
2357
2358/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2359/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2360/// when they refer multiple MIOperands inside a single one.
2361bool ARMAsmParser::
2362cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2363                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2364  // Create a writeback register dummy placeholder.
2365  Inst.addOperand(MCOperand::CreateImm(0));
2366  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2367  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2368  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2369  return true;
2370}
2371
2372/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2373/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2374/// when they refer multiple MIOperands inside a single one.
2375bool ARMAsmParser::
2376cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2377                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2378  // Rt
2379  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2380  // Create a writeback register dummy placeholder.
2381  Inst.addOperand(MCOperand::CreateImm(0));
2382  // addr
2383  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2384  // offset
2385  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2386  // pred
2387  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2388  return true;
2389}
2390
2391/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2392/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2393/// when they refer multiple MIOperands inside a single one.
2394bool ARMAsmParser::
2395cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2396                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2397  // Rt
2398  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2399  // Create a writeback register dummy placeholder.
2400  Inst.addOperand(MCOperand::CreateImm(0));
2401  // addr
2402  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2403  // offset
2404  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2405  // pred
2406  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2407  return true;
2408}
2409
2410/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2411/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2412/// when they refer multiple MIOperands inside a single one.
2413bool ARMAsmParser::
2414cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2415                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2416  // Create a writeback register dummy placeholder.
2417  Inst.addOperand(MCOperand::CreateImm(0));
2418  // Rt
2419  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2420  // addr
2421  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2422  // offset
2423  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2424  // pred
2425  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2426  return true;
2427}
2428
2429/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2430/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2431/// when they refer multiple MIOperands inside a single one.
2432bool ARMAsmParser::
2433cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2434                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2435  // Create a writeback register dummy placeholder.
2436  Inst.addOperand(MCOperand::CreateImm(0));
2437  // Rt
2438  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2439  // addr
2440  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2441  // offset
2442  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2443  // pred
2444  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2445  return true;
2446}
2447
2448/// cvtLdrdPre - Convert parsed operands to MCInst.
2449/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2450/// when they refer multiple MIOperands inside a single one.
2451bool ARMAsmParser::
2452cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2453           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2454  // Rt, Rt2
2455  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2456  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2457  // Create a writeback register dummy placeholder.
2458  Inst.addOperand(MCOperand::CreateImm(0));
2459  // addr
2460  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2461  // pred
2462  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2463  return true;
2464}
2465
2466/// cvtStrdPre - Convert parsed operands to MCInst.
2467/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2468/// when they refer multiple MIOperands inside a single one.
2469bool ARMAsmParser::
2470cvtStrdPre(MCInst &Inst, unsigned Opcode,
2471           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2472  // Create a writeback register dummy placeholder.
2473  Inst.addOperand(MCOperand::CreateImm(0));
2474  // Rt, Rt2
2475  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2476  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2477  // addr
2478  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2479  // pred
2480  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2481  return true;
2482}
2483
2484/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2485/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2486/// when they refer multiple MIOperands inside a single one.
2487bool ARMAsmParser::
2488cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2489                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2490  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2491  // Create a writeback register dummy placeholder.
2492  Inst.addOperand(MCOperand::CreateImm(0));
2493  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2494  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2495  return true;
2496}
2497
2498/// cvtThumbMultiple- Convert parsed operands to MCInst.
2499/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2500/// when they refer multiple MIOperands inside a single one.
2501bool ARMAsmParser::
2502cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2503           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2504  // The second source operand must be the same register as the destination
2505  // operand.
2506  if (Operands.size() == 6 &&
2507      (((ARMOperand*)Operands[3])->getReg() !=
2508       ((ARMOperand*)Operands[5])->getReg()) &&
2509      (((ARMOperand*)Operands[3])->getReg() !=
2510       ((ARMOperand*)Operands[4])->getReg())) {
2511    Error(Operands[3]->getStartLoc(),
2512          "destination register must match source register");
2513    return false;
2514  }
2515  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2516  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2517  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2518  // If we have a three-operand form, use that, else the second source operand
2519  // is just the destination operand again.
2520  if (Operands.size() == 6)
2521    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2522  else
2523    Inst.addOperand(Inst.getOperand(0));
2524  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2525
2526  return true;
2527}
2528
2529/// Parse an ARM memory expression, return false if successful else return true
2530/// or an error.  The first token must be a '[' when called.
2531bool ARMAsmParser::
2532parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2533  SMLoc S, E;
2534  assert(Parser.getTok().is(AsmToken::LBrac) &&
2535         "Token is not a Left Bracket");
2536  S = Parser.getTok().getLoc();
2537  Parser.Lex(); // Eat left bracket token.
2538
2539  const AsmToken &BaseRegTok = Parser.getTok();
2540  int BaseRegNum = tryParseRegister();
2541  if (BaseRegNum == -1)
2542    return Error(BaseRegTok.getLoc(), "register expected");
2543
2544  // The next token must either be a comma or a closing bracket.
2545  const AsmToken &Tok = Parser.getTok();
2546  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2547    return Error(Tok.getLoc(), "malformed memory operand");
2548
2549  if (Tok.is(AsmToken::RBrac)) {
2550    E = Tok.getLoc();
2551    Parser.Lex(); // Eat right bracket token.
2552
2553    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2554                                             0, false, S, E));
2555
2556    return false;
2557  }
2558
2559  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2560  Parser.Lex(); // Eat the comma.
2561
2562  // If we have a '#' it's an immediate offset, else assume it's a register
2563  // offset.
2564  if (Parser.getTok().is(AsmToken::Hash)) {
2565    Parser.Lex(); // Eat the '#'.
2566    E = Parser.getTok().getLoc();
2567
2568    // FIXME: Special case #-0 so we can correctly set the U bit.
2569
2570    const MCExpr *Offset;
2571    if (getParser().ParseExpression(Offset))
2572     return true;
2573
2574    // The expression has to be a constant. Memory references with relocations
2575    // don't come through here, as they use the <label> forms of the relevant
2576    // instructions.
2577    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2578    if (!CE)
2579      return Error (E, "constant expression expected");
2580
2581    // Now we should have the closing ']'
2582    E = Parser.getTok().getLoc();
2583    if (Parser.getTok().isNot(AsmToken::RBrac))
2584      return Error(E, "']' expected");
2585    Parser.Lex(); // Eat right bracket token.
2586
2587    // Don't worry about range checking the value here. That's handled by
2588    // the is*() predicates.
2589    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2590                                             ARM_AM::no_shift, 0, false, S,E));
2591
2592    // If there's a pre-indexing writeback marker, '!', just add it as a token
2593    // operand.
2594    if (Parser.getTok().is(AsmToken::Exclaim)) {
2595      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2596      Parser.Lex(); // Eat the '!'.
2597    }
2598
2599    return false;
2600  }
2601
2602  // The register offset is optionally preceded by a '+' or '-'
2603  bool isNegative = false;
2604  if (Parser.getTok().is(AsmToken::Minus)) {
2605    isNegative = true;
2606    Parser.Lex(); // Eat the '-'.
2607  } else if (Parser.getTok().is(AsmToken::Plus)) {
2608    // Nothing to do.
2609    Parser.Lex(); // Eat the '+'.
2610  }
2611
2612  E = Parser.getTok().getLoc();
2613  int OffsetRegNum = tryParseRegister();
2614  if (OffsetRegNum == -1)
2615    return Error(E, "register expected");
2616
2617  // If there's a shift operator, handle it.
2618  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2619  unsigned ShiftImm = 0;
2620  if (Parser.getTok().is(AsmToken::Comma)) {
2621    Parser.Lex(); // Eat the ','.
2622    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2623      return true;
2624  }
2625
2626  // Now we should have the closing ']'
2627  E = Parser.getTok().getLoc();
2628  if (Parser.getTok().isNot(AsmToken::RBrac))
2629    return Error(E, "']' expected");
2630  Parser.Lex(); // Eat right bracket token.
2631
2632  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2633                                           ShiftType, ShiftImm, isNegative,
2634                                           S, E));
2635
2636  // If there's a pre-indexing writeback marker, '!', just add it as a token
2637  // operand.
2638  if (Parser.getTok().is(AsmToken::Exclaim)) {
2639    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2640    Parser.Lex(); // Eat the '!'.
2641  }
2642
2643  return false;
2644}
2645
2646/// parseMemRegOffsetShift - one of these two:
2647///   ( lsl | lsr | asr | ror ) , # shift_amount
2648///   rrx
2649/// return true if it parses a shift otherwise it returns false.
2650bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2651                                          unsigned &Amount) {
2652  SMLoc Loc = Parser.getTok().getLoc();
2653  const AsmToken &Tok = Parser.getTok();
2654  if (Tok.isNot(AsmToken::Identifier))
2655    return true;
2656  StringRef ShiftName = Tok.getString();
2657  if (ShiftName == "lsl" || ShiftName == "LSL")
2658    St = ARM_AM::lsl;
2659  else if (ShiftName == "lsr" || ShiftName == "LSR")
2660    St = ARM_AM::lsr;
2661  else if (ShiftName == "asr" || ShiftName == "ASR")
2662    St = ARM_AM::asr;
2663  else if (ShiftName == "ror" || ShiftName == "ROR")
2664    St = ARM_AM::ror;
2665  else if (ShiftName == "rrx" || ShiftName == "RRX")
2666    St = ARM_AM::rrx;
2667  else
2668    return Error(Loc, "illegal shift operator");
2669  Parser.Lex(); // Eat shift type token.
2670
2671  // rrx stands alone.
2672  Amount = 0;
2673  if (St != ARM_AM::rrx) {
2674    Loc = Parser.getTok().getLoc();
2675    // A '#' and a shift amount.
2676    const AsmToken &HashTok = Parser.getTok();
2677    if (HashTok.isNot(AsmToken::Hash))
2678      return Error(HashTok.getLoc(), "'#' expected");
2679    Parser.Lex(); // Eat hash token.
2680
2681    const MCExpr *Expr;
2682    if (getParser().ParseExpression(Expr))
2683      return true;
2684    // Range check the immediate.
2685    // lsl, ror: 0 <= imm <= 31
2686    // lsr, asr: 0 <= imm <= 32
2687    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2688    if (!CE)
2689      return Error(Loc, "shift amount must be an immediate");
2690    int64_t Imm = CE->getValue();
2691    if (Imm < 0 ||
2692        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2693        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2694      return Error(Loc, "immediate shift value out of range");
2695    Amount = Imm;
2696  }
2697
2698  return false;
2699}
2700
2701/// Parse a arm instruction operand.  For now this parses the operand regardless
2702/// of the mnemonic.
2703bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2704                                StringRef Mnemonic) {
2705  SMLoc S, E;
2706
2707  // Check if the current operand has a custom associated parser, if so, try to
2708  // custom parse the operand, or fallback to the general approach.
2709  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2710  if (ResTy == MatchOperand_Success)
2711    return false;
2712  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2713  // there was a match, but an error occurred, in which case, just return that
2714  // the operand parsing failed.
2715  if (ResTy == MatchOperand_ParseFail)
2716    return true;
2717
2718  switch (getLexer().getKind()) {
2719  default:
2720    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2721    return true;
2722  case AsmToken::Identifier: {
2723    if (!tryParseRegisterWithWriteBack(Operands))
2724      return false;
2725    int Res = tryParseShiftRegister(Operands);
2726    if (Res == 0) // success
2727      return false;
2728    else if (Res == -1) // irrecoverable error
2729      return true;
2730
2731    // Fall though for the Identifier case that is not a register or a
2732    // special name.
2733  }
2734  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2735  case AsmToken::Dot: {   // . as a branch target
2736    // This was not a register so parse other operands that start with an
2737    // identifier (like labels) as expressions and create them as immediates.
2738    const MCExpr *IdVal;
2739    S = Parser.getTok().getLoc();
2740    if (getParser().ParseExpression(IdVal))
2741      return true;
2742    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2743    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2744    return false;
2745  }
2746  case AsmToken::LBrac:
2747    return parseMemory(Operands);
2748  case AsmToken::LCurly:
2749    return parseRegisterList(Operands);
2750  case AsmToken::Hash: {
2751    // #42 -> immediate.
2752    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2753    S = Parser.getTok().getLoc();
2754    Parser.Lex();
2755    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2756    const MCExpr *ImmVal;
2757    if (getParser().ParseExpression(ImmVal))
2758      return true;
2759    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
2760    if (!CE) {
2761      Error(S, "constant expression expected");
2762      return MatchOperand_ParseFail;
2763    }
2764    int32_t Val = CE->getValue();
2765    if (isNegative && Val == 0)
2766      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
2767    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2768    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2769    return false;
2770  }
2771  case AsmToken::Colon: {
2772    // ":lower16:" and ":upper16:" expression prefixes
2773    // FIXME: Check it's an expression prefix,
2774    // e.g. (FOO - :lower16:BAR) isn't legal.
2775    ARMMCExpr::VariantKind RefKind;
2776    if (parsePrefix(RefKind))
2777      return true;
2778
2779    const MCExpr *SubExprVal;
2780    if (getParser().ParseExpression(SubExprVal))
2781      return true;
2782
2783    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2784                                                   getContext());
2785    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2786    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2787    return false;
2788  }
2789  }
2790}
2791
2792// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2793//  :lower16: and :upper16:.
2794bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2795  RefKind = ARMMCExpr::VK_ARM_None;
2796
2797  // :lower16: and :upper16: modifiers
2798  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2799  Parser.Lex(); // Eat ':'
2800
2801  if (getLexer().isNot(AsmToken::Identifier)) {
2802    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2803    return true;
2804  }
2805
2806  StringRef IDVal = Parser.getTok().getIdentifier();
2807  if (IDVal == "lower16") {
2808    RefKind = ARMMCExpr::VK_ARM_LO16;
2809  } else if (IDVal == "upper16") {
2810    RefKind = ARMMCExpr::VK_ARM_HI16;
2811  } else {
2812    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2813    return true;
2814  }
2815  Parser.Lex();
2816
2817  if (getLexer().isNot(AsmToken::Colon)) {
2818    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2819    return true;
2820  }
2821  Parser.Lex(); // Eat the last ':'
2822  return false;
2823}
2824
2825const MCExpr *
2826ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2827                                MCSymbolRefExpr::VariantKind Variant) {
2828  // Recurse over the given expression, rebuilding it to apply the given variant
2829  // to the leftmost symbol.
2830  if (Variant == MCSymbolRefExpr::VK_None)
2831    return E;
2832
2833  switch (E->getKind()) {
2834  case MCExpr::Target:
2835    llvm_unreachable("Can't handle target expr yet");
2836  case MCExpr::Constant:
2837    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2838
2839  case MCExpr::SymbolRef: {
2840    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2841
2842    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2843      return 0;
2844
2845    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2846  }
2847
2848  case MCExpr::Unary:
2849    llvm_unreachable("Can't handle unary expressions yet");
2850
2851  case MCExpr::Binary: {
2852    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2853    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2854    const MCExpr *RHS = BE->getRHS();
2855    if (!LHS)
2856      return 0;
2857
2858    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2859  }
2860  }
2861
2862  assert(0 && "Invalid expression kind!");
2863  return 0;
2864}
2865
2866/// \brief Given a mnemonic, split out possible predication code and carry
2867/// setting letters to form a canonical mnemonic and flags.
2868//
2869// FIXME: Would be nice to autogen this.
2870// FIXME: This is a bit of a maze of special cases.
2871StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2872                                      unsigned &PredicationCode,
2873                                      bool &CarrySetting,
2874                                      unsigned &ProcessorIMod,
2875                                      StringRef &ITMask) {
2876  PredicationCode = ARMCC::AL;
2877  CarrySetting = false;
2878  ProcessorIMod = 0;
2879
2880  // Ignore some mnemonics we know aren't predicated forms.
2881  //
2882  // FIXME: Would be nice to autogen this.
2883  if ((Mnemonic == "movs" && isThumb()) ||
2884      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2885      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2886      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2887      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2888      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2889      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2890      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2891    return Mnemonic;
2892
2893  // First, split out any predication code. Ignore mnemonics we know aren't
2894  // predicated but do have a carry-set and so weren't caught above.
2895  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2896      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2897      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2898      Mnemonic != "sbcs") {
2899    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2900      .Case("eq", ARMCC::EQ)
2901      .Case("ne", ARMCC::NE)
2902      .Case("hs", ARMCC::HS)
2903      .Case("cs", ARMCC::HS)
2904      .Case("lo", ARMCC::LO)
2905      .Case("cc", ARMCC::LO)
2906      .Case("mi", ARMCC::MI)
2907      .Case("pl", ARMCC::PL)
2908      .Case("vs", ARMCC::VS)
2909      .Case("vc", ARMCC::VC)
2910      .Case("hi", ARMCC::HI)
2911      .Case("ls", ARMCC::LS)
2912      .Case("ge", ARMCC::GE)
2913      .Case("lt", ARMCC::LT)
2914      .Case("gt", ARMCC::GT)
2915      .Case("le", ARMCC::LE)
2916      .Case("al", ARMCC::AL)
2917      .Default(~0U);
2918    if (CC != ~0U) {
2919      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2920      PredicationCode = CC;
2921    }
2922  }
2923
2924  // Next, determine if we have a carry setting bit. We explicitly ignore all
2925  // the instructions we know end in 's'.
2926  if (Mnemonic.endswith("s") &&
2927      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2928        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2929        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2930        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2931        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2932        (Mnemonic == "movs" && isThumb()))) {
2933    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2934    CarrySetting = true;
2935  }
2936
2937  // The "cps" instruction can have a interrupt mode operand which is glued into
2938  // the mnemonic. Check if this is the case, split it and parse the imod op
2939  if (Mnemonic.startswith("cps")) {
2940    // Split out any imod code.
2941    unsigned IMod =
2942      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2943      .Case("ie", ARM_PROC::IE)
2944      .Case("id", ARM_PROC::ID)
2945      .Default(~0U);
2946    if (IMod != ~0U) {
2947      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2948      ProcessorIMod = IMod;
2949    }
2950  }
2951
2952  // The "it" instruction has the condition mask on the end of the mnemonic.
2953  if (Mnemonic.startswith("it")) {
2954    ITMask = Mnemonic.slice(2, Mnemonic.size());
2955    Mnemonic = Mnemonic.slice(0, 2);
2956  }
2957
2958  return Mnemonic;
2959}
2960
2961/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2962/// inclusion of carry set or predication code operands.
2963//
2964// FIXME: It would be nice to autogen this.
2965void ARMAsmParser::
2966getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2967                      bool &CanAcceptPredicationCode) {
2968  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2969      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2970      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2971      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2972      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2973      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2974      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2975      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2976      // FIXME: We need a better way. This really confused Thumb2
2977      // parsing for 'mov'.
2978      (Mnemonic == "mov" && !isThumbOne())) {
2979    CanAcceptCarrySet = true;
2980  } else {
2981    CanAcceptCarrySet = false;
2982  }
2983
2984  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2985      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2986      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2987      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2988      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2989      Mnemonic == "setend" ||
2990      (Mnemonic == "nop" && isThumbOne()) ||
2991      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
2992       !isThumb()) ||
2993      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
2994       !isThumb()) ||
2995      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2996    CanAcceptPredicationCode = false;
2997  } else {
2998    CanAcceptPredicationCode = true;
2999  }
3000
3001  if (isThumb())
3002    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3003        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3004      CanAcceptPredicationCode = false;
3005}
3006
3007bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3008                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3009
3010  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3011  // another does not. Specifically, the MOVW instruction does not. So we
3012  // special case it here and remove the defaulted (non-setting) cc_out
3013  // operand if that's the instruction we're trying to match.
3014  //
3015  // We do this as post-processing of the explicit operands rather than just
3016  // conditionally adding the cc_out in the first place because we need
3017  // to check the type of the parsed immediate operand.
3018  if (Mnemonic == "mov" && Operands.size() > 4 &&
3019      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3020      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3021      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3022    return true;
3023
3024  // Register-register 'add' for thumb does not have a cc_out operand
3025  // when there are only two register operands.
3026  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3027      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3028      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3029      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3030    return true;
3031  // Register-register 'add' for thumb does not have a cc_out operand
3032  // when it's an ADD Rdm, SP, {Rdm|#imm} instruction.
3033  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3034      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3035      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3036      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3037      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3038    return true;
3039  // Register-register 'add/sub' for thumb does not have a cc_out operand
3040  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3041  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3042  // right, this will result in better diagnostics (which operand is off)
3043  // anyway.
3044  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3045      (Operands.size() == 5 || Operands.size() == 6) &&
3046      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3047      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3048      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3049    return true;
3050
3051  return false;
3052}
3053
3054/// Parse an arm instruction mnemonic followed by its operands.
3055bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3056                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3057  // Create the leading tokens for the mnemonic, split by '.' characters.
3058  size_t Start = 0, Next = Name.find('.');
3059  StringRef Mnemonic = Name.slice(Start, Next);
3060
3061  // Split out the predication code and carry setting flag from the mnemonic.
3062  unsigned PredicationCode;
3063  unsigned ProcessorIMod;
3064  bool CarrySetting;
3065  StringRef ITMask;
3066  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3067                           ProcessorIMod, ITMask);
3068
3069  // In Thumb1, only the branch (B) instruction can be predicated.
3070  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3071    Parser.EatToEndOfStatement();
3072    return Error(NameLoc, "conditional execution not supported in Thumb1");
3073  }
3074
3075  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3076
3077  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3078  // is the mask as it will be for the IT encoding if the conditional
3079  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3080  // where the conditional bit0 is zero, the instruction post-processing
3081  // will adjust the mask accordingly.
3082  if (Mnemonic == "it") {
3083    unsigned Mask = 8;
3084    for (unsigned i = ITMask.size(); i != 0; --i) {
3085      char pos = ITMask[i - 1];
3086      if (pos != 't' && pos != 'e') {
3087        Parser.EatToEndOfStatement();
3088        return Error(NameLoc, "illegal IT instruction mask '" + ITMask + "'");
3089      }
3090      Mask >>= 1;
3091      if (ITMask[i - 1] == 't')
3092        Mask |= 8;
3093    }
3094    Operands.push_back(ARMOperand::CreateITMask(Mask, NameLoc));
3095  }
3096
3097  // FIXME: This is all a pretty gross hack. We should automatically handle
3098  // optional operands like this via tblgen.
3099
3100  // Next, add the CCOut and ConditionCode operands, if needed.
3101  //
3102  // For mnemonics which can ever incorporate a carry setting bit or predication
3103  // code, our matching model involves us always generating CCOut and
3104  // ConditionCode operands to match the mnemonic "as written" and then we let
3105  // the matcher deal with finding the right instruction or generating an
3106  // appropriate error.
3107  bool CanAcceptCarrySet, CanAcceptPredicationCode;
3108  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3109
3110  // If we had a carry-set on an instruction that can't do that, issue an
3111  // error.
3112  if (!CanAcceptCarrySet && CarrySetting) {
3113    Parser.EatToEndOfStatement();
3114    return Error(NameLoc, "instruction '" + Mnemonic +
3115                 "' can not set flags, but 's' suffix specified");
3116  }
3117  // If we had a predication code on an instruction that can't do that, issue an
3118  // error.
3119  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3120    Parser.EatToEndOfStatement();
3121    return Error(NameLoc, "instruction '" + Mnemonic +
3122                 "' is not predicable, but condition code specified");
3123  }
3124
3125  // Add the carry setting operand, if necessary.
3126  //
3127  // FIXME: It would be awesome if we could somehow invent a location such that
3128  // match errors on this operand would print a nice diagnostic about how the
3129  // 's' character in the mnemonic resulted in a CCOut operand.
3130  if (CanAcceptCarrySet)
3131    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3132                                               NameLoc));
3133
3134  // Add the predication code operand, if necessary.
3135  if (CanAcceptPredicationCode) {
3136    Operands.push_back(ARMOperand::CreateCondCode(
3137                         ARMCC::CondCodes(PredicationCode), NameLoc));
3138  }
3139
3140  // Add the processor imod operand, if necessary.
3141  if (ProcessorIMod) {
3142    Operands.push_back(ARMOperand::CreateImm(
3143          MCConstantExpr::Create(ProcessorIMod, getContext()),
3144                                 NameLoc, NameLoc));
3145  }
3146
3147  // Add the remaining tokens in the mnemonic.
3148  while (Next != StringRef::npos) {
3149    Start = Next;
3150    Next = Name.find('.', Start + 1);
3151    StringRef ExtraToken = Name.slice(Start, Next);
3152
3153    // For now, we're only parsing Thumb1 (for the most part), so
3154    // just ignore ".n" qualifiers. We'll use them to restrict
3155    // matching when we do Thumb2.
3156    if (ExtraToken != ".n")
3157      Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
3158  }
3159
3160  // Read the remaining operands.
3161  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3162    // Read the first operand.
3163    if (parseOperand(Operands, Mnemonic)) {
3164      Parser.EatToEndOfStatement();
3165      return true;
3166    }
3167
3168    while (getLexer().is(AsmToken::Comma)) {
3169      Parser.Lex();  // Eat the comma.
3170
3171      // Parse and remember the operand.
3172      if (parseOperand(Operands, Mnemonic)) {
3173        Parser.EatToEndOfStatement();
3174        return true;
3175      }
3176    }
3177  }
3178
3179  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3180    Parser.EatToEndOfStatement();
3181    return TokError("unexpected token in argument list");
3182  }
3183
3184  Parser.Lex(); // Consume the EndOfStatement
3185
3186  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3187  // do and don't have a cc_out optional-def operand. With some spot-checks
3188  // of the operand list, we can figure out which variant we're trying to
3189  // parse and adjust accordingly before actually matching. Reason number
3190  // #317 the table driven matcher doesn't fit well with the ARM instruction
3191  // set.
3192  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3193    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3194    Operands.erase(Operands.begin() + 1);
3195    delete Op;
3196  }
3197
3198  // ARM mode 'blx' need special handling, as the register operand version
3199  // is predicable, but the label operand version is not. So, we can't rely
3200  // on the Mnemonic based checking to correctly figure out when to put
3201  // a CondCode operand in the list. If we're trying to match the label
3202  // version, remove the CondCode operand here.
3203  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3204      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3205    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3206    Operands.erase(Operands.begin() + 1);
3207    delete Op;
3208  }
3209
3210  // The vector-compare-to-zero instructions have a literal token "#0" at
3211  // the end that comes to here as an immediate operand. Convert it to a
3212  // token to play nicely with the matcher.
3213  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3214      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3215      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3216    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3217    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3218    if (CE && CE->getValue() == 0) {
3219      Operands.erase(Operands.begin() + 5);
3220      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3221      delete Op;
3222    }
3223  }
3224  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3225  // end. Convert it to a token here.
3226  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3227      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3228    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3229    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3230    if (CE && CE->getValue() == 0) {
3231      Operands.erase(Operands.begin() + 5);
3232      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3233      delete Op;
3234    }
3235  }
3236
3237  return false;
3238}
3239
3240// Validate context-sensitive operand constraints.
3241
3242// return 'true' if register list contains non-low GPR registers,
3243// 'false' otherwise. If Reg is in the register list or is HiReg, set
3244// 'containsReg' to true.
3245static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3246                                 unsigned HiReg, bool &containsReg) {
3247  containsReg = false;
3248  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3249    unsigned OpReg = Inst.getOperand(i).getReg();
3250    if (OpReg == Reg)
3251      containsReg = true;
3252    // Anything other than a low register isn't legal here.
3253    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3254      return true;
3255  }
3256  return false;
3257}
3258
3259// FIXME: We would really like to be able to tablegen'erate this.
3260bool ARMAsmParser::
3261validateInstruction(MCInst &Inst,
3262                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3263  switch (Inst.getOpcode()) {
3264  case ARM::LDRD:
3265  case ARM::LDRD_PRE:
3266  case ARM::LDRD_POST:
3267  case ARM::LDREXD: {
3268    // Rt2 must be Rt + 1.
3269    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3270    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3271    if (Rt2 != Rt + 1)
3272      return Error(Operands[3]->getStartLoc(),
3273                   "destination operands must be sequential");
3274    return false;
3275  }
3276  case ARM::STRD: {
3277    // Rt2 must be Rt + 1.
3278    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3279    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3280    if (Rt2 != Rt + 1)
3281      return Error(Operands[3]->getStartLoc(),
3282                   "source operands must be sequential");
3283    return false;
3284  }
3285  case ARM::STRD_PRE:
3286  case ARM::STRD_POST:
3287  case ARM::STREXD: {
3288    // Rt2 must be Rt + 1.
3289    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3290    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3291    if (Rt2 != Rt + 1)
3292      return Error(Operands[3]->getStartLoc(),
3293                   "source operands must be sequential");
3294    return false;
3295  }
3296  case ARM::SBFX:
3297  case ARM::UBFX: {
3298    // width must be in range [1, 32-lsb]
3299    unsigned lsb = Inst.getOperand(2).getImm();
3300    unsigned widthm1 = Inst.getOperand(3).getImm();
3301    if (widthm1 >= 32 - lsb)
3302      return Error(Operands[5]->getStartLoc(),
3303                   "bitfield width must be in range [1,32-lsb]");
3304    return false;
3305  }
3306  case ARM::tLDMIA: {
3307    // Thumb LDM instructions are writeback iff the base register is not
3308    // in the register list.
3309    unsigned Rn = Inst.getOperand(0).getReg();
3310    bool hasWritebackToken =
3311      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3312       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3313    bool listContainsBase;
3314    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
3315      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3316                   "registers must be in range r0-r7");
3317    // If we should have writeback, then there should be a '!' token.
3318    if (!listContainsBase && !hasWritebackToken)
3319      return Error(Operands[2]->getStartLoc(),
3320                   "writeback operator '!' expected");
3321    // Likewise, if we should not have writeback, there must not be a '!'
3322    if (listContainsBase && hasWritebackToken)
3323      return Error(Operands[3]->getStartLoc(),
3324                   "writeback operator '!' not allowed when base register "
3325                   "in register list");
3326
3327    break;
3328  }
3329  case ARM::tPOP: {
3330    bool listContainsBase;
3331    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3332      return Error(Operands[2]->getStartLoc(),
3333                   "registers must be in range r0-r7 or pc");
3334    break;
3335  }
3336  case ARM::tPUSH: {
3337    bool listContainsBase;
3338    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3339      return Error(Operands[2]->getStartLoc(),
3340                   "registers must be in range r0-r7 or lr");
3341    break;
3342  }
3343  case ARM::tSTMIA_UPD: {
3344    bool listContainsBase;
3345    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3346      return Error(Operands[4]->getStartLoc(),
3347                   "registers must be in range r0-r7");
3348    break;
3349  }
3350  }
3351
3352  return false;
3353}
3354
3355void ARMAsmParser::
3356processInstruction(MCInst &Inst,
3357                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3358  switch (Inst.getOpcode()) {
3359  case ARM::LDMIA_UPD:
3360    // If this is a load of a single register via a 'pop', then we should use
3361    // a post-indexed LDR instruction instead, per the ARM ARM.
3362    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3363        Inst.getNumOperands() == 5) {
3364      MCInst TmpInst;
3365      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3366      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3367      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3368      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3369      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3370      TmpInst.addOperand(MCOperand::CreateImm(4));
3371      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3372      TmpInst.addOperand(Inst.getOperand(3));
3373      Inst = TmpInst;
3374    }
3375    break;
3376  case ARM::STMDB_UPD:
3377    // If this is a store of a single register via a 'push', then we should use
3378    // a pre-indexed STR instruction instead, per the ARM ARM.
3379    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3380        Inst.getNumOperands() == 5) {
3381      MCInst TmpInst;
3382      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3383      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3384      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3385      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3386      TmpInst.addOperand(MCOperand::CreateImm(-4));
3387      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3388      TmpInst.addOperand(Inst.getOperand(3));
3389      Inst = TmpInst;
3390    }
3391    break;
3392  case ARM::tADDi8:
3393    // If the immediate is in the range 0-7, we really wanted tADDi3.
3394    if (Inst.getOperand(3).getImm() < 8)
3395      Inst.setOpcode(ARM::tADDi3);
3396    break;
3397  case ARM::tBcc:
3398    // If the conditional is AL, we really want tB.
3399    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3400      Inst.setOpcode(ARM::tB);
3401    break;
3402  case ARM::t2IT: {
3403    // The mask bits for all but the first condition are represented as
3404    // the low bit of the condition code value implies 't'. We currently
3405    // always have 1 implies 't', so XOR toggle the bits if the low bit
3406    // of the condition code is zero. The encoding also expects the low
3407    // bit of the condition to be encoded as bit 4 of the mask operand,
3408    // so mask that in if needed
3409    MCOperand &MO = Inst.getOperand(1);
3410    unsigned Mask = MO.getImm();
3411    if ((Inst.getOperand(0).getImm() & 1) == 0) {
3412      unsigned TZ = CountTrailingZeros_32(Mask);
3413      assert(Mask && TZ <= 3 && "illegal IT mask value!");
3414      for (unsigned i = 3; i != TZ; --i)
3415        Mask ^= 1 << i;
3416    } else
3417      Mask |= 0x10;
3418    MO.setImm(Mask);
3419    break;
3420  }
3421  }
3422}
3423
3424// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3425// the ARMInsts array) instead. Getting that here requires awkward
3426// API changes, though. Better way?
3427namespace llvm {
3428extern MCInstrDesc ARMInsts[];
3429}
3430static MCInstrDesc &getInstDesc(unsigned Opcode) {
3431  return ARMInsts[Opcode];
3432}
3433
3434unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3435  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3436  // suffix depending on whether they're in an IT block or not.
3437  unsigned Opc = Inst.getOpcode();
3438  MCInstrDesc &MCID = getInstDesc(Opc);
3439  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3440    assert(MCID.hasOptionalDef() &&
3441           "optionally flag setting instruction missing optional def operand");
3442    assert(MCID.NumOperands == Inst.getNumOperands() &&
3443           "operand count mismatch!");
3444    // Find the optional-def operand (cc_out).
3445    unsigned OpNo;
3446    for (OpNo = 0;
3447         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3448         ++OpNo)
3449      ;
3450    // If we're parsing Thumb1, reject it completely.
3451    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3452      return Match_MnemonicFail;
3453    // If we're parsing Thumb2, which form is legal depends on whether we're
3454    // in an IT block.
3455    // FIXME: We don't yet do IT blocks, so just always consider it to be
3456    // that we aren't in one until we do.
3457    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3458      return Match_RequiresITBlock;
3459  }
3460  // Some high-register supporting Thumb1 encodings only allow both registers
3461  // to be from r0-r7 when in Thumb2.
3462  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3463           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3464           isARMLowRegister(Inst.getOperand(2).getReg()))
3465    return Match_RequiresThumb2;
3466  // Others only require ARMv6 or later.
3467  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3468           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3469           isARMLowRegister(Inst.getOperand(1).getReg()))
3470    return Match_RequiresV6;
3471  return Match_Success;
3472}
3473
3474bool ARMAsmParser::
3475MatchAndEmitInstruction(SMLoc IDLoc,
3476                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3477                        MCStreamer &Out) {
3478  MCInst Inst;
3479  unsigned ErrorInfo;
3480  unsigned MatchResult;
3481  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3482  switch (MatchResult) {
3483  default: break;
3484  case Match_Success:
3485    // Context sensitive operand constraints aren't handled by the matcher,
3486    // so check them here.
3487    if (validateInstruction(Inst, Operands))
3488      return true;
3489
3490    // Some instructions need post-processing to, for example, tweak which
3491    // encoding is selected.
3492    processInstruction(Inst, Operands);
3493
3494    Out.EmitInstruction(Inst);
3495    return false;
3496  case Match_MissingFeature:
3497    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3498    return true;
3499  case Match_InvalidOperand: {
3500    SMLoc ErrorLoc = IDLoc;
3501    if (ErrorInfo != ~0U) {
3502      if (ErrorInfo >= Operands.size())
3503        return Error(IDLoc, "too few operands for instruction");
3504
3505      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3506      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3507    }
3508
3509    return Error(ErrorLoc, "invalid operand for instruction");
3510  }
3511  case Match_MnemonicFail:
3512    return Error(IDLoc, "invalid instruction");
3513  case Match_ConversionFail:
3514    // The converter function will have already emited a diagnostic.
3515    return true;
3516  case Match_RequiresITBlock:
3517    return Error(IDLoc, "instruction only valid inside IT block");
3518  case Match_RequiresV6:
3519    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3520  case Match_RequiresThumb2:
3521    return Error(IDLoc, "instruction variant requires Thumb2");
3522  }
3523
3524  llvm_unreachable("Implement any new match types added!");
3525  return true;
3526}
3527
3528/// parseDirective parses the arm specific directives
3529bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3530  StringRef IDVal = DirectiveID.getIdentifier();
3531  if (IDVal == ".word")
3532    return parseDirectiveWord(4, DirectiveID.getLoc());
3533  else if (IDVal == ".thumb")
3534    return parseDirectiveThumb(DirectiveID.getLoc());
3535  else if (IDVal == ".thumb_func")
3536    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3537  else if (IDVal == ".code")
3538    return parseDirectiveCode(DirectiveID.getLoc());
3539  else if (IDVal == ".syntax")
3540    return parseDirectiveSyntax(DirectiveID.getLoc());
3541  return true;
3542}
3543
3544/// parseDirectiveWord
3545///  ::= .word [ expression (, expression)* ]
3546bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3547  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3548    for (;;) {
3549      const MCExpr *Value;
3550      if (getParser().ParseExpression(Value))
3551        return true;
3552
3553      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3554
3555      if (getLexer().is(AsmToken::EndOfStatement))
3556        break;
3557
3558      // FIXME: Improve diagnostic.
3559      if (getLexer().isNot(AsmToken::Comma))
3560        return Error(L, "unexpected token in directive");
3561      Parser.Lex();
3562    }
3563  }
3564
3565  Parser.Lex();
3566  return false;
3567}
3568
3569/// parseDirectiveThumb
3570///  ::= .thumb
3571bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3572  if (getLexer().isNot(AsmToken::EndOfStatement))
3573    return Error(L, "unexpected token in directive");
3574  Parser.Lex();
3575
3576  // TODO: set thumb mode
3577  // TODO: tell the MC streamer the mode
3578  // getParser().getStreamer().Emit???();
3579  return false;
3580}
3581
3582/// parseDirectiveThumbFunc
3583///  ::= .thumbfunc symbol_name
3584bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3585  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3586  bool isMachO = MAI.hasSubsectionsViaSymbols();
3587  StringRef Name;
3588
3589  // Darwin asm has function name after .thumb_func direction
3590  // ELF doesn't
3591  if (isMachO) {
3592    const AsmToken &Tok = Parser.getTok();
3593    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3594      return Error(L, "unexpected token in .thumb_func directive");
3595    Name = Tok.getString();
3596    Parser.Lex(); // Consume the identifier token.
3597  }
3598
3599  if (getLexer().isNot(AsmToken::EndOfStatement))
3600    return Error(L, "unexpected token in directive");
3601  Parser.Lex();
3602
3603  // FIXME: assuming function name will be the line following .thumb_func
3604  if (!isMachO) {
3605    Name = Parser.getTok().getString();
3606  }
3607
3608  // Mark symbol as a thumb symbol.
3609  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3610  getParser().getStreamer().EmitThumbFunc(Func);
3611  return false;
3612}
3613
3614/// parseDirectiveSyntax
3615///  ::= .syntax unified | divided
3616bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3617  const AsmToken &Tok = Parser.getTok();
3618  if (Tok.isNot(AsmToken::Identifier))
3619    return Error(L, "unexpected token in .syntax directive");
3620  StringRef Mode = Tok.getString();
3621  if (Mode == "unified" || Mode == "UNIFIED")
3622    Parser.Lex();
3623  else if (Mode == "divided" || Mode == "DIVIDED")
3624    return Error(L, "'.syntax divided' arm asssembly not supported");
3625  else
3626    return Error(L, "unrecognized syntax mode in .syntax directive");
3627
3628  if (getLexer().isNot(AsmToken::EndOfStatement))
3629    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3630  Parser.Lex();
3631
3632  // TODO tell the MC streamer the mode
3633  // getParser().getStreamer().Emit???();
3634  return false;
3635}
3636
3637/// parseDirectiveCode
3638///  ::= .code 16 | 32
3639bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3640  const AsmToken &Tok = Parser.getTok();
3641  if (Tok.isNot(AsmToken::Integer))
3642    return Error(L, "unexpected token in .code directive");
3643  int64_t Val = Parser.getTok().getIntVal();
3644  if (Val == 16)
3645    Parser.Lex();
3646  else if (Val == 32)
3647    Parser.Lex();
3648  else
3649    return Error(L, "invalid operand to .code directive");
3650
3651  if (getLexer().isNot(AsmToken::EndOfStatement))
3652    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3653  Parser.Lex();
3654
3655  if (Val == 16) {
3656    if (!isThumb()) {
3657      SwitchMode();
3658      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3659    }
3660  } else {
3661    if (isThumb()) {
3662      SwitchMode();
3663      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3664    }
3665  }
3666
3667  return false;
3668}
3669
3670extern "C" void LLVMInitializeARMAsmLexer();
3671
3672/// Force static initialization.
3673extern "C" void LLVMInitializeARMAsmParser() {
3674  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3675  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3676  LLVMInitializeARMAsmLexer();
3677}
3678
3679#define GET_REGISTER_MATCHER
3680#define GET_MATCHER_IMPLEMENTATION
3681#include "ARMGenAsmMatcher.inc"
3682