ARMAsmParser.cpp revision 89df996ab20609676ecc8823f58414d598b09b46 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  MCAsmParser &getParser() const { return Parser; }
48  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49
50  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
51  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52
53  int tryParseRegister();
54  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
55  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
56  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
57  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
58  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
59  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
60  const MCExpr *applyPrefixToExpr(const MCExpr *E,
61                                  MCSymbolRefExpr::VariantKind Variant);
62
63
64  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
65                              unsigned &ShiftAmount);
66  bool parseDirectiveWord(unsigned Size, SMLoc L);
67  bool parseDirectiveThumb(SMLoc L);
68  bool parseDirectiveThumbFunc(SMLoc L);
69  bool parseDirectiveCode(SMLoc L);
70  bool parseDirectiveSyntax(SMLoc L);
71
72  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
73                          bool &CarrySetting, unsigned &ProcessorIMod,
74                          StringRef &ITMask);
75  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
76                             bool &CanAcceptPredicationCode);
77
78  bool isThumb() const {
79    // FIXME: Can tablegen auto-generate this?
80    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
81  }
82  bool isThumbOne() const {
83    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
84  }
85  bool isThumbTwo() const {
86    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
87  }
88  bool hasV6Ops() const {
89    return STI.getFeatureBits() & ARM::HasV6Ops;
90  }
91  void SwitchMode() {
92    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
93    setAvailableFeatures(FB);
94  }
95
96  /// @name Auto-generated Match Functions
97  /// {
98
99#define GET_ASSEMBLER_HEADER
100#include "ARMGenAsmMatcher.inc"
101
102  /// }
103
104  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
105  OperandMatchResultTy parseCoprocNumOperand(
106    SmallVectorImpl<MCParsedAsmOperand*>&);
107  OperandMatchResultTy parseCoprocRegOperand(
108    SmallVectorImpl<MCParsedAsmOperand*>&);
109  OperandMatchResultTy parseMemBarrierOptOperand(
110    SmallVectorImpl<MCParsedAsmOperand*>&);
111  OperandMatchResultTy parseProcIFlagsOperand(
112    SmallVectorImpl<MCParsedAsmOperand*>&);
113  OperandMatchResultTy parseMSRMaskOperand(
114    SmallVectorImpl<MCParsedAsmOperand*>&);
115  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
116                                   StringRef Op, int Low, int High);
117  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
118    return parsePKHImm(O, "lsl", 0, 31);
119  }
120  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
121    return parsePKHImm(O, "asr", 1, 32);
122  }
123  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
124  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
125  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
126  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
127  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
128  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
129
130  // Asm Match Converter Methods
131  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
132                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
133  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
134                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
135  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
136                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
137  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
138                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
139  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
140                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
141  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
142                             const SmallVectorImpl<MCParsedAsmOperand*> &);
143  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
144                             const SmallVectorImpl<MCParsedAsmOperand*> &);
145  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
146                             const SmallVectorImpl<MCParsedAsmOperand*> &);
147  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
148                             const SmallVectorImpl<MCParsedAsmOperand*> &);
149  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
150                  const SmallVectorImpl<MCParsedAsmOperand*> &);
151  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
152                  const SmallVectorImpl<MCParsedAsmOperand*> &);
153  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
154                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
155  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
156                        const SmallVectorImpl<MCParsedAsmOperand*> &);
157
158  bool validateInstruction(MCInst &Inst,
159                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
160  void processInstruction(MCInst &Inst,
161                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
162  bool shouldOmitCCOutOperand(StringRef Mnemonic,
163                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
164
165public:
166  enum ARMMatchResultTy {
167    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
168    Match_RequiresV6,
169    Match_RequiresThumb2
170  };
171
172  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
173    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
174    MCAsmParserExtension::Initialize(_Parser);
175
176    // Initialize the set of available features.
177    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
178  }
179
180  // Implementation of the MCTargetAsmParser interface:
181  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
182  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
183                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
184  bool ParseDirective(AsmToken DirectiveID);
185
186  unsigned checkTargetMatchPredicate(MCInst &Inst);
187
188  bool MatchAndEmitInstruction(SMLoc IDLoc,
189                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
190                               MCStreamer &Out);
191};
192} // end anonymous namespace
193
194namespace {
195
196/// ARMOperand - Instances of this class represent a parsed ARM machine
197/// instruction.
198class ARMOperand : public MCParsedAsmOperand {
199  enum KindTy {
200    CondCode,
201    CCOut,
202    ITCondMask,
203    CoprocNum,
204    CoprocReg,
205    Immediate,
206    MemBarrierOpt,
207    Memory,
208    PostIndexRegister,
209    MSRMask,
210    ProcIFlags,
211    Register,
212    RegisterList,
213    DPRRegisterList,
214    SPRRegisterList,
215    ShiftedRegister,
216    ShiftedImmediate,
217    ShifterImmediate,
218    RotateImmediate,
219    BitfieldDescriptor,
220    Token
221  } Kind;
222
223  SMLoc StartLoc, EndLoc;
224  SmallVector<unsigned, 8> Registers;
225
226  union {
227    struct {
228      ARMCC::CondCodes Val;
229    } CC;
230
231    struct {
232      unsigned Val;
233    } Cop;
234
235    struct {
236      unsigned Mask:4;
237    } ITMask;
238
239    struct {
240      ARM_MB::MemBOpt Val;
241    } MBOpt;
242
243    struct {
244      ARM_PROC::IFlags Val;
245    } IFlags;
246
247    struct {
248      unsigned Val;
249    } MMask;
250
251    struct {
252      const char *Data;
253      unsigned Length;
254    } Tok;
255
256    struct {
257      unsigned RegNum;
258    } Reg;
259
260    struct {
261      const MCExpr *Val;
262    } Imm;
263
264    /// Combined record for all forms of ARM address expressions.
265    struct {
266      unsigned BaseRegNum;
267      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
268      // was specified.
269      const MCConstantExpr *OffsetImm;  // Offset immediate value
270      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
271      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
272      unsigned ShiftImm;      // shift for OffsetReg.
273      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
274    } Mem;
275
276    struct {
277      unsigned RegNum;
278      bool isAdd;
279      ARM_AM::ShiftOpc ShiftTy;
280      unsigned ShiftImm;
281    } PostIdxReg;
282
283    struct {
284      bool isASR;
285      unsigned Imm;
286    } ShifterImm;
287    struct {
288      ARM_AM::ShiftOpc ShiftTy;
289      unsigned SrcReg;
290      unsigned ShiftReg;
291      unsigned ShiftImm;
292    } RegShiftedReg;
293    struct {
294      ARM_AM::ShiftOpc ShiftTy;
295      unsigned SrcReg;
296      unsigned ShiftImm;
297    } RegShiftedImm;
298    struct {
299      unsigned Imm;
300    } RotImm;
301    struct {
302      unsigned LSB;
303      unsigned Width;
304    } Bitfield;
305  };
306
307  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
308public:
309  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
310    Kind = o.Kind;
311    StartLoc = o.StartLoc;
312    EndLoc = o.EndLoc;
313    switch (Kind) {
314    case CondCode:
315      CC = o.CC;
316      break;
317    case ITCondMask:
318      ITMask = o.ITMask;
319      break;
320    case Token:
321      Tok = o.Tok;
322      break;
323    case CCOut:
324    case Register:
325      Reg = o.Reg;
326      break;
327    case RegisterList:
328    case DPRRegisterList:
329    case SPRRegisterList:
330      Registers = o.Registers;
331      break;
332    case CoprocNum:
333    case CoprocReg:
334      Cop = o.Cop;
335      break;
336    case Immediate:
337      Imm = o.Imm;
338      break;
339    case MemBarrierOpt:
340      MBOpt = o.MBOpt;
341      break;
342    case Memory:
343      Mem = o.Mem;
344      break;
345    case PostIndexRegister:
346      PostIdxReg = o.PostIdxReg;
347      break;
348    case MSRMask:
349      MMask = o.MMask;
350      break;
351    case ProcIFlags:
352      IFlags = o.IFlags;
353      break;
354    case ShifterImmediate:
355      ShifterImm = o.ShifterImm;
356      break;
357    case ShiftedRegister:
358      RegShiftedReg = o.RegShiftedReg;
359      break;
360    case ShiftedImmediate:
361      RegShiftedImm = o.RegShiftedImm;
362      break;
363    case RotateImmediate:
364      RotImm = o.RotImm;
365      break;
366    case BitfieldDescriptor:
367      Bitfield = o.Bitfield;
368      break;
369    }
370  }
371
372  /// getStartLoc - Get the location of the first token of this operand.
373  SMLoc getStartLoc() const { return StartLoc; }
374  /// getEndLoc - Get the location of the last token of this operand.
375  SMLoc getEndLoc() const { return EndLoc; }
376
377  ARMCC::CondCodes getCondCode() const {
378    assert(Kind == CondCode && "Invalid access!");
379    return CC.Val;
380  }
381
382  unsigned getCoproc() const {
383    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
384    return Cop.Val;
385  }
386
387  StringRef getToken() const {
388    assert(Kind == Token && "Invalid access!");
389    return StringRef(Tok.Data, Tok.Length);
390  }
391
392  unsigned getReg() const {
393    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
394    return Reg.RegNum;
395  }
396
397  const SmallVectorImpl<unsigned> &getRegList() const {
398    assert((Kind == RegisterList || Kind == DPRRegisterList ||
399            Kind == SPRRegisterList) && "Invalid access!");
400    return Registers;
401  }
402
403  const MCExpr *getImm() const {
404    assert(Kind == Immediate && "Invalid access!");
405    return Imm.Val;
406  }
407
408  ARM_MB::MemBOpt getMemBarrierOpt() const {
409    assert(Kind == MemBarrierOpt && "Invalid access!");
410    return MBOpt.Val;
411  }
412
413  ARM_PROC::IFlags getProcIFlags() const {
414    assert(Kind == ProcIFlags && "Invalid access!");
415    return IFlags.Val;
416  }
417
418  unsigned getMSRMask() const {
419    assert(Kind == MSRMask && "Invalid access!");
420    return MMask.Val;
421  }
422
423  bool isCoprocNum() const { return Kind == CoprocNum; }
424  bool isCoprocReg() const { return Kind == CoprocReg; }
425  bool isCondCode() const { return Kind == CondCode; }
426  bool isCCOut() const { return Kind == CCOut; }
427  bool isITMask() const { return Kind == ITCondMask; }
428  bool isITCondCode() const { return Kind == CondCode; }
429  bool isImm() const { return Kind == Immediate; }
430  bool isImm0_1020s4() const {
431    if (Kind != Immediate)
432      return false;
433    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
434    if (!CE) return false;
435    int64_t Value = CE->getValue();
436    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
437  }
438  bool isImm0_508s4() const {
439    if (Kind != Immediate)
440      return false;
441    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
442    if (!CE) return false;
443    int64_t Value = CE->getValue();
444    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
445  }
446  bool isImm0_255() const {
447    if (Kind != Immediate)
448      return false;
449    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
450    if (!CE) return false;
451    int64_t Value = CE->getValue();
452    return Value >= 0 && Value < 256;
453  }
454  bool isImm0_7() const {
455    if (Kind != Immediate)
456      return false;
457    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
458    if (!CE) return false;
459    int64_t Value = CE->getValue();
460    return Value >= 0 && Value < 8;
461  }
462  bool isImm0_15() const {
463    if (Kind != Immediate)
464      return false;
465    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
466    if (!CE) return false;
467    int64_t Value = CE->getValue();
468    return Value >= 0 && Value < 16;
469  }
470  bool isImm0_31() const {
471    if (Kind != Immediate)
472      return false;
473    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474    if (!CE) return false;
475    int64_t Value = CE->getValue();
476    return Value >= 0 && Value < 32;
477  }
478  bool isImm1_16() const {
479    if (Kind != Immediate)
480      return false;
481    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
482    if (!CE) return false;
483    int64_t Value = CE->getValue();
484    return Value > 0 && Value < 17;
485  }
486  bool isImm1_32() const {
487    if (Kind != Immediate)
488      return false;
489    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
490    if (!CE) return false;
491    int64_t Value = CE->getValue();
492    return Value > 0 && Value < 33;
493  }
494  bool isImm0_65535() const {
495    if (Kind != Immediate)
496      return false;
497    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
498    if (!CE) return false;
499    int64_t Value = CE->getValue();
500    return Value >= 0 && Value < 65536;
501  }
502  bool isImm0_65535Expr() const {
503    if (Kind != Immediate)
504      return false;
505    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
506    // If it's not a constant expression, it'll generate a fixup and be
507    // handled later.
508    if (!CE) return true;
509    int64_t Value = CE->getValue();
510    return Value >= 0 && Value < 65536;
511  }
512  bool isImm24bit() const {
513    if (Kind != Immediate)
514      return false;
515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516    if (!CE) return false;
517    int64_t Value = CE->getValue();
518    return Value >= 0 && Value <= 0xffffff;
519  }
520  bool isImmThumbSR() const {
521    if (Kind != Immediate)
522      return false;
523    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
524    if (!CE) return false;
525    int64_t Value = CE->getValue();
526    return Value > 0 && Value < 33;
527  }
528  bool isPKHLSLImm() const {
529    if (Kind != Immediate)
530      return false;
531    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
532    if (!CE) return false;
533    int64_t Value = CE->getValue();
534    return Value >= 0 && Value < 32;
535  }
536  bool isPKHASRImm() const {
537    if (Kind != Immediate)
538      return false;
539    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
540    if (!CE) return false;
541    int64_t Value = CE->getValue();
542    return Value > 0 && Value <= 32;
543  }
544  bool isARMSOImm() const {
545    if (Kind != Immediate)
546      return false;
547    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
548    if (!CE) return false;
549    int64_t Value = CE->getValue();
550    return ARM_AM::getSOImmVal(Value) != -1;
551  }
552  bool isT2SOImm() const {
553    if (Kind != Immediate)
554      return false;
555    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
556    if (!CE) return false;
557    int64_t Value = CE->getValue();
558    return ARM_AM::getT2SOImmVal(Value) != -1;
559  }
560  bool isSetEndImm() const {
561    if (Kind != Immediate)
562      return false;
563    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564    if (!CE) return false;
565    int64_t Value = CE->getValue();
566    return Value == 1 || Value == 0;
567  }
568  bool isReg() const { return Kind == Register; }
569  bool isRegList() const { return Kind == RegisterList; }
570  bool isDPRRegList() const { return Kind == DPRRegisterList; }
571  bool isSPRRegList() const { return Kind == SPRRegisterList; }
572  bool isToken() const { return Kind == Token; }
573  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
574  bool isMemory() const { return Kind == Memory; }
575  bool isShifterImm() const { return Kind == ShifterImmediate; }
576  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
577  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
578  bool isRotImm() const { return Kind == RotateImmediate; }
579  bool isBitfield() const { return Kind == BitfieldDescriptor; }
580  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
581  bool isPostIdxReg() const {
582    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
583  }
584  bool isMemNoOffset() const {
585    if (Kind != Memory)
586      return false;
587    // No offset of any kind.
588    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
589  }
590  bool isAddrMode2() const {
591    if (Kind != Memory)
592      return false;
593    // Check for register offset.
594    if (Mem.OffsetRegNum) return true;
595    // Immediate offset in range [-4095, 4095].
596    if (!Mem.OffsetImm) return true;
597    int64_t Val = Mem.OffsetImm->getValue();
598    return Val > -4096 && Val < 4096;
599  }
600  bool isAM2OffsetImm() const {
601    if (Kind != Immediate)
602      return false;
603    // Immediate offset in range [-4095, 4095].
604    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
605    if (!CE) return false;
606    int64_t Val = CE->getValue();
607    return Val > -4096 && Val < 4096;
608  }
609  bool isAddrMode3() const {
610    if (Kind != Memory)
611      return false;
612    // No shifts are legal for AM3.
613    if (Mem.ShiftType != ARM_AM::no_shift) return false;
614    // Check for register offset.
615    if (Mem.OffsetRegNum) return true;
616    // Immediate offset in range [-255, 255].
617    if (!Mem.OffsetImm) return true;
618    int64_t Val = Mem.OffsetImm->getValue();
619    return Val > -256 && Val < 256;
620  }
621  bool isAM3Offset() const {
622    if (Kind != Immediate && Kind != PostIndexRegister)
623      return false;
624    if (Kind == PostIndexRegister)
625      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
626    // Immediate offset in range [-255, 255].
627    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
628    if (!CE) return false;
629    int64_t Val = CE->getValue();
630    // Special case, #-0 is INT32_MIN.
631    return (Val > -256 && Val < 256) || Val == INT32_MIN;
632  }
633  bool isAddrMode5() const {
634    if (Kind != Memory)
635      return false;
636    // Check for register offset.
637    if (Mem.OffsetRegNum) return false;
638    // Immediate offset in range [-1020, 1020] and a multiple of 4.
639    if (!Mem.OffsetImm) return true;
640    int64_t Val = Mem.OffsetImm->getValue();
641    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
642  }
643  bool isMemRegOffset() const {
644    if (Kind != Memory || !Mem.OffsetRegNum)
645      return false;
646    return true;
647  }
648  bool isMemThumbRR() const {
649    // Thumb reg+reg addressing is simple. Just two registers, a base and
650    // an offset. No shifts, negations or any other complicating factors.
651    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
652        Mem.ShiftType != ARM_AM::no_shift)
653      return false;
654    return isARMLowRegister(Mem.BaseRegNum) &&
655      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
656  }
657  bool isMemThumbRIs4() const {
658    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
659        !isARMLowRegister(Mem.BaseRegNum))
660      return false;
661    // Immediate offset, multiple of 4 in range [0, 124].
662    if (!Mem.OffsetImm) return true;
663    int64_t Val = Mem.OffsetImm->getValue();
664    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
665  }
666  bool isMemThumbRIs2() const {
667    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
668        !isARMLowRegister(Mem.BaseRegNum))
669      return false;
670    // Immediate offset, multiple of 4 in range [0, 62].
671    if (!Mem.OffsetImm) return true;
672    int64_t Val = Mem.OffsetImm->getValue();
673    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
674  }
675  bool isMemThumbRIs1() const {
676    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
677        !isARMLowRegister(Mem.BaseRegNum))
678      return false;
679    // Immediate offset in range [0, 31].
680    if (!Mem.OffsetImm) return true;
681    int64_t Val = Mem.OffsetImm->getValue();
682    return Val >= 0 && Val <= 31;
683  }
684  bool isMemThumbSPI() const {
685    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
686      return false;
687    // Immediate offset, multiple of 4 in range [0, 1020].
688    if (!Mem.OffsetImm) return true;
689    int64_t Val = Mem.OffsetImm->getValue();
690    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
691  }
692  bool isMemImm8Offset() const {
693    if (Kind != Memory || Mem.OffsetRegNum != 0)
694      return false;
695    // Immediate offset in range [-255, 255].
696    if (!Mem.OffsetImm) return true;
697    int64_t Val = Mem.OffsetImm->getValue();
698    return Val > -256 && Val < 256;
699  }
700  bool isMemImm12Offset() const {
701    // If we have an immediate that's not a constant, treat it as a label
702    // reference needing a fixup. If it is a constant, it's something else
703    // and we reject it.
704    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
705      return true;
706
707    if (Kind != Memory || Mem.OffsetRegNum != 0)
708      return false;
709    // Immediate offset in range [-4095, 4095].
710    if (!Mem.OffsetImm) return true;
711    int64_t Val = Mem.OffsetImm->getValue();
712    return Val > -4096 && Val < 4096;
713  }
714  bool isPostIdxImm8() const {
715    if (Kind != Immediate)
716      return false;
717    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
718    if (!CE) return false;
719    int64_t Val = CE->getValue();
720    return Val > -256 && Val < 256;
721  }
722
723  bool isMSRMask() const { return Kind == MSRMask; }
724  bool isProcIFlags() const { return Kind == ProcIFlags; }
725
726  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
727    // Add as immediates when possible.  Null MCExpr = 0.
728    if (Expr == 0)
729      Inst.addOperand(MCOperand::CreateImm(0));
730    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
731      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
732    else
733      Inst.addOperand(MCOperand::CreateExpr(Expr));
734  }
735
736  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
737    assert(N == 2 && "Invalid number of operands!");
738    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
739    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
740    Inst.addOperand(MCOperand::CreateReg(RegNum));
741  }
742
743  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
744    assert(N == 1 && "Invalid number of operands!");
745    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
746  }
747
748  void addITMaskOperands(MCInst &Inst, unsigned N) const {
749    assert(N == 1 && "Invalid number of operands!");
750    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
751  }
752
753  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
754    assert(N == 1 && "Invalid number of operands!");
755    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
756  }
757
758  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
759    assert(N == 1 && "Invalid number of operands!");
760    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
761  }
762
763  void addCCOutOperands(MCInst &Inst, unsigned N) const {
764    assert(N == 1 && "Invalid number of operands!");
765    Inst.addOperand(MCOperand::CreateReg(getReg()));
766  }
767
768  void addRegOperands(MCInst &Inst, unsigned N) const {
769    assert(N == 1 && "Invalid number of operands!");
770    Inst.addOperand(MCOperand::CreateReg(getReg()));
771  }
772
773  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
774    assert(N == 3 && "Invalid number of operands!");
775    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
776    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
777    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
778    Inst.addOperand(MCOperand::CreateImm(
779      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
780  }
781
782  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
783    assert(N == 2 && "Invalid number of operands!");
784    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
785    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
786    Inst.addOperand(MCOperand::CreateImm(
787      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
788  }
789
790
791  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
792    assert(N == 1 && "Invalid number of operands!");
793    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
794                                         ShifterImm.Imm));
795  }
796
797  void addRegListOperands(MCInst &Inst, unsigned N) const {
798    assert(N == 1 && "Invalid number of operands!");
799    const SmallVectorImpl<unsigned> &RegList = getRegList();
800    for (SmallVectorImpl<unsigned>::const_iterator
801           I = RegList.begin(), E = RegList.end(); I != E; ++I)
802      Inst.addOperand(MCOperand::CreateReg(*I));
803  }
804
805  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
806    addRegListOperands(Inst, N);
807  }
808
809  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
810    addRegListOperands(Inst, N);
811  }
812
813  void addRotImmOperands(MCInst &Inst, unsigned N) const {
814    assert(N == 1 && "Invalid number of operands!");
815    // Encoded as val>>3. The printer handles display as 8, 16, 24.
816    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
817  }
818
819  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
820    assert(N == 1 && "Invalid number of operands!");
821    // Munge the lsb/width into a bitfield mask.
822    unsigned lsb = Bitfield.LSB;
823    unsigned width = Bitfield.Width;
824    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
825    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
826                      (32 - (lsb + width)));
827    Inst.addOperand(MCOperand::CreateImm(Mask));
828  }
829
830  void addImmOperands(MCInst &Inst, unsigned N) const {
831    assert(N == 1 && "Invalid number of operands!");
832    addExpr(Inst, getImm());
833  }
834
835  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
836    assert(N == 1 && "Invalid number of operands!");
837    // The immediate is scaled by four in the encoding and is stored
838    // in the MCInst as such. Lop off the low two bits here.
839    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
840    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
841  }
842
843  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
844    assert(N == 1 && "Invalid number of operands!");
845    // The immediate is scaled by four in the encoding and is stored
846    // in the MCInst as such. Lop off the low two bits here.
847    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
849  }
850
851  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
852    assert(N == 1 && "Invalid number of operands!");
853    addExpr(Inst, getImm());
854  }
855
856  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
857    assert(N == 1 && "Invalid number of operands!");
858    addExpr(Inst, getImm());
859  }
860
861  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
862    assert(N == 1 && "Invalid number of operands!");
863    addExpr(Inst, getImm());
864  }
865
866  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
867    assert(N == 1 && "Invalid number of operands!");
868    addExpr(Inst, getImm());
869  }
870
871  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
872    assert(N == 1 && "Invalid number of operands!");
873    // The constant encodes as the immediate-1, and we store in the instruction
874    // the bits as encoded, so subtract off one here.
875    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
877  }
878
879  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
880    assert(N == 1 && "Invalid number of operands!");
881    // The constant encodes as the immediate-1, and we store in the instruction
882    // the bits as encoded, so subtract off one here.
883    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
885  }
886
887  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
888    assert(N == 1 && "Invalid number of operands!");
889    addExpr(Inst, getImm());
890  }
891
892  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
893    assert(N == 1 && "Invalid number of operands!");
894    addExpr(Inst, getImm());
895  }
896
897  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
898    assert(N == 1 && "Invalid number of operands!");
899    addExpr(Inst, getImm());
900  }
901
902  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
903    assert(N == 1 && "Invalid number of operands!");
904    // The constant encodes as the immediate, except for 32, which encodes as
905    // zero.
906    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
907    unsigned Imm = CE->getValue();
908    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
909  }
910
911  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
912    assert(N == 1 && "Invalid number of operands!");
913    addExpr(Inst, getImm());
914  }
915
916  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
917    assert(N == 1 && "Invalid number of operands!");
918    // An ASR value of 32 encodes as 0, so that's how we want to add it to
919    // the instruction as well.
920    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
921    int Val = CE->getValue();
922    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
923  }
924
925  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
926    assert(N == 1 && "Invalid number of operands!");
927    addExpr(Inst, getImm());
928  }
929
930  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
931    assert(N == 1 && "Invalid number of operands!");
932    addExpr(Inst, getImm());
933  }
934
935  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
936    assert(N == 1 && "Invalid number of operands!");
937    addExpr(Inst, getImm());
938  }
939
940  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
941    assert(N == 1 && "Invalid number of operands!");
942    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
943  }
944
945  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
946    assert(N == 1 && "Invalid number of operands!");
947    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
948  }
949
950  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
951    assert(N == 3 && "Invalid number of operands!");
952    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
953    if (!Mem.OffsetRegNum) {
954      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
955      // Special case for #-0
956      if (Val == INT32_MIN) Val = 0;
957      if (Val < 0) Val = -Val;
958      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
959    } else {
960      // For register offset, we encode the shift type and negation flag
961      // here.
962      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
963                              Mem.ShiftImm, Mem.ShiftType);
964    }
965    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
966    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
967    Inst.addOperand(MCOperand::CreateImm(Val));
968  }
969
970  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
971    assert(N == 2 && "Invalid number of operands!");
972    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973    assert(CE && "non-constant AM2OffsetImm operand!");
974    int32_t Val = CE->getValue();
975    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
976    // Special case for #-0
977    if (Val == INT32_MIN) Val = 0;
978    if (Val < 0) Val = -Val;
979    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
980    Inst.addOperand(MCOperand::CreateReg(0));
981    Inst.addOperand(MCOperand::CreateImm(Val));
982  }
983
984  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
985    assert(N == 3 && "Invalid number of operands!");
986    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
987    if (!Mem.OffsetRegNum) {
988      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
989      // Special case for #-0
990      if (Val == INT32_MIN) Val = 0;
991      if (Val < 0) Val = -Val;
992      Val = ARM_AM::getAM3Opc(AddSub, Val);
993    } else {
994      // For register offset, we encode the shift type and negation flag
995      // here.
996      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
997    }
998    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
999    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1000    Inst.addOperand(MCOperand::CreateImm(Val));
1001  }
1002
1003  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1004    assert(N == 2 && "Invalid number of operands!");
1005    if (Kind == PostIndexRegister) {
1006      int32_t Val =
1007        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1008      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1009      Inst.addOperand(MCOperand::CreateImm(Val));
1010      return;
1011    }
1012
1013    // Constant offset.
1014    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1015    int32_t Val = CE->getValue();
1016    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1017    // Special case for #-0
1018    if (Val == INT32_MIN) Val = 0;
1019    if (Val < 0) Val = -Val;
1020    Val = ARM_AM::getAM3Opc(AddSub, Val);
1021    Inst.addOperand(MCOperand::CreateReg(0));
1022    Inst.addOperand(MCOperand::CreateImm(Val));
1023  }
1024
1025  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1026    assert(N == 2 && "Invalid number of operands!");
1027    // The lower two bits are always zero and as such are not encoded.
1028    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1029    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1030    // Special case for #-0
1031    if (Val == INT32_MIN) Val = 0;
1032    if (Val < 0) Val = -Val;
1033    Val = ARM_AM::getAM5Opc(AddSub, Val);
1034    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1035    Inst.addOperand(MCOperand::CreateImm(Val));
1036  }
1037
1038  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1039    assert(N == 2 && "Invalid number of operands!");
1040    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1041    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1042    Inst.addOperand(MCOperand::CreateImm(Val));
1043  }
1044
1045  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1046    assert(N == 2 && "Invalid number of operands!");
1047    // If this is an immediate, it's a label reference.
1048    if (Kind == Immediate) {
1049      addExpr(Inst, getImm());
1050      Inst.addOperand(MCOperand::CreateImm(0));
1051      return;
1052    }
1053
1054    // Otherwise, it's a normal memory reg+offset.
1055    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1056    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1057    Inst.addOperand(MCOperand::CreateImm(Val));
1058  }
1059
1060  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1061    assert(N == 3 && "Invalid number of operands!");
1062    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1063                                     Mem.ShiftImm, Mem.ShiftType);
1064    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1065    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1066    Inst.addOperand(MCOperand::CreateImm(Val));
1067  }
1068
1069  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1070    assert(N == 2 && "Invalid number of operands!");
1071    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1072    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1073  }
1074
1075  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1076    assert(N == 2 && "Invalid number of operands!");
1077    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1078    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1079    Inst.addOperand(MCOperand::CreateImm(Val));
1080  }
1081
1082  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1083    assert(N == 2 && "Invalid number of operands!");
1084    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1085    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1086    Inst.addOperand(MCOperand::CreateImm(Val));
1087  }
1088
1089  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1090    assert(N == 2 && "Invalid number of operands!");
1091    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1092    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1093    Inst.addOperand(MCOperand::CreateImm(Val));
1094  }
1095
1096  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1097    assert(N == 2 && "Invalid number of operands!");
1098    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1099    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1100    Inst.addOperand(MCOperand::CreateImm(Val));
1101  }
1102
1103  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1104    assert(N == 1 && "Invalid number of operands!");
1105    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1106    assert(CE && "non-constant post-idx-imm8 operand!");
1107    int Imm = CE->getValue();
1108    bool isAdd = Imm >= 0;
1109    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1110    Inst.addOperand(MCOperand::CreateImm(Imm));
1111  }
1112
1113  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1114    assert(N == 2 && "Invalid number of operands!");
1115    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1116    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1117  }
1118
1119  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1120    assert(N == 2 && "Invalid number of operands!");
1121    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1122    // The sign, shift type, and shift amount are encoded in a single operand
1123    // using the AM2 encoding helpers.
1124    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1125    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1126                                     PostIdxReg.ShiftTy);
1127    Inst.addOperand(MCOperand::CreateImm(Imm));
1128  }
1129
1130  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1131    assert(N == 1 && "Invalid number of operands!");
1132    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1133  }
1134
1135  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1136    assert(N == 1 && "Invalid number of operands!");
1137    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1138  }
1139
1140  virtual void print(raw_ostream &OS) const;
1141
1142  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1143    ARMOperand *Op = new ARMOperand(ITCondMask);
1144    Op->ITMask.Mask = Mask;
1145    Op->StartLoc = S;
1146    Op->EndLoc = S;
1147    return Op;
1148  }
1149
1150  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1151    ARMOperand *Op = new ARMOperand(CondCode);
1152    Op->CC.Val = CC;
1153    Op->StartLoc = S;
1154    Op->EndLoc = S;
1155    return Op;
1156  }
1157
1158  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1159    ARMOperand *Op = new ARMOperand(CoprocNum);
1160    Op->Cop.Val = CopVal;
1161    Op->StartLoc = S;
1162    Op->EndLoc = S;
1163    return Op;
1164  }
1165
1166  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1167    ARMOperand *Op = new ARMOperand(CoprocReg);
1168    Op->Cop.Val = CopVal;
1169    Op->StartLoc = S;
1170    Op->EndLoc = S;
1171    return Op;
1172  }
1173
1174  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1175    ARMOperand *Op = new ARMOperand(CCOut);
1176    Op->Reg.RegNum = RegNum;
1177    Op->StartLoc = S;
1178    Op->EndLoc = S;
1179    return Op;
1180  }
1181
1182  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1183    ARMOperand *Op = new ARMOperand(Token);
1184    Op->Tok.Data = Str.data();
1185    Op->Tok.Length = Str.size();
1186    Op->StartLoc = S;
1187    Op->EndLoc = S;
1188    return Op;
1189  }
1190
1191  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1192    ARMOperand *Op = new ARMOperand(Register);
1193    Op->Reg.RegNum = RegNum;
1194    Op->StartLoc = S;
1195    Op->EndLoc = E;
1196    return Op;
1197  }
1198
1199  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1200                                           unsigned SrcReg,
1201                                           unsigned ShiftReg,
1202                                           unsigned ShiftImm,
1203                                           SMLoc S, SMLoc E) {
1204    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1205    Op->RegShiftedReg.ShiftTy = ShTy;
1206    Op->RegShiftedReg.SrcReg = SrcReg;
1207    Op->RegShiftedReg.ShiftReg = ShiftReg;
1208    Op->RegShiftedReg.ShiftImm = ShiftImm;
1209    Op->StartLoc = S;
1210    Op->EndLoc = E;
1211    return Op;
1212  }
1213
1214  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1215                                            unsigned SrcReg,
1216                                            unsigned ShiftImm,
1217                                            SMLoc S, SMLoc E) {
1218    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1219    Op->RegShiftedImm.ShiftTy = ShTy;
1220    Op->RegShiftedImm.SrcReg = SrcReg;
1221    Op->RegShiftedImm.ShiftImm = ShiftImm;
1222    Op->StartLoc = S;
1223    Op->EndLoc = E;
1224    return Op;
1225  }
1226
1227  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1228                                   SMLoc S, SMLoc E) {
1229    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1230    Op->ShifterImm.isASR = isASR;
1231    Op->ShifterImm.Imm = Imm;
1232    Op->StartLoc = S;
1233    Op->EndLoc = E;
1234    return Op;
1235  }
1236
1237  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1238    ARMOperand *Op = new ARMOperand(RotateImmediate);
1239    Op->RotImm.Imm = Imm;
1240    Op->StartLoc = S;
1241    Op->EndLoc = E;
1242    return Op;
1243  }
1244
1245  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1246                                    SMLoc S, SMLoc E) {
1247    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1248    Op->Bitfield.LSB = LSB;
1249    Op->Bitfield.Width = Width;
1250    Op->StartLoc = S;
1251    Op->EndLoc = E;
1252    return Op;
1253  }
1254
1255  static ARMOperand *
1256  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1257                SMLoc StartLoc, SMLoc EndLoc) {
1258    KindTy Kind = RegisterList;
1259
1260    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1261        contains(Regs.front().first))
1262      Kind = DPRRegisterList;
1263    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1264             contains(Regs.front().first))
1265      Kind = SPRRegisterList;
1266
1267    ARMOperand *Op = new ARMOperand(Kind);
1268    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1269           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1270      Op->Registers.push_back(I->first);
1271    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1272    Op->StartLoc = StartLoc;
1273    Op->EndLoc = EndLoc;
1274    return Op;
1275  }
1276
1277  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1278    ARMOperand *Op = new ARMOperand(Immediate);
1279    Op->Imm.Val = Val;
1280    Op->StartLoc = S;
1281    Op->EndLoc = E;
1282    return Op;
1283  }
1284
1285  static ARMOperand *CreateMem(unsigned BaseRegNum,
1286                               const MCConstantExpr *OffsetImm,
1287                               unsigned OffsetRegNum,
1288                               ARM_AM::ShiftOpc ShiftType,
1289                               unsigned ShiftImm,
1290                               bool isNegative,
1291                               SMLoc S, SMLoc E) {
1292    ARMOperand *Op = new ARMOperand(Memory);
1293    Op->Mem.BaseRegNum = BaseRegNum;
1294    Op->Mem.OffsetImm = OffsetImm;
1295    Op->Mem.OffsetRegNum = OffsetRegNum;
1296    Op->Mem.ShiftType = ShiftType;
1297    Op->Mem.ShiftImm = ShiftImm;
1298    Op->Mem.isNegative = isNegative;
1299    Op->StartLoc = S;
1300    Op->EndLoc = E;
1301    return Op;
1302  }
1303
1304  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1305                                      ARM_AM::ShiftOpc ShiftTy,
1306                                      unsigned ShiftImm,
1307                                      SMLoc S, SMLoc E) {
1308    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1309    Op->PostIdxReg.RegNum = RegNum;
1310    Op->PostIdxReg.isAdd = isAdd;
1311    Op->PostIdxReg.ShiftTy = ShiftTy;
1312    Op->PostIdxReg.ShiftImm = ShiftImm;
1313    Op->StartLoc = S;
1314    Op->EndLoc = E;
1315    return Op;
1316  }
1317
1318  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1319    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1320    Op->MBOpt.Val = Opt;
1321    Op->StartLoc = S;
1322    Op->EndLoc = S;
1323    return Op;
1324  }
1325
1326  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1327    ARMOperand *Op = new ARMOperand(ProcIFlags);
1328    Op->IFlags.Val = IFlags;
1329    Op->StartLoc = S;
1330    Op->EndLoc = S;
1331    return Op;
1332  }
1333
1334  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1335    ARMOperand *Op = new ARMOperand(MSRMask);
1336    Op->MMask.Val = MMask;
1337    Op->StartLoc = S;
1338    Op->EndLoc = S;
1339    return Op;
1340  }
1341};
1342
1343} // end anonymous namespace.
1344
1345void ARMOperand::print(raw_ostream &OS) const {
1346  switch (Kind) {
1347  case CondCode:
1348    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1349    break;
1350  case CCOut:
1351    OS << "<ccout " << getReg() << ">";
1352    break;
1353  case ITCondMask: {
1354    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1355      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1356      "(tee)", "(eee)" };
1357    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1358    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1359    break;
1360  }
1361  case CoprocNum:
1362    OS << "<coprocessor number: " << getCoproc() << ">";
1363    break;
1364  case CoprocReg:
1365    OS << "<coprocessor register: " << getCoproc() << ">";
1366    break;
1367  case MSRMask:
1368    OS << "<mask: " << getMSRMask() << ">";
1369    break;
1370  case Immediate:
1371    getImm()->print(OS);
1372    break;
1373  case MemBarrierOpt:
1374    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1375    break;
1376  case Memory:
1377    OS << "<memory "
1378       << " base:" << Mem.BaseRegNum;
1379    OS << ">";
1380    break;
1381  case PostIndexRegister:
1382    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1383       << PostIdxReg.RegNum;
1384    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1385      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1386         << PostIdxReg.ShiftImm;
1387    OS << ">";
1388    break;
1389  case ProcIFlags: {
1390    OS << "<ARM_PROC::";
1391    unsigned IFlags = getProcIFlags();
1392    for (int i=2; i >= 0; --i)
1393      if (IFlags & (1 << i))
1394        OS << ARM_PROC::IFlagsToString(1 << i);
1395    OS << ">";
1396    break;
1397  }
1398  case Register:
1399    OS << "<register " << getReg() << ">";
1400    break;
1401  case ShifterImmediate:
1402    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1403       << " #" << ShifterImm.Imm << ">";
1404    break;
1405  case ShiftedRegister:
1406    OS << "<so_reg_reg "
1407       << RegShiftedReg.SrcReg
1408       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1409       << ", " << RegShiftedReg.ShiftReg << ", "
1410       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1411       << ">";
1412    break;
1413  case ShiftedImmediate:
1414    OS << "<so_reg_imm "
1415       << RegShiftedImm.SrcReg
1416       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1417       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1418       << ">";
1419    break;
1420  case RotateImmediate:
1421    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1422    break;
1423  case BitfieldDescriptor:
1424    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1425       << ", width: " << Bitfield.Width << ">";
1426    break;
1427  case RegisterList:
1428  case DPRRegisterList:
1429  case SPRRegisterList: {
1430    OS << "<register_list ";
1431
1432    const SmallVectorImpl<unsigned> &RegList = getRegList();
1433    for (SmallVectorImpl<unsigned>::const_iterator
1434           I = RegList.begin(), E = RegList.end(); I != E; ) {
1435      OS << *I;
1436      if (++I < E) OS << ", ";
1437    }
1438
1439    OS << ">";
1440    break;
1441  }
1442  case Token:
1443    OS << "'" << getToken() << "'";
1444    break;
1445  }
1446}
1447
1448/// @name Auto-generated Match Functions
1449/// {
1450
1451static unsigned MatchRegisterName(StringRef Name);
1452
1453/// }
1454
1455bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1456                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1457  RegNo = tryParseRegister();
1458
1459  return (RegNo == (unsigned)-1);
1460}
1461
1462/// Try to parse a register name.  The token must be an Identifier when called,
1463/// and if it is a register name the token is eaten and the register number is
1464/// returned.  Otherwise return -1.
1465///
1466int ARMAsmParser::tryParseRegister() {
1467  const AsmToken &Tok = Parser.getTok();
1468  if (Tok.isNot(AsmToken::Identifier)) return -1;
1469
1470  // FIXME: Validate register for the current architecture; we have to do
1471  // validation later, so maybe there is no need for this here.
1472  std::string upperCase = Tok.getString().str();
1473  std::string lowerCase = LowercaseString(upperCase);
1474  unsigned RegNum = MatchRegisterName(lowerCase);
1475  if (!RegNum) {
1476    RegNum = StringSwitch<unsigned>(lowerCase)
1477      .Case("r13", ARM::SP)
1478      .Case("r14", ARM::LR)
1479      .Case("r15", ARM::PC)
1480      .Case("ip", ARM::R12)
1481      .Default(0);
1482  }
1483  if (!RegNum) return -1;
1484
1485  Parser.Lex(); // Eat identifier token.
1486  return RegNum;
1487}
1488
1489// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1490// If a recoverable error occurs, return 1. If an irrecoverable error
1491// occurs, return -1. An irrecoverable error is one where tokens have been
1492// consumed in the process of trying to parse the shifter (i.e., when it is
1493// indeed a shifter operand, but malformed).
1494int ARMAsmParser::tryParseShiftRegister(
1495                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1496  SMLoc S = Parser.getTok().getLoc();
1497  const AsmToken &Tok = Parser.getTok();
1498  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1499
1500  std::string upperCase = Tok.getString().str();
1501  std::string lowerCase = LowercaseString(upperCase);
1502  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1503      .Case("lsl", ARM_AM::lsl)
1504      .Case("lsr", ARM_AM::lsr)
1505      .Case("asr", ARM_AM::asr)
1506      .Case("ror", ARM_AM::ror)
1507      .Case("rrx", ARM_AM::rrx)
1508      .Default(ARM_AM::no_shift);
1509
1510  if (ShiftTy == ARM_AM::no_shift)
1511    return 1;
1512
1513  Parser.Lex(); // Eat the operator.
1514
1515  // The source register for the shift has already been added to the
1516  // operand list, so we need to pop it off and combine it into the shifted
1517  // register operand instead.
1518  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1519  if (!PrevOp->isReg())
1520    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1521  int SrcReg = PrevOp->getReg();
1522  int64_t Imm = 0;
1523  int ShiftReg = 0;
1524  if (ShiftTy == ARM_AM::rrx) {
1525    // RRX Doesn't have an explicit shift amount. The encoder expects
1526    // the shift register to be the same as the source register. Seems odd,
1527    // but OK.
1528    ShiftReg = SrcReg;
1529  } else {
1530    // Figure out if this is shifted by a constant or a register (for non-RRX).
1531    if (Parser.getTok().is(AsmToken::Hash)) {
1532      Parser.Lex(); // Eat hash.
1533      SMLoc ImmLoc = Parser.getTok().getLoc();
1534      const MCExpr *ShiftExpr = 0;
1535      if (getParser().ParseExpression(ShiftExpr)) {
1536        Error(ImmLoc, "invalid immediate shift value");
1537        return -1;
1538      }
1539      // The expression must be evaluatable as an immediate.
1540      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1541      if (!CE) {
1542        Error(ImmLoc, "invalid immediate shift value");
1543        return -1;
1544      }
1545      // Range check the immediate.
1546      // lsl, ror: 0 <= imm <= 31
1547      // lsr, asr: 0 <= imm <= 32
1548      Imm = CE->getValue();
1549      if (Imm < 0 ||
1550          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1551          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1552        Error(ImmLoc, "immediate shift value out of range");
1553        return -1;
1554      }
1555    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1556      ShiftReg = tryParseRegister();
1557      SMLoc L = Parser.getTok().getLoc();
1558      if (ShiftReg == -1) {
1559        Error (L, "expected immediate or register in shift operand");
1560        return -1;
1561      }
1562    } else {
1563      Error (Parser.getTok().getLoc(),
1564                    "expected immediate or register in shift operand");
1565      return -1;
1566    }
1567  }
1568
1569  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1570    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1571                                                         ShiftReg, Imm,
1572                                               S, Parser.getTok().getLoc()));
1573  else
1574    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1575                                               S, Parser.getTok().getLoc()));
1576
1577  return 0;
1578}
1579
1580
1581/// Try to parse a register name.  The token must be an Identifier when called.
1582/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1583/// if there is a "writeback". 'true' if it's not a register.
1584///
1585/// TODO this is likely to change to allow different register types and or to
1586/// parse for a specific register type.
1587bool ARMAsmParser::
1588tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1589  SMLoc S = Parser.getTok().getLoc();
1590  int RegNo = tryParseRegister();
1591  if (RegNo == -1)
1592    return true;
1593
1594  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1595
1596  const AsmToken &ExclaimTok = Parser.getTok();
1597  if (ExclaimTok.is(AsmToken::Exclaim)) {
1598    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1599                                               ExclaimTok.getLoc()));
1600    Parser.Lex(); // Eat exclaim token
1601  }
1602
1603  return false;
1604}
1605
1606/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1607/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1608/// "c5", ...
1609static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1610  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1611  // but efficient.
1612  switch (Name.size()) {
1613  default: break;
1614  case 2:
1615    if (Name[0] != CoprocOp)
1616      return -1;
1617    switch (Name[1]) {
1618    default:  return -1;
1619    case '0': return 0;
1620    case '1': return 1;
1621    case '2': return 2;
1622    case '3': return 3;
1623    case '4': return 4;
1624    case '5': return 5;
1625    case '6': return 6;
1626    case '7': return 7;
1627    case '8': return 8;
1628    case '9': return 9;
1629    }
1630    break;
1631  case 3:
1632    if (Name[0] != CoprocOp || Name[1] != '1')
1633      return -1;
1634    switch (Name[2]) {
1635    default:  return -1;
1636    case '0': return 10;
1637    case '1': return 11;
1638    case '2': return 12;
1639    case '3': return 13;
1640    case '4': return 14;
1641    case '5': return 15;
1642    }
1643    break;
1644  }
1645
1646  return -1;
1647}
1648
1649/// parseITCondCode - Try to parse a condition code for an IT instruction.
1650ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1651parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1652  SMLoc S = Parser.getTok().getLoc();
1653  const AsmToken &Tok = Parser.getTok();
1654  if (!Tok.is(AsmToken::Identifier))
1655    return MatchOperand_NoMatch;
1656  unsigned CC = StringSwitch<unsigned>(Tok.getString())
1657    .Case("eq", ARMCC::EQ)
1658    .Case("ne", ARMCC::NE)
1659    .Case("hs", ARMCC::HS)
1660    .Case("cs", ARMCC::HS)
1661    .Case("lo", ARMCC::LO)
1662    .Case("cc", ARMCC::LO)
1663    .Case("mi", ARMCC::MI)
1664    .Case("pl", ARMCC::PL)
1665    .Case("vs", ARMCC::VS)
1666    .Case("vc", ARMCC::VC)
1667    .Case("hi", ARMCC::HI)
1668    .Case("ls", ARMCC::LS)
1669    .Case("ge", ARMCC::GE)
1670    .Case("lt", ARMCC::LT)
1671    .Case("gt", ARMCC::GT)
1672    .Case("le", ARMCC::LE)
1673    .Case("al", ARMCC::AL)
1674    .Default(~0U);
1675  if (CC == ~0U)
1676    return MatchOperand_NoMatch;
1677  Parser.Lex(); // Eat the token.
1678
1679  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1680
1681  return MatchOperand_Success;
1682}
1683
1684/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1685/// token must be an Identifier when called, and if it is a coprocessor
1686/// number, the token is eaten and the operand is added to the operand list.
1687ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1688parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1689  SMLoc S = Parser.getTok().getLoc();
1690  const AsmToken &Tok = Parser.getTok();
1691  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1692
1693  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1694  if (Num == -1)
1695    return MatchOperand_NoMatch;
1696
1697  Parser.Lex(); // Eat identifier token.
1698  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1699  return MatchOperand_Success;
1700}
1701
1702/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1703/// token must be an Identifier when called, and if it is a coprocessor
1704/// number, the token is eaten and the operand is added to the operand list.
1705ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1706parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1707  SMLoc S = Parser.getTok().getLoc();
1708  const AsmToken &Tok = Parser.getTok();
1709  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1710
1711  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1712  if (Reg == -1)
1713    return MatchOperand_NoMatch;
1714
1715  Parser.Lex(); // Eat identifier token.
1716  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1717  return MatchOperand_Success;
1718}
1719
1720/// Parse a register list, return it if successful else return null.  The first
1721/// token must be a '{' when called.
1722bool ARMAsmParser::
1723parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1724  assert(Parser.getTok().is(AsmToken::LCurly) &&
1725         "Token is not a Left Curly Brace");
1726  SMLoc S = Parser.getTok().getLoc();
1727
1728  // Read the rest of the registers in the list.
1729  unsigned PrevRegNum = 0;
1730  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1731
1732  do {
1733    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1734    Parser.Lex(); // Eat non-identifier token.
1735
1736    const AsmToken &RegTok = Parser.getTok();
1737    SMLoc RegLoc = RegTok.getLoc();
1738    if (RegTok.isNot(AsmToken::Identifier)) {
1739      Error(RegLoc, "register expected");
1740      return true;
1741    }
1742
1743    int RegNum = tryParseRegister();
1744    if (RegNum == -1) {
1745      Error(RegLoc, "register expected");
1746      return true;
1747    }
1748
1749    if (IsRange) {
1750      int Reg = PrevRegNum;
1751      do {
1752        ++Reg;
1753        Registers.push_back(std::make_pair(Reg, RegLoc));
1754      } while (Reg != RegNum);
1755    } else {
1756      Registers.push_back(std::make_pair(RegNum, RegLoc));
1757    }
1758
1759    PrevRegNum = RegNum;
1760  } while (Parser.getTok().is(AsmToken::Comma) ||
1761           Parser.getTok().is(AsmToken::Minus));
1762
1763  // Process the right curly brace of the list.
1764  const AsmToken &RCurlyTok = Parser.getTok();
1765  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1766    Error(RCurlyTok.getLoc(), "'}' expected");
1767    return true;
1768  }
1769
1770  SMLoc E = RCurlyTok.getLoc();
1771  Parser.Lex(); // Eat right curly brace token.
1772
1773  // Verify the register list.
1774  bool EmittedWarning = false;
1775  unsigned HighRegNum = 0;
1776  BitVector RegMap(32);
1777  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1778    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1779    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1780
1781    if (RegMap[Reg]) {
1782      Error(RegInfo.second, "register duplicated in register list");
1783      return true;
1784    }
1785
1786    if (!EmittedWarning && Reg < HighRegNum)
1787      Warning(RegInfo.second,
1788              "register not in ascending order in register list");
1789
1790    RegMap.set(Reg);
1791    HighRegNum = std::max(Reg, HighRegNum);
1792  }
1793
1794  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1795  return false;
1796}
1797
1798/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1799ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1800parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1801  SMLoc S = Parser.getTok().getLoc();
1802  const AsmToken &Tok = Parser.getTok();
1803  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1804  StringRef OptStr = Tok.getString();
1805
1806  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1807    .Case("sy",    ARM_MB::SY)
1808    .Case("st",    ARM_MB::ST)
1809    .Case("sh",    ARM_MB::ISH)
1810    .Case("ish",   ARM_MB::ISH)
1811    .Case("shst",  ARM_MB::ISHST)
1812    .Case("ishst", ARM_MB::ISHST)
1813    .Case("nsh",   ARM_MB::NSH)
1814    .Case("un",    ARM_MB::NSH)
1815    .Case("nshst", ARM_MB::NSHST)
1816    .Case("unst",  ARM_MB::NSHST)
1817    .Case("osh",   ARM_MB::OSH)
1818    .Case("oshst", ARM_MB::OSHST)
1819    .Default(~0U);
1820
1821  if (Opt == ~0U)
1822    return MatchOperand_NoMatch;
1823
1824  Parser.Lex(); // Eat identifier token.
1825  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1826  return MatchOperand_Success;
1827}
1828
1829/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1830ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1831parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1832  SMLoc S = Parser.getTok().getLoc();
1833  const AsmToken &Tok = Parser.getTok();
1834  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1835  StringRef IFlagsStr = Tok.getString();
1836
1837  unsigned IFlags = 0;
1838  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1839    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1840    .Case("a", ARM_PROC::A)
1841    .Case("i", ARM_PROC::I)
1842    .Case("f", ARM_PROC::F)
1843    .Default(~0U);
1844
1845    // If some specific iflag is already set, it means that some letter is
1846    // present more than once, this is not acceptable.
1847    if (Flag == ~0U || (IFlags & Flag))
1848      return MatchOperand_NoMatch;
1849
1850    IFlags |= Flag;
1851  }
1852
1853  Parser.Lex(); // Eat identifier token.
1854  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1855  return MatchOperand_Success;
1856}
1857
1858/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1859ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1860parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1861  SMLoc S = Parser.getTok().getLoc();
1862  const AsmToken &Tok = Parser.getTok();
1863  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1864  StringRef Mask = Tok.getString();
1865
1866  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1867  size_t Start = 0, Next = Mask.find('_');
1868  StringRef Flags = "";
1869  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1870  if (Next != StringRef::npos)
1871    Flags = Mask.slice(Next+1, Mask.size());
1872
1873  // FlagsVal contains the complete mask:
1874  // 3-0: Mask
1875  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1876  unsigned FlagsVal = 0;
1877
1878  if (SpecReg == "apsr") {
1879    FlagsVal = StringSwitch<unsigned>(Flags)
1880    .Case("nzcvq",  0x8) // same as CPSR_f
1881    .Case("g",      0x4) // same as CPSR_s
1882    .Case("nzcvqg", 0xc) // same as CPSR_fs
1883    .Default(~0U);
1884
1885    if (FlagsVal == ~0U) {
1886      if (!Flags.empty())
1887        return MatchOperand_NoMatch;
1888      else
1889        FlagsVal = 0; // No flag
1890    }
1891  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1892    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1893      Flags = "fc";
1894    for (int i = 0, e = Flags.size(); i != e; ++i) {
1895      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1896      .Case("c", 1)
1897      .Case("x", 2)
1898      .Case("s", 4)
1899      .Case("f", 8)
1900      .Default(~0U);
1901
1902      // If some specific flag is already set, it means that some letter is
1903      // present more than once, this is not acceptable.
1904      if (FlagsVal == ~0U || (FlagsVal & Flag))
1905        return MatchOperand_NoMatch;
1906      FlagsVal |= Flag;
1907    }
1908  } else // No match for special register.
1909    return MatchOperand_NoMatch;
1910
1911  // Special register without flags are equivalent to "fc" flags.
1912  if (!FlagsVal)
1913    FlagsVal = 0x9;
1914
1915  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1916  if (SpecReg == "spsr")
1917    FlagsVal |= 16;
1918
1919  Parser.Lex(); // Eat identifier token.
1920  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1921  return MatchOperand_Success;
1922}
1923
1924ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1925parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1926            int Low, int High) {
1927  const AsmToken &Tok = Parser.getTok();
1928  if (Tok.isNot(AsmToken::Identifier)) {
1929    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1930    return MatchOperand_ParseFail;
1931  }
1932  StringRef ShiftName = Tok.getString();
1933  std::string LowerOp = LowercaseString(Op);
1934  std::string UpperOp = UppercaseString(Op);
1935  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1936    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1937    return MatchOperand_ParseFail;
1938  }
1939  Parser.Lex(); // Eat shift type token.
1940
1941  // There must be a '#' and a shift amount.
1942  if (Parser.getTok().isNot(AsmToken::Hash)) {
1943    Error(Parser.getTok().getLoc(), "'#' expected");
1944    return MatchOperand_ParseFail;
1945  }
1946  Parser.Lex(); // Eat hash token.
1947
1948  const MCExpr *ShiftAmount;
1949  SMLoc Loc = Parser.getTok().getLoc();
1950  if (getParser().ParseExpression(ShiftAmount)) {
1951    Error(Loc, "illegal expression");
1952    return MatchOperand_ParseFail;
1953  }
1954  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1955  if (!CE) {
1956    Error(Loc, "constant expression expected");
1957    return MatchOperand_ParseFail;
1958  }
1959  int Val = CE->getValue();
1960  if (Val < Low || Val > High) {
1961    Error(Loc, "immediate value out of range");
1962    return MatchOperand_ParseFail;
1963  }
1964
1965  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1966
1967  return MatchOperand_Success;
1968}
1969
1970ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1971parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1972  const AsmToken &Tok = Parser.getTok();
1973  SMLoc S = Tok.getLoc();
1974  if (Tok.isNot(AsmToken::Identifier)) {
1975    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1976    return MatchOperand_ParseFail;
1977  }
1978  int Val = StringSwitch<int>(Tok.getString())
1979    .Case("be", 1)
1980    .Case("le", 0)
1981    .Default(-1);
1982  Parser.Lex(); // Eat the token.
1983
1984  if (Val == -1) {
1985    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1986    return MatchOperand_ParseFail;
1987  }
1988  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1989                                                                  getContext()),
1990                                           S, Parser.getTok().getLoc()));
1991  return MatchOperand_Success;
1992}
1993
1994/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1995/// instructions. Legal values are:
1996///     lsl #n  'n' in [0,31]
1997///     asr #n  'n' in [1,32]
1998///             n == 32 encoded as n == 0.
1999ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2000parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2001  const AsmToken &Tok = Parser.getTok();
2002  SMLoc S = Tok.getLoc();
2003  if (Tok.isNot(AsmToken::Identifier)) {
2004    Error(S, "shift operator 'asr' or 'lsl' expected");
2005    return MatchOperand_ParseFail;
2006  }
2007  StringRef ShiftName = Tok.getString();
2008  bool isASR;
2009  if (ShiftName == "lsl" || ShiftName == "LSL")
2010    isASR = false;
2011  else if (ShiftName == "asr" || ShiftName == "ASR")
2012    isASR = true;
2013  else {
2014    Error(S, "shift operator 'asr' or 'lsl' expected");
2015    return MatchOperand_ParseFail;
2016  }
2017  Parser.Lex(); // Eat the operator.
2018
2019  // A '#' and a shift amount.
2020  if (Parser.getTok().isNot(AsmToken::Hash)) {
2021    Error(Parser.getTok().getLoc(), "'#' expected");
2022    return MatchOperand_ParseFail;
2023  }
2024  Parser.Lex(); // Eat hash token.
2025
2026  const MCExpr *ShiftAmount;
2027  SMLoc E = Parser.getTok().getLoc();
2028  if (getParser().ParseExpression(ShiftAmount)) {
2029    Error(E, "malformed shift expression");
2030    return MatchOperand_ParseFail;
2031  }
2032  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2033  if (!CE) {
2034    Error(E, "shift amount must be an immediate");
2035    return MatchOperand_ParseFail;
2036  }
2037
2038  int64_t Val = CE->getValue();
2039  if (isASR) {
2040    // Shift amount must be in [1,32]
2041    if (Val < 1 || Val > 32) {
2042      Error(E, "'asr' shift amount must be in range [1,32]");
2043      return MatchOperand_ParseFail;
2044    }
2045    // asr #32 encoded as asr #0.
2046    if (Val == 32) Val = 0;
2047  } else {
2048    // Shift amount must be in [1,32]
2049    if (Val < 0 || Val > 31) {
2050      Error(E, "'lsr' shift amount must be in range [0,31]");
2051      return MatchOperand_ParseFail;
2052    }
2053  }
2054
2055  E = Parser.getTok().getLoc();
2056  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2057
2058  return MatchOperand_Success;
2059}
2060
2061/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2062/// of instructions. Legal values are:
2063///     ror #n  'n' in {0, 8, 16, 24}
2064ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2065parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2066  const AsmToken &Tok = Parser.getTok();
2067  SMLoc S = Tok.getLoc();
2068  if (Tok.isNot(AsmToken::Identifier)) {
2069    Error(S, "rotate operator 'ror' expected");
2070    return MatchOperand_ParseFail;
2071  }
2072  StringRef ShiftName = Tok.getString();
2073  if (ShiftName != "ror" && ShiftName != "ROR") {
2074    Error(S, "rotate operator 'ror' expected");
2075    return MatchOperand_ParseFail;
2076  }
2077  Parser.Lex(); // Eat the operator.
2078
2079  // A '#' and a rotate amount.
2080  if (Parser.getTok().isNot(AsmToken::Hash)) {
2081    Error(Parser.getTok().getLoc(), "'#' expected");
2082    return MatchOperand_ParseFail;
2083  }
2084  Parser.Lex(); // Eat hash token.
2085
2086  const MCExpr *ShiftAmount;
2087  SMLoc E = Parser.getTok().getLoc();
2088  if (getParser().ParseExpression(ShiftAmount)) {
2089    Error(E, "malformed rotate expression");
2090    return MatchOperand_ParseFail;
2091  }
2092  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2093  if (!CE) {
2094    Error(E, "rotate amount must be an immediate");
2095    return MatchOperand_ParseFail;
2096  }
2097
2098  int64_t Val = CE->getValue();
2099  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2100  // normally, zero is represented in asm by omitting the rotate operand
2101  // entirely.
2102  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2103    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2104    return MatchOperand_ParseFail;
2105  }
2106
2107  E = Parser.getTok().getLoc();
2108  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2109
2110  return MatchOperand_Success;
2111}
2112
2113ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2114parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2115  SMLoc S = Parser.getTok().getLoc();
2116  // The bitfield descriptor is really two operands, the LSB and the width.
2117  if (Parser.getTok().isNot(AsmToken::Hash)) {
2118    Error(Parser.getTok().getLoc(), "'#' expected");
2119    return MatchOperand_ParseFail;
2120  }
2121  Parser.Lex(); // Eat hash token.
2122
2123  const MCExpr *LSBExpr;
2124  SMLoc E = Parser.getTok().getLoc();
2125  if (getParser().ParseExpression(LSBExpr)) {
2126    Error(E, "malformed immediate expression");
2127    return MatchOperand_ParseFail;
2128  }
2129  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2130  if (!CE) {
2131    Error(E, "'lsb' operand must be an immediate");
2132    return MatchOperand_ParseFail;
2133  }
2134
2135  int64_t LSB = CE->getValue();
2136  // The LSB must be in the range [0,31]
2137  if (LSB < 0 || LSB > 31) {
2138    Error(E, "'lsb' operand must be in the range [0,31]");
2139    return MatchOperand_ParseFail;
2140  }
2141  E = Parser.getTok().getLoc();
2142
2143  // Expect another immediate operand.
2144  if (Parser.getTok().isNot(AsmToken::Comma)) {
2145    Error(Parser.getTok().getLoc(), "too few operands");
2146    return MatchOperand_ParseFail;
2147  }
2148  Parser.Lex(); // Eat hash token.
2149  if (Parser.getTok().isNot(AsmToken::Hash)) {
2150    Error(Parser.getTok().getLoc(), "'#' expected");
2151    return MatchOperand_ParseFail;
2152  }
2153  Parser.Lex(); // Eat hash token.
2154
2155  const MCExpr *WidthExpr;
2156  if (getParser().ParseExpression(WidthExpr)) {
2157    Error(E, "malformed immediate expression");
2158    return MatchOperand_ParseFail;
2159  }
2160  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2161  if (!CE) {
2162    Error(E, "'width' operand must be an immediate");
2163    return MatchOperand_ParseFail;
2164  }
2165
2166  int64_t Width = CE->getValue();
2167  // The LSB must be in the range [1,32-lsb]
2168  if (Width < 1 || Width > 32 - LSB) {
2169    Error(E, "'width' operand must be in the range [1,32-lsb]");
2170    return MatchOperand_ParseFail;
2171  }
2172  E = Parser.getTok().getLoc();
2173
2174  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2175
2176  return MatchOperand_Success;
2177}
2178
2179ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2180parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2181  // Check for a post-index addressing register operand. Specifically:
2182  // postidx_reg := '+' register {, shift}
2183  //              | '-' register {, shift}
2184  //              | register {, shift}
2185
2186  // This method must return MatchOperand_NoMatch without consuming any tokens
2187  // in the case where there is no match, as other alternatives take other
2188  // parse methods.
2189  AsmToken Tok = Parser.getTok();
2190  SMLoc S = Tok.getLoc();
2191  bool haveEaten = false;
2192  bool isAdd = true;
2193  int Reg = -1;
2194  if (Tok.is(AsmToken::Plus)) {
2195    Parser.Lex(); // Eat the '+' token.
2196    haveEaten = true;
2197  } else if (Tok.is(AsmToken::Minus)) {
2198    Parser.Lex(); // Eat the '-' token.
2199    isAdd = false;
2200    haveEaten = true;
2201  }
2202  if (Parser.getTok().is(AsmToken::Identifier))
2203    Reg = tryParseRegister();
2204  if (Reg == -1) {
2205    if (!haveEaten)
2206      return MatchOperand_NoMatch;
2207    Error(Parser.getTok().getLoc(), "register expected");
2208    return MatchOperand_ParseFail;
2209  }
2210  SMLoc E = Parser.getTok().getLoc();
2211
2212  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2213  unsigned ShiftImm = 0;
2214  if (Parser.getTok().is(AsmToken::Comma)) {
2215    Parser.Lex(); // Eat the ','.
2216    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2217      return MatchOperand_ParseFail;
2218  }
2219
2220  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2221                                                  ShiftImm, S, E));
2222
2223  return MatchOperand_Success;
2224}
2225
2226ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2227parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2228  // Check for a post-index addressing register operand. Specifically:
2229  // am3offset := '+' register
2230  //              | '-' register
2231  //              | register
2232  //              | # imm
2233  //              | # + imm
2234  //              | # - imm
2235
2236  // This method must return MatchOperand_NoMatch without consuming any tokens
2237  // in the case where there is no match, as other alternatives take other
2238  // parse methods.
2239  AsmToken Tok = Parser.getTok();
2240  SMLoc S = Tok.getLoc();
2241
2242  // Do immediates first, as we always parse those if we have a '#'.
2243  if (Parser.getTok().is(AsmToken::Hash)) {
2244    Parser.Lex(); // Eat the '#'.
2245    // Explicitly look for a '-', as we need to encode negative zero
2246    // differently.
2247    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2248    const MCExpr *Offset;
2249    if (getParser().ParseExpression(Offset))
2250      return MatchOperand_ParseFail;
2251    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2252    if (!CE) {
2253      Error(S, "constant expression expected");
2254      return MatchOperand_ParseFail;
2255    }
2256    SMLoc E = Tok.getLoc();
2257    // Negative zero is encoded as the flag value INT32_MIN.
2258    int32_t Val = CE->getValue();
2259    if (isNegative && Val == 0)
2260      Val = INT32_MIN;
2261
2262    Operands.push_back(
2263      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2264
2265    return MatchOperand_Success;
2266  }
2267
2268
2269  bool haveEaten = false;
2270  bool isAdd = true;
2271  int Reg = -1;
2272  if (Tok.is(AsmToken::Plus)) {
2273    Parser.Lex(); // Eat the '+' token.
2274    haveEaten = true;
2275  } else if (Tok.is(AsmToken::Minus)) {
2276    Parser.Lex(); // Eat the '-' token.
2277    isAdd = false;
2278    haveEaten = true;
2279  }
2280  if (Parser.getTok().is(AsmToken::Identifier))
2281    Reg = tryParseRegister();
2282  if (Reg == -1) {
2283    if (!haveEaten)
2284      return MatchOperand_NoMatch;
2285    Error(Parser.getTok().getLoc(), "register expected");
2286    return MatchOperand_ParseFail;
2287  }
2288  SMLoc E = Parser.getTok().getLoc();
2289
2290  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2291                                                  0, S, E));
2292
2293  return MatchOperand_Success;
2294}
2295
2296/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2297/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2298/// when they refer multiple MIOperands inside a single one.
2299bool ARMAsmParser::
2300cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2301                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2302  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2303
2304  // Create a writeback register dummy placeholder.
2305  Inst.addOperand(MCOperand::CreateImm(0));
2306
2307  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2308  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2309  return true;
2310}
2311
2312/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2313/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2314/// when they refer multiple MIOperands inside a single one.
2315bool ARMAsmParser::
2316cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2317                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2318  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2319
2320  // Create a writeback register dummy placeholder.
2321  Inst.addOperand(MCOperand::CreateImm(0));
2322
2323  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2324  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2325  return true;
2326}
2327
2328
2329/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2330/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2331/// when they refer multiple MIOperands inside a single one.
2332bool ARMAsmParser::
2333cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2334                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2335  // Create a writeback register dummy placeholder.
2336  Inst.addOperand(MCOperand::CreateImm(0));
2337  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2338  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2339  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2340  return true;
2341}
2342
2343/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2344/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2345/// when they refer multiple MIOperands inside a single one.
2346bool ARMAsmParser::
2347cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2348                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2349  // Create a writeback register dummy placeholder.
2350  Inst.addOperand(MCOperand::CreateImm(0));
2351  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2352  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2353  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2354  return true;
2355}
2356
2357/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2358/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2359/// when they refer multiple MIOperands inside a single one.
2360bool ARMAsmParser::
2361cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2362                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2363  // Create a writeback register dummy placeholder.
2364  Inst.addOperand(MCOperand::CreateImm(0));
2365  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2366  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2367  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2368  return true;
2369}
2370
2371/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2372/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2373/// when they refer multiple MIOperands inside a single one.
2374bool ARMAsmParser::
2375cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2376                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2377  // Rt
2378  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2379  // Create a writeback register dummy placeholder.
2380  Inst.addOperand(MCOperand::CreateImm(0));
2381  // addr
2382  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2383  // offset
2384  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2385  // pred
2386  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2387  return true;
2388}
2389
2390/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2391/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2392/// when they refer multiple MIOperands inside a single one.
2393bool ARMAsmParser::
2394cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2395                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2396  // Rt
2397  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2398  // Create a writeback register dummy placeholder.
2399  Inst.addOperand(MCOperand::CreateImm(0));
2400  // addr
2401  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2402  // offset
2403  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2404  // pred
2405  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2406  return true;
2407}
2408
2409/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2410/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2411/// when they refer multiple MIOperands inside a single one.
2412bool ARMAsmParser::
2413cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2414                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2415  // Create a writeback register dummy placeholder.
2416  Inst.addOperand(MCOperand::CreateImm(0));
2417  // Rt
2418  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2419  // addr
2420  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2421  // offset
2422  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2423  // pred
2424  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2425  return true;
2426}
2427
2428/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2429/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2430/// when they refer multiple MIOperands inside a single one.
2431bool ARMAsmParser::
2432cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2433                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2434  // Create a writeback register dummy placeholder.
2435  Inst.addOperand(MCOperand::CreateImm(0));
2436  // Rt
2437  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2438  // addr
2439  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2440  // offset
2441  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2442  // pred
2443  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2444  return true;
2445}
2446
2447/// cvtLdrdPre - Convert parsed operands to MCInst.
2448/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2449/// when they refer multiple MIOperands inside a single one.
2450bool ARMAsmParser::
2451cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2452           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2453  // Rt, Rt2
2454  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2455  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2456  // Create a writeback register dummy placeholder.
2457  Inst.addOperand(MCOperand::CreateImm(0));
2458  // addr
2459  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2460  // pred
2461  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2462  return true;
2463}
2464
2465/// cvtStrdPre - Convert parsed operands to MCInst.
2466/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2467/// when they refer multiple MIOperands inside a single one.
2468bool ARMAsmParser::
2469cvtStrdPre(MCInst &Inst, unsigned Opcode,
2470           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2471  // Create a writeback register dummy placeholder.
2472  Inst.addOperand(MCOperand::CreateImm(0));
2473  // Rt, Rt2
2474  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2475  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2476  // addr
2477  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2478  // pred
2479  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2480  return true;
2481}
2482
2483/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2484/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2485/// when they refer multiple MIOperands inside a single one.
2486bool ARMAsmParser::
2487cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2488                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2489  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2490  // Create a writeback register dummy placeholder.
2491  Inst.addOperand(MCOperand::CreateImm(0));
2492  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2493  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2494  return true;
2495}
2496
2497/// cvtThumbMultiple- Convert parsed operands to MCInst.
2498/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2499/// when they refer multiple MIOperands inside a single one.
2500bool ARMAsmParser::
2501cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2502           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2503  // The second source operand must be the same register as the destination
2504  // operand.
2505  if (Operands.size() == 6 &&
2506      (((ARMOperand*)Operands[3])->getReg() !=
2507       ((ARMOperand*)Operands[5])->getReg()) &&
2508      (((ARMOperand*)Operands[3])->getReg() !=
2509       ((ARMOperand*)Operands[4])->getReg())) {
2510    Error(Operands[3]->getStartLoc(),
2511          "destination register must match source register");
2512    return false;
2513  }
2514  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2515  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2516  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2517  // If we have a three-operand form, use that, else the second source operand
2518  // is just the destination operand again.
2519  if (Operands.size() == 6)
2520    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2521  else
2522    Inst.addOperand(Inst.getOperand(0));
2523  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2524
2525  return true;
2526}
2527
2528/// Parse an ARM memory expression, return false if successful else return true
2529/// or an error.  The first token must be a '[' when called.
2530bool ARMAsmParser::
2531parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2532  SMLoc S, E;
2533  assert(Parser.getTok().is(AsmToken::LBrac) &&
2534         "Token is not a Left Bracket");
2535  S = Parser.getTok().getLoc();
2536  Parser.Lex(); // Eat left bracket token.
2537
2538  const AsmToken &BaseRegTok = Parser.getTok();
2539  int BaseRegNum = tryParseRegister();
2540  if (BaseRegNum == -1)
2541    return Error(BaseRegTok.getLoc(), "register expected");
2542
2543  // The next token must either be a comma or a closing bracket.
2544  const AsmToken &Tok = Parser.getTok();
2545  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2546    return Error(Tok.getLoc(), "malformed memory operand");
2547
2548  if (Tok.is(AsmToken::RBrac)) {
2549    E = Tok.getLoc();
2550    Parser.Lex(); // Eat right bracket token.
2551
2552    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2553                                             0, false, S, E));
2554
2555    return false;
2556  }
2557
2558  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2559  Parser.Lex(); // Eat the comma.
2560
2561  // If we have a '#' it's an immediate offset, else assume it's a register
2562  // offset.
2563  if (Parser.getTok().is(AsmToken::Hash)) {
2564    Parser.Lex(); // Eat the '#'.
2565    E = Parser.getTok().getLoc();
2566
2567    // FIXME: Special case #-0 so we can correctly set the U bit.
2568
2569    const MCExpr *Offset;
2570    if (getParser().ParseExpression(Offset))
2571     return true;
2572
2573    // The expression has to be a constant. Memory references with relocations
2574    // don't come through here, as they use the <label> forms of the relevant
2575    // instructions.
2576    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2577    if (!CE)
2578      return Error (E, "constant expression expected");
2579
2580    // Now we should have the closing ']'
2581    E = Parser.getTok().getLoc();
2582    if (Parser.getTok().isNot(AsmToken::RBrac))
2583      return Error(E, "']' expected");
2584    Parser.Lex(); // Eat right bracket token.
2585
2586    // Don't worry about range checking the value here. That's handled by
2587    // the is*() predicates.
2588    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2589                                             ARM_AM::no_shift, 0, false, S,E));
2590
2591    // If there's a pre-indexing writeback marker, '!', just add it as a token
2592    // operand.
2593    if (Parser.getTok().is(AsmToken::Exclaim)) {
2594      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2595      Parser.Lex(); // Eat the '!'.
2596    }
2597
2598    return false;
2599  }
2600
2601  // The register offset is optionally preceded by a '+' or '-'
2602  bool isNegative = false;
2603  if (Parser.getTok().is(AsmToken::Minus)) {
2604    isNegative = true;
2605    Parser.Lex(); // Eat the '-'.
2606  } else if (Parser.getTok().is(AsmToken::Plus)) {
2607    // Nothing to do.
2608    Parser.Lex(); // Eat the '+'.
2609  }
2610
2611  E = Parser.getTok().getLoc();
2612  int OffsetRegNum = tryParseRegister();
2613  if (OffsetRegNum == -1)
2614    return Error(E, "register expected");
2615
2616  // If there's a shift operator, handle it.
2617  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2618  unsigned ShiftImm = 0;
2619  if (Parser.getTok().is(AsmToken::Comma)) {
2620    Parser.Lex(); // Eat the ','.
2621    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2622      return true;
2623  }
2624
2625  // Now we should have the closing ']'
2626  E = Parser.getTok().getLoc();
2627  if (Parser.getTok().isNot(AsmToken::RBrac))
2628    return Error(E, "']' expected");
2629  Parser.Lex(); // Eat right bracket token.
2630
2631  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2632                                           ShiftType, ShiftImm, isNegative,
2633                                           S, E));
2634
2635  // If there's a pre-indexing writeback marker, '!', just add it as a token
2636  // operand.
2637  if (Parser.getTok().is(AsmToken::Exclaim)) {
2638    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2639    Parser.Lex(); // Eat the '!'.
2640  }
2641
2642  return false;
2643}
2644
2645/// parseMemRegOffsetShift - one of these two:
2646///   ( lsl | lsr | asr | ror ) , # shift_amount
2647///   rrx
2648/// return true if it parses a shift otherwise it returns false.
2649bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2650                                          unsigned &Amount) {
2651  SMLoc Loc = Parser.getTok().getLoc();
2652  const AsmToken &Tok = Parser.getTok();
2653  if (Tok.isNot(AsmToken::Identifier))
2654    return true;
2655  StringRef ShiftName = Tok.getString();
2656  if (ShiftName == "lsl" || ShiftName == "LSL")
2657    St = ARM_AM::lsl;
2658  else if (ShiftName == "lsr" || ShiftName == "LSR")
2659    St = ARM_AM::lsr;
2660  else if (ShiftName == "asr" || ShiftName == "ASR")
2661    St = ARM_AM::asr;
2662  else if (ShiftName == "ror" || ShiftName == "ROR")
2663    St = ARM_AM::ror;
2664  else if (ShiftName == "rrx" || ShiftName == "RRX")
2665    St = ARM_AM::rrx;
2666  else
2667    return Error(Loc, "illegal shift operator");
2668  Parser.Lex(); // Eat shift type token.
2669
2670  // rrx stands alone.
2671  Amount = 0;
2672  if (St != ARM_AM::rrx) {
2673    Loc = Parser.getTok().getLoc();
2674    // A '#' and a shift amount.
2675    const AsmToken &HashTok = Parser.getTok();
2676    if (HashTok.isNot(AsmToken::Hash))
2677      return Error(HashTok.getLoc(), "'#' expected");
2678    Parser.Lex(); // Eat hash token.
2679
2680    const MCExpr *Expr;
2681    if (getParser().ParseExpression(Expr))
2682      return true;
2683    // Range check the immediate.
2684    // lsl, ror: 0 <= imm <= 31
2685    // lsr, asr: 0 <= imm <= 32
2686    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2687    if (!CE)
2688      return Error(Loc, "shift amount must be an immediate");
2689    int64_t Imm = CE->getValue();
2690    if (Imm < 0 ||
2691        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2692        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2693      return Error(Loc, "immediate shift value out of range");
2694    Amount = Imm;
2695  }
2696
2697  return false;
2698}
2699
2700/// Parse a arm instruction operand.  For now this parses the operand regardless
2701/// of the mnemonic.
2702bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2703                                StringRef Mnemonic) {
2704  SMLoc S, E;
2705
2706  // Check if the current operand has a custom associated parser, if so, try to
2707  // custom parse the operand, or fallback to the general approach.
2708  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2709  if (ResTy == MatchOperand_Success)
2710    return false;
2711  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2712  // there was a match, but an error occurred, in which case, just return that
2713  // the operand parsing failed.
2714  if (ResTy == MatchOperand_ParseFail)
2715    return true;
2716
2717  switch (getLexer().getKind()) {
2718  default:
2719    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2720    return true;
2721  case AsmToken::Identifier: {
2722    if (!tryParseRegisterWithWriteBack(Operands))
2723      return false;
2724    int Res = tryParseShiftRegister(Operands);
2725    if (Res == 0) // success
2726      return false;
2727    else if (Res == -1) // irrecoverable error
2728      return true;
2729
2730    // Fall though for the Identifier case that is not a register or a
2731    // special name.
2732  }
2733  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2734  case AsmToken::Dot: {   // . as a branch target
2735    // This was not a register so parse other operands that start with an
2736    // identifier (like labels) as expressions and create them as immediates.
2737    const MCExpr *IdVal;
2738    S = Parser.getTok().getLoc();
2739    if (getParser().ParseExpression(IdVal))
2740      return true;
2741    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2742    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2743    return false;
2744  }
2745  case AsmToken::LBrac:
2746    return parseMemory(Operands);
2747  case AsmToken::LCurly:
2748    return parseRegisterList(Operands);
2749  case AsmToken::Hash:
2750    // #42 -> immediate.
2751    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2752    S = Parser.getTok().getLoc();
2753    Parser.Lex();
2754    const MCExpr *ImmVal;
2755    if (getParser().ParseExpression(ImmVal))
2756      return true;
2757    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2758    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2759    return false;
2760  case AsmToken::Colon: {
2761    // ":lower16:" and ":upper16:" expression prefixes
2762    // FIXME: Check it's an expression prefix,
2763    // e.g. (FOO - :lower16:BAR) isn't legal.
2764    ARMMCExpr::VariantKind RefKind;
2765    if (parsePrefix(RefKind))
2766      return true;
2767
2768    const MCExpr *SubExprVal;
2769    if (getParser().ParseExpression(SubExprVal))
2770      return true;
2771
2772    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2773                                                   getContext());
2774    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2775    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2776    return false;
2777  }
2778  }
2779}
2780
2781// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2782//  :lower16: and :upper16:.
2783bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2784  RefKind = ARMMCExpr::VK_ARM_None;
2785
2786  // :lower16: and :upper16: modifiers
2787  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2788  Parser.Lex(); // Eat ':'
2789
2790  if (getLexer().isNot(AsmToken::Identifier)) {
2791    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2792    return true;
2793  }
2794
2795  StringRef IDVal = Parser.getTok().getIdentifier();
2796  if (IDVal == "lower16") {
2797    RefKind = ARMMCExpr::VK_ARM_LO16;
2798  } else if (IDVal == "upper16") {
2799    RefKind = ARMMCExpr::VK_ARM_HI16;
2800  } else {
2801    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2802    return true;
2803  }
2804  Parser.Lex();
2805
2806  if (getLexer().isNot(AsmToken::Colon)) {
2807    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2808    return true;
2809  }
2810  Parser.Lex(); // Eat the last ':'
2811  return false;
2812}
2813
2814const MCExpr *
2815ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2816                                MCSymbolRefExpr::VariantKind Variant) {
2817  // Recurse over the given expression, rebuilding it to apply the given variant
2818  // to the leftmost symbol.
2819  if (Variant == MCSymbolRefExpr::VK_None)
2820    return E;
2821
2822  switch (E->getKind()) {
2823  case MCExpr::Target:
2824    llvm_unreachable("Can't handle target expr yet");
2825  case MCExpr::Constant:
2826    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2827
2828  case MCExpr::SymbolRef: {
2829    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2830
2831    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2832      return 0;
2833
2834    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2835  }
2836
2837  case MCExpr::Unary:
2838    llvm_unreachable("Can't handle unary expressions yet");
2839
2840  case MCExpr::Binary: {
2841    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2842    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2843    const MCExpr *RHS = BE->getRHS();
2844    if (!LHS)
2845      return 0;
2846
2847    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2848  }
2849  }
2850
2851  assert(0 && "Invalid expression kind!");
2852  return 0;
2853}
2854
2855/// \brief Given a mnemonic, split out possible predication code and carry
2856/// setting letters to form a canonical mnemonic and flags.
2857//
2858// FIXME: Would be nice to autogen this.
2859// FIXME: This is a bit of a maze of special cases.
2860StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2861                                      unsigned &PredicationCode,
2862                                      bool &CarrySetting,
2863                                      unsigned &ProcessorIMod,
2864                                      StringRef &ITMask) {
2865  PredicationCode = ARMCC::AL;
2866  CarrySetting = false;
2867  ProcessorIMod = 0;
2868
2869  // Ignore some mnemonics we know aren't predicated forms.
2870  //
2871  // FIXME: Would be nice to autogen this.
2872  if ((Mnemonic == "movs" && isThumb()) ||
2873      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2874      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2875      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2876      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2877      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2878      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2879      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2880    return Mnemonic;
2881
2882  // First, split out any predication code. Ignore mnemonics we know aren't
2883  // predicated but do have a carry-set and so weren't caught above.
2884  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2885      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2886      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2887      Mnemonic != "sbcs") {
2888    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2889      .Case("eq", ARMCC::EQ)
2890      .Case("ne", ARMCC::NE)
2891      .Case("hs", ARMCC::HS)
2892      .Case("cs", ARMCC::HS)
2893      .Case("lo", ARMCC::LO)
2894      .Case("cc", ARMCC::LO)
2895      .Case("mi", ARMCC::MI)
2896      .Case("pl", ARMCC::PL)
2897      .Case("vs", ARMCC::VS)
2898      .Case("vc", ARMCC::VC)
2899      .Case("hi", ARMCC::HI)
2900      .Case("ls", ARMCC::LS)
2901      .Case("ge", ARMCC::GE)
2902      .Case("lt", ARMCC::LT)
2903      .Case("gt", ARMCC::GT)
2904      .Case("le", ARMCC::LE)
2905      .Case("al", ARMCC::AL)
2906      .Default(~0U);
2907    if (CC != ~0U) {
2908      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2909      PredicationCode = CC;
2910    }
2911  }
2912
2913  // Next, determine if we have a carry setting bit. We explicitly ignore all
2914  // the instructions we know end in 's'.
2915  if (Mnemonic.endswith("s") &&
2916      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2917        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2918        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2919        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2920        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2921        (Mnemonic == "movs" && isThumb()))) {
2922    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2923    CarrySetting = true;
2924  }
2925
2926  // The "cps" instruction can have a interrupt mode operand which is glued into
2927  // the mnemonic. Check if this is the case, split it and parse the imod op
2928  if (Mnemonic.startswith("cps")) {
2929    // Split out any imod code.
2930    unsigned IMod =
2931      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2932      .Case("ie", ARM_PROC::IE)
2933      .Case("id", ARM_PROC::ID)
2934      .Default(~0U);
2935    if (IMod != ~0U) {
2936      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2937      ProcessorIMod = IMod;
2938    }
2939  }
2940
2941  // The "it" instruction has the condition mask on the end of the mnemonic.
2942  if (Mnemonic.startswith("it")) {
2943    ITMask = Mnemonic.slice(2, Mnemonic.size());
2944    Mnemonic = Mnemonic.slice(0, 2);
2945  }
2946
2947  return Mnemonic;
2948}
2949
2950/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2951/// inclusion of carry set or predication code operands.
2952//
2953// FIXME: It would be nice to autogen this.
2954void ARMAsmParser::
2955getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2956                      bool &CanAcceptPredicationCode) {
2957  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2958      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2959      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2960      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2961      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2962      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2963      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2964      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2965      // FIXME: We need a better way. This really confused Thumb2
2966      // parsing for 'mov'.
2967      (Mnemonic == "mov" && !isThumbOne())) {
2968    CanAcceptCarrySet = true;
2969  } else {
2970    CanAcceptCarrySet = false;
2971  }
2972
2973  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2974      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2975      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2976      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2977      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2978      Mnemonic == "setend" ||
2979      (Mnemonic == "nop" && isThumbOne()) ||
2980      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2981      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2982        && !isThumb()) ||
2983      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2984    CanAcceptPredicationCode = false;
2985  } else {
2986    CanAcceptPredicationCode = true;
2987  }
2988
2989  if (isThumb())
2990    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2991        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2992      CanAcceptPredicationCode = false;
2993}
2994
2995bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2996                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2997
2998  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2999  // another does not. Specifically, the MOVW instruction does not. So we
3000  // special case it here and remove the defaulted (non-setting) cc_out
3001  // operand if that's the instruction we're trying to match.
3002  //
3003  // We do this as post-processing of the explicit operands rather than just
3004  // conditionally adding the cc_out in the first place because we need
3005  // to check the type of the parsed immediate operand.
3006  if (Mnemonic == "mov" && Operands.size() > 4 &&
3007      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3008      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3009      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3010    return true;
3011
3012  // Register-register 'add' for thumb does not have a cc_out operand
3013  // when there are only two register operands.
3014  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3015      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3016      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3017      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3018    return true;
3019  // Register-register 'add' for thumb does not have a cc_out operand
3020  // when it's an ADD Rdm, SP, {Rdm|#imm} instruction.
3021  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3022      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3023      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3024      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3025      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3026    return true;
3027  // Register-register 'add/sub' for thumb does not have a cc_out operand
3028  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3029  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3030  // right, this will result in better diagnostics (which operand is off)
3031  // anyway.
3032  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3033      (Operands.size() == 5 || Operands.size() == 6) &&
3034      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3035      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3036      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3037    return true;
3038
3039  return false;
3040}
3041
3042/// Parse an arm instruction mnemonic followed by its operands.
3043bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3044                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3045  // Create the leading tokens for the mnemonic, split by '.' characters.
3046  size_t Start = 0, Next = Name.find('.');
3047  StringRef Mnemonic = Name.slice(Start, Next);
3048
3049  // Split out the predication code and carry setting flag from the mnemonic.
3050  unsigned PredicationCode;
3051  unsigned ProcessorIMod;
3052  bool CarrySetting;
3053  StringRef ITMask;
3054  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3055                           ProcessorIMod, ITMask);
3056
3057  // In Thumb1, only the branch (B) instruction can be predicated.
3058  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3059    Parser.EatToEndOfStatement();
3060    return Error(NameLoc, "conditional execution not supported in Thumb1");
3061  }
3062
3063  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3064
3065  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3066  // is the mask as it will be for the IT encoding if the conditional
3067  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3068  // where the conditional bit0 is zero, the instruction post-processing
3069  // will adjust the mask accordingly.
3070  if (Mnemonic == "it") {
3071    unsigned Mask = 8;
3072    for (unsigned i = ITMask.size(); i != 0; --i) {
3073      char pos = ITMask[i - 1];
3074      if (pos != 't' && pos != 'e') {
3075        Parser.EatToEndOfStatement();
3076        return Error(NameLoc, "illegal IT instruction mask '" + ITMask + "'");
3077      }
3078      Mask >>= 1;
3079      if (ITMask[i - 1] == 't')
3080        Mask |= 8;
3081    }
3082    Operands.push_back(ARMOperand::CreateITMask(Mask, NameLoc));
3083  }
3084
3085  // FIXME: This is all a pretty gross hack. We should automatically handle
3086  // optional operands like this via tblgen.
3087
3088  // Next, add the CCOut and ConditionCode operands, if needed.
3089  //
3090  // For mnemonics which can ever incorporate a carry setting bit or predication
3091  // code, our matching model involves us always generating CCOut and
3092  // ConditionCode operands to match the mnemonic "as written" and then we let
3093  // the matcher deal with finding the right instruction or generating an
3094  // appropriate error.
3095  bool CanAcceptCarrySet, CanAcceptPredicationCode;
3096  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3097
3098  // If we had a carry-set on an instruction that can't do that, issue an
3099  // error.
3100  if (!CanAcceptCarrySet && CarrySetting) {
3101    Parser.EatToEndOfStatement();
3102    return Error(NameLoc, "instruction '" + Mnemonic +
3103                 "' can not set flags, but 's' suffix specified");
3104  }
3105  // If we had a predication code on an instruction that can't do that, issue an
3106  // error.
3107  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3108    Parser.EatToEndOfStatement();
3109    return Error(NameLoc, "instruction '" + Mnemonic +
3110                 "' is not predicable, but condition code specified");
3111  }
3112
3113  // Add the carry setting operand, if necessary.
3114  //
3115  // FIXME: It would be awesome if we could somehow invent a location such that
3116  // match errors on this operand would print a nice diagnostic about how the
3117  // 's' character in the mnemonic resulted in a CCOut operand.
3118  if (CanAcceptCarrySet)
3119    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3120                                               NameLoc));
3121
3122  // Add the predication code operand, if necessary.
3123  if (CanAcceptPredicationCode) {
3124    Operands.push_back(ARMOperand::CreateCondCode(
3125                         ARMCC::CondCodes(PredicationCode), NameLoc));
3126  }
3127
3128  // Add the processor imod operand, if necessary.
3129  if (ProcessorIMod) {
3130    Operands.push_back(ARMOperand::CreateImm(
3131          MCConstantExpr::Create(ProcessorIMod, getContext()),
3132                                 NameLoc, NameLoc));
3133  }
3134
3135  // Add the remaining tokens in the mnemonic.
3136  while (Next != StringRef::npos) {
3137    Start = Next;
3138    Next = Name.find('.', Start + 1);
3139    StringRef ExtraToken = Name.slice(Start, Next);
3140
3141    // For now, we're only parsing Thumb1 (for the most part), so
3142    // just ignore ".n" qualifiers. We'll use them to restrict
3143    // matching when we do Thumb2.
3144    if (ExtraToken != ".n")
3145      Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
3146  }
3147
3148  // Read the remaining operands.
3149  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3150    // Read the first operand.
3151    if (parseOperand(Operands, Mnemonic)) {
3152      Parser.EatToEndOfStatement();
3153      return true;
3154    }
3155
3156    while (getLexer().is(AsmToken::Comma)) {
3157      Parser.Lex();  // Eat the comma.
3158
3159      // Parse and remember the operand.
3160      if (parseOperand(Operands, Mnemonic)) {
3161        Parser.EatToEndOfStatement();
3162        return true;
3163      }
3164    }
3165  }
3166
3167  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3168    Parser.EatToEndOfStatement();
3169    return TokError("unexpected token in argument list");
3170  }
3171
3172  Parser.Lex(); // Consume the EndOfStatement
3173
3174  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3175  // do and don't have a cc_out optional-def operand. With some spot-checks
3176  // of the operand list, we can figure out which variant we're trying to
3177  // parse and adjust accordingly before actually matching. Reason number
3178  // #317 the table driven matcher doesn't fit well with the ARM instruction
3179  // set.
3180  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3181    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3182    Operands.erase(Operands.begin() + 1);
3183    delete Op;
3184  }
3185
3186  // ARM mode 'blx' need special handling, as the register operand version
3187  // is predicable, but the label operand version is not. So, we can't rely
3188  // on the Mnemonic based checking to correctly figure out when to put
3189  // a CondCode operand in the list. If we're trying to match the label
3190  // version, remove the CondCode operand here.
3191  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3192      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3193    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3194    Operands.erase(Operands.begin() + 1);
3195    delete Op;
3196  }
3197
3198  // The vector-compare-to-zero instructions have a literal token "#0" at
3199  // the end that comes to here as an immediate operand. Convert it to a
3200  // token to play nicely with the matcher.
3201  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3202      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3203      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3204    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3205    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3206    if (CE && CE->getValue() == 0) {
3207      Operands.erase(Operands.begin() + 5);
3208      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3209      delete Op;
3210    }
3211  }
3212  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3213  // end. Convert it to a token here.
3214  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3215      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3216    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3217    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3218    if (CE && CE->getValue() == 0) {
3219      Operands.erase(Operands.begin() + 5);
3220      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3221      delete Op;
3222    }
3223  }
3224
3225  return false;
3226}
3227
3228// Validate context-sensitive operand constraints.
3229
3230// return 'true' if register list contains non-low GPR registers,
3231// 'false' otherwise. If Reg is in the register list or is HiReg, set
3232// 'containsReg' to true.
3233static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3234                                 unsigned HiReg, bool &containsReg) {
3235  containsReg = false;
3236  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3237    unsigned OpReg = Inst.getOperand(i).getReg();
3238    if (OpReg == Reg)
3239      containsReg = true;
3240    // Anything other than a low register isn't legal here.
3241    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3242      return true;
3243  }
3244  return false;
3245}
3246
3247// FIXME: We would really like to be able to tablegen'erate this.
3248bool ARMAsmParser::
3249validateInstruction(MCInst &Inst,
3250                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3251  switch (Inst.getOpcode()) {
3252  case ARM::LDRD:
3253  case ARM::LDRD_PRE:
3254  case ARM::LDRD_POST:
3255  case ARM::LDREXD: {
3256    // Rt2 must be Rt + 1.
3257    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3258    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3259    if (Rt2 != Rt + 1)
3260      return Error(Operands[3]->getStartLoc(),
3261                   "destination operands must be sequential");
3262    return false;
3263  }
3264  case ARM::STRD: {
3265    // Rt2 must be Rt + 1.
3266    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3267    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3268    if (Rt2 != Rt + 1)
3269      return Error(Operands[3]->getStartLoc(),
3270                   "source operands must be sequential");
3271    return false;
3272  }
3273  case ARM::STRD_PRE:
3274  case ARM::STRD_POST:
3275  case ARM::STREXD: {
3276    // Rt2 must be Rt + 1.
3277    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3278    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3279    if (Rt2 != Rt + 1)
3280      return Error(Operands[3]->getStartLoc(),
3281                   "source operands must be sequential");
3282    return false;
3283  }
3284  case ARM::SBFX:
3285  case ARM::UBFX: {
3286    // width must be in range [1, 32-lsb]
3287    unsigned lsb = Inst.getOperand(2).getImm();
3288    unsigned widthm1 = Inst.getOperand(3).getImm();
3289    if (widthm1 >= 32 - lsb)
3290      return Error(Operands[5]->getStartLoc(),
3291                   "bitfield width must be in range [1,32-lsb]");
3292    return false;
3293  }
3294  case ARM::tLDMIA: {
3295    // Thumb LDM instructions are writeback iff the base register is not
3296    // in the register list.
3297    unsigned Rn = Inst.getOperand(0).getReg();
3298    bool hasWritebackToken =
3299      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3300       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3301    bool listContainsBase;
3302    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
3303      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3304                   "registers must be in range r0-r7");
3305    // If we should have writeback, then there should be a '!' token.
3306    if (!listContainsBase && !hasWritebackToken)
3307      return Error(Operands[2]->getStartLoc(),
3308                   "writeback operator '!' expected");
3309    // Likewise, if we should not have writeback, there must not be a '!'
3310    if (listContainsBase && hasWritebackToken)
3311      return Error(Operands[3]->getStartLoc(),
3312                   "writeback operator '!' not allowed when base register "
3313                   "in register list");
3314
3315    break;
3316  }
3317  case ARM::tPOP: {
3318    bool listContainsBase;
3319    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3320      return Error(Operands[2]->getStartLoc(),
3321                   "registers must be in range r0-r7 or pc");
3322    break;
3323  }
3324  case ARM::tPUSH: {
3325    bool listContainsBase;
3326    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3327      return Error(Operands[2]->getStartLoc(),
3328                   "registers must be in range r0-r7 or lr");
3329    break;
3330  }
3331  case ARM::tSTMIA_UPD: {
3332    bool listContainsBase;
3333    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3334      return Error(Operands[4]->getStartLoc(),
3335                   "registers must be in range r0-r7");
3336    break;
3337  }
3338  }
3339
3340  return false;
3341}
3342
3343void ARMAsmParser::
3344processInstruction(MCInst &Inst,
3345                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3346  switch (Inst.getOpcode()) {
3347  case ARM::LDMIA_UPD:
3348    // If this is a load of a single register via a 'pop', then we should use
3349    // a post-indexed LDR instruction instead, per the ARM ARM.
3350    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3351        Inst.getNumOperands() == 5) {
3352      MCInst TmpInst;
3353      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3354      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3355      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3356      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3357      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3358      TmpInst.addOperand(MCOperand::CreateImm(4));
3359      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3360      TmpInst.addOperand(Inst.getOperand(3));
3361      Inst = TmpInst;
3362    }
3363    break;
3364  case ARM::STMDB_UPD:
3365    // If this is a store of a single register via a 'push', then we should use
3366    // a pre-indexed STR instruction instead, per the ARM ARM.
3367    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3368        Inst.getNumOperands() == 5) {
3369      MCInst TmpInst;
3370      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3371      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3372      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3373      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3374      TmpInst.addOperand(MCOperand::CreateImm(-4));
3375      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3376      TmpInst.addOperand(Inst.getOperand(3));
3377      Inst = TmpInst;
3378    }
3379    break;
3380  case ARM::tADDi8:
3381    // If the immediate is in the range 0-7, we really wanted tADDi3.
3382    if (Inst.getOperand(3).getImm() < 8)
3383      Inst.setOpcode(ARM::tADDi3);
3384    break;
3385  case ARM::tBcc:
3386    // If the conditional is AL, we really want tB.
3387    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3388      Inst.setOpcode(ARM::tB);
3389    break;
3390  case ARM::t2IT: {
3391    // The mask bits for all but the first condition are represented as
3392    // the low bit of the condition code value implies 't'. We currently
3393    // always have 1 implies 't', so XOR toggle the bits if the low bit
3394    // of the condition code is zero. The encoding also expects the low
3395    // bit of the condition to be encoded as bit 4 of the mask operand,
3396    // so mask that in if needed
3397    MCOperand &MO = Inst.getOperand(1);
3398    unsigned Mask = MO.getImm();
3399    if ((Inst.getOperand(0).getImm() & 1) == 0) {
3400      unsigned TZ = CountTrailingZeros_32(Mask);
3401      assert(Mask && TZ <= 3 && "illegal IT mask value!");
3402      for (unsigned i = 3; i != TZ; --i)
3403        Mask ^= 1 << i;
3404    } else
3405      Mask |= 0x10;
3406    MO.setImm(Mask);
3407    break;
3408  }
3409  }
3410}
3411
3412// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3413// the ARMInsts array) instead. Getting that here requires awkward
3414// API changes, though. Better way?
3415namespace llvm {
3416extern MCInstrDesc ARMInsts[];
3417}
3418static MCInstrDesc &getInstDesc(unsigned Opcode) {
3419  return ARMInsts[Opcode];
3420}
3421
3422unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3423  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3424  // suffix depending on whether they're in an IT block or not.
3425  unsigned Opc = Inst.getOpcode();
3426  MCInstrDesc &MCID = getInstDesc(Opc);
3427  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3428    assert(MCID.hasOptionalDef() &&
3429           "optionally flag setting instruction missing optional def operand");
3430    assert(MCID.NumOperands == Inst.getNumOperands() &&
3431           "operand count mismatch!");
3432    // Find the optional-def operand (cc_out).
3433    unsigned OpNo;
3434    for (OpNo = 0;
3435         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3436         ++OpNo)
3437      ;
3438    // If we're parsing Thumb1, reject it completely.
3439    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3440      return Match_MnemonicFail;
3441    // If we're parsing Thumb2, which form is legal depends on whether we're
3442    // in an IT block.
3443    // FIXME: We don't yet do IT blocks, so just always consider it to be
3444    // that we aren't in one until we do.
3445    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3446      return Match_RequiresITBlock;
3447  }
3448  // Some high-register supporting Thumb1 encodings only allow both registers
3449  // to be from r0-r7 when in Thumb2.
3450  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3451           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3452           isARMLowRegister(Inst.getOperand(2).getReg()))
3453    return Match_RequiresThumb2;
3454  // Others only require ARMv6 or later.
3455  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3456           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3457           isARMLowRegister(Inst.getOperand(1).getReg()))
3458    return Match_RequiresV6;
3459  return Match_Success;
3460}
3461
3462bool ARMAsmParser::
3463MatchAndEmitInstruction(SMLoc IDLoc,
3464                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3465                        MCStreamer &Out) {
3466  MCInst Inst;
3467  unsigned ErrorInfo;
3468  unsigned MatchResult;
3469  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3470  switch (MatchResult) {
3471  default: break;
3472  case Match_Success:
3473    // Context sensitive operand constraints aren't handled by the matcher,
3474    // so check them here.
3475    if (validateInstruction(Inst, Operands))
3476      return true;
3477
3478    // Some instructions need post-processing to, for example, tweak which
3479    // encoding is selected.
3480    processInstruction(Inst, Operands);
3481
3482    Out.EmitInstruction(Inst);
3483    return false;
3484  case Match_MissingFeature:
3485    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3486    return true;
3487  case Match_InvalidOperand: {
3488    SMLoc ErrorLoc = IDLoc;
3489    if (ErrorInfo != ~0U) {
3490      if (ErrorInfo >= Operands.size())
3491        return Error(IDLoc, "too few operands for instruction");
3492
3493      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3494      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3495    }
3496
3497    return Error(ErrorLoc, "invalid operand for instruction");
3498  }
3499  case Match_MnemonicFail:
3500    return Error(IDLoc, "invalid instruction");
3501  case Match_ConversionFail:
3502    // The converter function will have already emited a diagnostic.
3503    return true;
3504  case Match_RequiresITBlock:
3505    return Error(IDLoc, "instruction only valid inside IT block");
3506  case Match_RequiresV6:
3507    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3508  case Match_RequiresThumb2:
3509    return Error(IDLoc, "instruction variant requires Thumb2");
3510  }
3511
3512  llvm_unreachable("Implement any new match types added!");
3513  return true;
3514}
3515
3516/// parseDirective parses the arm specific directives
3517bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3518  StringRef IDVal = DirectiveID.getIdentifier();
3519  if (IDVal == ".word")
3520    return parseDirectiveWord(4, DirectiveID.getLoc());
3521  else if (IDVal == ".thumb")
3522    return parseDirectiveThumb(DirectiveID.getLoc());
3523  else if (IDVal == ".thumb_func")
3524    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3525  else if (IDVal == ".code")
3526    return parseDirectiveCode(DirectiveID.getLoc());
3527  else if (IDVal == ".syntax")
3528    return parseDirectiveSyntax(DirectiveID.getLoc());
3529  return true;
3530}
3531
3532/// parseDirectiveWord
3533///  ::= .word [ expression (, expression)* ]
3534bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3535  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3536    for (;;) {
3537      const MCExpr *Value;
3538      if (getParser().ParseExpression(Value))
3539        return true;
3540
3541      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3542
3543      if (getLexer().is(AsmToken::EndOfStatement))
3544        break;
3545
3546      // FIXME: Improve diagnostic.
3547      if (getLexer().isNot(AsmToken::Comma))
3548        return Error(L, "unexpected token in directive");
3549      Parser.Lex();
3550    }
3551  }
3552
3553  Parser.Lex();
3554  return false;
3555}
3556
3557/// parseDirectiveThumb
3558///  ::= .thumb
3559bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3560  if (getLexer().isNot(AsmToken::EndOfStatement))
3561    return Error(L, "unexpected token in directive");
3562  Parser.Lex();
3563
3564  // TODO: set thumb mode
3565  // TODO: tell the MC streamer the mode
3566  // getParser().getStreamer().Emit???();
3567  return false;
3568}
3569
3570/// parseDirectiveThumbFunc
3571///  ::= .thumbfunc symbol_name
3572bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3573  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3574  bool isMachO = MAI.hasSubsectionsViaSymbols();
3575  StringRef Name;
3576
3577  // Darwin asm has function name after .thumb_func direction
3578  // ELF doesn't
3579  if (isMachO) {
3580    const AsmToken &Tok = Parser.getTok();
3581    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3582      return Error(L, "unexpected token in .thumb_func directive");
3583    Name = Tok.getString();
3584    Parser.Lex(); // Consume the identifier token.
3585  }
3586
3587  if (getLexer().isNot(AsmToken::EndOfStatement))
3588    return Error(L, "unexpected token in directive");
3589  Parser.Lex();
3590
3591  // FIXME: assuming function name will be the line following .thumb_func
3592  if (!isMachO) {
3593    Name = Parser.getTok().getString();
3594  }
3595
3596  // Mark symbol as a thumb symbol.
3597  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3598  getParser().getStreamer().EmitThumbFunc(Func);
3599  return false;
3600}
3601
3602/// parseDirectiveSyntax
3603///  ::= .syntax unified | divided
3604bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3605  const AsmToken &Tok = Parser.getTok();
3606  if (Tok.isNot(AsmToken::Identifier))
3607    return Error(L, "unexpected token in .syntax directive");
3608  StringRef Mode = Tok.getString();
3609  if (Mode == "unified" || Mode == "UNIFIED")
3610    Parser.Lex();
3611  else if (Mode == "divided" || Mode == "DIVIDED")
3612    return Error(L, "'.syntax divided' arm asssembly not supported");
3613  else
3614    return Error(L, "unrecognized syntax mode in .syntax directive");
3615
3616  if (getLexer().isNot(AsmToken::EndOfStatement))
3617    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3618  Parser.Lex();
3619
3620  // TODO tell the MC streamer the mode
3621  // getParser().getStreamer().Emit???();
3622  return false;
3623}
3624
3625/// parseDirectiveCode
3626///  ::= .code 16 | 32
3627bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3628  const AsmToken &Tok = Parser.getTok();
3629  if (Tok.isNot(AsmToken::Integer))
3630    return Error(L, "unexpected token in .code directive");
3631  int64_t Val = Parser.getTok().getIntVal();
3632  if (Val == 16)
3633    Parser.Lex();
3634  else if (Val == 32)
3635    Parser.Lex();
3636  else
3637    return Error(L, "invalid operand to .code directive");
3638
3639  if (getLexer().isNot(AsmToken::EndOfStatement))
3640    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3641  Parser.Lex();
3642
3643  if (Val == 16) {
3644    if (!isThumb()) {
3645      SwitchMode();
3646      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3647    }
3648  } else {
3649    if (isThumb()) {
3650      SwitchMode();
3651      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3652    }
3653  }
3654
3655  return false;
3656}
3657
3658extern "C" void LLVMInitializeARMAsmLexer();
3659
3660/// Force static initialization.
3661extern "C" void LLVMInitializeARMAsmParser() {
3662  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3663  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3664  LLVMInitializeARMAsmLexer();
3665}
3666
3667#define GET_REGISTER_MATCHER
3668#define GET_MATCHER_IMPLEMENTATION
3669#include "ARMGenAsmMatcher.inc"
3670